| ixgbe_common.c (215911) | ixgbe_common.c (217593) |
|---|---|
| 1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 215911 2010-11-26 22:46:32Z jfv $*/ | 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 217593 2011-01-19 19:36:27Z jfv $*/ |
| 34 35#include "ixgbe_common.h" 36#include "ixgbe_phy.h" 37#include "ixgbe_api.h" 38 39static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 40static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 41static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); --- 136 unchanged lines hidden (view full) --- 178/** 179 * ixgbe_start_hw_gen2 - Init sequence for common device family 180 * @hw: pointer to hw structure 181 * 182 * Performs the init sequence common to the second generation 183 * of 10 GbE devices. 184 * Devices in the second generation: 185 * 82599 | 34 35#include "ixgbe_common.h" 36#include "ixgbe_phy.h" 37#include "ixgbe_api.h" 38 39static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 40static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 41static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); --- 136 unchanged lines hidden (view full) --- 178/** 179 * ixgbe_start_hw_gen2 - Init sequence for common device family 180 * @hw: pointer to hw structure 181 * 182 * Performs the init sequence common to the second generation 183 * of 10 GbE devices. 184 * Devices in the second generation: 185 * 82599 |
| 186 * X540 |
|
| 186 **/ 187s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 188{ 189 u32 i; 190 u32 regval; 191 192 /* Clear the rate limiters */ 193 for (i = 0; i < hw->mac.max_tx_queues; i++) { --- 1490 unchanged lines hidden (view full) --- 1684 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1685 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1686 hw->mac.addr[0], hw->mac.addr[1], 1687 hw->mac.addr[2]); 1688 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1689 hw->mac.addr[4], hw->mac.addr[5]); 1690 1691 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); | 187 **/ 188s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 189{ 190 u32 i; 191 u32 regval; 192 193 /* Clear the rate limiters */ 194 for (i = 0; i < hw->mac.max_tx_queues; i++) { --- 1490 unchanged lines hidden (view full) --- 1685 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1686 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1687 hw->mac.addr[0], hw->mac.addr[1], 1688 hw->mac.addr[2]); 1689 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1690 hw->mac.addr[4], hw->mac.addr[5]); 1691 1692 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
| 1693 1694 /* clear VMDq pool/queue selection for RAR 0 */ 1695 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); |
|
| 1692 } 1693 hw->addr_ctrl.overflow_promisc = 0; 1694 1695 hw->addr_ctrl.rar_used_count = 1; 1696 1697 /* Zero out the other receive addresses. */ 1698 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1699 for (i = 1; i < rar_entries; i++) { --- 819 unchanged lines hidden (view full) --- 2519 } 2520 2521 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 2522 reg_val |= IXGBE_CTRL_GIO_DIS; 2523 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 2524 2525 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2526 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) | 1696 } 1697 hw->addr_ctrl.overflow_promisc = 0; 1698 1699 hw->addr_ctrl.rar_used_count = 1; 1700 1701 /* Zero out the other receive addresses. */ 1702 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1703 for (i = 1; i < rar_entries; i++) { --- 819 unchanged lines hidden (view full) --- 2523 } 2524 2525 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 2526 reg_val |= IXGBE_CTRL_GIO_DIS; 2527 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 2528 2529 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2530 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) |
| 2527 goto out; | 2531 goto check_device_status; |
| 2528 usec_delay(100); 2529 } 2530 2531 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 2532 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2533 2534 /* | 2532 usec_delay(100); 2533 } 2534 2535 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 2536 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2537 2538 /* |
| 2535 * The GIO Master Disable bit didn't clear. There are multiple reasons 2536 * for this listed in the datasheet 5.2.5.3.2 Master Disable, and they 2537 * all require a double reset to recover from. Before proceeding, we 2538 * first wait a little more to try to ensure that, at a minimum, the 2539 * PCIe block has no transactions pending. | 2539 * Before proceeding, make sure that the PCIe block does not have 2540 * transactions pending. |
| 2540 */ | 2541 */ |
| 2542check_device_status: |
|
| 2541 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2542 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) & 2543 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2544 break; 2545 usec_delay(100); 2546 } 2547 2548 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT) 2549 DEBUGOUT("PCIe transaction pending bit also did not clear.\n"); | 2543 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2544 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) & 2545 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2546 break; 2547 usec_delay(100); 2548 } 2549 2550 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT) 2551 DEBUGOUT("PCIe transaction pending bit also did not clear.\n"); |
| 2552 else 2553 goto out; |
|
| 2550 2551 /* 2552 * Two consecutive resets are required via CTRL.RST per datasheet 2553 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2554 * of this need. The first reset prevents new master requests from 2555 * being issued by our device. We then must wait 1usec for any 2556 * remaining completions from the PCIe bus to trickle in, and then reset 2557 * again to clear out any effects they may have had on our device. --- 918 unchanged lines hidden (view full) --- 3476 3477 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3478 if (enable) 3479 pfvfspoof |= (1 << vf_target_shift); 3480 else 3481 pfvfspoof &= ~(1 << vf_target_shift); 3482 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3483} | 2554 2555 /* 2556 * Two consecutive resets are required via CTRL.RST per datasheet 2557 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2558 * of this need. The first reset prevents new master requests from 2559 * being issued by our device. We then must wait 1usec for any 2560 * remaining completions from the PCIe bus to trickle in, and then reset 2561 * again to clear out any effects they may have had on our device. --- 918 unchanged lines hidden (view full) --- 3480 3481 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3482 if (enable) 3483 pfvfspoof |= (1 << vf_target_shift); 3484 else 3485 pfvfspoof &= ~(1 << vf_target_shift); 3486 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3487} |
| 3488 3489/** 3490 * ixgbe_get_device_caps_generic - Get additional device capabilities 3491 * @hw: pointer to hardware structure 3492 * @device_caps: the EEPROM word with the extra device capabilities 3493 * 3494 * This function will read the EEPROM location for the device capabilities, 3495 * and return the word through device_caps. 3496 **/ 3497s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3498{ 3499 DEBUGFUNC("ixgbe_get_device_caps_generic"); 3500 3501 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3502 3503 return IXGBE_SUCCESS; 3504} 3505 3506/** 3507 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 3508 * @hw: pointer to hardware structure 3509 * 3510 **/ 3511void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 3512{ 3513 u32 regval; 3514 u32 i; 3515 3516 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 3517 3518 /* Enable relaxed ordering */ 3519 for (i = 0; i < hw->mac.max_tx_queues; i++) { 3520 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 3521 regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN; 3522 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 3523 } 3524 3525 for (i = 0; i < hw->mac.max_rx_queues; i++) { 3526 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 3527 regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN | 3528 IXGBE_DCA_RXCTRL_DESC_HSRO_EN); 3529 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 3530 } 3531 3532} |
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