33c33
< /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 215911 2010-11-26 22:46:32Z jfv $*/
---
> /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 217593 2011-01-19 19:36:27Z jfv $*/
185a186
> * X540
1691a1693,1695
>
> /* clear VMDq pool/queue selection for RAR 0 */
> hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2527c2531
< goto out;
---
> goto check_device_status;
2535,2539c2539,2540
< * The GIO Master Disable bit didn't clear. There are multiple reasons
< * for this listed in the datasheet 5.2.5.3.2 Master Disable, and they
< * all require a double reset to recover from. Before proceeding, we
< * first wait a little more to try to ensure that, at a minimum, the
< * PCIe block has no transactions pending.
---
> * Before proceeding, make sure that the PCIe block does not have
> * transactions pending.
2540a2542
> check_device_status:
2549a2552,2553
> else
> goto out;
3483a3488,3532
>
> /**
> * ixgbe_get_device_caps_generic - Get additional device capabilities
> * @hw: pointer to hardware structure
> * @device_caps: the EEPROM word with the extra device capabilities
> *
> * This function will read the EEPROM location for the device capabilities,
> * and return the word through device_caps.
> **/
> s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
> {
> DEBUGFUNC("ixgbe_get_device_caps_generic");
>
> hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
>
> return IXGBE_SUCCESS;
> }
>
> /**
> * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
> * @hw: pointer to hardware structure
> *
> **/
> void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
> {
> u32 regval;
> u32 i;
>
> DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
>
> /* Enable relaxed ordering */
> for (i = 0; i < hw->mac.max_tx_queues; i++) {
> regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
> regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
> IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
> }
>
> for (i = 0; i < hw->mac.max_rx_queues; i++) {
> regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
> regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
> IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
> IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
> }
>
> }