1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
--- 16 unchanged lines hidden (view full) ---
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 215911 2010-11-26 22:46:32Z jfv $*/
34
35#include "ixgbe_common.h"
36#include "ixgbe_phy.h"
37#include "ixgbe_api.h"
38
39static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
--- 136 unchanged lines hidden (view full) ---
178/**
179 * ixgbe_start_hw_gen2 - Init sequence for common device family
180 * @hw: pointer to hw structure
181 *
182 * Performs the init sequence common to the second generation
183 * of 10 GbE devices.
184 * Devices in the second generation:
185 * 82599
186 **/
187s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
188{
189 u32 i;
190 u32 regval;
191
192 /* Clear the rate limiters */
193 for (i = 0; i < hw->mac.max_tx_queues; i++) {
--- 1490 unchanged lines hidden (view full) ---
1684 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
1685 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
1686 hw->mac.addr[0], hw->mac.addr[1],
1687 hw->mac.addr[2]);
1688 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
1689 hw->mac.addr[4], hw->mac.addr[5]);
1690
1691 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1692 }
1693 hw->addr_ctrl.overflow_promisc = 0;
1694
1695 hw->addr_ctrl.rar_used_count = 1;
1696
1697 /* Zero out the other receive addresses. */
1698 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
1699 for (i = 1; i < rar_entries; i++) {
--- 819 unchanged lines hidden (view full) ---
2519 }
2520
2521 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2522 reg_val |= IXGBE_CTRL_GIO_DIS;
2523 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
2524
2525 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2526 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2527 goto out;
2528 usec_delay(100);
2529 }
2530
2531 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
2532 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2533
2534 /*
2535 * The GIO Master Disable bit didn't clear. There are multiple reasons
2536 * for this listed in the datasheet 5.2.5.3.2 Master Disable, and they
2537 * all require a double reset to recover from. Before proceeding, we
2538 * first wait a little more to try to ensure that, at a minimum, the
2539 * PCIe block has no transactions pending.
2540 */
2541 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2542 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2543 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2544 break;
2545 usec_delay(100);
2546 }
2547
2548 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
2549 DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
2550
2551 /*
2552 * Two consecutive resets are required via CTRL.RST per datasheet
2553 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2554 * of this need. The first reset prevents new master requests from
2555 * being issued by our device. We then must wait 1usec for any
2556 * remaining completions from the PCIe bus to trickle in, and then reset
2557 * again to clear out any effects they may have had on our device.
--- 918 unchanged lines hidden (view full) ---
3476
3477 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3478 if (enable)
3479 pfvfspoof |= (1 << vf_target_shift);
3480 else
3481 pfvfspoof &= ~(1 << vf_target_shift);
3482 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3483}
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
--- 16 unchanged lines hidden (view full) ---
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 215911 2010-11-26 22:46:32Z jfv $*/
34
35#include "ixgbe_common.h"
36#include "ixgbe_phy.h"
37#include "ixgbe_api.h"
38
39static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
--- 136 unchanged lines hidden (view full) ---
178/**
179 * ixgbe_start_hw_gen2 - Init sequence for common device family
180 * @hw: pointer to hw structure
181 *
182 * Performs the init sequence common to the second generation
183 * of 10 GbE devices.
184 * Devices in the second generation:
185 * 82599
186 **/
187s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
188{
189 u32 i;
190 u32 regval;
191
192 /* Clear the rate limiters */
193 for (i = 0; i < hw->mac.max_tx_queues; i++) {
--- 1490 unchanged lines hidden (view full) ---
1684 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
1685 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
1686 hw->mac.addr[0], hw->mac.addr[1],
1687 hw->mac.addr[2]);
1688 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
1689 hw->mac.addr[4], hw->mac.addr[5]);
1690
1691 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1692 }
1693 hw->addr_ctrl.overflow_promisc = 0;
1694
1695 hw->addr_ctrl.rar_used_count = 1;
1696
1697 /* Zero out the other receive addresses. */
1698 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
1699 for (i = 1; i < rar_entries; i++) {
--- 819 unchanged lines hidden (view full) ---
2519 }
2520
2521 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2522 reg_val |= IXGBE_CTRL_GIO_DIS;
2523 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
2524
2525 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2526 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2527 goto out;
2528 usec_delay(100);
2529 }
2530
2531 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
2532 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2533
2534 /*
2535 * The GIO Master Disable bit didn't clear. There are multiple reasons
2536 * for this listed in the datasheet 5.2.5.3.2 Master Disable, and they
2537 * all require a double reset to recover from. Before proceeding, we
2538 * first wait a little more to try to ensure that, at a minimum, the
2539 * PCIe block has no transactions pending.
2540 */
2541 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2542 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2543 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2544 break;
2545 usec_delay(100);
2546 }
2547
2548 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
2549 DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
2550
2551 /*
2552 * Two consecutive resets are required via CTRL.RST per datasheet
2553 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2554 * of this need. The first reset prevents new master requests from
2555 * being issued by our device. We then must wait 1usec for any
2556 * remaining completions from the PCIe bus to trickle in, and then reset
2557 * again to clear out any effects they may have had on our device.
--- 918 unchanged lines hidden (view full) ---
3476
3477 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3478 if (enable)
3479 pfvfspoof |= (1 << vf_target_shift);
3480 else
3481 pfvfspoof &= ~(1 << vf_target_shift);
3482 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3483}