| ispreg.h (155704) | ispreg.h (160080) |
|---|---|
| 1/* $FreeBSD: head/sys/dev/isp/ispreg.h 155704 2006-02-15 00:31:48Z mjacob $ */ | 1/* $FreeBSD: head/sys/dev/isp/ispreg.h 160080 2006-07-03 08:24:09Z mjacob $ */ |
| 2/*- 3 * Machine Independent (well, as best as possible) register 4 * definitions for Qlogic ISP SCSI adapters. 5 * 6 * Copyright (c) 1997-2006 by Matthew Jacob 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without --- 189 unchanged lines hidden (view full) --- 199 200/* ISP2100 Bus Control/Status Register */ 201 202#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 203#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 204#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 205#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 206#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ | 2/*- 3 * Machine Independent (well, as best as possible) register 4 * definitions for Qlogic ISP SCSI adapters. 5 * 6 * Copyright (c) 1997-2006 by Matthew Jacob 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without --- 189 unchanged lines hidden (view full) --- 199 200/* ISP2100 Bus Control/Status Register */ 201 202#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 203#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 204#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 205#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 206#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ |
| 207#define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ | 207#define BIU2100_NVRAM_OFFSET (1 << 14) 208#define BIU2100_FLASH_UPPER_64K 0x04 /* RW: Upper 64K Bank Select */ |
| 208#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 209#define BIU2100_SOFT_RESET 0x01 210/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 211 212 213/* BUS CONTROL REGISTER */ 214#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 215#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ --- 47 unchanged lines hidden (view full) --- 263#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 264#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 265 266/* NVRAM SEMAPHORE REGISTER */ 267#define BIU_NVRAM_CLOCK 0x0001 268#define BIU_NVRAM_SELECT 0x0002 269#define BIU_NVRAM_DATAOUT 0x0004 270#define BIU_NVRAM_DATAIN 0x0008 | 209#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 210#define BIU2100_SOFT_RESET 0x01 211/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 212 213 214/* BUS CONTROL REGISTER */ 215#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 216#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ --- 47 unchanged lines hidden (view full) --- 264#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 265#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 266 267/* NVRAM SEMAPHORE REGISTER */ 268#define BIU_NVRAM_CLOCK 0x0001 269#define BIU_NVRAM_SELECT 0x0002 270#define BIU_NVRAM_DATAOUT 0x0004 271#define BIU_NVRAM_DATAIN 0x0008 |
| 272#define BIU_NVRAM_BUSY 0x0080 /* 2322/24xx only */ |
|
| 271#define ISP_NVRAM_READ 6 272 273/* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 274#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 275#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 276#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 277#define DMA_DMA_DIRECTION 0x0001 /* 278 * Set DMA direction: --- 663 unchanged lines hidden (view full) --- 942 * 943 * This is followed by some general host adapter parameters, and ends with 944 * a checksum xor byte at offset 255. For non-byte entities data is stored 945 * in Little Endian order. 946 */ 947#define ISP2100_NVRAM_SIZE 256 948/* ISP_NVRAM_VERSION is in same overall place */ 949#define ISP2100_NVRAM_RISCVER(c) (c)[6] | 273#define ISP_NVRAM_READ 6 274 275/* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 276#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 277#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 278#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 279#define DMA_DMA_DIRECTION 0x0001 /* 280 * Set DMA direction: --- 663 unchanged lines hidden (view full) --- 944 * 945 * This is followed by some general host adapter parameters, and ends with 946 * a checksum xor byte at offset 255. For non-byte entities data is stored 947 * in Little Endian order. 948 */ 949#define ISP2100_NVRAM_SIZE 256 950/* ISP_NVRAM_VERSION is in same overall place */ 951#define ISP2100_NVRAM_RISCVER(c) (c)[6] |
| 950#define ISP2100_NVRAM_OPTIONS(c) (c)[8] | 952#define ISP2100_NVRAM_OPTIONS(c) ((c)[8] | ((c)[9] << 8)) |
| 951#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 952#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 953#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 954#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 955#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 956 957#define ISP2100_NVRAM_PORT_NAME(c) (\ 958 (((uint64_t)(c)[18]) << 56) | \ 959 (((uint64_t)(c)[19]) << 48) | \ 960 (((uint64_t)(c)[20]) << 40) | \ 961 (((uint64_t)(c)[21]) << 32) | \ 962 (((uint64_t)(c)[22]) << 24) | \ 963 (((uint64_t)(c)[23]) << 16) | \ 964 (((uint64_t)(c)[24]) << 8) | \ 965 (((uint64_t)(c)[25]) << 0)) 966 | 953#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 954#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 955#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 956#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 957#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 958 959#define ISP2100_NVRAM_PORT_NAME(c) (\ 960 (((uint64_t)(c)[18]) << 56) | \ 961 (((uint64_t)(c)[19]) << 48) | \ 962 (((uint64_t)(c)[20]) << 40) | \ 963 (((uint64_t)(c)[21]) << 32) | \ 964 (((uint64_t)(c)[22]) << 24) | \ 965 (((uint64_t)(c)[23]) << 16) | \ 966 (((uint64_t)(c)[24]) << 8) | \ 967 (((uint64_t)(c)[25]) << 0)) 968 |
| 967#define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] | 969#define ISP2100_NVRAM_HARDLOOPID(c) ((c)[26] | ((c)[27] << 8)) 970#define ISP2100_NVRAM_TOV(c) ((c)[29]) |
| 968 | 971 |
| 969#define ISP2200_NVRAM_NODE_NAME(c) (\ | 972#define ISP2100_NVRAM_NODE_NAME(c) (\ |
| 970 (((uint64_t)(c)[30]) << 56) | \ 971 (((uint64_t)(c)[31]) << 48) | \ 972 (((uint64_t)(c)[32]) << 40) | \ 973 (((uint64_t)(c)[33]) << 32) | \ 974 (((uint64_t)(c)[34]) << 24) | \ 975 (((uint64_t)(c)[35]) << 16) | \ 976 (((uint64_t)(c)[36]) << 8) | \ 977 (((uint64_t)(c)[37]) << 0)) 978 | 973 (((uint64_t)(c)[30]) << 56) | \ 974 (((uint64_t)(c)[31]) << 48) | \ 975 (((uint64_t)(c)[32]) << 40) | \ 976 (((uint64_t)(c)[33]) << 32) | \ 977 (((uint64_t)(c)[34]) << 24) | \ 978 (((uint64_t)(c)[35]) << 16) | \ 979 (((uint64_t)(c)[36]) << 8) | \ 980 (((uint64_t)(c)[37]) << 0)) 981 |
| 979#define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] | 982#define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8)) 983 984#define ISP2100_RACC_TIMER(c) (c)[40] 985#define ISP2100_IDELAY_TIMER(c) (c)[41] 986 987#define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8)) 988 989#define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8)) 990 991#define ISP2100_NVRAM_HBA_OPTIONS(c) ((c)[70] | ((c)[71] << 8)) |
| 980#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 981#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 982#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 983#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 984#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 985#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 986 987#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 988 (((uint64_t)(c)[72]) << 56) | \ 989 (((uint64_t)(c)[73]) << 48) | \ 990 (((uint64_t)(c)[74]) << 40) | \ 991 (((uint64_t)(c)[75]) << 32) | \ 992 (((uint64_t)(c)[76]) << 24) | \ 993 (((uint64_t)(c)[77]) << 16) | \ 994 (((uint64_t)(c)[78]) << 8) | \ 995 (((uint64_t)(c)[79]) << 0)) 996 997#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] | 992#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 993#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 994#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 995#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 996#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 997#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 998 999#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 1000 (((uint64_t)(c)[72]) << 56) | \ 1001 (((uint64_t)(c)[73]) << 48) | \ 1002 (((uint64_t)(c)[74]) << 40) | \ 1003 (((uint64_t)(c)[75]) << 32) | \ 1004 (((uint64_t)(c)[76]) << 24) | \ 1005 (((uint64_t)(c)[77]) << 16) | \ 1006 (((uint64_t)(c)[78]) << 8) | \ 1007 (((uint64_t)(c)[79]) << 0)) 1008 1009#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] |
| 1010#define ISP2100_RESET_DELAY(c) (c)[81] |
|
| 998 | 1011 |
| 999#define ISP2200_HBA_FEATURES(c) (c)[232] | ((c)[233] << 8) | 1012#define ISP2100_HBA_FEATURES(c) ((c)[232] | ((c)[233] << 8)) |
| 1000 1001/* 1002 * Firmware Crash Dump 1003 * 1004 * QLogic needs specific information format when they look at firmware crashes. 1005 * 1006 * This is incredibly kernel memory consumptive (to say the least), so this 1007 * code is only compiled in when needed. --- 15 unchanged lines hidden --- | 1013 1014/* 1015 * Firmware Crash Dump 1016 * 1017 * QLogic needs specific information format when they look at firmware crashes. 1018 * 1019 * This is incredibly kernel memory consumptive (to say the least), so this 1020 * code is only compiled in when needed. --- 15 unchanged lines hidden --- |