1/*-
2 * Copyright (c) 2002 Adaptec Inc.
3 * All rights reserved.
4 *
5 * Written by: David Jeffery
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
| 1/*-
2 * Copyright (c) 2002 Adaptec Inc.
3 * All rights reserved.
4 *
5 * Written by: David Jeffery
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
|
28 * $FreeBSD: head/sys/dev/ips/ipsreg.h 152919 2005-11-29 09:39:41Z scottl $
| 28 * $FreeBSD: head/sys/dev/ips/ipsreg.h 154005 2006-01-03 23:03:15Z scottl $
|
29 */
30
31#include <sys/param.h>
32
33/*
34 * IPS CONSTANTS
35 */
36#define IPS_VENDOR_ID 0x1014
37#define IPS_VENDOR_ID_ADAPTEC 0x9005
38#define IPS_MORPHEUS_DEVICE_ID 0x01BD
39#define IPS_COPPERHEAD_DEVICE_ID 0x002E
40#define IPS_MARCO_DEVICE_ID 0x0250
41#define IPS_CSL 0xff
42#define IPS_POCL 0x30
43
44/* amounts of memory to allocate for certain commands */
45#define IPS_ADAPTER_INFO_LEN (sizeof(ips_adapter_info_t))
46#define IPS_DRIVE_INFO_LEN (sizeof(ips_drive_info_t))
47#define IPS_COMMAND_LEN 24
48#define IPS_MAX_SG_LEN (sizeof(ips_sg_element_t) * IPS_MAX_SG_ELEMENTS)
49#define IPS_NVRAM_PAGE_SIZE 128
50/* various flags */
51#define IPS_STATIC_FLAG 0x01
52
53/* states for the card to be in */
54#define IPS_DEV_OPEN 0x01
55#define IPS_TIMEOUT 0x02 /* command time out, need reset */
56#define IPS_OFFLINE 0x04 /* can't reset card/card failure */
57#define IPS_STATIC_BUSY 0x08
58
59/* max number of commands set to something low for now */
60#define IPS_MAX_CMD_NUM 128
61#define IPS_MAX_NUM_DRIVES 8
62#define IPS_MAX_SG_ELEMENTS 32
63#define IPS_MAX_IOBUF_SIZE (64 * 1024)
64#define IPS_BLKSIZE 512
| 29 */
30
31#include <sys/param.h>
32
33/*
34 * IPS CONSTANTS
35 */
36#define IPS_VENDOR_ID 0x1014
37#define IPS_VENDOR_ID_ADAPTEC 0x9005
38#define IPS_MORPHEUS_DEVICE_ID 0x01BD
39#define IPS_COPPERHEAD_DEVICE_ID 0x002E
40#define IPS_MARCO_DEVICE_ID 0x0250
41#define IPS_CSL 0xff
42#define IPS_POCL 0x30
43
44/* amounts of memory to allocate for certain commands */
45#define IPS_ADAPTER_INFO_LEN (sizeof(ips_adapter_info_t))
46#define IPS_DRIVE_INFO_LEN (sizeof(ips_drive_info_t))
47#define IPS_COMMAND_LEN 24
48#define IPS_MAX_SG_LEN (sizeof(ips_sg_element_t) * IPS_MAX_SG_ELEMENTS)
49#define IPS_NVRAM_PAGE_SIZE 128
50/* various flags */
51#define IPS_STATIC_FLAG 0x01
52
53/* states for the card to be in */
54#define IPS_DEV_OPEN 0x01
55#define IPS_TIMEOUT 0x02 /* command time out, need reset */
56#define IPS_OFFLINE 0x04 /* can't reset card/card failure */
57#define IPS_STATIC_BUSY 0x08
58
59/* max number of commands set to something low for now */
60#define IPS_MAX_CMD_NUM 128
61#define IPS_MAX_NUM_DRIVES 8
62#define IPS_MAX_SG_ELEMENTS 32
63#define IPS_MAX_IOBUF_SIZE (64 * 1024)
64#define IPS_BLKSIZE 512
|
| 65#define IPS_MAX_LD 8
66#define IPS_MAX_CHANNELS 4
67#define IPS_MAX_TARGETS 15
68#define IPS_MAX_CHUNKS 16
|
65
66/* logical drive states */
67
68#define IPS_LD_OFFLINE 0x02
69#define IPS_LD_OKAY 0x03
70#define IPS_LD_DEGRADED 0x04
71#define IPS_LD_FREE 0x00
72#define IPS_LD_SYS 0x06
73#define IPS_LD_CRS 0x24
74
75/* register offsets */
76#define MORPHEUS_REG_OMR0 0x0018 /* Outbound Msg. Reg. 0 */
77#define MORPHEUS_REG_OMR1 0x001C /* Outbound Msg. Reg. 1 */
78#define MORPHEUS_REG_IDR 0x0020 /* Inbound Doorbell Reg. */
79#define MORPHEUS_REG_IISR 0x0024 /* Inbound IRQ Status Reg. */
80#define MORPHEUS_REG_IIMR 0x0028 /* Inbound IRQ Mask Reg. */
81#define MORPHEUS_REG_OISR 0x0030 /* Outbound IRQ Status Reg. */
82#define MORPHEUS_REG_OIMR 0x0034 /* Outbound IRQ Mask Reg. */
83#define MORPHEUS_REG_IQPR 0x0040 /* Inbound Queue Port Reg. */
84#define MORPHEUS_REG_OQPR 0x0044 /* Outbound Queue Port Reg. */
85
86#define COPPER_REG_SCPR 0x05 /* Subsystem Ctrl. Port Reg. */
87#define COPPER_REG_ISPR 0x06 /* IRQ Status Port Reg. */
88#define COPPER_REG_CBSP 0x07 /* ? Reg. */
89#define COPPER_REG_HISR 0x08 /* Host IRQ Status Reg. */
90#define COPPER_REG_CCSAR 0x10 /* Cmd. Channel Sys Addr Reg.*/
91#define COPPER_REG_CCCR 0x14 /* Cmd. Channel Ctrl. Reg. */
92#define COPPER_REG_SQHR 0x20 /* Status Queue Head Reg. */
93#define COPPER_REG_SQTR 0x24 /* Status Queue Tail Reg. */
94#define COPPER_REG_SQER 0x28 /* Status Queue End Reg. */
95#define COPPER_REG_SQSR 0x2C /* Status Queue Start Reg. */
96
97/* bit definitions */
98#define MORPHEUS_BIT_POST1 0x01
99#define MORPHEUS_BIT_POST2 0x02
100#define MORPHEUS_BIT_CMD_IRQ 0x08
101
102#define COPPER_CMD_START 0x101A
103#define COPPER_SEM_BIT 0x08
104#define COPPER_EI_BIT 0x80
105#define COPPER_EBM_BIT 0x02
106#define COPPER_RESET_BIT 0x80
107#define COPPER_GHI_BIT 0x04
108#define COPPER_SCE_BIT 0x01
109#define COPPER_OP_BIT 0x01
110#define COPPER_ILE_BIT 0x10
111
112/* status defines */
113#define IPS_POST1_OK 0x8000
114#define IPS_POST2_OK 0x000f
115
116/* command op codes */
117#define IPS_READ_CMD 0x02
118#define IPS_WRITE_CMD 0x03
119#define IPS_ADAPTER_INFO_CMD 0x05
120#define IPS_CACHE_FLUSH_CMD 0x0A
121#define IPS_REBUILD_STATUS_CMD 0x0C
122#define IPS_ERROR_TABLE_CMD 0x17
123#define IPS_DRIVE_INFO_CMD 0x19
| 69
70/* logical drive states */
71
72#define IPS_LD_OFFLINE 0x02
73#define IPS_LD_OKAY 0x03
74#define IPS_LD_DEGRADED 0x04
75#define IPS_LD_FREE 0x00
76#define IPS_LD_SYS 0x06
77#define IPS_LD_CRS 0x24
78
79/* register offsets */
80#define MORPHEUS_REG_OMR0 0x0018 /* Outbound Msg. Reg. 0 */
81#define MORPHEUS_REG_OMR1 0x001C /* Outbound Msg. Reg. 1 */
82#define MORPHEUS_REG_IDR 0x0020 /* Inbound Doorbell Reg. */
83#define MORPHEUS_REG_IISR 0x0024 /* Inbound IRQ Status Reg. */
84#define MORPHEUS_REG_IIMR 0x0028 /* Inbound IRQ Mask Reg. */
85#define MORPHEUS_REG_OISR 0x0030 /* Outbound IRQ Status Reg. */
86#define MORPHEUS_REG_OIMR 0x0034 /* Outbound IRQ Mask Reg. */
87#define MORPHEUS_REG_IQPR 0x0040 /* Inbound Queue Port Reg. */
88#define MORPHEUS_REG_OQPR 0x0044 /* Outbound Queue Port Reg. */
89
90#define COPPER_REG_SCPR 0x05 /* Subsystem Ctrl. Port Reg. */
91#define COPPER_REG_ISPR 0x06 /* IRQ Status Port Reg. */
92#define COPPER_REG_CBSP 0x07 /* ? Reg. */
93#define COPPER_REG_HISR 0x08 /* Host IRQ Status Reg. */
94#define COPPER_REG_CCSAR 0x10 /* Cmd. Channel Sys Addr Reg.*/
95#define COPPER_REG_CCCR 0x14 /* Cmd. Channel Ctrl. Reg. */
96#define COPPER_REG_SQHR 0x20 /* Status Queue Head Reg. */
97#define COPPER_REG_SQTR 0x24 /* Status Queue Tail Reg. */
98#define COPPER_REG_SQER 0x28 /* Status Queue End Reg. */
99#define COPPER_REG_SQSR 0x2C /* Status Queue Start Reg. */
100
101/* bit definitions */
102#define MORPHEUS_BIT_POST1 0x01
103#define MORPHEUS_BIT_POST2 0x02
104#define MORPHEUS_BIT_CMD_IRQ 0x08
105
106#define COPPER_CMD_START 0x101A
107#define COPPER_SEM_BIT 0x08
108#define COPPER_EI_BIT 0x80
109#define COPPER_EBM_BIT 0x02
110#define COPPER_RESET_BIT 0x80
111#define COPPER_GHI_BIT 0x04
112#define COPPER_SCE_BIT 0x01
113#define COPPER_OP_BIT 0x01
114#define COPPER_ILE_BIT 0x10
115
116/* status defines */
117#define IPS_POST1_OK 0x8000
118#define IPS_POST2_OK 0x000f
119
120/* command op codes */
121#define IPS_READ_CMD 0x02
122#define IPS_WRITE_CMD 0x03
123#define IPS_ADAPTER_INFO_CMD 0x05
124#define IPS_CACHE_FLUSH_CMD 0x0A
125#define IPS_REBUILD_STATUS_CMD 0x0C
126#define IPS_ERROR_TABLE_CMD 0x17
127#define IPS_DRIVE_INFO_CMD 0x19
|
| 128#define IPS_CMD_READ_CONF 0x38
|
124#define IPS_SUBSYS_PARAM_CMD 0x40
125#define IPS_CONFIG_SYNC_CMD 0x58
126#define IPS_SG_READ_CMD 0x82
127#define IPS_SG_WRITE_CMD 0x83
128#define IPS_RW_NVRAM_CMD 0xBC
129#define IPS_FFDC_CMD 0xD7
130
131/* basic_status information returned by the adapter */
132#define IPS_MIN_ERROR 0x02
133#define IPS_BASIC_STATUS_MASK 0xFF
134#define IPS_GSC_STATUS_MASK 0x0F
135#define IPS_CMD_SUCCESS 0x00
136#define IPS_CMD_RECOVERED_ERROR 0x01
137#define IPS_DRV_ERROR 0x02 /* Driver supplied error */
138#define IPS_INVAL_OPCO 0x03
139#define IPS_INVAL_CMD_BLK 0x04
140#define IPS_INVAL_PARM_BLK 0x05
141#define IPS_BUSY 0x08
142#define IPS_CMD_CMPLT_WERROR 0x0C
143#define IPS_LD_ERROR 0x0D
144#define IPS_CMD_TIMEOUT 0x0E
145#define IPS_PHYS_DRV_ERROR 0x0F
146
147/* extended_status information returned by the adapter */
148#define IPS_ERR_SEL_TO 0xF0
149#define IPS_ERR_OU_RUN 0xF2
150#define IPS_ERR_HOST_RESET 0xF7
151#define IPS_ERR_DEV_RESET 0xF8
152#define IPS_ERR_RECOVERY 0xFC
153#define IPS_ERR_CKCOND 0xFF
154
155#define IPS_OS_FREEBSD 8
156#define IPS_VERSION_MAJOR "0.90"
157#define IPS_VERSION_MINOR ".10"
158
159/* Adapter Types */
160#define IPS_ADAPTER_COPPERHEAD 0x01
161#define IPS_ADAPTER_COPPERHEAD2 0x02
162#define IPS_ADAPTER_COPPERHEADOB1 0x03
163#define IPS_ADAPTER_COPPERHEADOB2 0x04
164#define IPS_ADAPTER_CLARINET 0x05
165#define IPS_ADAPTER_CLARINETLITE 0x06
166#define IPS_ADAPTER_TROMBONE 0x07
167#define IPS_ADAPTER_MORPHEUS 0x08
168#define IPS_ADAPTER_MORPHEUSLITE 0x09
169#define IPS_ADAPTER_NEO 0x0A
170#define IPS_ADAPTER_NEOLITE 0x0B
171#define IPS_ADAPTER_SARASOTA2 0x0C
172#define IPS_ADAPTER_SARASOTA1 0x0D
173#define IPS_ADAPTER_MARCO 0x0E
174#define IPS_ADAPTER_SEBRING 0x0F
175#define IPS_ADAPTER_MAX_T IPS_ADAPTER_SEBRING
176
177/* values for ffdc_settime (from gmtime) */
178#define IPS_SECSPERMIN 60
179#define IPS_MINSPERHOUR 60
180#define IPS_HOURSPERDAY 24
181#define IPS_DAYSPERWEEK 7
182#define IPS_DAYSPERNYEAR 365
183#define IPS_DAYSPERLYEAR 366
184#define IPS_SECSPERHOUR (IPS_SECSPERMIN * IPS_MINSPERHOUR)
185#define IPS_SECSPERDAY ((long) IPS_SECSPERHOUR * IPS_HOURSPERDAY)
186#define IPS_MONSPERYEAR 12
187#define IPS_EPOCH_YEAR 1970
188#define IPS_LEAPS_THRU_END_OF(y) ((y) / 4 - (y) / 100 + (y) / 400)
189#define ips_isleap(y) (((y) % 4) == 0 && (((y) % 100) != 0 || ((y) % 400) == 0))
190
191/*
192 * IPS STRUCTS
193 */
194
195typedef struct{
196 u_int8_t command;
197 u_int8_t id;
198 u_int8_t drivenum;
199 u_int8_t reserve2;
200 u_int32_t lba;
201 u_int32_t buffaddr;
202 u_int32_t reserve3;
203} __attribute__ ((packed)) ips_generic_cmd;
204
205typedef struct{
206 u_int8_t command;
207 u_int8_t id;
208 u_int8_t drivenum;
209 u_int8_t segnum;
210 u_int32_t lba;
211 u_int32_t buffaddr;
212 u_int16_t length;
213 u_int16_t reserve1;
214} __attribute__ ((packed)) ips_io_cmd;
215
216typedef struct{
217 u_int8_t command;
218 u_int8_t id;
219 u_int8_t pagenum;
220 u_int8_t rw;
221 u_int32_t reserve1;
222 u_int32_t buffaddr;
223 u_int32_t reserve3;
224} __attribute__ ((packed)) ips_rw_nvram_cmd;
225
226typedef struct{
227 u_int8_t command;
228 u_int8_t id;
229 u_int8_t drivenum;
230 u_int8_t reserve1;
231 u_int32_t reserve2;
232 u_int32_t buffaddr;
233 u_int32_t reserve3;
234} __attribute__ ((packed)) ips_drive_cmd;
235
236typedef struct{
237 u_int8_t command;
238 u_int8_t id;
239 u_int8_t reserve1;
240 u_int8_t commandtype;
241 u_int32_t reserve2;
242 u_int32_t buffaddr;
243 u_int32_t reserve3;
244} __attribute__((packed)) ips_adapter_info_cmd;
245
246typedef struct{
247 u_int8_t command;
248 u_int8_t id;
249 u_int8_t reset_count;
250 u_int8_t reset_type;
251 u_int8_t second;
252 u_int8_t minute;
253 u_int8_t hour;
254 u_int8_t day;
255 u_int8_t reserve1[4];
256 u_int8_t month;
257 u_int8_t yearH;
258 u_int8_t yearL;
259 u_int8_t reserve2;
260} __attribute__((packed)) ips_adapter_ffdc_cmd;
261
262typedef union{
263 ips_generic_cmd generic_cmd;
264 ips_drive_cmd drive_cmd;
265 ips_adapter_info_cmd adapter_info_cmd;
266} ips_cmd_buff_t;
267
268typedef struct {
269 u_int32_t signature;
270 u_int8_t reserved;
271 u_int8_t adapter_slot;
272 u_int16_t adapter_type;
273 u_int8_t bios_high[4];
274 u_int8_t bios_low[4];
275 u_int16_t reserve2;
276 u_int8_t reserve3;
277 u_int8_t operating_system;
278 u_int8_t driver_high[4];
279 u_int8_t driver_low[4];
280 u_int8_t reserve4[100];
281}__attribute__((packed)) ips_nvram_page5;
282
283typedef struct{
284 u_int32_t addr;
285 u_int32_t len;
286} ips_sg_element_t;
287
288typedef struct{
289 u_int8_t drivenum;
290 u_int8_t merge_id;
291 u_int8_t raid_lvl;
292 u_int8_t state;
293 u_int32_t sector_count;
294} __attribute__((packed)) ips_drive_t;
295
296typedef struct{
297 u_int8_t drivecount;
298 u_int8_t reserve1;
299 u_int16_t reserve2;
300 ips_drive_t drives[IPS_MAX_NUM_DRIVES];
301}__attribute__((packed)) ips_drive_info_t;
302
303typedef struct{
304 u_int8_t drivecount;
305 u_int8_t miscflags;
306 u_int8_t SLTflags;
307 u_int8_t BSTflags;
308 u_int8_t pwr_chg_count;
309 u_int8_t wrong_addr_count;
310 u_int8_t unident_count;
311 u_int8_t nvram_dev_chg_count;
312 u_int8_t codeblock_version[8];
313 u_int8_t bootblock_version[8];
314 u_int32_t drive_sector_count[IPS_MAX_NUM_DRIVES];
315 u_int8_t max_concurrent_cmds;
316 u_int8_t max_phys_devices;
317 u_int16_t flash_prog_count;
318 u_int8_t defunct_disks;
319 u_int8_t rebuildflags;
320 u_int8_t offline_drivecount;
321 u_int8_t critical_drivecount;
322 u_int16_t config_update_count;
323 u_int8_t blockedflags;
324 u_int8_t psdn_error;
| 129#define IPS_SUBSYS_PARAM_CMD 0x40
130#define IPS_CONFIG_SYNC_CMD 0x58
131#define IPS_SG_READ_CMD 0x82
132#define IPS_SG_WRITE_CMD 0x83
133#define IPS_RW_NVRAM_CMD 0xBC
134#define IPS_FFDC_CMD 0xD7
135
136/* basic_status information returned by the adapter */
137#define IPS_MIN_ERROR 0x02
138#define IPS_BASIC_STATUS_MASK 0xFF
139#define IPS_GSC_STATUS_MASK 0x0F
140#define IPS_CMD_SUCCESS 0x00
141#define IPS_CMD_RECOVERED_ERROR 0x01
142#define IPS_DRV_ERROR 0x02 /* Driver supplied error */
143#define IPS_INVAL_OPCO 0x03
144#define IPS_INVAL_CMD_BLK 0x04
145#define IPS_INVAL_PARM_BLK 0x05
146#define IPS_BUSY 0x08
147#define IPS_CMD_CMPLT_WERROR 0x0C
148#define IPS_LD_ERROR 0x0D
149#define IPS_CMD_TIMEOUT 0x0E
150#define IPS_PHYS_DRV_ERROR 0x0F
151
152/* extended_status information returned by the adapter */
153#define IPS_ERR_SEL_TO 0xF0
154#define IPS_ERR_OU_RUN 0xF2
155#define IPS_ERR_HOST_RESET 0xF7
156#define IPS_ERR_DEV_RESET 0xF8
157#define IPS_ERR_RECOVERY 0xFC
158#define IPS_ERR_CKCOND 0xFF
159
160#define IPS_OS_FREEBSD 8
161#define IPS_VERSION_MAJOR "0.90"
162#define IPS_VERSION_MINOR ".10"
163
164/* Adapter Types */
165#define IPS_ADAPTER_COPPERHEAD 0x01
166#define IPS_ADAPTER_COPPERHEAD2 0x02
167#define IPS_ADAPTER_COPPERHEADOB1 0x03
168#define IPS_ADAPTER_COPPERHEADOB2 0x04
169#define IPS_ADAPTER_CLARINET 0x05
170#define IPS_ADAPTER_CLARINETLITE 0x06
171#define IPS_ADAPTER_TROMBONE 0x07
172#define IPS_ADAPTER_MORPHEUS 0x08
173#define IPS_ADAPTER_MORPHEUSLITE 0x09
174#define IPS_ADAPTER_NEO 0x0A
175#define IPS_ADAPTER_NEOLITE 0x0B
176#define IPS_ADAPTER_SARASOTA2 0x0C
177#define IPS_ADAPTER_SARASOTA1 0x0D
178#define IPS_ADAPTER_MARCO 0x0E
179#define IPS_ADAPTER_SEBRING 0x0F
180#define IPS_ADAPTER_MAX_T IPS_ADAPTER_SEBRING
181
182/* values for ffdc_settime (from gmtime) */
183#define IPS_SECSPERMIN 60
184#define IPS_MINSPERHOUR 60
185#define IPS_HOURSPERDAY 24
186#define IPS_DAYSPERWEEK 7
187#define IPS_DAYSPERNYEAR 365
188#define IPS_DAYSPERLYEAR 366
189#define IPS_SECSPERHOUR (IPS_SECSPERMIN * IPS_MINSPERHOUR)
190#define IPS_SECSPERDAY ((long) IPS_SECSPERHOUR * IPS_HOURSPERDAY)
191#define IPS_MONSPERYEAR 12
192#define IPS_EPOCH_YEAR 1970
193#define IPS_LEAPS_THRU_END_OF(y) ((y) / 4 - (y) / 100 + (y) / 400)
194#define ips_isleap(y) (((y) % 4) == 0 && (((y) % 100) != 0 || ((y) % 400) == 0))
195
196/*
197 * IPS STRUCTS
198 */
199
200typedef struct{
201 u_int8_t command;
202 u_int8_t id;
203 u_int8_t drivenum;
204 u_int8_t reserve2;
205 u_int32_t lba;
206 u_int32_t buffaddr;
207 u_int32_t reserve3;
208} __attribute__ ((packed)) ips_generic_cmd;
209
210typedef struct{
211 u_int8_t command;
212 u_int8_t id;
213 u_int8_t drivenum;
214 u_int8_t segnum;
215 u_int32_t lba;
216 u_int32_t buffaddr;
217 u_int16_t length;
218 u_int16_t reserve1;
219} __attribute__ ((packed)) ips_io_cmd;
220
221typedef struct{
222 u_int8_t command;
223 u_int8_t id;
224 u_int8_t pagenum;
225 u_int8_t rw;
226 u_int32_t reserve1;
227 u_int32_t buffaddr;
228 u_int32_t reserve3;
229} __attribute__ ((packed)) ips_rw_nvram_cmd;
230
231typedef struct{
232 u_int8_t command;
233 u_int8_t id;
234 u_int8_t drivenum;
235 u_int8_t reserve1;
236 u_int32_t reserve2;
237 u_int32_t buffaddr;
238 u_int32_t reserve3;
239} __attribute__ ((packed)) ips_drive_cmd;
240
241typedef struct{
242 u_int8_t command;
243 u_int8_t id;
244 u_int8_t reserve1;
245 u_int8_t commandtype;
246 u_int32_t reserve2;
247 u_int32_t buffaddr;
248 u_int32_t reserve3;
249} __attribute__((packed)) ips_adapter_info_cmd;
250
251typedef struct{
252 u_int8_t command;
253 u_int8_t id;
254 u_int8_t reset_count;
255 u_int8_t reset_type;
256 u_int8_t second;
257 u_int8_t minute;
258 u_int8_t hour;
259 u_int8_t day;
260 u_int8_t reserve1[4];
261 u_int8_t month;
262 u_int8_t yearH;
263 u_int8_t yearL;
264 u_int8_t reserve2;
265} __attribute__((packed)) ips_adapter_ffdc_cmd;
266
267typedef union{
268 ips_generic_cmd generic_cmd;
269 ips_drive_cmd drive_cmd;
270 ips_adapter_info_cmd adapter_info_cmd;
271} ips_cmd_buff_t;
272
273typedef struct {
274 u_int32_t signature;
275 u_int8_t reserved;
276 u_int8_t adapter_slot;
277 u_int16_t adapter_type;
278 u_int8_t bios_high[4];
279 u_int8_t bios_low[4];
280 u_int16_t reserve2;
281 u_int8_t reserve3;
282 u_int8_t operating_system;
283 u_int8_t driver_high[4];
284 u_int8_t driver_low[4];
285 u_int8_t reserve4[100];
286}__attribute__((packed)) ips_nvram_page5;
287
288typedef struct{
289 u_int32_t addr;
290 u_int32_t len;
291} ips_sg_element_t;
292
293typedef struct{
294 u_int8_t drivenum;
295 u_int8_t merge_id;
296 u_int8_t raid_lvl;
297 u_int8_t state;
298 u_int32_t sector_count;
299} __attribute__((packed)) ips_drive_t;
300
301typedef struct{
302 u_int8_t drivecount;
303 u_int8_t reserve1;
304 u_int16_t reserve2;
305 ips_drive_t drives[IPS_MAX_NUM_DRIVES];
306}__attribute__((packed)) ips_drive_info_t;
307
308typedef struct{
309 u_int8_t drivecount;
310 u_int8_t miscflags;
311 u_int8_t SLTflags;
312 u_int8_t BSTflags;
313 u_int8_t pwr_chg_count;
314 u_int8_t wrong_addr_count;
315 u_int8_t unident_count;
316 u_int8_t nvram_dev_chg_count;
317 u_int8_t codeblock_version[8];
318 u_int8_t bootblock_version[8];
319 u_int32_t drive_sector_count[IPS_MAX_NUM_DRIVES];
320 u_int8_t max_concurrent_cmds;
321 u_int8_t max_phys_devices;
322 u_int16_t flash_prog_count;
323 u_int8_t defunct_disks;
324 u_int8_t rebuildflags;
325 u_int8_t offline_drivecount;
326 u_int8_t critical_drivecount;
327 u_int16_t config_update_count;
328 u_int8_t blockedflags;
329 u_int8_t psdn_error;
|
325 u_int16_t addr_dead_disk[4*16];/* ugly, max # channels * max # scsi devices per channel */
| 330 u_int16_t addr_dead_disk[IPS_MAX_CHANNELS][IPS_MAX_TARGETS];
|
326}__attribute__((packed)) ips_adapter_info_t;
327
| 331}__attribute__((packed)) ips_adapter_info_t;
332
|
| 333typedef struct {
334 u_int8_t initiator;
335 u_int8_t parameters;
336 u_int8_t miscflag;
337 u_int8_t state;
338 u_int32_t blkcount;
339 u_int8_t deviceid[28];
340} __attribute__((packed)) ips_devstate_t;
341
342/*
343 * The states that a physical drive can be in. The 'present' value can be
344 * OR'd with the other values.
345 */
346#define IPS_DEVSTATE_PRESENT 0x81
347#define IPS_DEVSTATE_REBUILD 0x02
348#define IPS_DEVSTATE_SPARE 0x04
349#define IPS_DEVSTATE_MEMBER 0x08
350
351typedef struct {
352 u_int8_t channel;
353 u_int8_t target;
354 u_int16_t reserved;
355 u_int32_t startsectors;
356 u_int32_t numsectors;
357} __attribute__((packed)) ips_chunk_t;
358
359typedef struct {
360 u_int16_t userfield;
361 u_int8_t state;
362 u_int8_t raidcacheparam;
363 u_int8_t numchunkunits;
364 u_int8_t stripesize;
365 u_int8_t params;
366 u_int8_t reserved;
367 u_int32_t ldsize;
368 ips_chunk_t chunk[IPS_MAX_CHUNKS];
369} __attribute__((packed)) ips_ld_t;
370
371typedef struct {
372 u_int8_t boarddisc[8];
373 u_int8_t processor[8];
374 u_int8_t numchantype;
375 u_int8_t numhostinttype;
376 u_int8_t compression;
377 u_int8_t nvramtype;
378 u_int32_t nvramsize;
379} __attribute__((packed)) ips_hardware_t;
380
381typedef struct {
382 u_int8_t ldcount;
383 u_int8_t day;
384 u_int8_t month;
385 u_int8_t year;
386 u_int8_t initiatorid[4];
387 u_int8_t hostid[12];
388 u_int8_t timesign[8];
389 u_int32_t useropt;
390 u_int16_t userfield;
391 u_int8_t rebuildrate;
392 u_int8_t reserve;
393 ips_hardware_t hardwaredisc;
394 ips_ld_t ld[IPS_MAX_LD];
395 ips_devstate_t dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
396 u_int8_t reserved[512];
397} __attribute__((packed)) ips_conf_t;
398
|
328typedef union {
329 struct {
330 u_int8_t reserved;
331 u_int8_t command_id;
332 u_int8_t basic_status;
333 u_int8_t extended_status;
334 } fields;
335 volatile u_int32_t value;
336} ips_cmd_status_t;
337
| 399typedef union {
400 struct {
401 u_int8_t reserved;
402 u_int8_t command_id;
403 u_int8_t basic_status;
404 u_int8_t extended_status;
405 } fields;
406 volatile u_int32_t value;
407} ips_cmd_status_t;
408
|