| ns16550.h (5) | ns16550.h (619) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 16 unchanged lines hidden (view full) --- 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 16 unchanged lines hidden (view full) --- 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * |
| 33 * @(#)ns16550.h 7.1 (Berkeley) 5/9/91 | 33 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 34 * $Id$ |
| 34 */ 35 36/* 37 * NS16550 UART registers 38 */ 39 40#define com_data 0 /* data register (R/W) */ 41#define com_dlbl 0 /* divisor latch low (W) */ 42#define com_dlbh 1 /* divisor latch high (W) */ 43#define com_ier 1 /* interrupt enable (W) */ 44#define com_iir 2 /* interrupt identification (R) */ 45#define com_fifo 2 /* FIFO control (W) */ 46#define com_lctl 3 /* line control register (R/W) */ 47#define com_cfcr 3 /* line control register (R/W) */ 48#define com_mcr 4 /* modem control register (R/W) */ 49#define com_lsr 5 /* line status register (R/W) */ 50#define com_msr 6 /* modem status register (R/W) */ | 35 */ 36 37/* 38 * NS16550 UART registers 39 */ 40 41#define com_data 0 /* data register (R/W) */ 42#define com_dlbl 0 /* divisor latch low (W) */ 43#define com_dlbh 1 /* divisor latch high (W) */ 44#define com_ier 1 /* interrupt enable (W) */ 45#define com_iir 2 /* interrupt identification (R) */ 46#define com_fifo 2 /* FIFO control (W) */ 47#define com_lctl 3 /* line control register (R/W) */ 48#define com_cfcr 3 /* line control register (R/W) */ 49#define com_mcr 4 /* modem control register (R/W) */ 50#define com_lsr 5 /* line status register (R/W) */ 51#define com_msr 6 /* modem status register (R/W) */ |