| ns16550.h (194600) | ns16550.h (202062) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 13 unchanged lines hidden (view full) --- 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 13 unchanged lines hidden (view full) --- 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 |
| 30 * $FreeBSD: head/sys/dev/ic/ns16550.h 194600 2009-06-21 19:17:22Z sam $ | 30 * $FreeBSD: head/sys/dev/ic/ns16550.h 202062 2010-01-11 04:13:06Z imp $ |
| 31 */ 32 33/* 34 * NS8250... UART registers. 35 */ 36 37/* 8250 registers #[0-6]. */ 38 --- 8 unchanged lines hidden (view full) --- 47#define IER_EMSC 0x8 48 49#define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC" 50 51#define com_iir 2 /* interrupt identification register (R) */ 52#define REG_IIR com_iir 53#define IIR_IMASK 0xf 54#define IIR_RXTOUT 0xc | 31 */ 32 33/* 34 * NS8250... UART registers. 35 */ 36 37/* 8250 registers #[0-6]. */ 38 --- 8 unchanged lines hidden (view full) --- 47#define IER_EMSC 0x8 48 49#define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC" 50 51#define com_iir 2 /* interrupt identification register (R) */ 52#define REG_IIR com_iir 53#define IIR_IMASK 0xf 54#define IIR_RXTOUT 0xc |
| 55#define IIR_BUSY 0x7 |
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| 55#define IIR_RLS 0x6 56#define IIR_RXRDY 0x4 57#define IIR_TXRDY 0x2 58#define IIR_NOPEND 0x1 59#define IIR_MLSC 0x0 60#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 61 62#define IIR_BITS "\20\1NOPEND\2TXRDY\3RXRDY" --- 113 unchanged lines hidden (view full) --- 176#define EFR_AUTORTS EFR_RTS 177#define EFR_EFE 0x10 /* enhanced functions enable */ 178 179#define com_xon1 4 /* XON 1 character (R/W) */ 180#define com_xon2 5 /* XON 2 character (R/W) */ 181#define com_xoff1 6 /* XOFF 1 character (R/W) */ 182#define com_xoff2 7 /* XOFF 2 character (R/W) */ 183 | 56#define IIR_RLS 0x6 57#define IIR_RXRDY 0x4 58#define IIR_TXRDY 0x2 59#define IIR_NOPEND 0x1 60#define IIR_MLSC 0x0 61#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 62 63#define IIR_BITS "\20\1NOPEND\2TXRDY\3RXRDY" --- 113 unchanged lines hidden (view full) --- 177#define EFR_AUTORTS EFR_RTS 178#define EFR_EFE 0x10 /* enhanced functions enable */ 179 180#define com_xon1 4 /* XON 1 character (R/W) */ 181#define com_xon2 5 /* XON 2 character (R/W) */ 182#define com_xoff1 6 /* XOFF 1 character (R/W) */ 183#define com_xoff2 7 /* XOFF 2 character (R/W) */ 184 |
| 185#define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */ 186#define REG_USR com_usr 187#define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */ 188 |
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| 184/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 185#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 186 187/* 16950 register #3. R/W access enabled by ACR[7]. */ 188#define com_rfl 3 /* receiver fifo level (R) */ 189 190/* 191 * 16950 register #4. Access enabled by ACR[7]. Also requires --- 42 unchanged lines hidden --- | 189/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 190#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 191 192/* 16950 register #3. R/W access enabled by ACR[7]. */ 193#define com_rfl 3 /* receiver fifo level (R) */ 194 195/* 196 * 16950 register #4. Access enabled by ACR[7]. Also requires --- 42 unchanged lines hidden --- |