| ns16550.h (182442) | ns16550.h (194600) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 13 unchanged lines hidden (view full) --- 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 13 unchanged lines hidden (view full) --- 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 |
| 30 * $FreeBSD: head/sys/dev/ic/ns16550.h 182442 2008-08-29 12:25:58Z nyan $ | 30 * $FreeBSD: head/sys/dev/ic/ns16550.h 194600 2009-06-21 19:17:22Z sam $ |
| 31 */ 32 33/* 34 * NS8250... UART registers. 35 */ 36 37/* 8250 registers #[0-6]. */ 38 39#define com_data 0 /* data register (R/W) */ 40#define REG_DATA com_data 41 42#define com_ier 1 /* interrupt enable register (W) */ 43#define REG_IER com_ier 44#define IER_ERXRDY 0x1 45#define IER_ETXRDY 0x2 46#define IER_ERLS 0x4 47#define IER_EMSC 0x8 48 | 31 */ 32 33/* 34 * NS8250... UART registers. 35 */ 36 37/* 8250 registers #[0-6]. */ 38 39#define com_data 0 /* data register (R/W) */ 40#define REG_DATA com_data 41 42#define com_ier 1 /* interrupt enable register (W) */ 43#define REG_IER com_ier 44#define IER_ERXRDY 0x1 45#define IER_ETXRDY 0x2 46#define IER_ERLS 0x4 47#define IER_EMSC 0x8 48 |
| 49#define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC" 50 |
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| 49#define com_iir 2 /* interrupt identification register (R) */ 50#define REG_IIR com_iir 51#define IIR_IMASK 0xf 52#define IIR_RXTOUT 0xc 53#define IIR_RLS 0x6 54#define IIR_RXRDY 0x4 55#define IIR_TXRDY 0x2 56#define IIR_NOPEND 0x1 57#define IIR_MLSC 0x0 58#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 59 | 51#define com_iir 2 /* interrupt identification register (R) */ 52#define REG_IIR com_iir 53#define IIR_IMASK 0xf 54#define IIR_RXTOUT 0xc 55#define IIR_RLS 0x6 56#define IIR_RXRDY 0x4 57#define IIR_TXRDY 0x2 58#define IIR_NOPEND 0x1 59#define IIR_MLSC 0x0 60#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 61 |
| 62#define IIR_BITS "\20\1NOPEND\2TXRDY\3RXRDY" 63 |
|
| 60#define com_lcr 3 /* line control register (R/W) */ 61#define com_cfcr com_lcr /* character format control register (R/W) */ 62#define REG_LCR com_lcr 63#define LCR_DLAB 0x80 64#define CFCR_DLAB LCR_DLAB 65#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 66#define CFCR_EFR_ENABLE LCR_EFR_ENABLE 67#define LCR_SBREAK 0x40 --- 24 unchanged lines hidden (view full) --- 92#define MCR_PRESCALE 0x80 /* only available on 16650 up */ 93#define MCR_LOOPBACK 0x10 94#define MCR_IE 0x08 95#define MCR_IENABLE MCR_IE 96#define MCR_DRS 0x04 97#define MCR_RTS 0x02 98#define MCR_DTR 0x01 99 | 64#define com_lcr 3 /* line control register (R/W) */ 65#define com_cfcr com_lcr /* character format control register (R/W) */ 66#define REG_LCR com_lcr 67#define LCR_DLAB 0x80 68#define CFCR_DLAB LCR_DLAB 69#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 70#define CFCR_EFR_ENABLE LCR_EFR_ENABLE 71#define LCR_SBREAK 0x40 --- 24 unchanged lines hidden (view full) --- 96#define MCR_PRESCALE 0x80 /* only available on 16650 up */ 97#define MCR_LOOPBACK 0x10 98#define MCR_IE 0x08 99#define MCR_IENABLE MCR_IE 100#define MCR_DRS 0x04 101#define MCR_RTS 0x02 102#define MCR_DTR 0x01 103 |
| 104#define MCR_BITS "\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE" 105 |
|
| 100#define com_lsr 5 /* line status register (R/W) */ 101#define REG_LSR com_lsr 102#define LSR_RCV_FIFO 0x80 103#define LSR_TEMT 0x40 104#define LSR_TSRE LSR_TEMT 105#define LSR_THRE 0x20 106#define LSR_TXRDY LSR_THRE 107#define LSR_BI 0x10 108#define LSR_FE 0x08 109#define LSR_PE 0x04 110#define LSR_OE 0x02 111#define LSR_RXRDY 0x01 112#define LSR_RCV_MASK 0x1f 113 | 106#define com_lsr 5 /* line status register (R/W) */ 107#define REG_LSR com_lsr 108#define LSR_RCV_FIFO 0x80 109#define LSR_TEMT 0x40 110#define LSR_TSRE LSR_TEMT 111#define LSR_THRE 0x20 112#define LSR_TXRDY LSR_THRE 113#define LSR_BI 0x10 114#define LSR_FE 0x08 115#define LSR_PE 0x04 116#define LSR_OE 0x02 117#define LSR_RXRDY 0x01 118#define LSR_RCV_MASK 0x1f 119 |
| 120#define LSR_BITS "\20\1RXRDY\2OE\3PE\4FE\5BI\6THRE\7TEMT\10RCV_FIFO" 121 |
|
| 114#define com_msr 6 /* modem status register (R/W) */ 115#define REG_MSR com_msr 116#define MSR_DCD 0x80 117#define MSR_RI 0x40 118#define MSR_DSR 0x20 119#define MSR_CTS 0x10 120#define MSR_DDCD 0x08 121#define MSR_TERI 0x04 122#define MSR_DDSR 0x02 123#define MSR_DCTS 0x01 124 | 122#define com_msr 6 /* modem status register (R/W) */ 123#define REG_MSR com_msr 124#define MSR_DCD 0x80 125#define MSR_RI 0x40 126#define MSR_DSR 0x20 127#define MSR_CTS 0x10 128#define MSR_DDCD 0x08 129#define MSR_TERI 0x04 130#define MSR_DDSR 0x02 131#define MSR_DCTS 0x01 132 |
| 133#define MSR_BITS "\20\1DCTS\2DDSR\3TERI\4DDCD\5CTS\6DSR\7RI\10DCD" 134 |
|
| 125/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 126#define com_dll 0 /* divisor latch low (R/W) */ 127#define com_dlbl com_dll 128#define com_dlm 1 /* divisor latch high (R/W) */ 129#define com_dlbh com_dlm 130#define REG_DLL com_dll 131#define REG_DLH com_dlm 132 --- 16 unchanged lines hidden (view full) --- 149#define FIFO_RX_LOW FCR_RX_LOW 150#define FCR_RX_MEDL 0x40 151#define FIFO_RX_MEDL FCR_RX_MEDL 152#define FCR_RX_MEDH 0x80 153#define FIFO_RX_MEDH FCR_RX_MEDH 154#define FCR_RX_HIGH 0xc0 155#define FIFO_RX_HIGH FCR_RX_HIGH 156 | 135/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 136#define com_dll 0 /* divisor latch low (R/W) */ 137#define com_dlbl com_dll 138#define com_dlm 1 /* divisor latch high (R/W) */ 139#define com_dlbh com_dlm 140#define REG_DLL com_dll 141#define REG_DLH com_dlm 142 --- 16 unchanged lines hidden (view full) --- 159#define FIFO_RX_LOW FCR_RX_LOW 160#define FCR_RX_MEDL 0x40 161#define FIFO_RX_MEDL FCR_RX_MEDL 162#define FCR_RX_MEDH 0x80 163#define FIFO_RX_MEDH FCR_RX_MEDH 164#define FCR_RX_HIGH 0xc0 165#define FIFO_RX_HIGH FCR_RX_HIGH 166 |
| 167#define FCR_BITS "\20\1ENABLE\2RCV_RST\3XMT_RST\4DMA" 168 |
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| 157/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 158 159#define com_efr 2 /* enhanced features register (R/W) */ 160#define REG_EFR com_efr 161#define EFR_CTS 0x80 162#define EFR_AUTOCTS EFR_CTS 163#define EFR_RTS 0x40 164#define EFR_AUTORTS EFR_RTS --- 57 unchanged lines hidden --- | 169/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 170 171#define com_efr 2 /* enhanced features register (R/W) */ 172#define REG_EFR com_efr 173#define EFR_CTS 0x80 174#define EFR_AUTOCTS EFR_CTS 175#define EFR_RTS 0x40 176#define EFR_AUTORTS EFR_RTS --- 57 unchanged lines hidden --- |