| ns16550.h (128019) | ns16550.h (137948) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 13 unchanged lines hidden (view full) --- 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 13 unchanged lines hidden (view full) --- 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 |
| 30 * $FreeBSD: head/sys/dev/ic/ns16550.h 128019 2004-04-07 20:46:16Z imp $ | 30 * $FreeBSD: head/sys/dev/ic/ns16550.h 137948 2004-11-20 23:19:42Z marcel $ |
| 31 */ 32 33/* 34 * NS8250... UART registers. 35 */ 36 37/* 8250 registers #[0-6]. */ 38 39#define com_data 0 /* data register (R/W) */ | 31 */ 32 33/* 34 * NS8250... UART registers. 35 */ 36 37/* 8250 registers #[0-6]. */ 38 39#define com_data 0 /* data register (R/W) */ |
| 40#define com_thr com_data /* transmitter holding register (W) */ 41#define com_rhr com_data /* receiver holding register (R) */ | 40#define REG_DATA com_data |
| 42 43#define com_ier 1 /* interrupt enable register (W) */ | 41 42#define com_ier 1 /* interrupt enable register (W) */ |
| 43#define REG_IER com_ier |
|
| 44#define IER_ERXRDY 0x1 45#define IER_ETXRDY 0x2 46#define IER_ERLS 0x4 47#define IER_EMSC 0x8 48 49#define com_iir 2 /* interrupt identification register (R) */ | 44#define IER_ERXRDY 0x1 45#define IER_ETXRDY 0x2 46#define IER_ERLS 0x4 47#define IER_EMSC 0x8 48 49#define com_iir 2 /* interrupt identification register (R) */ |
| 50#define com_isr com_iir /* interrupt status register (R) */ | 50#define REG_IIR com_iir |
| 51#define IIR_IMASK 0xf 52#define IIR_RXTOUT 0xc 53#define IIR_RLS 0x6 54#define IIR_RXRDY 0x4 55#define IIR_TXRDY 0x2 56#define IIR_NOPEND 0x1 57#define IIR_MLSC 0x0 58#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 59 60#define com_lcr 3 /* line control register (R/W) */ | 51#define IIR_IMASK 0xf 52#define IIR_RXTOUT 0xc 53#define IIR_RLS 0x6 54#define IIR_RXRDY 0x4 55#define IIR_TXRDY 0x2 56#define IIR_NOPEND 0x1 57#define IIR_MLSC 0x0 58#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 59 60#define com_lcr 3 /* line control register (R/W) */ |
| 61#define com_lctl com_lcr | |
| 62#define com_cfcr com_lcr /* character format control register (R/W) */ | 61#define com_cfcr com_lcr /* character format control register (R/W) */ |
| 62#define REG_LCR com_lcr |
|
| 63#define LCR_DLAB 0x80 64#define CFCR_DLAB LCR_DLAB 65#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 66#define CFCR_EFR_ENABLE LCR_EFR_ENABLE | 63#define LCR_DLAB 0x80 64#define CFCR_DLAB LCR_DLAB 65#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 66#define CFCR_EFR_ENABLE LCR_EFR_ENABLE |
| 67#define CFCR_SBREAK 0x40 68#define CFCR_PZERO 0x30 69#define CFCR_PONE 0x20 70#define CFCR_PEVEN 0x10 71#define CFCR_PODD 0x00 72#define CFCR_PENAB 0x08 73#define CFCR_STOPB 0x04 74#define CFCR_8BITS 0x03 75#define CFCR_7BITS 0x02 76#define CFCR_6BITS 0x01 77#define CFCR_5BITS 0x00 | 67#define LCR_SBREAK 0x40 68#define CFCR_SBREAK LCR_SBREAK 69#define LCR_PZERO 0x30 70#define CFCR_PZERO LCR_PZERO 71#define LCR_PONE 0x20 72#define CFCR_PONE LCR_PONE 73#define LCR_PEVEN 0x10 74#define CFCR_PEVEN LCR_PEVEN 75#define LCR_PODD 0x00 76#define CFCR_PODD LCR_PODD 77#define LCR_PENAB 0x08 78#define CFCR_PENAB LCR_PENAB 79#define LCR_STOPB 0x04 80#define CFCR_STOPB LCR_STOPB 81#define LCR_8BITS 0x03 82#define CFCR_8BITS LCR_8BITS 83#define LCR_7BITS 0x02 84#define CFCR_7BITS LCR_7BITS 85#define LCR_6BITS 0x01 86#define CFCR_6BITS LCR_6BITS 87#define LCR_5BITS 0x00 88#define CFCR_5BITS LCR_5BITS |
| 78 79#define com_mcr 4 /* modem control register (R/W) */ | 89 90#define com_mcr 4 /* modem control register (R/W) */ |
| 91#define REG_MCR com_mcr |
|
| 80#define MCR_PRESCALE 0x80 /* only available on 16650 up */ 81#define MCR_LOOPBACK 0x10 | 92#define MCR_PRESCALE 0x80 /* only available on 16650 up */ 93#define MCR_LOOPBACK 0x10 |
| 82#define MCR_IENABLE 0x08 | 94#define MCR_IE 0x08 95#define MCR_IENABLE MCR_IE |
| 83#define MCR_DRS 0x04 84#define MCR_RTS 0x02 85#define MCR_DTR 0x01 86 87#define com_lsr 5 /* line status register (R/W) */ | 96#define MCR_DRS 0x04 97#define MCR_RTS 0x02 98#define MCR_DTR 0x01 99 100#define com_lsr 5 /* line status register (R/W) */ |
| 101#define REG_LSR com_lsr |
|
| 88#define LSR_RCV_FIFO 0x80 | 102#define LSR_RCV_FIFO 0x80 |
| 89#define LSR_TSRE 0x40 90#define LSR_TXRDY 0x20 | 103#define LSR_TEMT 0x40 104#define LSR_TSRE LSR_TEMT 105#define LSR_THRE 0x20 106#define LSR_TXRDY LSR_THRE |
| 91#define LSR_BI 0x10 92#define LSR_FE 0x08 93#define LSR_PE 0x04 94#define LSR_OE 0x02 95#define LSR_RXRDY 0x01 96#define LSR_RCV_MASK 0x1f 97 98#define com_msr 6 /* modem status register (R/W) */ | 107#define LSR_BI 0x10 108#define LSR_FE 0x08 109#define LSR_PE 0x04 110#define LSR_OE 0x02 111#define LSR_RXRDY 0x01 112#define LSR_RCV_MASK 0x1f 113 114#define com_msr 6 /* modem status register (R/W) */ |
| 115#define REG_MSR com_msr |
|
| 99#define MSR_DCD 0x80 100#define MSR_RI 0x40 101#define MSR_DSR 0x20 102#define MSR_CTS 0x10 103#define MSR_DDCD 0x08 104#define MSR_TERI 0x04 105#define MSR_DDSR 0x02 106#define MSR_DCTS 0x01 107 108/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 109#define com_dll 0 /* divisor latch low (R/W) */ 110#define com_dlbl com_dll 111#define com_dlm 1 /* divisor latch high (R/W) */ 112#define com_dlbh com_dlm | 116#define MSR_DCD 0x80 117#define MSR_RI 0x40 118#define MSR_DSR 0x20 119#define MSR_CTS 0x10 120#define MSR_DDCD 0x08 121#define MSR_TERI 0x04 122#define MSR_DDSR 0x02 123#define MSR_DCTS 0x01 124 125/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 126#define com_dll 0 /* divisor latch low (R/W) */ 127#define com_dlbl com_dll 128#define com_dlm 1 /* divisor latch high (R/W) */ 129#define com_dlbh com_dlm |
| 130#define REG_DL com_dll |
|
| 113 114/* 16450 register #7. Not multiplexed. */ 115#define com_scr 7 /* scratch register (R/W) */ 116 117/* 16550 register #2. Not multiplexed. */ 118#define com_fcr 2 /* FIFO control register (W) */ 119#define com_fifo com_fcr | 131 132/* 16450 register #7. Not multiplexed. */ 133#define com_scr 7 /* scratch register (R/W) */ 134 135/* 16550 register #2. Not multiplexed. */ 136#define com_fcr 2 /* FIFO control register (W) */ 137#define com_fifo com_fcr |
| 120#define FIFO_ENABLE 0x01 121#define FIFO_RCV_RST 0x02 122#define FIFO_XMT_RST 0x04 123#define FIFO_DMA_MODE 0x08 124#define FIFO_RX_LOW 0x00 125#define FIFO_RX_MEDL 0x40 126#define FIFO_RX_MEDH 0x80 127#define FIFO_RX_HIGH 0xc0 | 138#define REG_FCR com_fcr 139#define FCR_ENABLE 0x01 140#define FIFO_ENABLE FCR_ENABLE 141#define FCR_RCV_RST 0x02 142#define FIFO_RCV_RST FCR_RCV_RST 143#define FCR_XMT_RST 0x04 144#define FIFO_XMT_RST FCR_XMT_RST 145#define FCR_DMA 0x08 146#define FIFO_DMA_MODE FCR_DMA 147#define FCR_RX_LOW 0x00 148#define FIFO_RX_LOW FCR_RX_LOW 149#define FCR_RX_MEDL 0x40 150#define FIFO_RX_MEDL FCR_RX_MEDL 151#define FCR_RX_MEDH 0x80 152#define FIFO_RX_MEDH FCR_RX_MEDH 153#define FCR_RX_HIGH 0xc0 154#define FIFO_RX_HIGH FCR_RX_HIGH |
| 128 129/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 130 131#define com_efr 2 /* enhanced features register (R/W) */ | 155 156/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 157 158#define com_efr 2 /* enhanced features register (R/W) */ |
| 132#define EFR_AUTOCTS 0x80 133#define EFR_AUTORTS 0x40 | 159#define REG_EFR com_efr 160#define EFR_CTS 0x80 161#define EFR_AUTOCTS EFR_CTS 162#define EFR_RTS 0x40 163#define EFR_AUTORTS EFR_RTS |
| 134#define EFR_EFE 0x10 /* enhanced functions enable */ 135 136#define com_xon1 4 /* XON 1 character (R/W) */ 137#define com_xon2 5 /* XON 2 character (R/W) */ 138#define com_xoff1 6 /* XOFF 1 character (R/W) */ 139#define com_xoff2 7 /* XOFF 2 character (R/W) */ 140 141/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ --- 15 unchanged lines hidden (view full) --- 157#define com_icr 5 /* index control register (R/W) */ 158 159/* 160 * 16950 register #7. It is the same as com_scr except it has a different 161 * abbreviation in the manufacturer's data sheet and it also serves as an 162 * index into the Indexed Control register set. 163 */ 164#define com_spr com_scr /* scratch pad (and index) register (R/W) */ | 164#define EFR_EFE 0x10 /* enhanced functions enable */ 165 166#define com_xon1 4 /* XON 1 character (R/W) */ 167#define com_xon2 5 /* XON 2 character (R/W) */ 168#define com_xoff1 6 /* XOFF 1 character (R/W) */ 169#define com_xoff2 7 /* XOFF 2 character (R/W) */ 170 171/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ --- 15 unchanged lines hidden (view full) --- 187#define com_icr 5 /* index control register (R/W) */ 188 189/* 190 * 16950 register #7. It is the same as com_scr except it has a different 191 * abbreviation in the manufacturer's data sheet and it also serves as an 192 * index into the Indexed Control register set. 193 */ 194#define com_spr com_scr /* scratch pad (and index) register (R/W) */ |
| 195#define REG_SPR com_scr |
|
| 165 166/* 167 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 168 * data in ICR (if ICR is accessible). 169 */ 170 171#define com_acr 0 /* additional control register (R/W) */ 172#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ --- 19 unchanged lines hidden --- | 196 197/* 198 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 199 * data in ICR (if ICR is accessible). 200 */ 201 202#define com_acr 0 /* additional control register (R/W) */ 203#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ --- 19 unchanged lines hidden --- |