| ns16550.h (120123) | ns16550.h (120124) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 |
| 34 * $FreeBSD: head/sys/dev/ic/ns16550.h 120123 2003-09-16 14:08:54Z bde $ | 34 * $FreeBSD: head/sys/dev/ic/ns16550.h 120124 2003-09-16 14:21:17Z bde $ |
| 35 */ 36 37/* 38 * NS8250... UART registers. 39 */ 40 41/* 8250 registers #[0-6]. */ 42 --- 94 unchanged lines hidden (view full) --- 137#define EFR_AUTORTS 0x40 138#define EFR_EFE 0x10 /* enhanced functions enable */ 139 140#define com_xon1 4 /* XON 1 character (R/W) */ 141#define com_xon2 5 /* XON 2 character (R/W) */ 142#define com_xoff1 6 /* XOFF 1 character (R/W) */ 143#define com_xoff2 7 /* XOFF 2 character (R/W) */ 144 | 35 */ 36 37/* 38 * NS8250... UART registers. 39 */ 40 41/* 8250 registers #[0-6]. */ 42 --- 94 unchanged lines hidden (view full) --- 137#define EFR_AUTORTS 0x40 138#define EFR_EFE 0x10 /* enhanced functions enable */ 139 140#define com_xon1 4 /* XON 1 character (R/W) */ 141#define com_xon2 5 /* XON 2 character (R/W) */ 142#define com_xoff1 6 /* XOFF 1 character (R/W) */ 143#define com_xoff2 7 /* XOFF 2 character (R/W) */ 144 |
| 145/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 146#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 147 148/* 16950 register #3. R/W access enabled by ACR[7]. */ 149#define com_rfl 3 /* receiver fifo level (R) */ 150 151/* 152 * 16950 register #4. Access enabled by ACR[7]. Also requires 153 * !LCR_EFR_ENABLE. 154 */ 155#define com_tfl 4 /* transmitter fifo level (R) */ 156 157/* 158 * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also 159 * requires ACR[6]. 160 */ 161#define com_icr 5 /* index control register (R/W) */ 162 163/* 164 * 16950 register #7. It is the same as com_scr except it has a different 165 * abbreviation in the manufacturer's data sheet and it also serves as an 166 * index into the Indexed Control register set. 167 */ 168#define com_spr com_scr /* scratch pad (and index) register (R/W) */ 169 170/* 171 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 172 * data in ICR (if ICR is accessible). 173 */ 174 175#define com_acr 0 /* additional control register (R/W) */ 176#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ 177#define ACR_ICRE 0x40 /* ICR enable */ 178#define ACR_TLE 0x20 /* TTL/RTL enable */ 179 180#define com_cpr 1 /* clock prescaler register (R/W) */ 181#define com_tcr 2 /* times clock register (R/W) */ 182#define com_ttl 4 /* transmitter trigger level (R/W) */ 183#define com_rtl 5 /* receiver trigger level (R/W) */ 184/* ... */ 185 |
|
| 145#ifdef PC98 146/* Hardware extension mode register for RSB-2000/3000. */ 147#define com_emr com_msr 148#define EMR_EXBUFF 0x04 149#define EMR_CTSFLW 0x08 150#define EMR_DSRFLW 0x10 151#define EMR_RTSFLW 0x20 152#define EMR_DTRFLW 0x40 153#define EMR_EFMODE 0x80 154#endif | 186#ifdef PC98 187/* Hardware extension mode register for RSB-2000/3000. */ 188#define com_emr com_msr 189#define EMR_EXBUFF 0x04 190#define EMR_CTSFLW 0x08 191#define EMR_DSRFLW 0x10 192#define EMR_RTSFLW 0x20 193#define EMR_DTRFLW 0x40 194#define EMR_EFMODE 0x80 195#endif |