| ns16550.h (120119) | ns16550.h (120122) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 |
| 34 * $FreeBSD: head/sys/dev/ic/ns16550.h 120119 2003-09-16 11:54:29Z bde $ | 34 * $FreeBSD: head/sys/dev/ic/ns16550.h 120122 2003-09-16 13:52:01Z bde $ |
| 35 */ 36 37/* 38 * NS8250... UART registers. 39 */ 40 41/* 8250 registers #[0-6]. */ 42 43#define com_data 0 /* data register (R/W) */ | 35 */ 36 37/* 38 * NS8250... UART registers. 39 */ 40 41/* 8250 registers #[0-6]. */ 42 43#define com_data 0 /* data register (R/W) */ |
| 44#define com_thr com_data /* transmitter holding register (W) */ 45#define com_rhr com_data /* receiver holding register (R) */ |
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| 44 45#define com_ier 1 /* interrupt enable register (W) */ 46#define IER_ERXRDY 0x1 47#define IER_ETXRDY 0x2 48#define IER_ERLS 0x4 49#define IER_EMSC 0x8 50 51#define com_iir 2 /* interrupt identification register (R) */ | 46 47#define com_ier 1 /* interrupt enable register (W) */ 48#define IER_ERXRDY 0x1 49#define IER_ETXRDY 0x2 50#define IER_ERLS 0x4 51#define IER_EMSC 0x8 52 53#define com_iir 2 /* interrupt identification register (R) */ |
| 54#define com_isr com_iir /* interrupt status register (R) */ |
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| 52#define IIR_IMASK 0xf 53#define IIR_RXTOUT 0xc 54#define IIR_RLS 0x6 55#define IIR_RXRDY 0x4 56#define IIR_TXRDY 0x2 57#define IIR_NOPEND 0x1 58#define IIR_MLSC 0x0 59#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 60 | 55#define IIR_IMASK 0xf 56#define IIR_RXTOUT 0xc 57#define IIR_RLS 0x6 58#define IIR_RXRDY 0x4 59#define IIR_TXRDY 0x2 60#define IIR_NOPEND 0x1 61#define IIR_MLSC 0x0 62#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 63 |
| 61#define com_lctl 3 /* line control register (R/W) */ 62#define com_cfcr 3 /* character format control register (R/W) */ 63#define CFCR_DLAB 0x80 | 64#define com_lcr 3 /* line control register (R/W) */ 65#define com_lctl com_lcr 66#define com_cfcr com_lcr /* character format control register (R/W) */ 67#define LCR_DLAB 0x80 68#define CFCR_DLAB LCR_DLAB 69#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 70#define CFCR_EFR_ENABLE LCR_EFR_ENABLE |
| 64#define CFCR_SBREAK 0x40 65#define CFCR_PZERO 0x30 66#define CFCR_PONE 0x20 67#define CFCR_PEVEN 0x10 68#define CFCR_PODD 0x00 69#define CFCR_PENAB 0x08 70#define CFCR_STOPB 0x04 71#define CFCR_8BITS 0x03 72#define CFCR_7BITS 0x02 73#define CFCR_6BITS 0x01 74#define CFCR_5BITS 0x00 | 71#define CFCR_SBREAK 0x40 72#define CFCR_PZERO 0x30 73#define CFCR_PONE 0x20 74#define CFCR_PEVEN 0x10 75#define CFCR_PODD 0x00 76#define CFCR_PENAB 0x08 77#define CFCR_STOPB 0x04 78#define CFCR_8BITS 0x03 79#define CFCR_7BITS 0x02 80#define CFCR_6BITS 0x01 81#define CFCR_5BITS 0x00 |
| 75#define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ | |
| 76 77#define com_mcr 4 /* modem control register (R/W) */ 78#define MCR_PRESCALE 0x80 /* only available on 16650 up */ 79#define MCR_LOOPBACK 0x10 80#define MCR_IENABLE 0x08 81#define MCR_DRS 0x04 82#define MCR_RTS 0x02 83#define MCR_DTR 0x01 --- 15 unchanged lines hidden (view full) --- 99#define MSR_DSR 0x20 100#define MSR_CTS 0x10 101#define MSR_DDCD 0x08 102#define MSR_TERI 0x04 103#define MSR_DDSR 0x02 104#define MSR_DCTS 0x01 105 106/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ | 82 83#define com_mcr 4 /* modem control register (R/W) */ 84#define MCR_PRESCALE 0x80 /* only available on 16650 up */ 85#define MCR_LOOPBACK 0x10 86#define MCR_IENABLE 0x08 87#define MCR_DRS 0x04 88#define MCR_RTS 0x02 89#define MCR_DTR 0x01 --- 15 unchanged lines hidden (view full) --- 105#define MSR_DSR 0x20 106#define MSR_CTS 0x10 107#define MSR_DDCD 0x08 108#define MSR_TERI 0x04 109#define MSR_DDSR 0x02 110#define MSR_DCTS 0x01 111 112/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ |
| 107#define com_dlbl 0 /* divisor latch low (W) */ 108#define com_dlbh 1 /* divisor latch high (W) */ | 113#define com_dll 0 /* divisor latch low (R/W) */ 114#define com_dlbl com_dll 115#define com_dlm 1 /* divisor latch high (R/W) */ 116#define com_dlbh com_dlm |
| 109 110/* 16450 register #7. Not multiplexed. */ 111#define com_scr 7 /* scratch register (R/W) */ 112 113/* 16550 register #2. Not multiplexed. */ | 117 118/* 16450 register #7. Not multiplexed. */ 119#define com_scr 7 /* scratch register (R/W) */ 120 121/* 16550 register #2. Not multiplexed. */ |
| 114#define com_fifo 2 /* FIFO control register (W) */ | 122#define com_fcr 2 /* FIFO control register (W) */ 123#define com_fifo com_fcr |
| 115#define FIFO_ENABLE 0x01 116#define FIFO_RCV_RST 0x02 117#define FIFO_XMT_RST 0x04 118#define FIFO_DMA_MODE 0x08 119#define FIFO_RX_LOW 0x00 120#define FIFO_RX_MEDL 0x40 121#define FIFO_RX_MEDH 0x80 122#define FIFO_RX_HIGH 0xc0 123 124/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 125 | 124#define FIFO_ENABLE 0x01 125#define FIFO_RCV_RST 0x02 126#define FIFO_XMT_RST 0x04 127#define FIFO_DMA_MODE 0x08 128#define FIFO_RX_LOW 0x00 129#define FIFO_RX_MEDL 0x40 130#define FIFO_RX_MEDH 0x80 131#define FIFO_RX_HIGH 0xc0 132 133/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 134 |
| 126#define com_efr com_fifo /* enhanced feature register (R/W) */ | 135#define com_efr 2 /* enhanced features register (R/W) */ |
| 127#define EFR_EFE 0x10 /* enhanced functions enable */ 128 129#ifdef PC98 130/* Hardware extension mode register for RSB-2000/3000. */ 131#define com_emr com_msr 132#define EMR_EXBUFF 0x04 133#define EMR_CTSFLW 0x08 134#define EMR_DSRFLW 0x10 135#define EMR_RTSFLW 0x20 136#define EMR_DTRFLW 0x40 137#define EMR_EFMODE 0x80 138#endif | 136#define EFR_EFE 0x10 /* enhanced functions enable */ 137 138#ifdef PC98 139/* Hardware extension mode register for RSB-2000/3000. */ 140#define com_emr com_msr 141#define EMR_EXBUFF 0x04 142#define EMR_CTSFLW 0x08 143#define EMR_DSRFLW 0x10 144#define EMR_RTSFLW 0x20 145#define EMR_DTRFLW 0x40 146#define EMR_EFMODE 0x80 147#endif |