| ns16550.h (120116) | ns16550.h (120119) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 |
| 34 * $FreeBSD: head/sys/dev/ic/ns16550.h 120116 2003-09-16 08:08:08Z bde $ | 34 * $FreeBSD: head/sys/dev/ic/ns16550.h 120119 2003-09-16 11:54:29Z bde $ |
| 35 */ 36 37/* | 35 */ 36 37/* |
| 38 * NS16550 UART registers | 38 * NS8250... UART registers. |
| 39 */ | 39 */ |
| 40 41/* 8250 registers #[0-6]. */ 42 |
|
| 40#define com_data 0 /* data register (R/W) */ | 43#define com_data 0 /* data register (R/W) */ |
| 41#define com_dlbl 0 /* divisor latch low (W) */ 42#define com_dlbh 1 /* divisor latch high (W) */ 43#define com_ier 1 /* interrupt enable (W) */ 44#define com_iir 2 /* interrupt identification (R) */ 45#define com_fifo 2 /* FIFO control (W) */ 46#define com_lctl 3 /* line control register (R/W) */ 47#define com_cfcr 3 /* line control register (R/W) */ 48#define com_mcr 4 /* modem control register (R/W) */ 49#define com_lsr 5 /* line status register (R/W) */ 50#define com_msr 6 /* modem status register (R/W) */ 51#define com_scr 7 /* scratch register for 16450 up (R/W) */ | |
| 52 | 44 |
| 53/* interrupt enable register */ | 45#define com_ier 1 /* interrupt enable register (W) */ |
| 54#define IER_ERXRDY 0x1 55#define IER_ETXRDY 0x2 56#define IER_ERLS 0x4 57#define IER_EMSC 0x8 58 | 46#define IER_ERXRDY 0x1 47#define IER_ETXRDY 0x2 48#define IER_ERLS 0x4 49#define IER_EMSC 0x8 50 |
| 59/* interrupt identification register */ | 51#define com_iir 2 /* interrupt identification register (R) */ |
| 60#define IIR_IMASK 0xf 61#define IIR_RXTOUT 0xc 62#define IIR_RLS 0x6 63#define IIR_RXRDY 0x4 64#define IIR_TXRDY 0x2 65#define IIR_NOPEND 0x1 66#define IIR_MLSC 0x0 67#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 68 | 52#define IIR_IMASK 0xf 53#define IIR_RXTOUT 0xc 54#define IIR_RLS 0x6 55#define IIR_RXRDY 0x4 56#define IIR_TXRDY 0x2 57#define IIR_NOPEND 0x1 58#define IIR_MLSC 0x0 59#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 60 |
| 69/* fifo control register */ 70#define FIFO_ENABLE 0x01 71#define FIFO_RCV_RST 0x02 72#define FIFO_XMT_RST 0x04 73#define FIFO_DMA_MODE 0x08 74#define FIFO_RX_LOW 0x00 75#define FIFO_RX_MEDL 0x40 76#define FIFO_RX_MEDH 0x80 77#define FIFO_RX_HIGH 0xc0 78 79/* character format control register (aka line control register) */ | 61#define com_lctl 3 /* line control register (R/W) */ 62#define com_cfcr 3 /* character format control register (R/W) */ |
| 80#define CFCR_DLAB 0x80 81#define CFCR_SBREAK 0x40 82#define CFCR_PZERO 0x30 83#define CFCR_PONE 0x20 84#define CFCR_PEVEN 0x10 85#define CFCR_PODD 0x00 86#define CFCR_PENAB 0x08 87#define CFCR_STOPB 0x04 88#define CFCR_8BITS 0x03 89#define CFCR_7BITS 0x02 90#define CFCR_6BITS 0x01 91#define CFCR_5BITS 0x00 | 63#define CFCR_DLAB 0x80 64#define CFCR_SBREAK 0x40 65#define CFCR_PZERO 0x30 66#define CFCR_PONE 0x20 67#define CFCR_PEVEN 0x10 68#define CFCR_PODD 0x00 69#define CFCR_PENAB 0x08 70#define CFCR_STOPB 0x04 71#define CFCR_8BITS 0x03 72#define CFCR_7BITS 0x02 73#define CFCR_6BITS 0x01 74#define CFCR_5BITS 0x00 |
| 92#define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ | 75#define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ |
| 93 | 76 |
| 94/* modem control register */ 95#define MCR_PRESCALE 0x80 /* only available on 16650 up */ | 77#define com_mcr 4 /* modem control register (R/W) */ 78#define MCR_PRESCALE 0x80 /* only available on 16650 up */ |
| 96#define MCR_LOOPBACK 0x10 97#define MCR_IENABLE 0x08 98#define MCR_DRS 0x04 99#define MCR_RTS 0x02 100#define MCR_DTR 0x01 101 | 79#define MCR_LOOPBACK 0x10 80#define MCR_IENABLE 0x08 81#define MCR_DRS 0x04 82#define MCR_RTS 0x02 83#define MCR_DTR 0x01 84 |
| 102/* line status register */ | 85#define com_lsr 5 /* line status register (R/W) */ |
| 103#define LSR_RCV_FIFO 0x80 104#define LSR_TSRE 0x40 105#define LSR_TXRDY 0x20 106#define LSR_BI 0x10 107#define LSR_FE 0x08 108#define LSR_PE 0x04 109#define LSR_OE 0x02 110#define LSR_RXRDY 0x01 111#define LSR_RCV_MASK 0x1f 112 | 86#define LSR_RCV_FIFO 0x80 87#define LSR_TSRE 0x40 88#define LSR_TXRDY 0x20 89#define LSR_BI 0x10 90#define LSR_FE 0x08 91#define LSR_PE 0x04 92#define LSR_OE 0x02 93#define LSR_RXRDY 0x01 94#define LSR_RCV_MASK 0x1f 95 |
| 113/* modem status register */ | 96#define com_msr 6 /* modem status register (R/W) */ |
| 114#define MSR_DCD 0x80 115#define MSR_RI 0x40 116#define MSR_DSR 0x20 117#define MSR_CTS 0x10 118#define MSR_DDCD 0x08 119#define MSR_TERI 0x04 120#define MSR_DDSR 0x02 121#define MSR_DCTS 0x01 122 | 97#define MSR_DCD 0x80 98#define MSR_RI 0x40 99#define MSR_DSR 0x20 100#define MSR_CTS 0x10 101#define MSR_DDCD 0x08 102#define MSR_TERI 0x04 103#define MSR_DDSR 0x02 104#define MSR_DCTS 0x01 105 |
| 123/* enhanced feature register (only available on 16650 up) */ 124#define com_efr com_fifo 125#define EFR_EFE 0x10 /* enhanced functions enable */ | 106/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 107#define com_dlbl 0 /* divisor latch low (W) */ 108#define com_dlbh 1 /* divisor latch high (W) */ |
| 126 | 109 |
| 110/* 16450 register #7. Not multiplexed. */ 111#define com_scr 7 /* scratch register (R/W) */ 112 113/* 16550 register #2. Not multiplexed. */ 114#define com_fifo 2 /* FIFO control register (W) */ 115#define FIFO_ENABLE 0x01 116#define FIFO_RCV_RST 0x02 117#define FIFO_XMT_RST 0x04 118#define FIFO_DMA_MODE 0x08 119#define FIFO_RX_LOW 0x00 120#define FIFO_RX_MEDL 0x40 121#define FIFO_RX_MEDH 0x80 122#define FIFO_RX_HIGH 0xc0 123 124/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 125 126#define com_efr com_fifo /* enhanced feature register (R/W) */ 127#define EFR_EFE 0x10 /* enhanced functions enable */ 128 |
|
| 127#ifdef PC98 128/* Hardware extension mode register for RSB-2000/3000. */ 129#define com_emr com_msr 130#define EMR_EXBUFF 0x04 131#define EMR_CTSFLW 0x08 132#define EMR_DSRFLW 0x10 133#define EMR_RTSFLW 0x20 134#define EMR_DTRFLW 0x40 135#define EMR_EFMODE 0x80 136#endif | 129#ifdef PC98 130/* Hardware extension mode register for RSB-2000/3000. */ 131#define com_emr com_msr 132#define EMR_EXBUFF 0x04 133#define EMR_CTSFLW 0x08 134#define EMR_DSRFLW 0x10 135#define EMR_RTSFLW 0x20 136#define EMR_DTRFLW 0x40 137#define EMR_EFMODE 0x80 138#endif |