1/* 2 * Intel 8237 DMA Controller 3 *
| 1/* 2 * Intel 8237 DMA Controller 3 *
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4 * $FreeBSD: head/sys/dev/ic/i8237.h 50477 1999-08-28 01:08:13Z peter $
| 4 * $FreeBSD: head/sys/dev/ic/i8237.h 141391 2005-02-06 13:46:39Z phk $
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5 */ 6 7#define DMA37MD_SINGLE 0x40 /* single pass mode */ 8#define DMA37MD_CASCADE 0xc0 /* cascade mode */ 9#define DMA37MD_AUTO 0x50 /* autoinitialise single pass mode */ 10#define DMA37MD_WRITE 0x04 /* read the device, write memory operation */ 11#define DMA37MD_READ 0x08 /* write the device, read memory operation */ 12
| 5 */ 6 7#define DMA37MD_SINGLE 0x40 /* single pass mode */ 8#define DMA37MD_CASCADE 0xc0 /* cascade mode */ 9#define DMA37MD_AUTO 0x50 /* autoinitialise single pass mode */ 10#define DMA37MD_WRITE 0x04 /* read the device, write memory operation */ 11#define DMA37MD_READ 0x08 /* write the device, read memory operation */ 12
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| 13#ifndef PC98 14/* 15** Register definitions for DMA controller 1 (channels 0..3): 16*/ 17#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 18#define DMA1_STATUS (IO_DMA1 + 1*8) /* status register */ 19#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 20#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 21#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 22#define DMA1_RESET (IO_DMA1 + 1*13) /* reset */ 23 24/* 25** Register definitions for DMA controller 2 (channels 4..7): 26*/ 27#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 28#define DMA2_STATUS (IO_DMA2 + 2*8) /* status register */ 29#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 30#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 31#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 32#define DMA2_RESET (IO_DMA2 + 2*13) /* reset */ 33#endif 34
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