hwpmc_intel.c (185341) | hwpmc_intel.c (185363) |
---|---|
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Common code for handling Intel CPUs. 29 */ 30 31#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Common code for handling Intel CPUs. 29 */ 30 31#include <sys/cdefs.h> |
32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_intel.c 185341 2008-11-26 19:25:13Z jkim $"); | 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_intel.c 185363 2008-11-27 09:00:47Z jkoshy $"); |
33 34#include <sys/param.h> 35#include <sys/pmc.h> 36#include <sys/pmckern.h> 37#include <sys/systm.h> 38 39#include <machine/cpu.h> 40#include <machine/cputypes.h> --- 42 unchanged lines hidden (view full) --- 83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 84 ("[intel,%d] Initializing non-intel processor", __LINE__)); 85 86 PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 87 88 cputype = -1; 89 nclasses = 2; 90 | 33 34#include <sys/param.h> 35#include <sys/pmc.h> 36#include <sys/pmckern.h> 37#include <sys/systm.h> 38 39#include <machine/cpu.h> 40#include <machine/cputypes.h> --- 42 unchanged lines hidden (view full) --- 83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 84 ("[intel,%d] Initializing non-intel processor", __LINE__)); 85 86 PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 87 88 cputype = -1; 89 nclasses = 2; 90 |
91 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 92 |
|
91 switch (cpu_id & 0xF00) { 92#if defined(__i386__) 93 case 0x500: /* Pentium family processors */ 94 cputype = PMC_CPU_INTEL_P5; 95 break; | 93 switch (cpu_id & 0xF00) { 94#if defined(__i386__) 95 case 0x500: /* Pentium family processors */ 96 cputype = PMC_CPU_INTEL_P5; 97 break; |
98#endif |
|
96 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ | 99 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ |
97 switch ((cpu_id & 0xF0) >> 4) { /* model number field */ | 100 switch (model) { 101#if defined(__i386__) |
98 case 0x1: 99 cputype = PMC_CPU_INTEL_P6; 100 break; 101 case 0x3: case 0x5: 102 cputype = PMC_CPU_INTEL_PII; 103 break; | 102 case 0x1: 103 cputype = PMC_CPU_INTEL_P6; 104 break; 105 case 0x3: case 0x5: 106 cputype = PMC_CPU_INTEL_PII; 107 break; |
104 case 0x6: | 108 case 0x6: case 0x16: |
105 cputype = PMC_CPU_INTEL_CL; 106 break; 107 case 0x7: case 0x8: case 0xA: case 0xB: 108 cputype = PMC_CPU_INTEL_PIII; 109 break; 110 case 0x9: case 0xD: 111 cputype = PMC_CPU_INTEL_PM; 112 break; | 109 cputype = PMC_CPU_INTEL_CL; 110 break; 111 case 0x7: case 0x8: case 0xA: case 0xB: 112 cputype = PMC_CPU_INTEL_PIII; 113 break; 114 case 0x9: case 0xD: 115 cputype = PMC_CPU_INTEL_PM; 116 break; |
117#endif 118 case 0xE: 119 cputype = PMC_CPU_INTEL_CORE; 120 break; 121 case 0xF: 122 cputype = PMC_CPU_INTEL_CORE2; 123 nclasses = 3; 124 break; 125 case 0x17: 126 cputype = PMC_CPU_INTEL_CORE2EXTREME; 127 nclasses = 3; 128 break; 129 case 0x1C: /* Per Intel document 320047-002. */ 130 cputype = PMC_CPU_INTEL_ATOM; 131 nclasses = 3; 132 break; |
|
113 } 114 break; | 133 } 134 break; |
115#endif | |
116#if defined(__i386__) || defined(__amd64__) 117 case 0xF00: /* P4 */ | 135#if defined(__i386__) || defined(__amd64__) 136 case 0xF00: /* P4 */ |
118 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); | |
119 if (model >= 0 && model <= 6) /* known models */ 120 cputype = PMC_CPU_INTEL_PIV; 121 break; 122 } 123#endif 124 125 if ((int) cputype == -1) { 126 printf("pmc: Unknown Intel CPU.\n"); --- 12 unchanged lines hidden (view full) --- 139 ncpus = pmc_cpu_max(); 140 141 error = pmc_tsc_initialize(pmc_mdep, ncpus); 142 if (error) 143 goto error; 144 145 switch (cputype) { 146#if defined(__i386__) || defined(__amd64__) | 137 if (model >= 0 && model <= 6) /* known models */ 138 cputype = PMC_CPU_INTEL_PIV; 139 break; 140 } 141#endif 142 143 if ((int) cputype == -1) { 144 printf("pmc: Unknown Intel CPU.\n"); --- 12 unchanged lines hidden (view full) --- 157 ncpus = pmc_cpu_max(); 158 159 error = pmc_tsc_initialize(pmc_mdep, ncpus); 160 if (error) 161 goto error; 162 163 switch (cputype) { 164#if defined(__i386__) || defined(__amd64__) |
165 /* 166 * Intel Core, Core 2 and Atom processors. 167 */ 168 case PMC_CPU_INTEL_ATOM: 169 case PMC_CPU_INTEL_CORE: 170 case PMC_CPU_INTEL_CORE2: 171 error = pmc_core_initialize(pmc_mdep, ncpus); 172 break; |
|
147 148 /* 149 * Intel Pentium 4 Processors, and P4/EMT64 processors. 150 */ 151 152 case PMC_CPU_INTEL_PIV: 153 error = pmc_p4_initialize(pmc_mdep, ncpus); 154 --- 24 unchanged lines hidden (view full) --- 179 * Intel Pentium PMCs. 180 */ 181 182 case PMC_CPU_INTEL_P5: 183 error = pmc_p5_initialize(pmc_mdep, ncpus); 184 185 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + PENTIUM_NPMCS, 186 ("[intel,%d] incorrect npmc count %d", __LINE__, | 173 174 /* 175 * Intel Pentium 4 Processors, and P4/EMT64 processors. 176 */ 177 178 case PMC_CPU_INTEL_PIV: 179 error = pmc_p4_initialize(pmc_mdep, ncpus); 180 --- 24 unchanged lines hidden (view full) --- 205 * Intel Pentium PMCs. 206 */ 207 208 case PMC_CPU_INTEL_P5: 209 error = pmc_p5_initialize(pmc_mdep, ncpus); 210 211 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + PENTIUM_NPMCS, 212 ("[intel,%d] incorrect npmc count %d", __LINE__, |
187 md->pmd_npmc)); | 213 pmc_mdep->pmd_npmc)); |
188 break; 189#endif 190 191 default: 192 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 193 } 194 195 --- 8 unchanged lines hidden (view full) --- 204 205void 206pmc_intel_finalize(struct pmc_mdep *md) 207{ 208 pmc_tsc_finalize(md); 209 210 switch (md->pmd_cputype) { 211#if defined(__i386__) || defined(__amd64__) | 214 break; 215#endif 216 217 default: 218 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 219 } 220 221 --- 8 unchanged lines hidden (view full) --- 230 231void 232pmc_intel_finalize(struct pmc_mdep *md) 233{ 234 pmc_tsc_finalize(md); 235 236 switch (md->pmd_cputype) { 237#if defined(__i386__) || defined(__amd64__) |
238 case PMC_CPU_INTEL_ATOM: 239 case PMC_CPU_INTEL_CORE: 240 case PMC_CPU_INTEL_CORE2: 241 pmc_core_finalize(md); 242 break; 243 |
|
212 case PMC_CPU_INTEL_PIV: 213 pmc_p4_finalize(md); 214 break; 215#endif 216#if defined(__i386__) 217 case PMC_CPU_INTEL_P6: 218 case PMC_CPU_INTEL_CL: 219 case PMC_CPU_INTEL_PII: --- 12 unchanged lines hidden --- | 244 case PMC_CPU_INTEL_PIV: 245 pmc_p4_finalize(md); 246 break; 247#endif 248#if defined(__i386__) 249 case PMC_CPU_INTEL_P6: 250 case PMC_CPU_INTEL_CL: 251 case PMC_CPU_INTEL_PII: --- 12 unchanged lines hidden --- |