| hwpmc_core.h (206089) | hwpmc_core.h (210012) |
|---|---|
| 1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/dev/hwpmc/hwpmc_core.h 206089 2010-04-02 13:23:49Z fabient $ | 26 * $FreeBSD: head/sys/dev/hwpmc/hwpmc_core.h 210012 2010-07-13 19:37:45Z gnn $ |
| 27 */ 28 29#ifndef _DEV_HWPMC_CORE_H_ 30#define _DEV_HWPMC_CORE_H_ 1 31 32/* 33 * Fixed-function PMCs. 34 */ --- 27 unchanged lines hidden (view full) --- 62 63#define IA_OFFCORE_RSP_MASK 0xF7FF 64 65#ifdef _KERNEL 66 67/* 68 * Fixed-function counters. 69 */ | 27 */ 28 29#ifndef _DEV_HWPMC_CORE_H_ 30#define _DEV_HWPMC_CORE_H_ 1 31 32/* 33 * Fixed-function PMCs. 34 */ --- 27 unchanged lines hidden (view full) --- 62 63#define IA_OFFCORE_RSP_MASK 0xF7FF 64 65#ifdef _KERNEL 66 67/* 68 * Fixed-function counters. 69 */ |
| 70 |
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| 70#define IAF_MASK 0xF 71 | 71#define IAF_MASK 0xF 72 |
| 73#define IAF_COUNTER_MASK 0x0000ffffffffffff |
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| 72#define IAF_CTR0 0x309 73#define IAF_CTR1 0x30A 74#define IAF_CTR2 0x30B 75 | 74#define IAF_CTR0 0x309 75#define IAF_CTR1 0x30A 76#define IAF_CTR2 0x30B 77 |
| 78/* 79 * The IAF_CTRL MSR is laid out in the following way. 80 * 81 * Bit Position Use 82 * 63 - 12 Reserved (do not touch) 83 * 11 Ctr 2 PMI 84 * 10 Reserved (do not touch) 85 * 9-8 Ctr 2 Enable 86 * 7 Ctr 1 PMI 87 * 6 Reserved (do not touch) 88 * 5-4 Ctr 1 Enable 89 * 3 Ctr 0 PMI 90 * 2 Reserved (do not touch) 91 * 1-0 Ctr 0 Enable (3: All Levels, 2: User, 1: OS, 0: Disable) 92 */ 93 |
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| 76#define IAF_OFFSET 32 77#define IAF_CTRL 0x38D | 94#define IAF_OFFSET 32 95#define IAF_CTRL 0x38D |
| 96#define IAF_CTRL_MASK 0x0000000000000bbb |
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| 78 79/* 80 * Programmable counters. 81 */ 82 83#define IAP_PMC0 0x0C1 | 97 98/* 99 * Programmable counters. 100 */ 101 102#define IAP_PMC0 0x0C1 |
| 103 104/* 105 * IAP_EVSEL(n) is laid out in the following way. 106 * 107 * Bit Position Use 108 * 63-31 Reserved (do not touch) 109 * 31-24 Counter Mask 110 * 23 Invert 111 * 22 Enable 112 * 21 Reserved (do not touch) 113 * 20 APIC Interrupt Enable 114 * 19 Pin Control 115 * 18 Edge Detect 116 * 17 OS 117 * 16 User 118 * 15-8 Unit Mask 119 * 7-0 Event Select 120 */ 121 122#define IAP_EVSEL_MASK 0x00000000ffdfffff |
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| 84#define IAP_EVSEL0 0x186 85 86/* 87 * Simplified programming interface in Intel Performance Architecture 88 * v2 and later. 89 */ 90 91#define IA_GLOBAL_STATUS 0x38E 92#define IA_GLOBAL_CTRL 0x38F | 123#define IAP_EVSEL0 0x186 124 125/* 126 * Simplified programming interface in Intel Performance Architecture 127 * v2 and later. 128 */ 129 130#define IA_GLOBAL_STATUS 0x38E 131#define IA_GLOBAL_CTRL 0x38F |
| 132 133/* 134 * IA_GLOBAL_CTRL is layed out in the following way. 135 * 136 * Bit Position Use 137 * 63-35 Reserved (do not touch) 138 * 34 IAF Counter 2 Enable 139 * 33 IAF Counter 1 Enable 140 * 32 IAF Counter 0 Enable 141 * 31-0 Depends on programmable counters 142 */ 143 144/* The mask is only for the fixed porttion of the register. */ 145#define IAF_GLOBAL_CTRL_MASK 0x0000000700000000 146 |
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| 93#define IA_GLOBAL_OVF_CTRL 0x390 94 95#define IA_GLOBAL_STATUS_FLAG_CONDCHG (1ULL << 63) 96#define IA_GLOBAL_STATUS_FLAG_OVFBUF (1ULL << 62) 97 98/* 99 * Offcore response configuration. 100 */ --- 30 unchanged lines hidden --- | 147#define IA_GLOBAL_OVF_CTRL 0x390 148 149#define IA_GLOBAL_STATUS_FLAG_CONDCHG (1ULL << 63) 150#define IA_GLOBAL_STATUS_FLAG_OVFBUF (1ULL << 62) 151 152/* 153 * Offcore response configuration. 154 */ --- 30 unchanged lines hidden --- |