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1/*-
2 * Copyright (c) 2003-2004 HighPoint Technologies, Inc.
1/*
2 * Copyright (c) 2004-2005 HighPoint Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 7 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 7 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/hptmv/entry.c 144264 2005-03-29 01:46:25Z sam $
26 * $FreeBSD: head/sys/dev/hptmv/entry.c 149871 2005-09-07 23:33:26Z scottl $
27 */
27 */
28
28#include <sys/param.h>
29#include <sys/systm.h>
30#include <sys/kernel.h>
31#include <sys/bus.h>
32#include <sys/malloc.h>
33#include <sys/resource.h>
34#include <sys/time.h>
35#include <sys/callout.h>
36#include <sys/signalvar.h>
37#include <sys/eventhandler.h>
38#include <sys/proc.h>
39#include <sys/kthread.h>
40
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/kernel.h>
32#include <sys/bus.h>
33#include <sys/malloc.h>
34#include <sys/resource.h>
35#include <sys/time.h>
36#include <sys/callout.h>
37#include <sys/signalvar.h>
38#include <sys/eventhandler.h>
39#include <sys/proc.h>
40#include <sys/kthread.h>
41
42#if (__FreeBSD_version >= 500000)
43#include <sys/mutex.h>
44#include <sys/module.h>
45#endif
46
47#if (__FreeBSD_version >= 500000)
41#include <dev/pci/pcireg.h>
42#include <dev/pci/pcivar.h>
48#include <dev/pci/pcireg.h>
49#include <dev/pci/pcivar.h>
50#else
51#include <pci/pcireg.h>
52#include <pci/pcivar.h>
53#include <machine/clock.h>
54#include <sys/wait.h>
55#include <sys/sysproto.h>
56#endif
43
57
58#ifndef __KERNEL__
59#define __KERNEL__
60#endif
61
44#include <dev/hptmv/global.h>
45#include <dev/hptmv/hptintf.h>
46#include <dev/hptmv/osbsd.h>
47#include <dev/hptmv/access601.h>
48
62#include <dev/hptmv/global.h>
63#include <dev/hptmv/hptintf.h>
64#include <dev/hptmv/osbsd.h>
65#include <dev/hptmv/access601.h>
66
67
49#ifdef DEBUG
50#ifdef DEBUG_LEVEL
51int hpt_dbg_level = DEBUG_LEVEL;
68#ifdef DEBUG
69#ifdef DEBUG_LEVEL
70int hpt_dbg_level = DEBUG_LEVEL;
52#else
71#else
53int hpt_dbg_level = 0;
54#endif
55#endif
56
57#define MV_ERROR printf
72int hpt_dbg_level = 0;
73#endif
74#endif
75
76#define MV_ERROR printf
77
58/*
59 * CAM SIM entry points
60 */
78/*
79 * CAM SIM entry points
80 */
61static int hpt_probe(device_t dev);
62static int hpt_attach(device_t dev);
63static int hpt_detach(device_t dev);
64static int hpt_shutdown(device_t dev);
65static void hpt_poll(struct cam_sim *sim);
66static void hpt_intr(void *arg);
67static void hpt_action(struct cam_sim *sim, union ccb *ccb);
68static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev);
69static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb);
70static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd);
71static void ccb_done(union ccb *ccb);
72static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb);
73static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb);
74static void launch_worker_thread(void);
75static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM];
81static int hpt_probe (device_t dev);
82static void launch_worker_thread(void);
83static int hpt_attach(device_t dev);
84static int hpt_detach(device_t dev);
85static int hpt_shutdown(device_t dev);
86static void hpt_poll(struct cam_sim *sim);
87static void hpt_intr(void *arg);
88static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg);
89static void hpt_action(struct cam_sim *sim, union ccb *ccb);
90
91static device_method_t driver_methods[] = {
92 /* Device interface */
93 DEVMETHOD(device_probe, hpt_probe),
94 DEVMETHOD(device_attach, hpt_attach),
95 DEVMETHOD(device_detach, hpt_detach),
96
97/* DEVMETHOD(device_shutdown, hpt_shutdown), */
98 { 0, 0 }
99};
100
101static driver_t hpt_pci_driver = {
102 __str(PROC_DIR_NAME),
103 driver_methods,
104 sizeof(IAL_ADAPTER_T)
105};
106
107static devclass_t hpt_devclass;
108
109#define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6)
110__DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0);
111
112#define ccb_ccb_ptr spriv_ptr0
113#define ccb_adapter ccb_h.spriv_ptr1
114
115static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev);
116static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb);
117static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd);
118static void ccb_done(union ccb *ccb);
119static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb);
120static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb);
76static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter);
77static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
78static void handleEdmaError(_VBUS_ARG PCommand pCmd);
79static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
80static int fResetActiveCommands(PVBus _vbus_p);
81static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter);
82static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter);
83static void hptmv_handle_event_disconnect(void *data);
84static void hptmv_handle_event_connect(void *data);
85static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
86static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel);
87static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel);
121static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter);
122static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
123static void handleEdmaError(_VBUS_ARG PCommand pCmd);
124static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
125static int fResetActiveCommands(PVBus _vbus_p);
126static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter);
127static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter);
128static void hptmv_handle_event_disconnect(void *data);
129static void hptmv_handle_event_connect(void *data);
130static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
131static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel);
132static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel);
88static void hpt_async(void *callback_arg, u_int32_t code,
89 struct cam_path *path, void *arg);
90static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg,
91 int logical);
92static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
93 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId,
94 MV_U16 responseFlags, MV_U32 timeStamp,
95 MV_STORAGE_DEVICE_REGISTERS *registerStruct);
96static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter,
97 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2);
98
99#define ccb_ccb_ptr spriv_ptr0
100#define ccb_adapter ccb_h.spriv_ptr1
101
102IAL_ADAPTER_T *gIal_Adapter = 0;
103IAL_ADAPTER_T *pCurAdapter = 0;
133static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg,
134 int logical);
135static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
136 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId,
137 MV_U16 responseFlags, MV_U32 timeStamp,
138 MV_STORAGE_DEVICE_REGISTERS *registerStruct);
139static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter,
140 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2);
141
142#define ccb_ccb_ptr spriv_ptr0
143#define ccb_adapter ccb_h.spriv_ptr1
144
145IAL_ADAPTER_T *gIal_Adapter = 0;
146IAL_ADAPTER_T *pCurAdapter = 0;
147static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM];
104
105typedef struct st_HPT_DPC {
106 IAL_ADAPTER_T *pAdapter;
107 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR);
108 void *arg;
109 UCHAR flags;
110} ST_HPT_DPC;
111
112#define MAX_DPC 16
113UCHAR DPC_Request_Nums = 0;
114static ST_HPT_DPC DpcQueue[MAX_DPC];
115static int DpcQueue_First=0;
116static int DpcQueue_Last = 0;
117
148
149typedef struct st_HPT_DPC {
150 IAL_ADAPTER_T *pAdapter;
151 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR);
152 void *arg;
153 UCHAR flags;
154} ST_HPT_DPC;
155
156#define MAX_DPC 16
157UCHAR DPC_Request_Nums = 0;
158static ST_HPT_DPC DpcQueue[MAX_DPC];
159static int DpcQueue_First=0;
160static int DpcQueue_Last = 0;
161
118static device_method_t driver_methods[] = {
119 /* Device interface */
120 DEVMETHOD(device_probe, hpt_probe),
121 DEVMETHOD(device_attach, hpt_attach),
122 DEVMETHOD(device_detach, hpt_detach),
123 { 0, 0 }
124};
162char DRIVER_VERSION[] = "v1.12 (" __DATE__ " " __TIME__ ")";
125
163
126static driver_t hpt_pci_driver = {
127 __str(PROC_DIR_NAME),
128 driver_methods,
129 sizeof(IAL_ADAPTER_T)
130};
164#if (__FreeBSD_version >= 500000)
165static struct mtx driver_lock;
166intrmask_t lock_driver()
167{
131
168
132static devclass_t hpt_devclass;
133
134DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0);
135MODULE_DEPEND(PROC_DIR_NAME, cam, 1, 1, 1);
136
137intrmask_t
138lock_driver()
169 intrmask_t spl = 0;
170 mtx_lock_spin(&driver_lock);
171 return spl;
172}
173void unlock_driver(intrmask_t spl)
139{
174{
175 mtx_unlock_spin(&driver_lock);
176}
177#else
178static int driver_locked = 0;
179intrmask_t lock_driver()
180{
140 intrmask_t spl = splcam();
181 intrmask_t spl = splcam();
182loop:
183 while (driver_locked)
184 tsleep(&driver_locked, PRIBIO, "hptlck", hz);
185 atomic_add_int(&driver_locked, 1);
186 if (driver_locked>1) {
187 atomic_subtract_int(&driver_locked, 1);
188 goto loop;
189 }
141 return spl;
142}
143
190 return spl;
191}
192
144void
145unlock_driver(intrmask_t spl)
193void unlock_driver(intrmask_t spl)
146{
194{
195 atomic_subtract_int(&driver_locked, 1);
196 if (driver_locked==0) {
197 wakeup(&driver_locked);
198 }
147 splx(spl);
148}
199 splx(spl);
200}
201#endif
149
150/*******************************************************************************
151 * Name: hptmv_free_channel
152 *
153 * Description: free allocated queues for the given channel
154 *
155 * Parameters: pMvSataAdapter - pointer to the RR182x controler this
156 * channel connected to.
157 * channelNum - channel number.
158 *
159 ******************************************************************************/
160static void
161hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
162{
202
203/*******************************************************************************
204 * Name: hptmv_free_channel
205 *
206 * Description: free allocated queues for the given channel
207 *
208 * Parameters: pMvSataAdapter - pointer to the RR182x controler this
209 * channel connected to.
210 * channelNum - channel number.
211 *
212 ******************************************************************************/
213static void
214hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
215{
163 PVDevice pVDev = &(pAdapter->VDevices[channelNum]);
164 _VBUS_INST(&pAdapter->VBus);
165
166 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM);
216 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM);
167
168 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL;
217 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL;
218}
169
219
170 if(pVDev->vf_online)
171 {
172 pVDev->u.disk.df_on_line = 0;
173 pVDev->vf_online = 0;
174 if (pVDev->pfnDeviceFailed) {
175 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed,
176 pVDev);
177 }
220static void failDevice(PVDevice pVDev)
221{
222 PVBus _vbus_p = pVDev->pVBus;
223 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt;
224
225 pVDev->u.disk.df_on_line = 0;
226 pVDev->vf_online = 0;
227 if (pVDev->pfnDeviceFailed)
228 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev);
229
230 fNotifyGUI(ET_DEVICE_REMOVED, pVDev);
231
232#ifndef FOR_DEMO
233 if (pAdapter->ver_601==2 && !pAdapter->beeping) {
234 pAdapter->beeping = 1;
235 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress);
236 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1);
178 }
237 }
238#endif
179}
180
181int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel);
239}
240
241int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel);
242/*void fDeviceSendCommand(_VBUS_ARG PCommand pCmd); */
182
183static void
184handleEdmaError(_VBUS_ARG PCommand pCmd)
185{
186 PDevice pDevice = &pCmd->pVDevice->u.disk;
187 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter;
188
243
244static void
245handleEdmaError(_VBUS_ARG PCommand pCmd)
246{
247 PDevice pDevice = &pCmd->pVDevice->u.disk;
248 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter;
249
189 MV_ERROR("Reset channel\n");
190
191 MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber);
192 /*now no other cmds on this channel*/
193 if (!pDevice->df_on_line) {
194 KdPrint(("Device is offline"));
195 pCmd->Result = RETURN_BAD_DEVICE;
196 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
197 return;
198 }
199
200 if (pCmd->RetryCount++>5) {
250 if (!pDevice->df_on_line) {
251 KdPrint(("Device is offline"));
252 pCmd->Result = RETURN_BAD_DEVICE;
253 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
254 return;
255 }
256
257 if (pCmd->RetryCount++>5) {
201 pDevice->df_on_line = 0;
202 pCmd->pVDevice->vf_online = 0;
203 if (pCmd->pVDevice->pfnDeviceFailed)
204 CallWhenIdle(_VBUS_P
205 (DPC_PROC)pCmd->pVDevice->pfnDeviceFailed,
206 pCmd->pVDevice);
207 fNotifyGUI(ET_DEVICE_REMOVED, Map2pVDevice(pDevice));
258 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber));
259failed:
260 failDevice(pCmd->pVDevice);
208 pCmd->Result = RETURN_IDE_ERROR;
209 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
210 return;
211 }
261 pCmd->Result = RETURN_IDE_ERROR;
262 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
263 return;
264 }
212 /* retry the command */
265
266 /* reset the channel and retry the command */
267 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber))
268 goto failed;
269
270 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice));
271
272 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber));
213 fDeviceSendCommand(_VBUS_P pCmd);
214}
215
216/****************************************************************
217 * Name: hptmv_init_channel
218 *
273 fDeviceSendCommand(_VBUS_P pCmd);
274}
275
276/****************************************************************
277 * Name: hptmv_init_channel
278 *
219 * Description: allocate request and response queues for the EDMA of
220 * the given channel and sets other fields.
279 * Description: allocate request and response queues for the EDMA of the
280 * given channel and sets other fields.
281 *
221 * Parameters:
222 * pAdapter - pointer to the emulated adapter data structure
223 * channelNum - channel number.
224 * Return: 0 on success, otherwise on failure
225 ****************************************************************/
226static int
227hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
228{
229 MV_SATA_CHANNEL *pMvSataChannel;
230 dma_addr_t req_dma_addr;
231 dma_addr_t rsp_dma_addr;
232
233 if (channelNum >= MV_SATA_CHANNELS_NUM)
234 {
235 MV_ERROR("RR182x[%d]: Bad channelNum=%d",
236 pAdapter->mvSataAdapter.adapterId, channelNum);
237 return -1;
238 }
239
282 * Parameters:
283 * pAdapter - pointer to the emulated adapter data structure
284 * channelNum - channel number.
285 * Return: 0 on success, otherwise on failure
286 ****************************************************************/
287static int
288hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
289{
290 MV_SATA_CHANNEL *pMvSataChannel;
291 dma_addr_t req_dma_addr;
292 dma_addr_t rsp_dma_addr;
293
294 if (channelNum >= MV_SATA_CHANNELS_NUM)
295 {
296 MV_ERROR("RR182x[%d]: Bad channelNum=%d",
297 pAdapter->mvSataAdapter.adapterId, channelNum);
298 return -1;
299 }
300
240 pMvSataChannel =
241 &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum];
301 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum];
242 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel;
243 pMvSataChannel->channelNumber = channelNum;
244 pMvSataChannel->lba48Address = MV_FALSE;
245 pMvSataChannel->maxReadTransfer = MV_FALSE;
246
302 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel;
303 pMvSataChannel->channelNumber = channelNum;
304 pMvSataChannel->lba48Address = MV_FALSE;
305 pMvSataChannel->maxReadTransfer = MV_FALSE;
306
247 pMvSataChannel->requestQueue =
248 (struct mvDmaRequestQueueEntry *)
249 (pAdapter->requestsArrayBaseAlignedAddr +
250 (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE));
251 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr +
252 (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE);
307 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *)
308 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE));
309 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE);
253
254
310
311
255 KdPrint(("requestQueue addr is 0x%lX", (u_long)req_dma_addr));
312 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr));
256
257 /* check the 1K alignment of the request queue*/
258 if (req_dma_addr & 0x3ff)
259 {
313
314 /* check the 1K alignment of the request queue*/
315 if (req_dma_addr & 0x3ff)
316 {
260 MV_ERROR("RR182x[%d]: request queue allocated not 1 K aligned,"
261 " dma_addr=%lx channel=%d\n",
262 pAdapter->mvSataAdapter.adapterId,(u_long)req_dma_addr,
263 channelNum);
317 MV_ERROR("RR182x[%d]: request queue allocated isn't 1 K aligned,"
318 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId,
319 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum);
264 return -1;
265 }
266 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr;
267 pMvSataChannel->requestQueuePciHiAddress = 0;
268 KdPrint(("RR182x[%d,%d]: request queue allocated: 0x%p",
320 return -1;
321 }
322 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr;
323 pMvSataChannel->requestQueuePciHiAddress = 0;
324 KdPrint(("RR182x[%d,%d]: request queue allocated: 0x%p",
269 pAdapter->mvSataAdapter.adapterId, channelNum,
270 pMvSataChannel->requestQueue));
271 pMvSataChannel->responseQueue =
272 (struct mvDmaResponseQueueEntry *)
273 (pAdapter->responsesArrayBaseAlignedAddr +
274 (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE));
275 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr +
276 (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE);
325 pAdapter->mvSataAdapter.adapterId, channelNum,
326 pMvSataChannel->requestQueue));
327 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *)
328 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE));
329 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE);
277
278 /* check the 256 alignment of the response queue*/
279 if (rsp_dma_addr & 0xff)
280 {
330
331 /* check the 256 alignment of the response queue*/
332 if (rsp_dma_addr & 0xff)
333 {
281 MV_ERROR("RR182x[%d,%d]: response queue allocated not 256 byte"
282 " aligned, dma_addr=%lx\n",
283 pAdapter->mvSataAdapter.adapterId, channelNum,
284 (u_long)rsp_dma_addr);
334 MV_ERROR("RR182x[%d,%d]: response queue allocated isn't 256 byte "
335 "aligned, dma_addr=%llx\n",
336 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr);
285 return -1;
286 }
287 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr;
288 pMvSataChannel->responseQueuePciHiAddress = 0;
289 KdPrint(("RR182x[%d,%d]: response queue allocated: 0x%p",
337 return -1;
338 }
339 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr;
340 pMvSataChannel->responseQueuePciHiAddress = 0;
341 KdPrint(("RR182x[%d,%d]: response queue allocated: 0x%p",
290 pAdapter->mvSataAdapter.adapterId, channelNum,
291 pMvSataChannel->responseQueue));
342 pAdapter->mvSataAdapter.adapterId, channelNum,
343 pMvSataChannel->responseQueue));
292
293 pAdapter->mvChannel[channelNum].online = MV_TRUE;
294 return 0;
295}
296
297/******************************************************************************
298 * Name: hptmv_parse_identify_results
299 *
344
345 pAdapter->mvChannel[channelNum].online = MV_TRUE;
346 return 0;
347}
348
349/******************************************************************************
350 * Name: hptmv_parse_identify_results
351 *
300 * Description: this functions parses the identify command results,
301 * checks that the connected deives can be accesed by
302 * RR182x EDMA, and updates the channel stucture
303 * accordingly.
352 * Description: this functions parses the identify command results, checks
353 * that the connected deives can be accesed by RR182x EDMA,
354 * and updates the channel stucture accordingly.
355 *
304 * Parameters: pMvSataChannel, pointer to the channel data structure.
305 *
306 * Returns: =0 ->success, < 0 ->failure.
307 *
308 ******************************************************************************/
309static int
310hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel)
311{
312 MV_U16 *iden = pMvSataChannel->identifyDevice;
313
314 /*LBA addressing*/
356 * Parameters: pMvSataChannel, pointer to the channel data structure.
357 *
358 * Returns: =0 ->success, < 0 ->failure.
359 *
360 ******************************************************************************/
361static int
362hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel)
363{
364 MV_U16 *iden = pMvSataChannel->identifyDevice;
365
366 /*LBA addressing*/
315 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) {
367 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200))
368 {
316 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n"));
317 return -1;
369 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n"));
370 return -1;
318 } else {
371 }
372 else
373 {
319 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported"));
320 }
321 /*DMA support*/
374 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported"));
375 }
376 /*DMA support*/
322 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) {
377 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100))
378 {
323 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n"));
324 return -1;
379 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n"));
380 return -1;
325 } else {
381 }
382 else
383 {
326 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported"));
327 }
328 /* PIO */
384 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported"));
385 }
386 /* PIO */
329 if ((iden[IDEN_VALID] & 2) == 0) {
330 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO "
331 "mode\n"));
387 if ((iden[IDEN_VALID] & 2) == 0)
388 {
389 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n"));
332 return -1;
333 }
334 KdPrint(("%25s - 0x%02x\n", "PIO modes supported",
335 iden[IDEN_PIO_MODE_SPPORTED] & 0xff));
336
337 /*UDMA*/
390 return -1;
391 }
392 KdPrint(("%25s - 0x%02x\n", "PIO modes supported",
393 iden[IDEN_PIO_MODE_SPPORTED] & 0xff));
394
395 /*UDMA*/
338 if ((iden[IDEN_VALID] & 4) == 0) {
339 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA "
340 "mode\n"));
396 if ((iden[IDEN_VALID] & 4) == 0)
397 {
398 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n"));
341 return -1;
342 }
343
344 /* 48 bit address */
399 return -1;
400 }
401
402 /* 48 bit address */
345 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) {
403 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400))
404 {
346 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported"));
347 pMvSataChannel->lba48Address = MV_TRUE;
405 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported"));
406 pMvSataChannel->lba48Address = MV_TRUE;
348 } else {
407 }
408 else
409 {
349 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported"));
350 pMvSataChannel->lba48Address = MV_FALSE;
351 }
352 return 0;
353}
354
355static void
356init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel)
357{
410 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported"));
411 pMvSataChannel->lba48Address = MV_FALSE;
412 }
413 return 0;
414}
415
416static void
417init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel)
418{
358 PVDevice pVDev;
359 MV_SATA_CHANNEL *pMvSataChannel;
360 MV_U16_PTR IdentifyData;
419 PVDevice pVDev = &pAdapter->VDevices[channel];
420 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel];
421 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice;
361
422
362 pVDev = &pAdapter->VDevices[channel];
363 pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel];
364 pMvSataChannel->outstandingCommands = 0;
423 pMvSataChannel->outstandingCommands = 0;
365 IdentifyData = pMvSataChannel->identifyDevice;
366
367 pVDev->u.disk.mv = pMvSataChannel;
368 pVDev->u.disk.df_on_line = 1;
369 pVDev->u.disk.pVBus = &pAdapter->VBus;
370 pVDev->pVBus = &pAdapter->VBus;
371
372#ifdef SUPPORT_48BIT_LBA
373 if (pMvSataChannel->lba48Address == MV_TRUE)
424
425 pVDev->u.disk.mv = pMvSataChannel;
426 pVDev->u.disk.df_on_line = 1;
427 pVDev->u.disk.pVBus = &pAdapter->VBus;
428 pVDev->pVBus = &pAdapter->VBus;
429
430#ifdef SUPPORT_48BIT_LBA
431 if (pMvSataChannel->lba48Address == MV_TRUE)
374 pVDev->u.disk.dDeRealCapacity =
375 ((IdentifyData[101]<<16) | IdentifyData[100]) - 1;
432 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1;
376 else
377#endif
378 if(IdentifyData[53] & 1) {
433 else
434#endif
435 if(IdentifyData[53] & 1) {
379 pVDev->u.disk.dDeRealCapacity =
380 (((IdentifyData[58]<<16 | IdentifyData[57]) <
381 (IdentifyData[61]<<16 | IdentifyData[60])) ?
382 (IdentifyData[61]<<16 | IdentifyData[60]) :
383 (IdentifyData[58]<<16 | IdentifyData[57])) - 1;
436 pVDev->u.disk.dDeRealCapacity =
437 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ?
438 (IdentifyData[61]<<16 | IdentifyData[60]) :
439 (IdentifyData[58]<<16 | IdentifyData[57])) - 1;
384 } else
385 pVDev->u.disk.dDeRealCapacity =
440 } else
441 pVDev->u.disk.dDeRealCapacity =
386 (IdentifyData[61]<<16 | IdentifyData[60]) - 1;
442 (IdentifyData[61]<<16 | IdentifyData[60]) - 1;
387
388 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
443
444 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
389 pAdapter->mvChannel[channel].maxPioModeSupported -
390 MV_ATA_TRANSFER_PIO_0;
445 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0;
391
392 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) {
393 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
446
447 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) {
448 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
394 pAdapter->mvChannel[channel].maxUltraDmaModeSupported -
395 MV_ATA_TRANSFER_UDMA_0 + 8;
449 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8;
396 }
397}
398
450 }
451}
452
399static void
400device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged)
453static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged)
401{
402 PVDevice pVDev;
454{
455 PVDevice pVDev;
403 MV_SATA_ADAPTER *pMvSataAdapter;
404 MV_SATA_CHANNEL *pMvSataChannel;
405 PVBus _vbus_p;
456 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
457 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex];
458
459 if (!pMvSataChannel) return;
406
460
407 pMvSataAdapter = &pAdapter->mvSataAdapter;
408 pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex];
409 _vbus_p = &pAdapter->VBus;
410
411 if (!pMvSataChannel)
412 return;
413
414 if (plugged) {
461 if (plugged)
462 {
415 pVDev = &(pAdapter->VDevices[channelIndex]);
416 init_vdev_params(pAdapter, channelIndex);
417
463 pVDev = &(pAdapter->VDevices[channelIndex]);
464 init_vdev_params(pAdapter, channelIndex);
465
418 pVDev->VDeviceType = pVDev->u.disk.df_atapi ? VD_ATAPI :
419 pVDev->u.disk.df_removable_drive ? VD_REMOVABLE :
420 VD_SINGLE_DISK;
466 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI :
467 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
421
468
422 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity;
469 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO;
423 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
424 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
425 pVDev->vf_online = 1;
426
427#ifdef SUPPORT_ARRAY
470 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
471 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
472 pVDev->vf_online = 1;
473
474#ifdef SUPPORT_ARRAY
428 if(pVDev->pParent) {
475 if(pVDev->pParent)
476 {
429 int iMember;
477 int iMember;
430
431 for (iMember = 0;
432 iMember < pVDev->pParent->u.array.bArnMember;
433 iMember++)
434 if ((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev)
478 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++)
479 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev)
435 pVDev->pParent->u.array.pMember[iMember] = NULL;
436 pVDev->pParent = NULL;
437 }
438#endif
439 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev);
440 fCheckBootable(pVDev);
441 RegisterVDevice(pVDev);
442
443#ifndef FOR_DEMO
444 if (pAdapter->beeping) {
445 pAdapter->beeping = 0;
446 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress);
447 }
448#endif
449
480 pVDev->pParent->u.array.pMember[iMember] = NULL;
481 pVDev->pParent = NULL;
482 }
483#endif
484 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev);
485 fCheckBootable(pVDev);
486 RegisterVDevice(pVDev);
487
488#ifndef FOR_DEMO
489 if (pAdapter->beeping) {
490 pAdapter->beeping = 0;
491 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress);
492 }
493#endif
494
450 } else {
495 }
496 else
497 {
451 pVDev = &(pAdapter->VDevices[channelIndex]);
498 pVDev = &(pAdapter->VDevices[channelIndex]);
452 pVDev->u.disk.df_on_line = 0;
453 pVDev->vf_online = 0;
454 if (pVDev->pfnDeviceFailed) {
455 _VBUS_INST(&pAdapter->VBus)
456 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed,
457 pVDev);
458 }
459 fNotifyGUI(ET_DEVICE_REMOVED,pVDev);
460
461#ifndef FOR_DEMO
462 if (pAdapter->ver_601==2 && !pAdapter->beeping) {
463 pAdapter->beeping = 1;
464 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress);
465 set_fail_led(&pAdapter->mvSataAdapter, channelIndex, 1);
466 }
467#endif
468
499 failDevice(pVDev);
469 }
470}
471
472static int
473start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
474{
500 }
501}
502
503static int
504start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
505{
475 MV_SATA_ADAPTER *pMvSataAdapter;
476 MV_SATA_CHANNEL *pMvSataChannel;
477 MV_CHANNEL *pChannelInfo;
478 MV_U32 udmaMode,pioMode;
506 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
507 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum];
508 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]);
509 MV_U32 udmaMode,pioMode;
479
510
480 pMvSataAdapter = &pAdapter->mvSataAdapter;
481 pMvSataChannel = pMvSataAdapter->sataChannel[channelNum];
482 pChannelInfo = &(pAdapter->mvChannel[channelNum]);
483
484 KdPrint(("RR182x [%d]: start channel (%d)", pMvSataAdapter->adapterId,
511 KdPrint(("RR182x [%d]: start channel (%d)", pMvSataAdapter->adapterId,
485 channelNum));
512 channelNum));
486
487
488 /* Software reset channel */
513
514
515 /* Software reset channel */
489 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) ==
490 MV_FALSE) {
516 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
517 {
491 MV_ERROR("RR182x [%d,%d]: failed to perform Software reset\n",
518 MV_ERROR("RR182x [%d,%d]: failed to perform Software reset\n",
492 pMvSataAdapter->adapterId, channelNum);
519 pMvSataAdapter->adapterId, channelNum);
493 return -1;
494 }
495
496 /* Hardware reset channel */
520 return -1;
521 }
522
523 /* Hardware reset channel */
497 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) {
498 /*
499 * If failed, try again - this is when trying to hardreset a
500 * channel when drive is just spinning up
501 */
524 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
525 {
526 /* If failed, try again - this is when trying to hardreset a channel */
527 /* when drive is just spinning up */
502 StallExec(5000000); /* wait 5 sec before trying again */
528 StallExec(5000000); /* wait 5 sec before trying again */
503 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) ==
504 MV_FALSE) {
505 MV_ERROR("RR182x [%d,%d]: failed to perform Hard "
506 "reset\n", pMvSataAdapter->adapterId,
507 channelNum);
529 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
530 {
531 MV_ERROR("RR182x [%d,%d]: failed to perform Hard reset\n",
532 pMvSataAdapter->adapterId, channelNum);
508 return -1;
509 }
510 }
511
512 /* identify device*/
533 return -1;
534 }
535 }
536
537 /* identify device*/
513 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) ==
514 MV_FALSE) {
515 MV_ERROR("RR182x [%d,%d]: failed to perform ATA Identify "
516 "command\n", pMvSataAdapter->adapterId, channelNum);
538 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE)
539 {
540 MV_ERROR("RR182x [%d,%d]: failed to perform ATA Identify command\n"
541 , pMvSataAdapter->adapterId, channelNum);
517 return -1;
518 }
542 return -1;
543 }
519 if (hptmv_parse_identify_results(pMvSataChannel)) {
520 MV_ERROR("RR182x [%d,%d]: Error in parsing ATA Identify "
521 "message\n", pMvSataAdapter->adapterId, channelNum);
544 if (hptmv_parse_identify_results(pMvSataChannel))
545 {
546 MV_ERROR("RR182x [%d,%d]: Error in parsing ATA Identify message\n"
547 , pMvSataAdapter->adapterId, channelNum);
522 return -1;
523 }
524
525 /* mvStorageDevATASetFeatures */
526 /* Disable 8 bit PIO in case CFA enabled */
548 return -1;
549 }
550
551 /* mvStorageDevATASetFeatures */
552 /* Disable 8 bit PIO in case CFA enabled */
527 if (pMvSataChannel->identifyDevice[86] & 4) {
553 if (pMvSataChannel->identifyDevice[86] & 4)
554 {
528 KdPrint(("RR182x [%d]: Disable 8 bit PIO (CFA enabled) \n",
555 KdPrint(("RR182x [%d]: Disable 8 bit PIO (CFA enabled) \n",
529 pMvSataAdapter->adapterId));
556 pMvSataAdapter->adapterId));
530 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
557 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
531 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 0, 0, 0) ==
532 MV_FALSE) {
533 MV_ERROR("RR182x [%d]: channel %d: "
534 "mvStorageDevATASetFeatures failed\n",
535 pMvSataAdapter->adapterId, channelNum);
558 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0,
559 0, 0, 0) == MV_FALSE)
560 {
561 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures"
562 " failed\n", pMvSataAdapter->adapterId, channelNum);
536 return -1;
537 }
538 }
563 return -1;
564 }
565 }
539
540#ifdef ENABLE_WRITE_CACHE
541 /* Write cache */
566 /* Write cache */
542 if (pMvSataChannel->identifyDevice[82] & 0x20) {
543 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) {
544 /* if not enabled by default */
545 if (mvStorageDevATASetFeatures(pMvSataAdapter,
546 channelNum, MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0,
547 0, 0, 0) == MV_FALSE) {
548 MV_ERROR("RR182x [%d]: channel %d: "
549 "mvStorageDevATASetFeatures failed\n",
550 pMvSataAdapter->adapterId, channelNum);
567#ifdef ENABLE_WRITE_CACHE
568 if (pMvSataChannel->identifyDevice[82] & 0x20)
569 {
570 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */
571 {
572 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
573 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0,
574 0, 0, 0) == MV_FALSE)
575 {
576 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
577 pMvSataAdapter->adapterId, channelNum);
551 return -1;
552 }
553 }
554 KdPrint(("RR182x [%d]: channel %d, write cache enabled\n",
578 return -1;
579 }
580 }
581 KdPrint(("RR182x [%d]: channel %d, write cache enabled\n",
555 pMvSataAdapter->adapterId, channelNum));
556 } else {
582 pMvSataAdapter->adapterId, channelNum));
583 }
584 else
585 {
557 KdPrint(("RR182x [%d]: channel %d, write cache not supported\n",
586 KdPrint(("RR182x [%d]: channel %d, write cache not supported\n",
558 pMvSataAdapter->adapterId, channelNum));
587 pMvSataAdapter->adapterId, channelNum));
559 }
588 }
560#else
561 /* disable write cache */
562 if (pMvSataChannel->identifyDevice[85] & 0x20) {
563 KdPrint(("RR182x [%d]: channel =%d, disable write cache\n",
564 pMvSataAdapter->adapterId, channelNum));
565 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
566 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0) ==
567 MV_FALSE) {
568 MV_ERROR("RR182x [%d]: channel %d: "
569 "mvStorageDevATASetFeatures failed\n",
570 pMvSataAdapter->adapterId, channelNum);
571 return -1;
589#else /* disable write cache */
590 {
591 if (pMvSataChannel->identifyDevice[85] & 0x20)
592 {
593 KdPrint(("RR182x [%d]: channel =%d, disable write cache\n",
594 pMvSataAdapter->adapterId, channelNum));
595 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
596 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0,
597 0, 0, 0) == MV_FALSE)
598 {
599 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
600 pMvSataAdapter->adapterId, channelNum);
601 return -1;
602 }
572 }
603 }
604 KdPrint(("RR182x [%d]: channel=%d, write cache disabled\n",
605 pMvSataAdapter->adapterId, channelNum));
573 }
606 }
574 KdPrint(("RR182x [%d]: channel=%d, write cache disabled\n",
575 pMvSataAdapter->adapterId, channelNum));
576#endif
577
578 /* Set transfer mode */
579 KdPrint(("RR182x [%d] Set transfer mode XFER_PIO_SLOW\n",
607#endif
608
609 /* Set transfer mode */
610 KdPrint(("RR182x [%d] Set transfer mode XFER_PIO_SLOW\n",
580 pMvSataAdapter->adapterId));
611 pMvSataAdapter->adapterId));
581 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
612 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
582 MV_ATA_SET_FEATURES_TRANSFER, MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) ==
583 MV_FALSE) {
613 MV_ATA_SET_FEATURES_TRANSFER,
614 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) ==
615 MV_FALSE)
616 {
584 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n",
617 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n",
585 pMvSataAdapter->adapterId, channelNum);
618 pMvSataAdapter->adapterId, channelNum);
586 return -1;
587 }
588
619 return -1;
620 }
621
589 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) {
622 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1)
623 {
590 pioMode = MV_ATA_TRANSFER_PIO_4;
624 pioMode = MV_ATA_TRANSFER_PIO_4;
591 } else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) {
625 }
626 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2)
627 {
592 pioMode = MV_ATA_TRANSFER_PIO_3;
628 pioMode = MV_ATA_TRANSFER_PIO_3;
593 } else {
594 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not "
595 "supported\n");
629 }
630 else
631 {
632 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n");
596 pioMode = MV_ATA_TRANSFER_PIO_SLOW;
597 }
598
599 KdPrint(("RR182x [%d] Set transfer mode XFER_PIO_4\n",
633 pioMode = MV_ATA_TRANSFER_PIO_SLOW;
634 }
635
636 KdPrint(("RR182x [%d] Set transfer mode XFER_PIO_4\n",
600 pMvSataAdapter->adapterId));
637 pMvSataAdapter->adapterId));
601 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode;
602 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
638 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode;
639 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
603 MV_ATA_SET_FEATURES_TRANSFER, pioMode, 0, 0, 0) == MV_FALSE) {
640 MV_ATA_SET_FEATURES_TRANSFER,
641 pioMode, 0, 0, 0) == MV_FALSE)
642 {
604 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n",
643 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n",
605 pMvSataAdapter->adapterId, channelNum);
644 pMvSataAdapter->adapterId, channelNum);
606 return -1;
607 }
608
609 udmaMode = MV_ATA_TRANSFER_UDMA_0;
645 return -1;
646 }
647
648 udmaMode = MV_ATA_TRANSFER_UDMA_0;
610 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) {
649 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40)
650 {
611 udmaMode = MV_ATA_TRANSFER_UDMA_6;
651 udmaMode = MV_ATA_TRANSFER_UDMA_6;
612 } else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) {
652 }
653 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20)
654 {
613 udmaMode = MV_ATA_TRANSFER_UDMA_5;
655 udmaMode = MV_ATA_TRANSFER_UDMA_5;
614 } else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) {
656 }
657 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10)
658 {
615 udmaMode = MV_ATA_TRANSFER_UDMA_4;
659 udmaMode = MV_ATA_TRANSFER_UDMA_4;
616 } else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) {
660 }
661 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8)
662 {
617 udmaMode = MV_ATA_TRANSFER_UDMA_3;
663 udmaMode = MV_ATA_TRANSFER_UDMA_3;
618 } else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) {
664 }
665 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4)
666 {
619 udmaMode = MV_ATA_TRANSFER_UDMA_2;
620 }
621
622 KdPrint(("RR182x [%d] Set transfer mode XFER_UDMA_%d\n",
667 udmaMode = MV_ATA_TRANSFER_UDMA_2;
668 }
669
670 KdPrint(("RR182x [%d] Set transfer mode XFER_UDMA_%d\n",
623 pMvSataAdapter->adapterId, udmaMode & 0xf));
671 pMvSataAdapter->adapterId, udmaMode & 0xf));
624 pChannelInfo->maxUltraDmaModeSupported = udmaMode;
625
672 pChannelInfo->maxUltraDmaModeSupported = udmaMode;
673
626#if 0
627 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
628 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 0, 0, 0) == MV_FALSE) {
674 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
675 MV_ATA_SET_FEATURES_TRANSFER, udmaMode,
676 0, 0, 0) == MV_FALSE)
677 {
629 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n",
678 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n",
630 pMvSataAdapter->adapterId, channelNum);
679 pMvSataAdapter->adapterId, channelNum);
631 return -1;
680 return -1;
632 }
633#endif
681 }*/
634 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF)
635 return TRUE;
682 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF)
683 return TRUE;
636
637 do {
638 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
639 MV_ATA_SET_FEATURES_TRANSFER,
640 pChannelInfo->maxUltraDmaModeSupported, 0, 0, 0) !=
641 MV_FALSE) {
684 else
685 do
686 {
687 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
688 MV_ATA_SET_FEATURES_TRANSFER,
689 pChannelInfo->maxUltraDmaModeSupported,
690 0, 0, 0) == MV_FALSE)
691 {
692 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0)
693 {
694 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
695 {
696 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress,
697 pMvSataChannel->eDmaRegsOffset +
698 0x11c, /* command reg */
699 MV_ATA_COMMAND_IDLE_IMMEDIATE);
700 mvMicroSecondsDelay(10000);
701 mvSataChannelHardReset(pMvSataAdapter, channelNum);
702 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
703 return FALSE;
704 }
705 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
706 return FALSE;
707 pChannelInfo->maxUltraDmaModeSupported--;
708 continue;
709 }
710 else return FALSE;
711 }
642 break;
712 break;
643 }
713 }while (1);
644
714
645 if (pChannelInfo->maxUltraDmaModeSupported <=
646 MV_ATA_TRANSFER_UDMA_0) {
647 return FALSE;
648 }
649 if (mvStorageDevATASoftResetDevice(pMvSataAdapter,
650 channelNum) == MV_FALSE) {
651 mv_reg_write_byte(pMvSataAdapter->adapterIoBaseAddress,
652 pMvSataChannel->eDmaRegsOffset + 0x11c,
653 /* command reg */ MV_ATA_COMMAND_IDLE_IMMEDIATE);
654 mvMicroSecondsDelay(10000);
655 mvSataChannelHardReset(pMvSataAdapter, channelNum);
656 if (mvStorageDevATASoftResetDevice(pMvSataAdapter,
657 channelNum) == MV_FALSE)
658 return FALSE;
659 }
660 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) ==
661 MV_FALSE)
662 return FALSE;
663 pChannelInfo->maxUltraDmaModeSupported--;
664 } while (1);
665
666#ifdef ENABLE_READ_AHEAD
667 /* Read look ahead */
715 /* Read look ahead */
668 if (pMvSataChannel->identifyDevice[82] & 0x40) {
669 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) {
670 /* if not enabled by default */
671 if (mvStorageDevATASetFeatures(pMvSataAdapter,
672 channelNum, MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0,
673 0, 0) == MV_FALSE) {
674 MV_ERROR("RR182x [%d] channel %d: Set Features "
675 "failed\n", pMvSataAdapter->adapterId,
676 channelNum);
716#ifdef ENABLE_READ_AHEAD
717 if (pMvSataChannel->identifyDevice[82] & 0x40)
718 {
719 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */
720 {
721 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
722 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0,
723 0, 0) == MV_FALSE)
724 {
725 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n",
726 pMvSataAdapter->adapterId, channelNum);
677 return -1;
678 }
679 }
680 KdPrint(("RR182x [%d]: channel=%d, read look ahead enabled\n",
727 return -1;
728 }
729 }
730 KdPrint(("RR182x [%d]: channel=%d, read look ahead enabled\n",
681 pMvSataAdapter->adapterId, channelNum));
682 } else {
683 KdPrint(("RR182x [%d]: channel %d, Read Look Ahead not "
684 "supported\n", pMvSataAdapter->adapterId, channelNum));
731 pMvSataAdapter->adapterId, channelNum));
685 }
732 }
686#else
687 if (pMvSataChannel->identifyDevice[86] & 0x20) {
688 KdPrint(("RR182x [%d]:channel %d, disable read look ahead\n",
689 pMvSataAdapter->adapterId, channelNum));
690 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
691 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0) == MV_FALSE) {
692 MV_ERROR("RR182x [%d]:channel %d: ATA Set Features "
693 "failed\n", pMvSataAdapter->adapterId,
694 channelNum);
695 return -1;
696 }
733 else
734 {
735 KdPrint(("RR182x [%d]: channel %d, Read Look Ahead not supported\n",
736 pMvSataAdapter->adapterId, channelNum));
697 }
737 }
698 KdPrint(("RR182x [%d]:channel %d, read look ahead disabled\n",
699 pMvSataAdapter->adapterId, channelNum));
738#else
739 {
740 if (pMvSataChannel->identifyDevice[86] & 0x20)
741 {
742 KdPrint(("RR182x [%d]:channel %d, disable read look ahead\n",
743 pMvSataAdapter->adapterId, channelNum));
744 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
745 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0,
746 0, 0) == MV_FALSE)
747 {
748 MV_ERROR("RR182x [%d]:channel %d: ATA Set Features failed\n",
749 pMvSataAdapter->adapterId, channelNum);
750 return -1;
751 }
752 }
753 KdPrint(("RR182x [%d]:channel %d, read look ahead disabled\n",
754 pMvSataAdapter->adapterId, channelNum));
755 }
700#endif
701
756#endif
757
702#if 0
703 KdPrint(("RR182x [%d]:channel %d, Set standby timer to 200 seconds\n",
704 pMvSataAdapter->adapterId, channelNum));
705 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channelNum,
706 MV_NON_UDMA_PROTOCOL_NON_DATA,
707 MV_FALSE, /* isEXT*/
708 NULL, 0, 0, /* features*/
709 40, /*sectorCount*/
710 0, /*lbaLow*/
711 0, /*lbaMid*/
712 0, /*lbaHigh*/
713 0, /*device*/
714 MV_ATA_COMMAND_IDLE) ==
715 MV_FALSE) {
716 MV_ERROR("RR182x [%d]:channel %d: ATA Idle command failed\n",
717 pMvSataAdapter->adapterId, channelNum);
718 return -1;
719 }
720#endif
721
758
722#if 0
723 /* 2003-9-16 disable TCQ until we have better solution */
724 if ((pMvSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & 2)) {
725 MV_U8 depth;
726 MV_BOOLEAN result;
727
728 depth = (pMvSataChannel->identifyDevice[IDEN_QUEUE_DEPTH] &
729 0x1f) + 1;
730 KdPrint(("RR182x [%d]: channel %d config EDMA, Queued Mode, "
731 "queue depth %d\n", pMvSataAdapter->adapterId,
732 channelNum, depth));
733 result = mvSataConfigEdmaMode(pMvSataAdapter, channelNum,
734 MV_EDMA_MODE_QUEUED, depth);
735 if (result == MV_FALSE) {
736 MV_ERROR("RR182x [%d] Error: mvSataConfigEdmaMode "
737 "failed\n", pMvSataAdapter->adapterId);
759 {
760 KdPrint(("RR182x [%d]: channel %d config EDMA, Non Queued Mode\n",
761 pMvSataAdapter->adapterId,
762 channelNum));
763 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum,
764 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE)
765 {
766 MV_ERROR("RR182x [%d] channel %d Error: mvSataConfigEdmaMode failed\n",
767 pMvSataAdapter->adapterId, channelNum);
738 return -1;
739 }
768 return -1;
769 }
740 } else {
741#endif
742 KdPrint(("RR182x [%d]: channel %d config EDMA, Non Queued Mode\n",
743 pMvSataAdapter->adapterId, channelNum));
744 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum,
745 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) {
746 MV_ERROR("RR182x [%d] channel %d Error: mvSataConfigEdmaMode "
747 "failed\n", pMvSataAdapter->adapterId, channelNum);
748 return -1;
749 }
770 }
750
751 /* Enable EDMA */
771 /* Enable EDMA */
752 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) {
772 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE)
773 {
753 MV_ERROR("RR182x [%d] Failed to enable DMA, channel=%d\n",
774 MV_ERROR("RR182x [%d] Failed to enable DMA, channel=%d\n",
754 pMvSataAdapter->adapterId, channelNum);
775 pMvSataAdapter->adapterId, channelNum);
755 return -1;
756 }
757 MV_ERROR("RR182x [%d,%d]: channel started successfully\n",
776 return -1;
777 }
778 MV_ERROR("RR182x [%d,%d]: channel started successfully\n",
758 pMvSataAdapter->adapterId, channelNum);
779 pMvSataAdapter->adapterId, channelNum);
759
760#ifndef FOR_DEMO
761 set_fail_led(pMvSataAdapter, channelNum, 0);
762#endif
763 return 0;
764}
765
766static void
767hptmv_handle_event(void * data, int flag)
768{
780
781#ifndef FOR_DEMO
782 set_fail_led(pMvSataAdapter, channelNum, 0);
783#endif
784 return 0;
785}
786
787static void
788hptmv_handle_event(void * data, int flag)
789{
769 IAL_ADAPTER_T *pAdapter;
770 MV_SATA_ADAPTER *pMvSataAdapter;
771 MV_U8 channelIndex;
772
773 pAdapter = (IAL_ADAPTER_T *)data;
774 pMvSataAdapter = &pAdapter->mvSataAdapter;
775
776 mvOsSemTake(&pMvSataAdapter->semaphore);
777 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM;
778 channelIndex++) {
779 switch(pAdapter->sataEvents[channelIndex]) {
780 case SATA_EVENT_CHANNEL_CONNECTED:
781 /* Handle only connects */
782 if (flag == 1)
783 break;
784 KdPrint(("RR182x [%d,%d]: new device connected\n",
785 pMvSataAdapter->adapterId, channelIndex));
786 hptmv_init_channel(pAdapter, channelIndex);
787 if (mvSataConfigureChannel( pMvSataAdapter,
788 channelIndex) == MV_FALSE) {
789 MV_ERROR("RR182x [%d,%d] Failed to configure\n",
790 pMvSataAdapter->adapterId,
791 channelIndex);
792 hptmv_free_channel(pAdapter, channelIndex);
793 } else {
794#if 0
795 mvSataChannelHardReset(pMvSataAdapter, channel);
796#endif
797 if (start_channel( pAdapter, channelIndex)) {
798 MV_ERROR("RR182x [%d,%d]Failed to start"
799 " channel\n",
800 pMvSataAdapter->adapterId,
801 channelIndex);
802 hptmv_free_channel(pAdapter,
803 channelIndex);
804 } else {
805 device_change(pAdapter, channelIndex,
806 TRUE);
790 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data;
791 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
792 MV_U8 channelIndex;
793
794/* mvOsSemTake(&pMvSataAdapter->semaphore); */
795 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++)
796 {
797 switch(pAdapter->sataEvents[channelIndex])
798 {
799 case SATA_EVENT_CHANNEL_CONNECTED:
800 /* Handle only connects */
801 if (flag == 1)
802 break;
803 KdPrint(("RR182x [%d,%d]: new device connected\n",
804 pMvSataAdapter->adapterId, channelIndex));
805 hptmv_init_channel(pAdapter, channelIndex);
806 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE)
807 {
808 MV_ERROR("RR182x [%d,%d] Failed to configure\n",
809 pMvSataAdapter->adapterId, channelIndex);
810 hptmv_free_channel(pAdapter, channelIndex);
807 }
811 }
808 }
809 pAdapter->sataEvents[channelIndex] =
810 SATA_EVENT_NO_CHANGE;
811 break;
812 else
813 {
814 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/
815 if (start_channel( pAdapter, channelIndex))
816 {
817 MV_ERROR("RR182x [%d,%d]Failed to start channel\n",
818 pMvSataAdapter->adapterId, channelIndex);
819 hptmv_free_channel(pAdapter, channelIndex);
820 }
821 else
822 {
823 device_change(pAdapter, channelIndex, TRUE);
824 }
825 }
826 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
827 break;
812
828
813 case SATA_EVENT_CHANNEL_DISCONNECTED:
814 /* Handle only disconnects */
815 if (flag == 0)
829 case SATA_EVENT_CHANNEL_DISCONNECTED:
830 /* Handle only disconnects */
831 if (flag == 0)
832 break;
833 KdPrint(("RR182x [%d,%d]: device disconnected\n",
834 pMvSataAdapter->adapterId, channelIndex));
835 /* Flush pending commands */
836 if(pMvSataAdapter->sataChannel[channelIndex])
837 {
838 _VBUS_INST(&pAdapter->VBus)
839 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex,
840 MV_FLUSH_TYPE_CALLBACK);
841 CheckPendingCall(_VBUS_P0);
842 mvSataRemoveChannel(pMvSataAdapter,channelIndex);
843 hptmv_free_channel(pAdapter, channelIndex);
844 pMvSataAdapter->sataChannel[channelIndex] = NULL;
845 KdPrint(("RR182x [%d,%d]: channel removed\n",
846 pMvSataAdapter->adapterId, channelIndex));
847 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
848 Check_Idle_Call(pAdapter);
849 }
850 else
851 {
852 KdPrint(("RR182x [%d,%d]: channel already removed!!\n",
853 pMvSataAdapter->adapterId, channelIndex));
854 }
855 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
816 break;
856 break;
817 KdPrint(("RR182x [%d,%d]: device disconnected\n",
818 pMvSataAdapter->adapterId, channelIndex));
819 /* Flush pending commands */
820 if(pMvSataAdapter->sataChannel[channelIndex]) {
821 _VBUS_INST(&pAdapter->VBus)
822 mvSataFlushDmaQueue (pMvSataAdapter,
823 channelIndex, MV_FLUSH_TYPE_CALLBACK);
824 CheckPendingCall(_VBUS_P0);
825 mvSataRemoveChannel(pMvSataAdapter,
826 channelIndex);
827 hptmv_free_channel(pAdapter, channelIndex);
828 pMvSataAdapter->sataChannel[channelIndex] =
829 NULL;
830 KdPrint(("RR182x [%d,%d]: channel removed\n",
831 pMvSataAdapter->adapterId,
832 channelIndex));
833 if (pAdapter->outstandingCommands==0 &&
834 DPC_Request_Nums==0)
835 Check_Idle_Call(pAdapter);
836 } else {
837 KdPrint(("RR182x [%d,%d]: channel already "
838 "removed!!\n",
839 pMvSataAdapter->adapterId,
840 channelIndex));
841 }
842 pAdapter->sataEvents[channelIndex] =
843 SATA_EVENT_NO_CHANGE;
844 break;
845
857
846 case SATA_EVENT_NO_CHANGE:
847 break;
858 case SATA_EVENT_NO_CHANGE:
859 break;
848
860
849 default:
850 break;
861 default:
862 break;
851 }
852 }
863 }
864 }
853 mvOsSemRelease(&pMvSataAdapter->semaphore);
865/* mvOsSemRelease(&pMvSataAdapter->semaphore); */
854}
855
856#define EVENT_CONNECT 1
857#define EVENT_DISCONNECT 0
858
859static void
860hptmv_handle_event_connect(void *data)
861{
866}
867
868#define EVENT_CONNECT 1
869#define EVENT_DISCONNECT 0
870
871static void
872hptmv_handle_event_connect(void *data)
873{
862 hptmv_handle_event (data, 0);
874 hptmv_handle_event (data, 0);
863}
864
865static void
866hptmv_handle_event_disconnect(void *data)
867{
875}
876
877static void
878hptmv_handle_event_disconnect(void *data)
879{
868 hptmv_handle_event (data, 1);
880 hptmv_handle_event (data, 1);
869}
870
871static MV_BOOLEAN
872hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType,
881}
882
883static MV_BOOLEAN
884hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType,
873 MV_U32 param1, MV_U32 param2)
885 MV_U32 param1, MV_U32 param2)
874{
886{
875 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData;
887 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData;
876
888
877 switch (eventType) {
878 case MV_EVENT_TYPE_SATA_CABLE:
889 switch (eventType)
879 {
890 {
880 MV_U8 channel = param2;
891 case MV_EVENT_TYPE_SATA_CABLE:
892 {
893 MV_U8 channel = param2;
881
894
882 if (param1 == EVENT_CONNECT) {
883 pAdapter->sataEvents[channel] =
884 SATA_EVENT_CHANNEL_CONNECTED;
885 KdPrint(("RR182x [%d,%d]: device connected event "
886 "received\n", pMvSataAdapter->adapterId,
887 channel));
888 /*
889 * Delete previous timers (if multiple drives connected
890 * in the same time
891 */
892 pAdapter->event_timer_connect =
893 timeout(hptmv_handle_event_connect, pAdapter,10*hz);
894 } else if (param1 == EVENT_DISCONNECT) {
895 pAdapter->sataEvents[channel] =
896 SATA_EVENT_CHANNEL_DISCONNECTED;
897 KdPrint(("RR182x [%d,%d]: device disconnected event "
898 "received \n", pMvSataAdapter->adapterId,
899 channel));
900 device_change(pAdapter, channel, FALSE);
901 /*
902 * Delete previous timers (if multiple drives
903 * disconnected in the same time
904 */
905 pAdapter->event_timer_disconnect =
906 timeout(hptmv_handle_event_disconnect, pAdapter,
907 10*hz);
908 } else {
909 MV_ERROR("RR182x: illigal value for param1(%d) at "
910 "connect/disconect event, host=%d\n", param1,
911 pMvSataAdapter->adapterId );
895 if (param1 == EVENT_CONNECT)
896 {
897 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED;
898 KdPrint(("RR182x [%d,%d]: device connected event received\n",
899 pMvSataAdapter->adapterId, channel));
900 /* Delete previous timers (if multiple drives connected in the same time */
901 pAdapter->event_timer_connect = timeout(hptmv_handle_event_connect, pAdapter, 10*hz);
902 }
903 else if (param1 == EVENT_DISCONNECT)
904 {
905 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED;
906 KdPrint(("RR182x [%d,%d]: device disconnected event received \n",
907 pMvSataAdapter->adapterId, channel));
908 device_change(pAdapter, channel, FALSE);
909 /* Delete previous timers (if multiple drives disconnected in the same time */
910 /*pAdapter->event_timer_disconnect = timeout(hptmv_handle_event_disconnect, pAdapter, 10*hz); */
911 /*It is not necessary to wait, handle it directly*/
912 hptmv_handle_event_disconnect(pAdapter);
913 }
914 else
915 {
912
916
913 }
914 break;
917 MV_ERROR("RR182x: illigal value for param1(%d) at "
918 "connect/disconect event, host=%d\n", param1,
919 pMvSataAdapter->adapterId );
920
921 }
922 }
923 break;
924 case MV_EVENT_TYPE_ADAPTER_ERROR:
925 KdPrint(("RR182x: DEVICE error event received, pci cause "
926 "reg=%x, don't how to handle this\n", param1));
927 return MV_TRUE;
928 default:
929 MV_ERROR("RR182x[%d]: unknown event type (%d)\n",
930 pMvSataAdapter->adapterId, eventType);
931 return MV_FALSE;
915 }
932 }
916 case MV_EVENT_TYPE_ADAPTER_ERROR:
917 KdPrint(("RR182x: DEVICE error event received, pci cause "
918 "reg=%x, don't how to handle this\n", param1));
919 return MV_TRUE;
920 default:
921 MV_ERROR("RR182x[%d]: unknown event type (%d)\n",
922 pMvSataAdapter->adapterId, eventType);
923 return MV_FALSE;
924 }
925 return MV_TRUE;
926}
927
933 return MV_TRUE;
934}
935
928static void
929hptmv_map_req(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
930{
931 dma_addr_t *addr;
932
933 addr = (dma_addr_t *)arg;
934
935 if (error || nsegs != 1)
936 return;
937
938 *addr = segs[0].ds_addr;
939
940 return;
941}
942
943static int
936static int
944hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter)
945{
937hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter)
938{
946 if (bus_dmamem_alloc(pAdapter->req_dmat,
947 (void **)&pAdapter->requestsArrayBaseAddr, BUS_DMA_WAITOK,
948 &pAdapter->req_map) != 0) {
949 MV_ERROR("RR182x[%d]: Failed to allocate memory for EDMA "
950 "request queues\n", pAdapter->mvSataAdapter.adapterId);
939 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE,
940 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
941 if (pAdapter->requestsArrayBaseAddr == NULL)
942 {
943 MV_ERROR("RR182x[%d]: Failed to allocate memory for EDMA request"
944 " queues\n", pAdapter->mvSataAdapter.adapterId);
951 return -1;
952 }
945 return -1;
946 }
953
954 (void)bus_dmamap_load(pAdapter->req_dmat, pAdapter->req_map,
955 pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, hptmv_map_req,
956 &pAdapter->requestsArrayBaseDmaAddr, 0);
957
958 pAdapter->requestsArrayBaseAlignedAddr =
959 pAdapter->requestsArrayBaseAddr;
947 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr);
948 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr;
960 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
949 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
961 pAdapter->requestsArrayBaseAlignedAddr =
962 (MV_U8 *)(((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) &
963 ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1));
964 pAdapter->requestsArrayBaseDmaAlignedAddr =
965 pAdapter->requestsArrayBaseDmaAddr;
950 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *)
951 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1));
952 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr;
966 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
953 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
967 pAdapter->requestsArrayBaseDmaAlignedAddr &=
968 ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1);
954 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1);
969
955
970 if ((pAdapter->requestsArrayBaseDmaAlignedAddr -
971 pAdapter->requestsArrayBaseDmaAddr) !=
972 (pAdapter->requestsArrayBaseAlignedAddr -
973 pAdapter->requestsArrayBaseAddr)) {
956 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) !=
957 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr))
958 {
974 MV_ERROR("RR182x[%d]: Error in Request Quueues Alignment\n",
959 MV_ERROR("RR182x[%d]: Error in Request Quueues Alignment\n",
975 pAdapter->mvSataAdapter.adapterId);
976 bus_dmamap_unload(pAdapter->req_dmat, pAdapter->req_map);
977 bus_dmamem_free(pAdapter->req_dmat,
978 pAdapter->requestsArrayBaseAddr, pAdapter->req_map);
960 pAdapter->mvSataAdapter.adapterId);
961 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
979 return -1;
980 }
981 /* response queues */
962 return -1;
963 }
964 /* response queues */
982 if (bus_dmamem_alloc(pAdapter->resp_dmat,
983 (void **)&pAdapter->responsesArrayBaseAddr, BUS_DMA_WAITOK,
984 &pAdapter->resp_map) != 0) {
985 MV_ERROR("RR182x[%d]: Failed to allocate memory for EDMA "
986 "response queues\n", pAdapter->mvSataAdapter.adapterId);
987 bus_dmamap_unload(pAdapter->req_dmat, pAdapter->req_map);
988 bus_dmamem_free(pAdapter->req_dmat,
989 pAdapter->requestsArrayBaseAddr, pAdapter->req_map);
965 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE,
966 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
967 if (pAdapter->responsesArrayBaseAddr == NULL)
968 {
969 MV_ERROR("RR182x[%d]: Failed to allocate memory for EDMA response"
970 " queues\n", pAdapter->mvSataAdapter.adapterId);
971 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
990 return -1;
991 }
972 return -1;
973 }
992
993 (void)bus_dmamap_load(pAdapter->resp_dmat, pAdapter->resp_map,
994 pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE,
995 hptmv_map_req, &pAdapter->responsesArrayBaseDmaAddr, 0);
996
997 pAdapter->responsesArrayBaseAlignedAddr =
998 pAdapter->responsesArrayBaseAddr;
974 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr);
975 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr;
999 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
976 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
1000 pAdapter->responsesArrayBaseAlignedAddr =
1001 (MV_U8 *)(((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) &
1002 ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1));
1003 pAdapter->responsesArrayBaseDmaAlignedAddr =
1004 pAdapter->responsesArrayBaseDmaAddr;
1005 pAdapter->responsesArrayBaseDmaAlignedAddr +=
1006 MV_EDMA_RESPONSE_QUEUE_SIZE;
1007 pAdapter->responsesArrayBaseDmaAlignedAddr &=
1008 ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1);
977 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *)
978 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1));
979 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr;
980 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
981 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1);
1009
982
1010 if ((pAdapter->responsesArrayBaseDmaAlignedAddr -
1011 pAdapter->responsesArrayBaseDmaAddr) !=
1012 (pAdapter->responsesArrayBaseAlignedAddr -
1013 pAdapter->responsesArrayBaseAddr)) {
983 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) !=
984 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr))
985 {
1014 MV_ERROR("RR182x[%d]: Error in Response Quueues Alignment\n",
986 MV_ERROR("RR182x[%d]: Error in Response Quueues Alignment\n",
1015 pAdapter->mvSataAdapter.adapterId);
1016 hptmv_free_edma_queues(pAdapter);
987 pAdapter->mvSataAdapter.adapterId);
988 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
989 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
1017 return -1;
1018 }
1019 return 0;
1020}
1021
1022static void
1023hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter)
1024{
990 return -1;
991 }
992 return 0;
993}
994
995static void
996hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter)
997{
1025 bus_dmamap_unload(pAdapter->req_dmat, pAdapter->req_map);
1026 bus_dmamem_free(pAdapter->req_dmat, pAdapter->requestsArrayBaseAddr,
1027 pAdapter->req_map);
1028 bus_dmamap_unload(pAdapter->resp_dmat, pAdapter->resp_map);
1029 bus_dmamem_free(pAdapter->resp_dmat, pAdapter->responsesArrayBaseAddr,
1030 pAdapter->resp_map);
998 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF);
999 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF);
1031}
1032
1033static PVOID
1034AllocatePRDTable(IAL_ADAPTER_T *pAdapter)
1035{
1036 PVOID ret;
1037 if (pAdapter->pFreePRDLink) {
1000}
1001
1002static PVOID
1003AllocatePRDTable(IAL_ADAPTER_T *pAdapter)
1004{
1005 PVOID ret;
1006 if (pAdapter->pFreePRDLink) {
1038 KdPrint(("pAdapter->pFreePRDLink:%p\n",
1039 pAdapter->pFreePRDLink));
1007 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink));
1040 ret = pAdapter->pFreePRDLink;
1041 pAdapter->pFreePRDLink = *(void**)ret;
1042 return ret;
1043 }
1044 return NULL;
1045}
1046
1047static void

--- 7 unchanged lines hidden (view full) ---

1055extern void fResetBootMark(PVDevice pLogical);
1056static void
1057fRegisterVdevice(IAL_ADAPTER_T *pAdapter)
1058{
1059 PVDevice pPhysical, pLogical;
1060 PVBus pVBus;
1061 int i,j;
1062
1008 ret = pAdapter->pFreePRDLink;
1009 pAdapter->pFreePRDLink = *(void**)ret;
1010 return ret;
1011 }
1012 return NULL;
1013}
1014
1015static void

--- 7 unchanged lines hidden (view full) ---

1023extern void fResetBootMark(PVDevice pLogical);
1024static void
1025fRegisterVdevice(IAL_ADAPTER_T *pAdapter)
1026{
1027 PVDevice pPhysical, pLogical;
1028 PVBus pVBus;
1029 int i,j;
1030
1063 for(i = 0; i < MV_SATA_CHANNELS_NUM; i++) {
1031 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) {
1064 pPhysical = &(pAdapter->VDevices[i]);
1065 pLogical = pPhysical;
1066 while (pLogical->pParent) pLogical = pLogical->pParent;
1067 if (pLogical->vf_online==0) {
1068 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0;
1069 continue;
1070 }
1032 pPhysical = &(pAdapter->VDevices[i]);
1033 pLogical = pPhysical;
1034 while (pLogical->pParent) pLogical = pLogical->pParent;
1035 if (pLogical->vf_online==0) {
1036 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0;
1037 continue;
1038 }
1071 if (pLogical->VDeviceType == VD_SPARE ||
1072 pPhysical != fGetFirstChild(pLogical))
1039 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical))
1073 continue;
1074
1075 pVBus = &pAdapter->VBus;
1040 continue;
1041
1042 pVBus = &pAdapter->VBus;
1076 if(pVBus) {
1043 if(pVBus)
1044 {
1077 j=0;
1045 j=0;
1078 while(j < MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j])
1079 j++;
1080 if (j < MAX_VDEVICE_PER_VBUS) {
1046 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++;
1047 if(j<MAX_VDEVICE_PER_VBUS){
1081 pVBus->pVDevice[j] = pLogical;
1082 pLogical->pVBus = pVBus;
1083
1084 if (j>0 && pLogical->vf_bootmark) {
1085 if (pVBus->pVDevice[0]->vf_bootmark) {
1086 fResetBootMark(pLogical);
1048 pVBus->pVDevice[j] = pLogical;
1049 pLogical->pVBus = pVBus;
1050
1051 if (j>0 && pLogical->vf_bootmark) {
1052 if (pVBus->pVDevice[0]->vf_bootmark) {
1053 fResetBootMark(pLogical);
1087 } else {
1088 do {
1089 pVBus->pVDevice[j] =
1090 pVBus->pVDevice[j-1];
1091 } while (--j);
1054 }
1055 else {
1056 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j);
1092 pVBus->pVDevice[0] = pLogical;
1093 }
1094 }
1095 }
1096 }
1097 }
1098}
1099
1100PVDevice
1101GetSpareDisk(_VBUS_ARG PVDevice pArray)
1102{
1057 pVBus->pVDevice[0] = pLogical;
1058 }
1059 }
1060 }
1061 }
1062 }
1063}
1064
1065PVDevice
1066GetSpareDisk(_VBUS_ARG PVDevice pArray)
1067{
1103 IAL_ADAPTER_T *pAdapter;
1104 ULONG capacity;
1068 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt;
1069 ULONG capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1);
1105 ULONG thiscap, maxcap = MAX_LBA_T;
1106 PVDevice pVDevice, pFind = NULL;
1107 int i;
1108
1070 ULONG thiscap, maxcap = MAX_LBA_T;
1071 PVDevice pVDevice, pFind = NULL;
1072 int i;
1073
1109 pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt;
1110 capacity =
1111 LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1);
1112 for (i = 0;i < MV_SATA_CHANNELS_NUM; i++) {
1074 for(i=0;i<MV_SATA_CHANNELS_NUM;i++)
1075 {
1113 pVDevice = &pAdapter->VDevices[i];
1114 if(!pVDevice)
1115 continue;
1076 pVDevice = &pAdapter->VDevices[i];
1077 if(!pVDevice)
1078 continue;
1116 thiscap = pArray->vf_format_v2 ?
1117 pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity;
1079 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity;
1118 /* find the smallest usable spare disk */
1119 if (pVDevice->VDeviceType==VD_SPARE &&
1080 /* find the smallest usable spare disk */
1081 if (pVDevice->VDeviceType==VD_SPARE &&
1120 pVDevice->u.disk.df_on_line && thiscap < maxcap &&
1121 thiscap >= capacity) {
1122 maxcap = pVDevice->VDeviceCapacity;
1123 pFind = pVDevice;
1082 pVDevice->u.disk.df_on_line &&
1083 thiscap < maxcap &&
1084 thiscap >= capacity)
1085 {
1086 maxcap = pVDevice->VDeviceCapacity;
1087 pFind = pVDevice;
1124 }
1125 }
1126 return pFind;
1127}
1128
1129/******************************************************************
1130 * IO ATA Command
1131 *******************************************************************/
1132int HPTLIBAPI
1133fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer)
1134{
1135 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer);
1136}
1137
1138void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode)
1139{
1088 }
1089 }
1090 return pFind;
1091}
1092
1093/******************************************************************
1094 * IO ATA Command
1095 *******************************************************************/
1096int HPTLIBAPI
1097fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer)
1098{
1099 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer);
1100}
1101
1102void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode)
1103{
1140#ifndef SIMULATE
1141 MV_SATA_CHANNEL *pSataChannel;
1142 MV_SATA_ADAPTER *pSataAdapter;
1143 MV_U8 channelIndex;
1104 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1105 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1106 MV_U8 channelIndex = pSataChannel->channelNumber;
1144 UCHAR mvMode;
1107 UCHAR mvMode;
1145
1146 pSataChannel = pDev->mv;
1147 pSataAdapter = pSataChannel->mvSataAdapter;
1148 channelIndex = pSataChannel->channelNumber;
1149
1150 /* 508x don't use MW-DMA? */
1151 if (NewMode>4 && NewMode<8) NewMode = 4;
1152 pDev->bDeModeSetting = NewMode;
1153 if (NewMode<=4)
1154 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode;
1155 else
1156 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8);
1157
1158 /*To fix 88i8030 bug*/
1159 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4)
1160 mvMode = MV_ATA_TRANSFER_UDMA_0;
1161
1162 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1163 /* Flush pending commands */
1164 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE);
1165
1166 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1108 /* 508x don't use MW-DMA? */
1109 if (NewMode>4 && NewMode<8) NewMode = 4;
1110 pDev->bDeModeSetting = NewMode;
1111 if (NewMode<=4)
1112 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode;
1113 else
1114 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8);
1115
1116 /*To fix 88i8030 bug*/
1117 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4)
1118 mvMode = MV_ATA_TRANSFER_UDMA_0;
1119
1120 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1121 /* Flush pending commands */
1122 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE);
1123
1124 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1167 MV_ATA_SET_FEATURES_TRANSFER, mvMode, 0, 0, 0) == MV_FALSE) {
1125 MV_ATA_SET_FEATURES_TRANSFER,
1126 mvMode, 0, 0, 0) == MV_FALSE)
1127 {
1168 KdPrint(("channel %d: Set Features failed\n", channelIndex));
1169 }
1170 /* Enable EDMA */
1171 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE)
1172 KdPrint(("Failed to enable DMA, channel=%d", channelIndex));
1128 KdPrint(("channel %d: Set Features failed\n", channelIndex));
1129 }
1130 /* Enable EDMA */
1131 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE)
1132 KdPrint(("Failed to enable DMA, channel=%d", channelIndex));
1173#endif
1174}
1175
1176#ifdef SUPPORT_ARRAY
1177#define IdeRegisterVDevice fCheckArray
1133}
1134
1135#ifdef SUPPORT_ARRAY
1136#define IdeRegisterVDevice fCheckArray
1178#else
1137#else
1179void
1180IdeRegisterVDevice(PDevice pDev)
1181{
1182 PVDevice pVDev = Map2pVDevice(pDev);
1183
1184 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI :
1138void
1139IdeRegisterVDevice(PDevice pDev)
1140{
1141 PVDevice pVDev = Map2pVDevice(pDev);
1142
1143 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI :
1185 pDev->df_removable_drive ? VD_REMOVABLE : VD_SINGLE_DISK;
1144 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
1186 pVDev->vf_online = 1;
1187 pVDev->VDeviceCapacity = pDev->dDeRealCapacity;
1188 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
1189 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
1190}
1191#endif
1192
1145 pVDev->vf_online = 1;
1146 pVDev->VDeviceCapacity = pDev->dDeRealCapacity;
1147 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
1148 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
1149}
1150#endif
1151
1152static __inline PBUS_DMAMAP
1153dmamap_get(struct IALAdapter * pAdapter)
1154{
1155 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list;
1156 if (p)
1157 pAdapter->pbus_dmamap_list = p-> next;
1158 return p;
1159}
1160
1161static __inline void
1162dmamap_put(PBUS_DMAMAP p)
1163{
1164 p->next = p->pAdapter->pbus_dmamap_list;
1165 p->pAdapter->pbus_dmamap_list = p;
1166}
1167
1168/*Since mtx not provide the initialize when declare, so we Final init here to initialize the global mtx*/
1169#if __FreeBSD_version >= 500000
1170static void hpt_init(void *dummy)
1171{
1172 mtx_init(&driver_lock, "hptlock", NULL, MTX_SPIN);
1173}
1174SYSINIT(hptinit, SI_SUB_CONFIGURE, SI_ORDER_FIRST, hpt_init, NULL);
1175#endif
1176
1193static int num_adapters = 0;
1194static int
1195init_adapter(IAL_ADAPTER_T *pAdapter)
1196{
1177static int num_adapters = 0;
1178static int
1179init_adapter(IAL_ADAPTER_T *pAdapter)
1180{
1197 PCommand pCmd;
1198 pPrivCommand prvCmd;
1199 PVBus _vbus_p = &pAdapter->VBus;
1200 MV_SATA_ADAPTER *pMvSataAdapter;
1181 PVBus _vbus_p = &pAdapter->VBus;
1182 MV_SATA_ADAPTER *pMvSataAdapter;
1201 PUCHAR PRDTable;
1202 int i, channel, rid, error;
1183 int i, channel, rid;
1203
1204 PVDevice pVDev;
1205
1206 intrmask_t oldspl = lock_driver();
1207
1208 pAdapter->next = 0;
1209
1184
1185 PVDevice pVDev;
1186
1187 intrmask_t oldspl = lock_driver();
1188
1189 pAdapter->next = 0;
1190
1210 if(gIal_Adapter == 0) {
1191 if(gIal_Adapter == 0){
1211 gIal_Adapter = pAdapter;
1212 pCurAdapter = gIal_Adapter;
1192 gIal_Adapter = pAdapter;
1193 pCurAdapter = gIal_Adapter;
1213 } else {
1194 }
1195 else {
1214 pCurAdapter->next = pAdapter;
1215 pCurAdapter = pAdapter;
1216 }
1217
1218 pAdapter->outstandingCommands = 0;
1219
1220 pMvSataAdapter = &(pAdapter->mvSataAdapter);
1221 _vbus_p->OsExt = (void *)pAdapter;
1222 pMvSataAdapter->IALData = pAdapter;
1223
1196 pCurAdapter->next = pAdapter;
1197 pCurAdapter = pAdapter;
1198 }
1199
1200 pAdapter->outstandingCommands = 0;
1201
1202 pMvSataAdapter = &(pAdapter->mvSataAdapter);
1203 _vbus_p->OsExt = (void *)pAdapter;
1204 pMvSataAdapter->IALData = pAdapter;
1205
1224 if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
1225 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT,
1226 MV_MAX_SEGMENTS, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
1227 &pAdapter->parent_dmat) != 0) {
1228 MV_ERROR("RR182x: Failed to create busdma resources\n");
1229 unlock_driver(oldspl);
1230 return (ENOMEM);
1206 if (bus_dma_tag_create(NULL,/* parent */
1207 4, /* alignment */
1208 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */
1209 BUS_SPACE_MAXADDR, /* lowaddr */
1210 BUS_SPACE_MAXADDR, /* highaddr */
1211 NULL, NULL, /* filter, filterarg */
1212 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */
1213 MAX_SG_DESCRIPTORS, /* nsegments */
1214 0x10000, /* maxsegsize */
1215 BUS_DMA_WAITOK, /* flags */
1216#if __FreeBSD_version>502000
1217 busdma_lock_mutex, /* lockfunc */
1218 &driver_lock, /* lockfuncarg */
1219#endif
1220 &pAdapter->io_dma_parent /* tag */))
1221 {
1222 return ENXIO;;
1231 }
1232
1223 }
1224
1233 if (bus_dma_tag_create(pAdapter->parent_dmat, PAGE_SIZE, 0,
1234 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1235 REQUESTS_ARRAY_SIZE, 1, REQUESTS_ARRAY_SIZE, 0, NULL, NULL,
1236 &pAdapter->req_dmat) != 0) {
1237 MV_ERROR("RR182x: Failed to create busdma resources\n");
1238 error = ENOMEM;
1239 goto unregister;
1240 }
1241
1225
1242 if (bus_dma_tag_create(pAdapter->parent_dmat, PAGE_SIZE, 0,
1243 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1244 RESPONSES_ARRAY_SIZE, 1, RESPONSES_ARRAY_SIZE, 0, NULL, NULL,
1245 &pAdapter->resp_dmat) != 0) {
1246 MV_ERROR("RR182x: Failed to create busdma resources\n");
1247 error = ENOMEM;
1248 goto unregister;
1249 }
1250
1251 if (bus_dma_tag_create(pAdapter->parent_dmat, 1, 0,
1252 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1253 MAXBSIZE, MV_MAX_SEGMENTS, MAXBSIZE, 0, busdma_lock_mutex, &Giant,
1254 &pAdapter->buf_dmat) != 0) {
1255 MV_ERROR("RR182x: Failed to create busdma resources\n");
1256 error = ENOMEM;
1257 goto unregister;
1258 }
1259
1260 if (hptmv_allocate_edma_queues(pAdapter)) {
1226 if (hptmv_allocate_edma_queues(pAdapter))
1227 {
1261 MV_ERROR("RR182x: Failed to allocate memory for EDMA queues\n");
1228 MV_ERROR("RR182x: Failed to allocate memory for EDMA queues\n");
1262 error = ENOMEM;
1263 goto unregister;
1229 unlock_driver(oldspl);
1230 return ENOMEM;
1264 }
1265
1266 /* also map EPROM address */
1267 rid = 0x10;
1231 }
1232
1233 /* also map EPROM address */
1234 rid = 0x10;
1268 if ((pAdapter->mem_res = bus_alloc_resource(pAdapter->hpt_dev,
1269 SYS_RES_MEMORY, &rid, 0, ~0, MV_SATA_PCI_BAR0_SPACE_SIZE+0x40000,
1270 RF_ACTIVE)) == 0) {
1235 if (!(pAdapter->mem_res = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, &rid,
1236 0, ~0, MV_SATA_PCI_BAR0_SPACE_SIZE+0x40000, RF_ACTIVE))
1237 ||
1238 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res)))
1239 {
1271 MV_ERROR("RR182x: Failed to remap memory space\n");
1240 MV_ERROR("RR182x: Failed to remap memory space\n");
1272 error = ENXIO;
1273 goto unregister;
1241 hptmv_free_edma_queues(pAdapter);
1242 unlock_driver(oldspl);
1243 return ENXIO;
1274 }
1244 }
1245 else
1246 {
1247 KdPrint(("RR182x: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress));
1248 }
1275
1249
1276 /*
1277 * This field is opaque. Abuse it so that the bus_space functions
1278 * can get the info that they need when called.
1279 */
1280 pMvSataAdapter->adapterIoBaseAddress = pAdapter;
1281 pAdapter->mem_bsh = rman_get_bushandle(pAdapter->mem_res);
1282 pAdapter->mem_btag = rman_get_bustag(pAdapter->mem_res);
1283
1284 pMvSataAdapter->adapterId = num_adapters++;
1285 /* get the revision ID */
1250 pMvSataAdapter->adapterId = num_adapters++;
1251 /* get the revision ID */
1286 pMvSataAdapter->pciConfigRevisionId =
1287 pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1);
1252 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1);
1288 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev);
1253 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev);
1289
1254
1290 /* init RR182x */
1291 pMvSataAdapter->intCoalThre[0]= 1;
1292 pMvSataAdapter->intCoalThre[1]= 1;
1293 pMvSataAdapter->intTimeThre[0] = 1;
1294 pMvSataAdapter->intTimeThre[1] = 1;
1295 pMvSataAdapter->pciCommand = 0x0107E371;
1296 pMvSataAdapter->pciSerrMask = 0xd77fe6ul;
1297 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul;
1298 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify;
1299
1255 /* init RR182x */
1256 pMvSataAdapter->intCoalThre[0]= 1;
1257 pMvSataAdapter->intCoalThre[1]= 1;
1258 pMvSataAdapter->intTimeThre[0] = 1;
1259 pMvSataAdapter->intTimeThre[1] = 1;
1260 pMvSataAdapter->pciCommand = 0x0107E371;
1261 pMvSataAdapter->pciSerrMask = 0xd77fe6ul;
1262 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul;
1263 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify;
1264
1300 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) {
1265 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE)
1266 {
1301 MV_ERROR("RR182x[%d]: core failed to initialize the adapter\n",
1267 MV_ERROR("RR182x[%d]: core failed to initialize the adapter\n",
1302 pMvSataAdapter->adapterId);
1303 error = ENXIO;
1304 goto unregister;
1268 pMvSataAdapter->adapterId);
1269unregister:
1270 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res);
1271 hptmv_free_edma_queues(pAdapter);
1272 unlock_driver(oldspl);
1273 return ENXIO;
1305 }
1306 pAdapter->ver_601 = pMvSataAdapter->pcbVersion;
1307
1308#ifndef FOR_DEMO
1309 set_fail_leds(pMvSataAdapter, 0);
1310#endif
1311
1312 /* setup command blocks */
1313 KdPrint(("Allocate command blocks\n"));
1314 _vbus_(pFreeCommands) = 0;
1274 }
1275 pAdapter->ver_601 = pMvSataAdapter->pcbVersion;
1276
1277#ifndef FOR_DEMO
1278 set_fail_leds(pMvSataAdapter, 0);
1279#endif
1280
1281 /* setup command blocks */
1282 KdPrint(("Allocate command blocks\n"));
1283 _vbus_(pFreeCommands) = 0;
1315 pAdapter->pCommandBlocks = malloc(sizeof(struct _Command) *
1316 MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_ZERO | M_WAITOK);
1317 KdPrint(("pCommandBlocks:%p\n", pAdapter->pCommandBlocks));
1284 pAdapter->pCommandBlocks =
1285 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT);
1286 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks));
1287 if (!pAdapter->pCommandBlocks) {
1288 MV_ERROR("insufficient memory\n");
1289 goto unregister;
1290 }
1318
1291
1319 /*
1320 * Gotta cheat here. The _Command struct only gives us a single
1321 * pointer for private data, but we need to store more than that.
1322 * Of course the pCommand retains no type stability, and FreeCommand
1323 * is hidden in the binary object, so gotta track these on our own
1324 * list.
1325 */
1326 pAdapter->pPrivateBlocks = malloc(sizeof(struct _privCommand) *
1327 MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_ZERO | M_WAITOK);
1328 TAILQ_INIT(&pAdapter->PrivCmdTQH);
1329
1330 for (i = 0; i < MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) {
1331 pCmd = &pAdapter->pCommandBlocks[i];
1332 prvCmd = &pAdapter->pPrivateBlocks[i];
1333 prvCmd->pAdapter = pAdapter;
1334 if ((error = bus_dmamap_create(pAdapter->buf_dmat, 0,
1335 &prvCmd->buf_map)) == 0) {
1336 FreeCommand(_VBUS_P (pCmd));
1337 FreePrivCommand(pAdapter, prvCmd);
1338 } else
1339 break;
1292 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) {
1293 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i]));
1340 }
1341
1294 }
1295
1342 /* setup PRD Tables */
1343 KdPrint(("Allocate PRD Tables\n"));
1344 pAdapter->pFreePRDLink = 0;
1345
1346 if (bus_dma_tag_create(pAdapter->parent_dmat, PAGE_SIZE, 0,
1347 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1348 PRD_ENTRIES_SIZE * PRD_TABLES_FOR_VBUS, 1,
1349 PRD_ENTRIES_SIZE * PRD_TABLES_FOR_VBUS, 0, NULL, NULL,
1350 &pAdapter->prd_dmat) != 0) {
1351 MV_ERROR("RR182x: Failed to create busdma resources\n");
1352 error = ENOMEM;
1296 /*Set up the bus_dmamap*/
1297 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT);
1298 if(!pAdapter->pbus_dmamap) {
1299 MV_ERROR("insufficient memory\n");
1300 free(pAdapter->pCommandBlocks, M_DEVBUF);
1353 goto unregister;
1354 }
1355
1301 goto unregister;
1302 }
1303
1356 if (bus_dmamem_alloc(pAdapter->prd_dmat,
1357 (void **)&pAdapter->prdTableAddr, BUS_DMA_WAITOK,
1358 &pAdapter->prd_map) != 0)
1359 goto unregister;
1304 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM);
1305 pAdapter->pbus_dmamap_list = 0;
1306 for (i=0; i < MAX_QUEUE_COMM; i++) {
1307 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]);
1308 pmap->pAdapter = pAdapter;
1309 dmamap_put(pmap);
1360
1310
1361 (void)bus_dmamap_load(pAdapter->prd_dmat, pAdapter->prd_map,
1362 pAdapter->prdTableAddr, PRD_ENTRIES_SIZE * PRD_TABLES_FOR_VBUS,
1363 hptmv_map_req, &pAdapter->prdTableDmaAddr, 0);
1364
1311 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) {
1312 MV_ERROR("Can not allocate dma map\n");
1313 free(pAdapter->pCommandBlocks, M_DEVBUF);
1314 free(pAdapter->pbus_dmamap, M_DEVBUF);
1315 goto unregister;
1316 }
1317 }
1318 /* setup PRD Tables */
1319 KdPrint(("Allocate PRD Tables\n"));
1320 pAdapter->pFreePRDLink = 0;
1321
1322 pAdapter->prdTableAddr = (PUCHAR)contigmalloc(
1323 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
1324
1365 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr));
1366 if (!pAdapter->prdTableAddr) {
1367 MV_ERROR("insufficient PRD Tables\n");
1325 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr));
1326 if (!pAdapter->prdTableAddr) {
1327 MV_ERROR("insufficient PRD Tables\n");
1368 error = ENOMEM;
1369 goto unregister;
1370 }
1328 goto unregister;
1329 }
1371
1372 PRDTable = pAdapter->prdTableAddr;
1373 for (i = 0; i < PRD_TABLES_FOR_VBUS; i++) {
1374 KdPrint(("i= %d, pAdapter->pFreePRDLink= %p\n", i,
1375 pAdapter->pFreePRDLink));
1376 FreePRDTable(pAdapter, PRDTable);
1377 PRDTable += PRD_ENTRIES_SIZE;
1330 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL);
1331 {
1332 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr;
1333 for (i=0; i<PRD_TABLES_FOR_VBUS; i++)
1334 {
1335/* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */
1336 FreePRDTable(pAdapter, PRDTable);
1337 PRDTable += PRD_ENTRIES_SIZE;
1338 }
1378 }
1379
1380 /* enable the adapter interrupts */
1381
1382 /* configure and start the connected channels*/
1339 }
1340
1341 /* enable the adapter interrupts */
1342
1343 /* configure and start the connected channels*/
1383 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1344 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++)
1345 {
1384 pAdapter->mvChannel[channel].online = MV_FALSE;
1385 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel)
1346 pAdapter->mvChannel[channel].online = MV_FALSE;
1347 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel)
1386 != MV_TRUE)
1387 continue;
1348 == MV_TRUE)
1349 {
1350 KdPrint(("RR182x[%d]: channel %d is connected\n",
1351 pMvSataAdapter->adapterId, channel));
1388
1352
1389 KdPrint(("RR182x[%d]: channel %d is connected\n",
1390 pMvSataAdapter->adapterId, channel));
1391
1392 if (hptmv_init_channel(pAdapter, channel) == 0) {
1393 if (mvSataConfigureChannel(pMvSataAdapter, channel)
1394 == MV_FALSE) {
1395 MV_ERROR("RR182x[%d]: Failed to configure "
1396 "channel %d\n", pMvSataAdapter->adapterId,
1397 channel);
1398 hptmv_free_channel(pAdapter, channel);
1399 continue;
1353 if (hptmv_init_channel(pAdapter, channel) == 0)
1354 {
1355 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE)
1356 {
1357 MV_ERROR("RR182x[%d]: Failed to configure channel"
1358 " %d\n",pMvSataAdapter->adapterId, channel);
1359 hptmv_free_channel(pAdapter, channel);
1360 }
1361 else
1362 {
1363 if (start_channel(pAdapter, channel))
1364 {
1365 MV_ERROR("RR182x[%d]: Failed to start channel,"
1366 " channel=%d\n",pMvSataAdapter->adapterId,
1367 channel);
1368 hptmv_free_channel(pAdapter, channel);
1369 }
1370 pAdapter->mvChannel[channel].online = MV_TRUE;
1371 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter,
1372 channel,
1373 MV_TRUE);*/
1374 }
1400 }
1375 }
1401 if (start_channel(pAdapter, channel)) {
1402 MV_ERROR("RR182x[%d]: Failed to start channel, "
1403 "channel=%d\n", pMvSataAdapter->adapterId,
1404 channel);
1405 hptmv_free_channel(pAdapter, channel);
1406 }
1407 pAdapter->mvChannel[channel].online = MV_TRUE;
1408#if 0
1409 mvSataChannelSetEdmaLoopBackMode(
1410 pMvSataAdapter, channel, MV_TRUE);
1411#endif
1412 }
1413 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n",
1414 pAdapter->mvChannel[channel].online, channel));
1415 }
1416
1417#ifdef SUPPORT_ARRAY
1418 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) {
1419 pVDev = ArrayTables(i);
1420 mArFreeArrayTable(pVDev);
1421 }
1422#endif
1423
1424 KdPrint(("Initialize Devices\n"));
1425 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1376 }
1377 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n",
1378 pAdapter->mvChannel[channel].online, channel));
1379 }
1380
1381#ifdef SUPPORT_ARRAY
1382 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) {
1383 pVDev = ArrayTables(i);
1384 mArFreeArrayTable(pVDev);
1385 }
1386#endif
1387
1388 KdPrint(("Initialize Devices\n"));
1389 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1426 MV_SATA_CHANNEL *pMvSataChannel;
1427
1428 pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1390 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1429 if (pMvSataChannel) {
1430 init_vdev_params(pAdapter, channel);
1431 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk);
1432 }
1433 }
1434#ifdef SUPPORT_ARRAY
1435 CheckArrayCritical(_VBUS_P0);
1436#endif

--- 4 unchanged lines hidden (view full) ---

1441 pVDev = _vbus_p->pVDevice[channel];
1442 if (pVDev && pVDev->vf_online)
1443 fCheckBootable(pVDev);
1444 }
1445
1446#if defined(SUPPORT_ARRAY) && defined(_RAID5N_)
1447 init_raid5_memory(_VBUS_P0);
1448 _vbus_(r5).enable_write_back = 1;
1391 if (pMvSataChannel) {
1392 init_vdev_params(pAdapter, channel);
1393 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk);
1394 }
1395 }
1396#ifdef SUPPORT_ARRAY
1397 CheckArrayCritical(_VBUS_P0);
1398#endif

--- 4 unchanged lines hidden (view full) ---

1403 pVDev = _vbus_p->pVDevice[channel];
1404 if (pVDev && pVDev->vf_online)
1405 fCheckBootable(pVDev);
1406 }
1407
1408#if defined(SUPPORT_ARRAY) && defined(_RAID5N_)
1409 init_raid5_memory(_VBUS_P0);
1410 _vbus_(r5).enable_write_back = 1;
1449 printf("RR182x: RAID5 write-back %s\n",
1450 _vbus_(r5).enable_write_back? "enabled" : "disabled");
1411 printf("RR182x: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled");
1451#endif
1452
1453 mvSataUnmaskAdapterInterrupt(pMvSataAdapter);
1454 unlock_driver(oldspl);
1455 return 0;
1412#endif
1413
1414 mvSataUnmaskAdapterInterrupt(pMvSataAdapter);
1415 unlock_driver(oldspl);
1416 return 0;
1456
1457unregister:
1458 if (pAdapter->mem_res != 0)
1459 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid,
1460 pAdapter->mem_res);
1461
1462 hptmv_free_edma_queues(pAdapter);
1463
1464 if (pAdapter->resp_dmat != NULL)
1465 bus_dma_tag_destroy(pAdapter->resp_dmat);
1466 if (pAdapter->req_dmat != NULL)
1467 bus_dma_tag_destroy(pAdapter->req_dmat);
1468 if (pAdapter->buf_dmat != NULL)
1469 bus_dma_tag_destroy(pAdapter->buf_dmat);
1470 if (pAdapter->parent_dmat != NULL)
1471 bus_dma_tag_destroy(pAdapter->parent_dmat);
1472
1473 unlock_driver(oldspl);
1474 return error;
1475}
1476
1477int
1478MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel)
1479{
1417}
1418
1419int
1420MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel)
1421{
1480 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData;
1422 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData;
1481
1482 mvSataDisableChannelDma(pMvSataAdapter, channel);
1423
1424 mvSataDisableChannelDma(pMvSataAdapter, channel);
1483
1484 /* Flush pending commands */
1485 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1486
1487 /* Software reset channel */
1425 /* Flush pending commands */
1426 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1427
1428 /* Software reset channel */
1488 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) ==
1489 MV_FALSE) {
1429 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE)
1430 {
1490 MV_ERROR("RR182x [%d,%d]: failed to perform Software reset\n",
1431 MV_ERROR("RR182x [%d,%d]: failed to perform Software reset\n",
1491 pMvSataAdapter->adapterId, channel);
1432 pMvSataAdapter->adapterId, channel);
1433 hptmv_free_channel(pAdapter, channel);
1492 return -1;
1493 }
1494
1495 /* Hardware reset channel */
1434 return -1;
1435 }
1436
1437 /* Hardware reset channel */
1496 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) {
1497 MV_ERROR("RR182x [%d,%d] Failed to Hard reser the SATA "
1498 "channel\n", pMvSataAdapter->adapterId, channel);
1438 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE)
1439 {
1440 MV_ERROR("RR182x [%d,%d] Failed to Hard reser the SATA channel\n",
1441 pMvSataAdapter->adapterId, channel);
1499 hptmv_free_channel(pAdapter, channel);
1500 return -1;
1501 }
1502
1442 hptmv_free_channel(pAdapter, channel);
1443 return -1;
1444 }
1445
1503 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) ==
1504 MV_FALSE) {
1505 MV_ERROR("RR182x [%d,%d] Failed to Connect Device\n",
1506 pMvSataAdapter->adapterId, channel);
1446 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE)
1447 {
1448 MV_ERROR("RR182x [%d,%d] Failed to Connect Device\n",
1449 pMvSataAdapter->adapterId, channel);
1507 hptmv_free_channel(pAdapter, channel);
1508 return -1;
1450 hptmv_free_channel(pAdapter, channel);
1451 return -1;
1509 } else {
1452 }else
1453 {
1454 MV_ERROR("channel %d: perform recalibrate command", channel);
1455 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1456 MV_NON_UDMA_PROTOCOL_NON_DATA,
1457 MV_FALSE,
1458 NULL, /* pBuffer*/
1459 0, /* count */
1460 0, /*features*/
1461 /* sectorCount */
1462 0,
1463 0, /* lbaLow */
1464 0, /* lbaMid */
1465 /* lbaHigh */
1466 0,
1467 0, /* device */
1468 /* command */
1469 0x10))
1470 MV_ERROR("channel %d: recalibrate failed", channel);
1471
1510 /* Set transfer mode */
1511 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1472 /* Set transfer mode */
1473 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1512 MV_ATA_SET_FEATURES_TRANSFER, MV_ATA_TRANSFER_PIO_SLOW, 0,
1513 0, 0) == MV_FALSE) ||
1514 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1515 MV_ATA_SET_FEATURES_TRANSFER,
1516 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0)
1517 == MV_FALSE) || (mvStorageDevATASetFeatures(pMvSataAdapter,
1518 channel, MV_ATA_SET_FEATURES_TRANSFER,
1519 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0,
1520 0, 0) == MV_FALSE)) {
1474 MV_ATA_SET_FEATURES_TRANSFER,
1475 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) ||
1476 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1477 MV_ATA_SET_FEATURES_TRANSFER,
1478 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) ||
1479 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1480 MV_ATA_SET_FEATURES_TRANSFER,
1481 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) )
1482 {
1521 MV_ERROR("channel %d: Set Features failed", channel);
1522 hptmv_free_channel(pAdapter, channel);
1523 return -1;
1524 }
1525 /* Enable EDMA */
1483 MV_ERROR("channel %d: Set Features failed", channel);
1484 hptmv_free_channel(pAdapter, channel);
1485 return -1;
1486 }
1487 /* Enable EDMA */
1526 if (mvSataEnableChannelDma(pMvSataAdapter, channel)==MV_FALSE) {
1488 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE)
1489 {
1527 MV_ERROR("Failed to enable DMA, channel=%d", channel);
1528 hptmv_free_channel(pAdapter, channel);
1529 return -1;
1530 }
1531 }
1532 return 0;
1533}
1534
1535static int
1536fResetActiveCommands(PVBus _vbus_p)
1537{
1490 MV_ERROR("Failed to enable DMA, channel=%d", channel);
1491 hptmv_free_channel(pAdapter, channel);
1492 return -1;
1493 }
1494 }
1495 return 0;
1496}
1497
1498static int
1499fResetActiveCommands(PVBus _vbus_p)
1500{
1538 MV_SATA_ADAPTER *pMvSataAdapter;
1501 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1539 MV_U8 channel;
1502 MV_U8 channel;
1540 int rtn = 0;
1541
1542 pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1543 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) {
1503 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) {
1544 if (pMvSataAdapter->sataChannel[channel] &&
1545 pMvSataAdapter->sataChannel[channel]->outstandingCommands)
1546 if (MvSataResetChannel(pMvSataAdapter,channel) == -1)
1547 rtn = -1;
1504 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands)
1505 MvSataResetChannel(pMvSataAdapter,channel);
1548 }
1506 }
1549 HPT_ASSERT(rtn==0);
1550 return 0;
1551}
1552
1507 return 0;
1508}
1509
1553void
1554fCompleteAllCommandsSynchronously(PVBus _vbus_p)
1510void fCompleteAllCommandsSynchronously(PVBus _vbus_p)
1555{
1556 UINT cont;
1557 ULONG ticks = 0;
1558 MV_U8 channel;
1511{
1512 UINT cont;
1513 ULONG ticks = 0;
1514 MV_U8 channel;
1559 MV_SATA_ADAPTER *pMvSataAdapter;
1515 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1560 MV_SATA_CHANNEL *pMvSataChannel;
1561
1516 MV_SATA_CHANNEL *pMvSataChannel;
1517
1562 pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1563 do {
1564check_cmds:
1565 cont = 0;
1566 CheckPendingCall(_VBUS_P0);
1567#ifdef _RAID5N_
1568 dataxfer_poll();
1569 xor_poll();
1570#endif
1518 do {
1519check_cmds:
1520 cont = 0;
1521 CheckPendingCall(_VBUS_P0);
1522#ifdef _RAID5N_
1523 dataxfer_poll();
1524 xor_poll();
1525#endif
1571 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1526 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) {
1572 pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1527 pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1573 if (pMvSataChannel &&
1574 pMvSataChannel->outstandingCommands) {
1528 if (pMvSataChannel && pMvSataChannel->outstandingCommands)
1529 {
1575 while (pMvSataChannel->outstandingCommands) {
1530 while (pMvSataChannel->outstandingCommands) {
1576 if (!mvSataInterruptServiceRoutine(
1577 pMvSataAdapter)) {
1531 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) {
1578 StallExec(1000);
1579 if (ticks++ > 3000) {
1532 StallExec(1000);
1533 if (ticks++ > 3000) {
1580 MvSataResetChannel(
1581 pMvSataAdapter,
1582 channel);
1534 MvSataResetChannel(pMvSataAdapter,channel);
1583 goto check_cmds;
1584 }
1535 goto check_cmds;
1536 }
1585 } else
1537 }
1538 else
1586 ticks = 0;
1587 }
1588 cont = 1;
1589 }
1590 }
1591 } while (cont);
1592}
1593

--- 12 unchanged lines hidden (view full) ---

1606 fCompleteAllCommandsSynchronously(_vbus_p);
1607
1608 /* Now there should be no pending commands. No more action needed. */
1609 CheckIdleCall(_VBUS_P0);
1610
1611 KdPrint(("fMvResetBus() done"));
1612}
1613
1539 ticks = 0;
1540 }
1541 cont = 1;
1542 }
1543 }
1544 } while (cont);
1545}
1546

--- 12 unchanged lines hidden (view full) ---

1559 fCompleteAllCommandsSynchronously(_vbus_p);
1560
1561 /* Now there should be no pending commands. No more action needed. */
1562 CheckIdleCall(_VBUS_P0);
1563
1564 KdPrint(("fMvResetBus() done"));
1565}
1566
1567/*No rescan function*/
1614void
1615fRescanAllDevice(_VBUS_ARG0)
1616{
1617}
1618
1619static MV_BOOLEAN
1568void
1569fRescanAllDevice(_VBUS_ARG0)
1570{
1571}
1572
1573static MV_BOOLEAN
1620CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channelNum,
1621 MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, MV_U16 responseFlags,
1622 MV_U32 timeStamp, MV_STORAGE_DEVICE_REGISTERS *registerStruct)
1574CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
1575 MV_U8 channelNum,
1576 MV_COMPLETION_TYPE comp_type,
1577 MV_VOID_PTR commandId,
1578 MV_U16 responseFlags,
1579 MV_U32 timeStamp,
1580 MV_STORAGE_DEVICE_REGISTERS *registerStruct)
1623{
1624 PCommand pCmd = (PCommand) commandId;
1625 _VBUS_INST(pCmd->pVDevice->pVBus)
1626
1627 if (pCmd->uScratch.sata_param.prdAddr)
1581{
1582 PCommand pCmd = (PCommand) commandId;
1583 _VBUS_INST(pCmd->pVDevice->pVBus)
1584
1585 if (pCmd->uScratch.sata_param.prdAddr)
1628 FreePRDTable(pMvSataAdapter->IALData,
1629 pCmd->uScratch.sata_param.prdAddr);
1586 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr);
1630
1587
1631 switch (comp_type) {
1588 switch (comp_type)
1589 {
1632 case MV_COMPLETION_TYPE_NORMAL:
1633 pCmd->Result = RETURN_SUCCESS;
1634 break;
1635 case MV_COMPLETION_TYPE_ABORT:
1636 pCmd->Result = RETURN_BUS_RESET;
1637 break;
1638 case MV_COMPLETION_TYPE_ERROR:
1590 case MV_COMPLETION_TYPE_NORMAL:
1591 pCmd->Result = RETURN_SUCCESS;
1592 break;
1593 case MV_COMPLETION_TYPE_ABORT:
1594 pCmd->Result = RETURN_BUS_RESET;
1595 break;
1596 case MV_COMPLETION_TYPE_ERROR:
1639 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, "
1640 "flags=%x\n", pMvSataAdapter->adapterId, channelNum,
1641 responseFlags);
1597 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n",
1598 pMvSataAdapter->adapterId, channelNum, responseFlags);
1642
1643 if (responseFlags & 4) {
1599
1600 if (responseFlags & 4) {
1644 MV_ERROR("ATA regs: error %x, sector count %x, LBA low "
1645 "%x, LBA mid %x, LBA high %x, device %x, "
1646 "status %x\n", registerStruct->errorRegister,
1647 registerStruct->sectorCountRegister,
1648 registerStruct->lbaLowRegister,
1649 registerStruct->lbaMidRegister,
1650 registerStruct->lbaHighRegister,
1651 registerStruct->deviceRegister,
1652 registerStruct->statusRegister);
1601 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x,"
1602 " LBA high %x, device %x, status %x\n",
1603 registerStruct->errorRegister,
1604 registerStruct->sectorCountRegister,
1605 registerStruct->lbaLowRegister,
1606 registerStruct->lbaMidRegister,
1607 registerStruct->lbaHighRegister,
1608 registerStruct->deviceRegister,
1609 registerStruct->statusRegister);
1653 }
1610 }
1654 /*
1655 * We can't do handleEdmaError directly here, because
1656 * CommandCompletionCB is called by mv's ISR, if we retry the
1657 * command, than the internel data structure may be destroyed
1658 */
1611 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by
1612 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/
1659 pCmd->uScratch.sata_param.responseFlags = responseFlags;
1613 pCmd->uScratch.sata_param.responseFlags = responseFlags;
1660 pCmd->uScratch.sata_param.bIdeStatus =
1661 registerStruct->statusRegister;
1662 pCmd->uScratch.sata_param.errorRegister =
1663 registerStruct->errorRegister;
1614 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister;
1615 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister;
1664 pCmd->pVDevice->u.disk.QueueLength--;
1665 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd);
1666 return TRUE;
1667
1668 default:
1669 MV_ERROR(" Unknown completion type (%d)\n", comp_type);
1670 return MV_FALSE;
1671 }
1672
1616 pCmd->pVDevice->u.disk.QueueLength--;
1617 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd);
1618 return TRUE;
1619
1620 default:
1621 MV_ERROR(" Unknown completion type (%d)\n", comp_type);
1622 return MV_FALSE;
1623 }
1624
1673 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY &&
1674 pCmd->uScratch.sata_param.cmd_priv > 1) {
1625 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) {
1675 pCmd->uScratch.sata_param.cmd_priv --;
1676 return TRUE;
1677 }
1678 pCmd->pVDevice->u.disk.QueueLength--;
1679 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1680 return TRUE;
1681}
1682
1683void
1684fDeviceSendCommand(_VBUS_ARG PCommand pCmd)
1685{
1626 pCmd->uScratch.sata_param.cmd_priv --;
1627 return TRUE;
1628 }
1629 pCmd->pVDevice->u.disk.QueueLength--;
1630 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1631 return TRUE;
1632}
1633
1634void
1635fDeviceSendCommand(_VBUS_ARG PCommand pCmd)
1636{
1686 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0;
1637 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0;
1687 MV_SATA_ADAPTER *pMvSataAdapter;
1688 MV_SATA_CHANNEL *pMvSataChannel;
1638 MV_SATA_ADAPTER *pMvSataAdapter;
1639 MV_SATA_CHANNEL *pMvSataChannel;
1689 IAL_ADAPTER_T *pAdapter;
1640 PVDevice pVDevice = pCmd->pVDevice;
1641 PDevice pDevice = &pVDevice->u.disk;
1642 ULONG Lba = pCmd->uCmd.Ide.Lba;
1643 USHORT nSector = pCmd->uCmd.Ide.nSectors;
1644
1690 MV_QUEUE_COMMAND_RESULT result;
1691 MV_QUEUE_COMMAND_INFO commandInfo;
1645 MV_QUEUE_COMMAND_RESULT result;
1646 MV_QUEUE_COMMAND_INFO commandInfo;
1692 MV_UDMA_COMMAND_PARAMS *pUdmaParams;
1693 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams;
1694 MV_BOOLEAN is48bit = MV_FALSE;
1695 PVDevice pVDevice;
1696 PDevice pDevice;
1697 ULONG Lba;
1698 USHORT nSector;
1699 MV_U8 channel;
1700 int i=0;
1647 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand;
1648 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand;
1701
1649
1702 pVDevice = pCmd->pVDevice;
1703 pDevice = &pVDevice->u.disk;
1704 Lba = pCmd->uCmd.Ide.Lba;
1705 nSector = pCmd->uCmd.Ide.nSectors;
1706 pUdmaParams = &commandInfo.commandParams.udmaCommand;
1707 pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand;
1708
1650 MV_BOOLEAN is48bit = MV_FALSE;
1651 MV_U8 channel;
1652 int i=0;
1653
1709 DECLARE_BUFFER(FPSCAT_GATH, tmpSg);
1710
1711 if (!pDevice->df_on_line) {
1712 MV_ERROR("Device is offline");
1713 pCmd->Result = RETURN_BAD_DEVICE;
1714 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1715 return;
1716 }
1717
1718 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors;
1719 pMvSataChannel = pDevice->mv;
1720 pMvSataAdapter = pMvSataChannel->mvSataAdapter;
1721 channel = pMvSataChannel->channelNumber;
1654 DECLARE_BUFFER(FPSCAT_GATH, tmpSg);
1655
1656 if (!pDevice->df_on_line) {
1657 MV_ERROR("Device is offline");
1658 pCmd->Result = RETURN_BAD_DEVICE;
1659 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1660 return;
1661 }
1662
1663 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors;
1664 pMvSataChannel = pDevice->mv;
1665 pMvSataAdapter = pMvSataChannel->mvSataAdapter;
1666 channel = pMvSataChannel->channelNumber;
1722 pAdapter = pMvSataAdapter->IALData;
1723
1667
1724 /*
1725 * Old RAID0 has hidden lba. Remember to clear dDeHiddenLba when
1726 * deleting array!
1727 */
1668 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */
1728 Lba += pDevice->dDeHiddenLba;
1729 /* check LBA */
1730 if (Lba+nSector-1 > pDevice->dDeRealCapacity) {
1731 pCmd->Result = RETURN_INVALID_REQUEST;
1732 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1733 return;
1734 }
1735
1736 if(Lba & 0xF0000000){
1737 is48bit = MV_TRUE;
1738 }
1739
1669 Lba += pDevice->dDeHiddenLba;
1670 /* check LBA */
1671 if (Lba+nSector-1 > pDevice->dDeRealCapacity) {
1672 pCmd->Result = RETURN_INVALID_REQUEST;
1673 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1674 return;
1675 }
1676
1677 if(Lba & 0xF0000000){
1678 is48bit = MV_TRUE;
1679 }
1680
1740 switch (pCmd->uCmd.Ide.Command) {
1681 switch (pCmd->uCmd.Ide.Command)
1682 {
1741 case IDE_COMMAND_READ:
1742 case IDE_COMMAND_WRITE:
1743 if (pDevice->bDeModeSetting<8) goto pio;
1744
1745 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA;
1746 pUdmaParams->isEXT = is48bit;
1747 pUdmaParams->numOfSectors = nSector;
1748 pUdmaParams->lowLBAAddress = Lba;
1749 pUdmaParams->highLBAAddress = 0;
1750 pUdmaParams->prdHighAddr = 0;
1751 pUdmaParams->callBack = CommandCompletionCB;
1752 pUdmaParams->commandId = (MV_VOID_PTR )pCmd;
1753 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ)
1754 pUdmaParams->readWrite = MV_UDMA_TYPE_READ;
1755 else
1756 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE;
1757
1758 if (pCmd->pSgTable && pCmd->cf_physical_sg) {
1759 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1683 case IDE_COMMAND_READ:
1684 case IDE_COMMAND_WRITE:
1685 if (pDevice->bDeModeSetting<8) goto pio;
1686
1687 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA;
1688 pUdmaParams->isEXT = is48bit;
1689 pUdmaParams->numOfSectors = nSector;
1690 pUdmaParams->lowLBAAddress = Lba;
1691 pUdmaParams->highLBAAddress = 0;
1692 pUdmaParams->prdHighAddr = 0;
1693 pUdmaParams->callBack = CommandCompletionCB;
1694 pUdmaParams->commandId = (MV_VOID_PTR )pCmd;
1695 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ)
1696 pUdmaParams->readWrite = MV_UDMA_TYPE_READ;
1697 else
1698 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE;
1699
1700 if (pCmd->pSgTable && pCmd->cf_physical_sg) {
1701 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1760 do {
1761 *sg1++=*sg2;
1762 } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1763 } else if (!pCmd->pfnBuildSgl ||
1764 !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) {
1702 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1703 }
1704 else {
1705 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) {
1765pio:
1706pio:
1766 mvSataDisableChannelDma(pMvSataAdapter, channel);
1767 mvSataFlushDmaQueue(pMvSataAdapter, channel,
1768 MV_FLUSH_TYPE_CALLBACK);
1769
1770 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) {
1771 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1772 do {
1773 *sg1++=*sg2;
1774 } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1775 } else if (!pCmd->pfnBuildSgl ||
1776 !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)){
1777 pCmd->Result = RETURN_NEED_LOGICAL_SG;
1778 goto finish_cmd;
1779 }
1780
1781 do {
1782 ULONG size;
1783 ULONG_PTR addr = tmpSg->dSgAddress;
1784
1785 size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000;
1786 if (size & 0x1ff) {
1787 pCmd->Result = RETURN_INVALID_REQUEST;
1788 goto finish_cmd;
1707 mvSataDisableChannelDma(pMvSataAdapter, channel);
1708 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1709
1710 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) {
1711 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1712 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1789 }
1713 }
1790 if (mvStorageDevATAExecuteNonUDMACommand(
1791 pMvSataAdapter, channel,
1792 (pCmd->cf_data_out) ?
1793 MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT :
1794 MV_NON_UDMA_PROTOCOL_PIO_DATA_IN,
1795 is48bit, (MV_U16_PTR)addr,
1796 size >> 1, /* count */
1797 0, /* features N/A */
1798 (MV_U16)(size>>9), /*sector count*/
1799 (MV_U16)((is48bit ?
1800 (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) |
1801 (UCHAR)(Lba & 0xFF) ), /*lbalow*/
1802 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */
1803 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHig */
1804 (MV_U8)(0x40 | (is48bit ? 0 :
1805 (UCHAR)(Lba >> 24) & 0xFF )),/* device */
1806 (MV_U8)(is48bit ? (pCmd->cf_data_in ?
1807 IDE_COMMAND_READ_EXT :
1808 IDE_COMMAND_WRITE_EXT) :
1809 pCmd->uCmd.Ide.Command))==MV_FALSE) {
1810 pCmd->Result = RETURN_IDE_ERROR;
1811 goto finish_cmd;
1714 else {
1715 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) {
1716 pCmd->Result = RETURN_NEED_LOGICAL_SG;
1717 goto finish_cmd;
1718 }
1812 }
1719 }
1813 Lba += size>>9;
1814 if(Lba & 0xF0000000) is48bit = MV_TRUE;
1815 }
1816 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1817 pCmd->Result = RETURN_SUCCESS;
1720
1721 do {
1722 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000;
1723 ULONG_PTR addr = tmpSg->dSgAddress;
1724 if (size & 0x1ff) {
1725 pCmd->Result = RETURN_INVALID_REQUEST;
1726 goto finish_cmd;
1727 }
1728 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1729 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN,
1730 is48bit,
1731 (MV_U16_PTR)addr,
1732 size >> 1, /* count */
1733 0, /* features N/A */
1734 (MV_U16)(size>>9), /*sector count*/
1735 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/
1736 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */
1737 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */
1738 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */
1739 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command)
1740 )==MV_FALSE)
1741 {
1742 pCmd->Result = RETURN_IDE_ERROR;
1743 goto finish_cmd;
1744 }
1745 Lba += size>>9;
1746 if(Lba & 0xF0000000) is48bit = MV_TRUE;
1747 }
1748 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1749 pCmd->Result = RETURN_SUCCESS;
1818finish_cmd:
1750finish_cmd:
1819 mvSataEnableChannelDma(pMvSataAdapter,channel);
1820 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion,
1821 pCmd);
1822 return;
1751 mvSataEnableChannelDma(pMvSataAdapter,channel);
1752 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1753 return;
1754 }
1823 }
1824
1755 }
1756
1825 pPRDTable = AllocatePRDTable(pAdapter);
1757 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData);
1826 KdPrint(("pPRDTable:%p\n",pPRDTable));
1827 if (!pPRDTable) {
1828 pCmd->Result = RETURN_DEVICE_BUSY;
1758 KdPrint(("pPRDTable:%p\n",pPRDTable));
1759 if (!pPRDTable) {
1760 pCmd->Result = RETURN_DEVICE_BUSY;
1829 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion,
1830 pCmd);
1761 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1831 HPT_ASSERT(0);
1832 return;
1833 }
1834
1762 HPT_ASSERT(0);
1763 return;
1764 }
1765
1835 do {
1836 pPRDTable[i].highBaseAddr = 0;
1766 do{
1767 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0);
1837 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag;
1838 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize;
1839 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress;
1840 pPRDTable[i].reserved = 0;
1841 i++;
1768 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag;
1769 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize;
1770 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress;
1771 pPRDTable[i].reserved = 0;
1772 i++;
1842 } while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1773 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1843
1774
1844 pUdmaParams->prdLowAddr = pAdapter->prdTableDmaAddr +
1845 ((ULONG)pPRDTable - (ULONG)pAdapter->prdTableAddr);
1846
1847 if ((pUdmaParams->numOfSectors == 256) &&
1848 (pMvSataChannel->lba48Address == MV_FALSE)) {
1775 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable);
1776 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) {
1849 pUdmaParams->numOfSectors = 0;
1850 }
1851
1852 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable;
1853
1777 pUdmaParams->numOfSectors = 0;
1778 }
1779
1780 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable;
1781
1854 result = mvSataQueueCommand(pMvSataAdapter, channel,
1855 &commandInfo);
1782 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1856
1783
1857 if (result != MV_QUEUE_COMMAND_RESULT_OK) {
1784 if (result != MV_QUEUE_COMMAND_RESULT_OK)
1785 {
1858queue_failed:
1786queue_failed:
1859 switch (result) {
1787 switch (result)
1788 {
1860 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS:
1789 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS:
1861 MV_ERROR("IAL Error: Edma Queue command "
1862 "failed. Bad LBA LBA[31:0](0x%08x)\n",
1863 pUdmaParams->lowLBAAddress);
1790 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA "
1791 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress);
1864 pCmd->Result = RETURN_IDE_ERROR;
1865 break;
1866 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED:
1792 pCmd->Result = RETURN_IDE_ERROR;
1793 break;
1794 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED:
1867 MV_ERROR("IAL Error: Edma Queue command "
1868 "failed. EDMA disabled adapter %d "
1869 "channel %d\n",
1870 pMvSataAdapter->adapterId, channel);
1795 MV_ERROR("IAL Error: Edma Queue command failed. EDMA"
1796 " disabled adapter %d channel %d\n",
1797 pMvSataAdapter->adapterId, channel);
1871 mvSataEnableChannelDma(pMvSataAdapter,channel);
1872 pCmd->Result = RETURN_IDE_ERROR;
1873 break;
1874 case MV_QUEUE_COMMAND_RESULT_FULL:
1798 mvSataEnableChannelDma(pMvSataAdapter,channel);
1799 pCmd->Result = RETURN_IDE_ERROR;
1800 break;
1801 case MV_QUEUE_COMMAND_RESULT_FULL:
1875 MV_ERROR("IAL Error: Edma Queue command "
1876 "failed. Queue is Full adapter %d "
1877 "channel %d\n",
1878 pMvSataAdapter->adapterId, channel);
1802 MV_ERROR("IAL Error: Edma Queue command failed. Queue is"
1803 " Full adapter %d channel %d\n",
1804 pMvSataAdapter->adapterId, channel);
1879 pCmd->Result = RETURN_DEVICE_BUSY;
1880 break;
1881 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS:
1805 pCmd->Result = RETURN_DEVICE_BUSY;
1806 break;
1807 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS:
1882 MV_ERROR("IAL Error: Edma Queue command "
1883 "failed. (Bad Params), pMvSataAdapter:"
1884 " %p, pSataChannel: %p.\n",
1885 pMvSataAdapter,
1886 pMvSataAdapter->sataChannel[channel]);
1808 MV_ERROR("IAL Error: Edma Queue command failed. (Bad "
1809 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n",
1810 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]);
1887 pCmd->Result = RETURN_IDE_ERROR;
1888 break;
1889 default:
1811 pCmd->Result = RETURN_IDE_ERROR;
1812 break;
1813 default:
1890 MV_ERROR("IAL Error: Bad result value (%d) "
1891 "from queue command\n", result);
1814 MV_ERROR("IAL Error: Bad result value (%d) from queue"
1815 " command\n", result);
1892 pCmd->Result = RETURN_IDE_ERROR;
1893 }
1894 if(pPRDTable)
1816 pCmd->Result = RETURN_IDE_ERROR;
1817 }
1818 if(pPRDTable)
1895 FreePRDTable(pAdapter, pPRDTable);
1896 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion,
1897 pCmd);
1819 FreePRDTable(pMvSataAdapter->IALData,pPRDTable);
1820 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1898 }
1899 pDevice->QueueLength++;
1900 return;
1901
1902 case IDE_COMMAND_VERIFY:
1903 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA;
1904 pNoUdmaParams->bufPtr = NULL;
1905 pNoUdmaParams->callBack = CommandCompletionCB;
1906 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd;
1907 pNoUdmaParams->count = 0;
1908 pNoUdmaParams->features = 0;
1909 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA;
1910
1911 pCmd->uScratch.sata_param.cmd_priv = 1;
1912 if (pMvSataChannel->lba48Address == MV_TRUE){
1821 }
1822 pDevice->QueueLength++;
1823 return;
1824
1825 case IDE_COMMAND_VERIFY:
1826 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA;
1827 pNoUdmaParams->bufPtr = NULL;
1828 pNoUdmaParams->callBack = CommandCompletionCB;
1829 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd;
1830 pNoUdmaParams->count = 0;
1831 pNoUdmaParams->features = 0;
1832 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA;
1833
1834 pCmd->uScratch.sata_param.cmd_priv = 1;
1835 if (pMvSataChannel->lba48Address == MV_TRUE){
1913 pNoUdmaParams->command =
1914 MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT;
1836 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT;
1915 pNoUdmaParams->isEXT = MV_TRUE;
1837 pNoUdmaParams->isEXT = MV_TRUE;
1916 pNoUdmaParams->lbaHigh =
1917 (MV_U16)((Lba & 0xff0000) >> 16);
1838 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1918 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1919 pNoUdmaParams->lbaLow =
1839 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1840 pNoUdmaParams->lbaLow =
1920 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff));
1841 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff));
1921 pNoUdmaParams->sectorCount = nSector;
1922 pNoUdmaParams->device = 0x40;
1842 pNoUdmaParams->sectorCount = nSector;
1843 pNoUdmaParams->device = 0x40;
1923 result = mvSataQueueCommand(pMvSataAdapter, channel,
1924 &commandInfo);
1925 if (result != MV_QUEUE_COMMAND_RESULT_OK) {
1844 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1845 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1926 goto queue_failed;
1927 }
1928 return;
1929 }
1846 goto queue_failed;
1847 }
1848 return;
1849 }
1930 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS;
1931 pNoUdmaParams->isEXT = MV_FALSE;
1932 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1933 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1934 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff);
1935 pNoUdmaParams->sectorCount = 0xff & nSector;
1936 pNoUdmaParams->device = (MV_U8)(0x40 |
1937 ((Lba & 0xf000000) >> 24));
1938 pNoUdmaParams->callBack = CommandCompletionCB;
1939 result = mvSataQueueCommand(pMvSataAdapter, channel,
1940 &commandInfo);
1941 /*
1942 * FIXME: how about the commands already queued? but marvel
1943 * also forgets to consider this
1944 */
1945 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1946 goto queue_failed;
1850 else{
1851 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS;
1852 pNoUdmaParams->isEXT = MV_FALSE;
1853 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1854 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1855 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff);
1856 pNoUdmaParams->sectorCount = 0xff & nSector;
1857 pNoUdmaParams->device = (MV_U8)(0x40 |
1858 ((Lba & 0xf000000) >> 24));
1859 pNoUdmaParams->callBack = CommandCompletionCB;
1860 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1861 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/
1862 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1863 goto queue_failed;
1864 }
1947 }
1948 break;
1949 default:
1950 pCmd->Result = RETURN_INVALID_REQUEST;
1951 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1952 break;
1953 }
1954}

--- 6 unchanged lines hidden (view full) ---

1961static int
1962hpt_probe(device_t dev)
1963{
1964 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) &&
1965 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081
1966#ifdef FOR_DEMO
1967 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080
1968#endif
1865 }
1866 break;
1867 default:
1868 pCmd->Result = RETURN_INVALID_REQUEST;
1869 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1870 break;
1871 }
1872}

--- 6 unchanged lines hidden (view full) ---

1879static int
1880hpt_probe(device_t dev)
1881{
1882 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) &&
1883 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081
1884#ifdef FOR_DEMO
1885 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080
1886#endif
1969 )) {
1887 ))
1888 {
1970 KdPrintI((CONTROLLER_NAME " found\n"));
1971 device_set_desc(dev, CONTROLLER_NAME);
1972 return 0;
1973 }
1974 else
1975 return(ENXIO);
1976}
1977
1978/***********************************************************
1979 *
1980 * Auto configuration: attach and init a host adapter.
1981 *
1982 ***********************************************************/
1983static int
1984hpt_attach(device_t dev)
1985{
1889 KdPrintI((CONTROLLER_NAME " found\n"));
1890 device_set_desc(dev, CONTROLLER_NAME);
1891 return 0;
1892 }
1893 else
1894 return(ENXIO);
1895}
1896
1897/***********************************************************
1898 *
1899 * Auto configuration: attach and init a host adapter.
1900 *
1901 ***********************************************************/
1902static int
1903hpt_attach(device_t dev)
1904{
1986 IAL_ADAPTER_T * pAdapter;
1905 IAL_ADAPTER_T * pAdapter = device_get_softc(dev);
1987 int rid;
1988 union ccb *ccb;
1989 struct cam_devq *devq;
1990 struct cam_sim *hpt_vsim;
1991
1906 int rid;
1907 union ccb *ccb;
1908 struct cam_devq *devq;
1909 struct cam_sim *hpt_vsim;
1910
1992 printf("%s Version %s\n", DRIVER_NAME, DRIVER_VERSION);
1911 printf("%s Version %s \n", DRIVER_NAME, DRIVER_VERSION);
1993
1912
1994 pAdapter = device_get_softc(dev);
1913 if (!pAdapter)
1914 {
1915 pAdapter = (IAL_ADAPTER_T *)malloc(sizeof (IAL_ADAPTER_T), M_DEVBUF, M_NOWAIT);
1916#if __FreeBSD_version > 410000
1917 device_set_softc(dev, (void *)pAdapter);
1918#else
1919 device_set_driver(dev, (driver_t *)pAdapter);
1920#endif
1921 }
1922
1923 if (!pAdapter) return (ENOMEM);
1924 bzero(pAdapter, sizeof(IAL_ADAPTER_T));
1925
1995 pAdapter->hpt_dev = dev;
1996
1997 rid = init_adapter(pAdapter);
1998 if (rid)
1999 return rid;
2000
2001 rid = 0;
1926 pAdapter->hpt_dev = dev;
1927
1928 rid = init_adapter(pAdapter);
1929 if (rid)
1930 return rid;
1931
1932 rid = 0;
2002 if ((pAdapter->hpt_irq = bus_alloc_resource(pAdapter->hpt_dev,
2003 SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL){
1933 if ((pAdapter->hpt_irq = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL)
1934 {
2004 hpt_printk(("can't allocate interrupt\n"));
2005 return(ENXIO);
2006 }
2007
1935 hpt_printk(("can't allocate interrupt\n"));
1936 return(ENXIO);
1937 }
1938
2008 if(bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, INTR_TYPE_CAM,
2009 hpt_intr, pAdapter, &pAdapter->hpt_intr)) {
1939 if(bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, INTR_TYPE_CAM, hpt_intr, pAdapter, &pAdapter->hpt_intr))
1940 {
2010 hpt_printk(("can't set up interrupt\n"));
2011 free(pAdapter, M_DEVBUF);
2012 return(ENXIO);
2013 }
2014
1941 hpt_printk(("can't set up interrupt\n"));
1942 free(pAdapter, M_DEVBUF);
1943 return(ENXIO);
1944 }
1945
2015#if 1
2016 if ((ccb = malloc(sizeof(*ccb), M_DEVBUF, M_WAITOK | M_ZERO)) != NULL) {
1946
1947 if((ccb = (union ccb *)malloc(sizeof(*ccb), M_DEVBUF, M_WAITOK)) != (union ccb*)NULL)
1948 {
1949 bzero(ccb, sizeof(*ccb));
2017 ccb->ccb_h.pinfo.priority = 1;
2018 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX;
1950 ccb->ccb_h.pinfo.priority = 1;
1951 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX;
2019 } else {
1952 }
1953 else
1954 {
2020 return ENOMEM;
2021 }
1955 return ENOMEM;
1956 }
2022#endif
2023 /*
2024 * Create the device queue for our SIM(s).
2025 */
1957 /*
1958 * Create the device queue for our SIM(s).
1959 */
2026 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) {
1960 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL)
1961 {
2027 KdPrint(("ENXIO\n"));
1962 KdPrint(("ENXIO\n"));
2028 free(ccb, M_DEVBUF);
2029 return ENOMEM;
2030 }
2031
2032 /*
2033 * Construct our SIM entry
2034 */
1963 return ENOMEM;
1964 }
1965
1966 /*
1967 * Construct our SIM entry
1968 */
2035 if ((hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll,__str(PROC_DIR_NAME),
2036 pAdapter, device_get_unit(pAdapter->hpt_dev), /*untagged*/1,
2037 /*tagged*/8, devq)) == NULL) {
2038 free(ccb, M_DEVBUF);
1969 if ((hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME),
1970 pAdapter, device_get_unit(pAdapter->hpt_dev), /*untagged*/1, /*tagged*/8, devq)) == NULL) {
2039 cam_simq_free(devq);
2040 return ENOMEM;
2041 }
2042
1971 cam_simq_free(devq);
1972 return ENOMEM;
1973 }
1974
2043 if(xpt_bus_register(hpt_vsim, 0) != CAM_SUCCESS) {
2044 free(ccb, M_DEVBUF);
1975 if(xpt_bus_register(hpt_vsim, 0) != CAM_SUCCESS)
1976 {
2045 cam_sim_free(hpt_vsim, /*free devq*/ TRUE);
2046 hpt_vsim = NULL;
2047 return ENXIO;
2048 }
2049
2050 if(xpt_create_path(&pAdapter->path, /*periph */ NULL,
1977 cam_sim_free(hpt_vsim, /*free devq*/ TRUE);
1978 hpt_vsim = NULL;
1979 return ENXIO;
1980 }
1981
1982 if(xpt_create_path(&pAdapter->path, /*periph */ NULL,
2051 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
2052 != CAM_REQ_CMP) {
2053 free(ccb, M_DEVBUF);
1983 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD,
1984 CAM_LUN_WILDCARD) != CAM_REQ_CMP)
1985 {
2054 xpt_bus_deregister(cam_sim_path(hpt_vsim));
2055 cam_sim_free(hpt_vsim, /*free_devq*/TRUE);
2056 hpt_vsim = NULL;
2057 return ENXIO;
2058 }
2059
2060 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5);
2061 ccb->ccb_h.func_code = XPT_SASYNC_CB;
2062 ccb->csa.event_enable = AC_LOST_DEVICE;
2063 ccb->csa.callback = hpt_async;
2064 ccb->csa.callback_arg = hpt_vsim;
2065 xpt_action((union ccb *)ccb);
2066 free(ccb, M_DEVBUF);
2067
1986 xpt_bus_deregister(cam_sim_path(hpt_vsim));
1987 cam_sim_free(hpt_vsim, /*free_devq*/TRUE);
1988 hpt_vsim = NULL;
1989 return ENXIO;
1990 }
1991
1992 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5);
1993 ccb->ccb_h.func_code = XPT_SASYNC_CB;
1994 ccb->csa.event_enable = AC_LOST_DEVICE;
1995 ccb->csa.callback = hpt_async;
1996 ccb->csa.callback_arg = hpt_vsim;
1997 xpt_action((union ccb *)ccb);
1998 free(ccb, M_DEVBUF);
1999
2068 /* Only do this setup for the first device. */
2000 /* Register shutdown handler, and start the work thread. */
2069 if (device_get_unit(dev) == 0) {
2001 if (device_get_unit(dev) == 0) {
2070 pAdapter->eh = EVENTHANDLER_REGISTER(shutdown_final,
2071 hpt_shutdown, dev, SHUTDOWN_PRI_DEFAULT);
2072 if (pAdapter->eh != NULL)
2002 pAdapter->eh = EVENTHANDLER_REGISTER(shutdown_final,
2003 hpt_shutdown, dev, SHUTDOWN_PRI_DEFAULT);
2004 if (pAdapter->eh)
2073 launch_worker_thread();
2074 else
2005 launch_worker_thread();
2006 else
2075 printf("hptmv: shutdown event registration failed\n");
2007 hpt_printk(("shutdown event registration failed\n"));
2076 }
2077
2078 return 0;
2079}
2080
2081static int
2082hpt_detach(device_t dev)
2008 }
2009
2010 return 0;
2011}
2012
2013static int
2014hpt_detach(device_t dev)
2083{
2015{
2084 return (EBUSY);
2085}
2086
2016 return (EBUSY);
2017}
2018
2019
2087/***************************************************************
2088 * The poll function is used to simulate the interrupt when
2089 * the interrupt subsystem is not functioning.
2090 *
2091 ***************************************************************/
2092static void
2093hpt_poll(struct cam_sim *sim)
2094{
2095 hpt_intr((void *)cam_sim_softc(sim));
2096}
2097
2098/****************************************************************
2099 * Name: hpt_intr
2100 * Description: Interrupt handler.
2101 ****************************************************************/
2102static void
2103hpt_intr(void *arg)
2104{
2105 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)arg;
2020/***************************************************************
2021 * The poll function is used to simulate the interrupt when
2022 * the interrupt subsystem is not functioning.
2023 *
2024 ***************************************************************/
2025static void
2026hpt_poll(struct cam_sim *sim)
2027{
2028 hpt_intr((void *)cam_sim_softc(sim));
2029}
2030
2031/****************************************************************
2032 * Name: hpt_intr
2033 * Description: Interrupt handler.
2034 ****************************************************************/
2035static void
2036hpt_intr(void *arg)
2037{
2038 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)arg;
2106 intrmask_t oldspl;
2039 intrmask_t oldspl = lock_driver();
2107
2040
2108 oldspl = lock_driver();
2109 /* KdPrintI(("----- Entering Isr() -----\n")); */
2041 /* KdPrintI(("----- Entering Isr() -----\n")); */
2110 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE){
2042 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE)
2043 {
2111 _VBUS_INST(&pAdapter->VBus)
2112 CheckPendingCall(_VBUS_P0);
2113 }
2114
2115 /* KdPrintI(("----- Leaving Isr() -----\n")); */
2116 unlock_driver(oldspl);
2117}
2118

--- 22 unchanged lines hidden (view full) ---

2141{
2142 int i;
2143
2144 hpt_printk(("flush all devices\n"));
2145
2146 /* flush all devices */
2147 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) {
2148 PVDevice pVDev = pAdapter->VBus.pVDevice[i];
2044 _VBUS_INST(&pAdapter->VBus)
2045 CheckPendingCall(_VBUS_P0);
2046 }
2047
2048 /* KdPrintI(("----- Leaving Isr() -----\n")); */
2049 unlock_driver(oldspl);
2050}
2051

--- 22 unchanged lines hidden (view full) ---

2074{
2075 int i;
2076
2077 hpt_printk(("flush all devices\n"));
2078
2079 /* flush all devices */
2080 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) {
2081 PVDevice pVDev = pAdapter->VBus.pVDevice[i];
2149 if (pVDev)
2150 fFlushVDev(pVDev);
2082 if(pVDev) fFlushVDev(pVDev);
2151 }
2152}
2153
2154static int
2155hpt_shutdown(device_t dev)
2156{
2083 }
2084}
2085
2086static int
2087hpt_shutdown(device_t dev)
2088{
2157 IAL_ADAPTER_T *pAdapter;
2089 IAL_ADAPTER_T *pAdapter;
2090
2091 pAdapter = device_get_softc(dev);
2092 if (pAdapter == NULL)
2093 return (EINVAL);
2158
2094
2159 pAdapter = device_get_softc(dev);
2160 if (pAdapter == NULL)
2161 return (EINVAL);
2162
2163 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh);
2164 FlushAdapter(pAdapter);
2165
2166 return 0;
2095 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh);
2096 FlushAdapter(pAdapter);
2097 /* give the flush some time to happen,
2098 *otherwise "shutdown -p now" will make file system corrupted */
2099 DELAY(1000 * 1000 * 5);
2100 return 0;
2167}
2168
2169void
2170Check_Idle_Call(IAL_ADAPTER_T *pAdapter)
2171{
2101}
2102
2103void
2104Check_Idle_Call(IAL_ADAPTER_T *pAdapter)
2105{
2172 int i = 0;
2173
2174 _VBUS_INST(&pAdapter->VBus)
2175
2176 if (mWaitingForIdle(_VBUS_P0)) {
2177 CheckIdleCall(_VBUS_P0);
2178#ifdef SUPPORT_ARRAY
2106 _VBUS_INST(&pAdapter->VBus)
2107
2108 if (mWaitingForIdle(_VBUS_P0)) {
2109 CheckIdleCall(_VBUS_P0);
2110#ifdef SUPPORT_ARRAY
2179 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){
2111 {
2112 int i;
2180 PVDevice pArray;
2113 PVDevice pArray;
2181
2182 if ((pArray = ArrayTables(i))->u.array.dArStamp == 0)
2183 continue;
2184 else if (pArray->u.array.rf_auto_rebuild) {
2185 KdPrint(("auto rebuild.\n"));
2186 pArray->u.array.rf_auto_rebuild = 0;
2187 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block,
2188 pAdapter, pArray, DUPLICATE);
2114 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){
2115 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2116 continue;
2117 else if (pArray->u.array.rf_auto_rebuild) {
2118 KdPrint(("auto rebuild.\n"));
2119 pArray->u.array.rf_auto_rebuild = 0;
2120 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE);
2121 }
2189 }
2190 }
2191#endif
2192 }
2193 /* launch the awaiting commands blocked by mWaitingForIdle */
2122 }
2123 }
2124#endif
2125 }
2126 /* launch the awaiting commands blocked by mWaitingForIdle */
2194 while(pAdapter->pending_Q!= NULL) {
2127 while(pAdapter->pending_Q!= NULL)
2128 {
2195 _VBUS_INST(&pAdapter->VBus)
2129 _VBUS_INST(&pAdapter->VBus)
2196 union ccb *ccb =
2197 (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr;
2198
2130 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr;
2199 hpt_free_ccb(&pAdapter->pending_Q, ccb);
2200 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb);
2201 }
2202}
2203
2204static void
2205ccb_done(union ccb *ccb)
2206{
2131 hpt_free_ccb(&pAdapter->pending_Q, ccb);
2132 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb);
2133 }
2134}
2135
2136static void
2137ccb_done(union ccb *ccb)
2138{
2207 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *)ccb->ccb_adapter;
2208 KdPrintI(("ccb_done: ccb %p status %x", ccb, ccb->ccb_h.status));
2139 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2140 IAL_ADAPTER_T * pAdapter = pmap->pAdapter;
2141 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status));
2209
2142
2143 dmamap_put(pmap);
2210 xpt_done(ccb);
2211
2212 pAdapter->outstandingCommands--;
2213
2144 xpt_done(ccb);
2145
2146 pAdapter->outstandingCommands--;
2147
2214 if (pAdapter->outstandingCommands == 0) {
2148 if (pAdapter->outstandingCommands == 0)
2149 {
2215 if(DPC_Request_Nums == 0)
2216 Check_Idle_Call(pAdapter);
2217 }
2218}
2219
2220/****************************************************************
2221 * Name: hpt_action
2222 * Description: Process a queued command from the CAM layer.
2223 * Parameters: sim - Pointer to SIM object
2224 * ccb - Pointer to SCSI command structure.
2225 ****************************************************************/
2226
2227void
2228hpt_action(struct cam_sim *sim, union ccb *ccb)
2229{
2230 intrmask_t oldspl;
2231 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim);
2150 if(DPC_Request_Nums == 0)
2151 Check_Idle_Call(pAdapter);
2152 }
2153}
2154
2155/****************************************************************
2156 * Name: hpt_action
2157 * Description: Process a queued command from the CAM layer.
2158 * Parameters: sim - Pointer to SIM object
2159 * ccb - Pointer to SCSI command structure.
2160 ****************************************************************/
2161
2162void
2163hpt_action(struct cam_sim *sim, union ccb *ccb)
2164{
2165 intrmask_t oldspl;
2166 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim);
2167 PBUS_DMAMAP pmap;
2232 _VBUS_INST(&pAdapter->VBus)
2168 _VBUS_INST(&pAdapter->VBus)
2233
2234 ccb->ccb_adapter = pAdapter;
2235
2169
2236 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n"));
2237 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb,
2238 ccb->ccb_h.func_code));
2170 CAM_DEBUG(ccb->ccb_h->path, CAM_DEBUG_TRACE, ("hpt_action\n"));
2171 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code));
2239
2172
2240 switch (ccb->ccb_h.func_code) {
2241 case XPT_SCSI_IO: /* Execute the requested I/O operation */
2242 /* ccb->ccb_h.path_id is not our bus id - don't check it */
2173 switch (ccb->ccb_h.func_code)
2174 {
2175 case XPT_SCSI_IO: /* Execute the requested I/O operation */
2176 {
2177 /* ccb->ccb_h.path_id is not our bus id - don't check it */
2243
2178
2244 if (ccb->ccb_h.target_lun) {
2245 ccb->ccb_h.status = CAM_LUN_INVALID;
2246 xpt_done(ccb);
2247 return;
2248 }
2249 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS ||
2250 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) {
2251 ccb->ccb_h.status = CAM_TID_INVALID;
2252 xpt_done(ccb);
2253 return;
2254 }
2179 if (ccb->ccb_h.target_lun) {
2180 ccb->ccb_h.status = CAM_LUN_INVALID;
2181 xpt_done(ccb);
2182 return;
2183 }
2184 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS ||
2185 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) {
2186 ccb->ccb_h.status = CAM_TID_INVALID;
2187 xpt_done(ccb);
2188 return;
2189 }
2255
2190
2256 oldspl = lock_driver();
2257 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
2258 Check_Idle_Call(pAdapter);
2191 oldspl = lock_driver();
2192 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
2193 Check_Idle_Call(pAdapter);
2259
2194
2260 if (mWaitingForIdle(_VBUS_P0))
2261 hpt_queue_ccb(&pAdapter->pending_Q, ccb);
2262 else
2263 OsSendCommand(_VBUS_P ccb);
2264 unlock_driver(oldspl);
2195 pmap = dmamap_get(pAdapter);
2196 HPT_ASSERT(pmap);
2197 ccb->ccb_adapter = pmap;
2198 memset((void *)pmap->psg, 0, sizeof(pmap->psg));
2265
2199
2266 /* KdPrint(("leave scsiio\n")); */
2267 break;
2200 if (mWaitingForIdle(_VBUS_P0))
2201 hpt_queue_ccb(&pAdapter->pending_Q, ccb);
2202 else
2203 OsSendCommand(_VBUS_P ccb);
2204 unlock_driver(oldspl);
2268
2205
2269 case XPT_RESET_BUS:
2270 KdPrint(("reset bus\n"));
2271 oldspl = lock_driver();
2272 fResetVBus(_VBUS_P0);
2273 unlock_driver(oldspl);
2274 xpt_done(ccb);
2275 break;
2206 /* KdPrint(("leave scsiio\n")); */
2207 break;
2208 }
2276
2209
2277 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2278 case XPT_EN_LUN: /* Enable LUN as a target */
2279 case XPT_TARGET_IO: /* Execute target I/O request */
2280 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2281 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2282 case XPT_ABORT: /* Abort the specified CCB */
2283 case XPT_TERM_IO: /* Terminate the I/O process */
2284 /* XXX Implement */
2285 ccb->ccb_h.status = CAM_REQ_INVALID;
2286 xpt_done(ccb);
2287 break;
2210 case XPT_RESET_BUS:
2211 KdPrint(("reset bus\n"));
2212 oldspl = lock_driver();
2213 fResetVBus(_VBUS_P0);
2214 unlock_driver(oldspl);
2215 xpt_done(ccb);
2216 break;
2288
2217
2289 case XPT_GET_TRAN_SETTINGS:
2290 case XPT_SET_TRAN_SETTINGS:
2291 /* XXX Implement */
2292 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
2293 xpt_done(ccb);
2294 break;
2218 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2219 case XPT_EN_LUN: /* Enable LUN as a target */
2220 case XPT_TARGET_IO: /* Execute target I/O request */
2221 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2222 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2223 case XPT_ABORT: /* Abort the specified CCB */
2224 case XPT_TERM_IO: /* Terminate the I/O process */
2225 /* XXX Implement */
2226 ccb->ccb_h.status = CAM_REQ_INVALID;
2227 xpt_done(ccb);
2228 break;
2295
2229
2296 case XPT_CALC_GEOMETRY:
2297 {
2298 struct ccb_calc_geometry *ccg;
2299 u_int32_t size_mb;
2300 u_int32_t secs_per_cylinder;
2230 case XPT_GET_TRAN_SETTINGS:
2231 case XPT_SET_TRAN_SETTINGS:
2232 /* XXX Implement */
2233 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
2234 xpt_done(ccb);
2235 break;
2301
2236
2302 ccg = &ccb->ccg;
2303 size_mb = ccg->volume_size / ((1024L*1024L) / ccg->block_size);
2237 case XPT_CALC_GEOMETRY:
2238 {
2239 struct ccb_calc_geometry *ccg;
2240 u_int32_t size_mb;
2241 u_int32_t secs_per_cylinder;
2304
2242
2305 if (size_mb > 1024 ) {
2306 ccg->heads = 255;
2307 ccg->secs_per_track = 63;
2308 } else {
2309 ccg->heads = 64;
2310 ccg->secs_per_track = 32;
2243 ccg = &ccb->ccg;
2244 size_mb = ccg->volume_size / ((1024L * 1024L) / ccg->block_size);
2245
2246 if (size_mb > 1024 ) {
2247 ccg->heads = 255;
2248 ccg->secs_per_track = 63;
2249 } else {
2250 ccg->heads = 64;
2251 ccg->secs_per_track = 32;
2252 }
2253 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
2254 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
2255 ccb->ccb_h.status = CAM_REQ_CMP;
2256 xpt_done(ccb);
2257 break;
2311 }
2258 }
2312 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
2313 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
2314 ccb->ccb_h.status = CAM_REQ_CMP;
2315 xpt_done(ccb);
2316 break;
2317 }
2318
2259
2319 case XPT_PATH_INQ: /* Path routing inquiry */
2320 {
2321 struct ccb_pathinq *cpi = &ccb->cpi;
2260 case XPT_PATH_INQ: /* Path routing inquiry */
2261 {
2262 struct ccb_pathinq *cpi = &ccb->cpi;
2322
2263
2323 cpi->version_num = 1; /* XXX??? */
2324 cpi->hba_inquiry = PI_SDTR_ABLE;
2325 cpi->target_sprt = 0;
2326 /* Not necessary to reset bus */
2327 cpi->hba_misc = PIM_NOBUSRESET;
2328 cpi->hba_eng_cnt = 0;
2264 cpi->version_num = 1; /* XXX??? */
2265 cpi->hba_inquiry = PI_SDTR_ABLE;
2266 cpi->target_sprt = 0;
2267 /* Not necessary to reset bus */
2268 cpi->hba_misc = PIM_NOBUSRESET;
2269 cpi->hba_eng_cnt = 0;
2329
2270
2330 cpi->max_target = MAX_VDEVICE_PER_VBUS;
2331 cpi->max_lun = 0;
2332 cpi->initiator_id = MAX_VDEVICE_PER_VBUS;
2271 cpi->max_target = MAX_VDEVICE_PER_VBUS;
2272 cpi->max_lun = 0;
2273 cpi->initiator_id = MAX_VDEVICE_PER_VBUS;
2333
2274
2334 cpi->bus_id = cam_sim_bus(sim);
2335 cpi->base_transfer_speed = 3300;
2336 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2337 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN);
2338 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2339 cpi->unit_number = cam_sim_unit(sim);
2340 cpi->ccb_h.status = CAM_REQ_CMP;
2341 xpt_done(ccb);
2342 break;
2343 }
2275 cpi->bus_id = cam_sim_bus(sim);
2276 cpi->base_transfer_speed = 3300;
2277 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2278 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN);
2279 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2280 cpi->unit_number = cam_sim_unit(sim);
2281 cpi->ccb_h.status = CAM_REQ_CMP;
2282 xpt_done(ccb);
2283 break;
2284 }
2344
2285
2345 default:
2346 KdPrint(("invalid cmd\n"));
2347 ccb->ccb_h.status = CAM_REQ_INVALID;
2348 xpt_done(ccb);
2349 break;
2286 default:
2287 KdPrint(("invalid cmd\n"));
2288 ccb->ccb_h.status = CAM_REQ_INVALID;
2289 xpt_done(ccb);
2290 break;
2350 }
2351 /* KdPrint(("leave hpt_action..............\n")); */
2352}
2353
2354/* shall be called at lock_driver() */
2355static void
2356hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb)
2357{

--- 10 unchanged lines hidden (view full) ---

2368/* shall be called at lock_driver() */
2369static void
2370hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb)
2371{
2372 union ccb *TempCCB;
2373
2374 TempCCB = *ccb_Q;
2375
2291 }
2292 /* KdPrint(("leave hpt_action..............\n")); */
2293}
2294
2295/* shall be called at lock_driver() */
2296static void
2297hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb)
2298{

--- 10 unchanged lines hidden (view full) ---

2309/* shall be called at lock_driver() */
2310static void
2311hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb)
2312{
2313 union ccb *TempCCB;
2314
2315 TempCCB = *ccb_Q;
2316
2376 if(ccb->ccb_h.ccb_ccb_ptr == ccb)
2377 /*it means SCpnt is the last one in CURRCMDs*/
2317 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/
2378 *ccb_Q = NULL;
2379 else {
2380 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb)
2381 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr;
2382
2383 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr;
2384
2385 if(*ccb_Q == ccb)

--- 9 unchanged lines hidden (view full) ---

2395 ***************************************************************************/
2396static void hpt_worker_thread(void)
2397{
2398 intrmask_t oldspl;
2399
2400 for(;;) {
2401 while (DpcQueue_First!=DpcQueue_Last) {
2402 ST_HPT_DPC p;
2318 *ccb_Q = NULL;
2319 else {
2320 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb)
2321 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr;
2322
2323 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr;
2324
2325 if(*ccb_Q == ccb)

--- 9 unchanged lines hidden (view full) ---

2335 ***************************************************************************/
2336static void hpt_worker_thread(void)
2337{
2338 intrmask_t oldspl;
2339
2340 for(;;) {
2341 while (DpcQueue_First!=DpcQueue_Last) {
2342 ST_HPT_DPC p;
2403 IAL_ADAPTER_T *pAdapter;
2404 PVDevice pArray;
2405 PVBus _vbus_p;
2406 int i;
2407
2408 oldspl = lock_driver();
2409 p = DpcQueue[DpcQueue_First];
2410 DpcQueue_First++;
2411 DpcQueue_First %= MAX_DPC;
2412 DPC_Request_Nums++;
2413 unlock_driver(oldspl);
2414 p.dpc(p.pAdapter, p.arg, p.flags);
2415
2416 oldspl = lock_driver();
2417 DPC_Request_Nums--;
2343 oldspl = lock_driver();
2344 p = DpcQueue[DpcQueue_First];
2345 DpcQueue_First++;
2346 DpcQueue_First %= MAX_DPC;
2347 DPC_Request_Nums++;
2348 unlock_driver(oldspl);
2349 p.dpc(p.pAdapter, p.arg, p.flags);
2350
2351 oldspl = lock_driver();
2352 DPC_Request_Nums--;
2418 /*
2419 * since we may have prevented Check_Idle_Call, do it
2420 * here
2421 */
2353 /* since we may have prevented Check_Idle_Call, do it here */
2422 if (DPC_Request_Nums==0) {
2423 if (p.pAdapter->outstandingCommands == 0) {
2424 _VBUS_INST(&p.pAdapter->VBus);
2425 Check_Idle_Call(p.pAdapter);
2426 CheckPendingCall(_VBUS_P0);
2427 }
2428 }
2429 unlock_driver(oldspl);
2354 if (DPC_Request_Nums==0) {
2355 if (p.pAdapter->outstandingCommands == 0) {
2356 _VBUS_INST(&p.pAdapter->VBus);
2357 Check_Idle_Call(p.pAdapter);
2358 CheckPendingCall(_VBUS_P0);
2359 }
2360 }
2361 unlock_driver(oldspl);
2430 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP) == 0)
2431 continue;
2432
2362
2433 /* abort rebuilding process. */
2434 pAdapter = gIal_Adapter;
2435 while (pAdapter != 0) {
2436 _vbus_p = &pAdapter->VBus;
2437 for (i = 0; i < MAX_ARRAY_PER_VBUS;i++){
2438 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2439 continue;
2440 if (pArray->u.array.rf_rebuilding ||
2441 pArray->u.array.rf_verifying ||
2442 pArray->u.array.rf_initializing) {
2443 pArray->u.array.rf_abort_rebuild = 1;
2363 /*Schedule out*/
2364#if (__FreeBSD_version < 500000)
2365 YIELD_THREAD;
2366#else
2367 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "sched", 1);
2368#endif
2369 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) {
2370 /* abort rebuilding process. */
2371 IAL_ADAPTER_T *pAdapter;
2372 PVDevice pArray;
2373 PVBus _vbus_p;
2374 int i;
2375 pAdapter = gIal_Adapter;
2376
2377 while(pAdapter != 0){
2378
2379 _vbus_p = &pAdapter->VBus;
2380
2381 for (i=0;i<MAX_ARRAY_PER_VBUS;i++)
2382 {
2383 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2384 continue;
2385 else if (pArray->u.array.rf_rebuilding ||
2386 pArray->u.array.rf_verifying ||
2387 pArray->u.array.rf_initializing)
2388 {
2389 pArray->u.array.rf_abort_rebuild = 1;
2390 }
2444 }
2391 }
2392 pAdapter = pAdapter->next;
2445 }
2393 }
2446 pAdapter = pAdapter->next;
2447 }
2448 }
2449
2394 }
2395 }
2396
2397/*Remove this debug option*/
2398/*
2450#ifdef DEBUG
2451 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP))
2399#ifdef DEBUG
2400 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP))
2452 tsleep(hpt_worker_thread, PPAUSE, "hptrdy", 2 * hz);
2401 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz);
2453#endif
2402#endif
2454#if (__FreeBSD_version >= 500043)
2403*/
2404 #if (__FreeBSD_version >= 500043)
2455 kthread_suspend_check(curproc);
2405 kthread_suspend_check(curproc);
2456#else
2406 #else
2457 kproc_suspend_loop(curproc);
2407 kproc_suspend_loop(curproc);
2458#endif
2459 /* wait for something to do */
2460 tsleep(hpt_worker_thread, PPAUSE, "hptrdy", 2 * hz);
2408 #endif
2409 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz); /* wait for something to do */
2461 }
2462}
2463
2464static struct proc *hptdaemonproc;
2465static struct kproc_desc hpt_kp = {
2466 "hpt_wt",
2467 hpt_worker_thread,
2468 &hptdaemonproc
2469};
2470
2410 }
2411}
2412
2413static struct proc *hptdaemonproc;
2414static struct kproc_desc hpt_kp = {
2415 "hpt_wt",
2416 hpt_worker_thread,
2417 &hptdaemonproc
2418};
2419
2420/*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/
2471static void
2472launch_worker_thread(void)
2473{
2474 IAL_ADAPTER_T *pAdapTemp;
2475
2476 kproc_start(&hpt_kp);
2477
2478 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) {
2479
2480 _VBUS_INST(&pAdapTemp->VBus)
2481 int i;
2482 PVDevice pVDev;
2483
2484 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++)
2485 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0)
2486 continue;
2421static void
2422launch_worker_thread(void)
2423{
2424 IAL_ADAPTER_T *pAdapTemp;
2425
2426 kproc_start(&hpt_kp);
2427
2428 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) {
2429
2430 _VBUS_INST(&pAdapTemp->VBus)
2431 int i;
2432 PVDevice pVDev;
2433
2434 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++)
2435 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0)
2436 continue;
2487 if (pVDev->u.array.rf_need_rebuild &&
2488 !pVDev->u.array.rf_rebuilding) {
2489 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block,
2490 pAdapTemp, pVDev,
2491 (UCHAR)((pVDev->u.array.CriticalMembers ||
2492 pVDev->VDeviceType == VD_RAID_1) ?
2493 DUPLICATE : REBUILD_PARITY));
2494 }
2437 else{
2438 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding)
2439 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev,
2440 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY));
2441 }
2495 }
2496
2497 /*
2442 }
2443
2444 /*
2498 * hpt_worker_thread needs to be suspended after shutdown sync, when fs
2499 * sync finished.
2445 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished.
2500 */
2501#if (__FreeBSD_version < 500043)
2446 */
2447#if (__FreeBSD_version < 500043)
2502 EVENTHANDLER_REGISTER(shutdown_post_sync, shutdown_kproc,
2503 hptdaemonproc, SHUTDOWN_PRI_FIRST);
2504#else
2505 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown,
2506 hptdaemonproc, SHUTDOWN_PRI_FIRST);
2448 EVENTHANDLER_REGISTER(shutdown_post_sync, shutdown_kproc, hptdaemonproc, SHUTDOWN_PRI_FIRST);
2449#else
2450 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc, SHUTDOWN_PRI_FIRST);
2507#endif
2508}
2451#endif
2452}
2453/*
2454 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL);
2455*/
2509
2456
2510#endif /* SUPPORT_ARRAY */
2457#endif
2511
2458
2512/* build sgl with merge function */
2513#define ON64KBOUNDARY(x) (((ULONG_PTR)(x) & 0xFFFF) == 0)
2514
2515/* XXX */
2516/* #define NOTNEIGHBORPAGE(x, y) (max(x, y) - min(x, y) > PAGE_SIZE) */
2517#define NOTNEIGHBORPAGE(highvaddr, lowvaddr) \
2518 ((ULONG_PTR)(highvaddr) - (ULONG_PTR)(lowvaddr) != PAGE_SIZE)
2519
2520
2521/********************************************************************************/
2522
2459/********************************************************************************/
2460
2523static void
2524hptmv_buffer_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2461int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical)
2525{
2462{
2526 FPSCAT_GATH pSg;
2463 union ccb *ccb = (union ccb *)pCmd->pOrgCommand;
2464 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr;
2527 int idx;
2528
2465 int idx;
2466
2529 if (error || nsegs == 0) {
2530 panic("busdma bewm");
2531 return;
2532 }
2533
2534 pSg = *(FPSCAT_GATH *)arg;
2535
2536 for (idx = 0; idx < nsegs; idx++) {
2537 pSg[idx].dSgAddress = (ULONG_PTR)segs[idx].ds_addr;
2538 pSg[idx].wSgSize = segs[idx].ds_len;
2539 pSg[idx].wSgFlag = 0;
2540 }
2541 pSg[idx - 1].wSgFlag = SG_FLAG_EOT;
2542
2543 return;
2544}
2467 if(logical) {
2468 if (ccb->ccb_h.flags & CAM_DATA_PHYS)
2469 panic("physical address unsupported");
2545
2470
2546static int HPTLIBAPI
2547fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical)
2548{
2549 IAL_ADAPTER_T *pAdapter;
2550 pPrivCommand prvCmd;
2551 union ccb *ccb;
2552 struct ccb_hdr *ccb_h;
2553 struct ccb_scsiio *csio;
2554 bus_dma_segment_t *sgList;
2555 int error;
2556
2557 prvCmd = pCmd->pOrgCommand;
2558 pAdapter = prvCmd->pAdapter;
2559 ccb = prvCmd->ccb;
2560 ccb_h = &ccb->ccb_h;
2561 csio = &ccb->csio;
2562 sgList = (bus_dma_segment_t *)(csio->data_ptr);
2563
2564 if ((ccb_h->flags & CAM_DIR_MASK) == CAM_DIR_NONE)
2471 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) {
2472 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS)
2473 panic("physical address unsupported");
2474
2475 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) {
2476 pSg[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr;
2477 pSg[idx].wSgSize = sgList[idx].ds_len;
2478 pSg[idx].wSgFlag = (idx==ccb->csio.sglist_cnt-1)? SG_FLAG_EOT : 0;
2479 }
2480 }
2481 else {
2482 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr;
2483 pSg->wSgSize = ccb->csio.dxfer_len;
2484 pSg->wSgFlag = SG_FLAG_EOT;
2485 }
2565 return TRUE;
2486 return TRUE;
2566
2567 if ((ccb_h->flags & CAM_SCATTER_VALID) != 0) {
2568 if((ccb_h->flags & CAM_DATA_PHYS) != 0)
2569 panic(KMSG_LEADING "physical address unsupported!");
2570
2571 hptmv_buffer_callback(&pSg, sgList, csio->sglist_cnt, 0);
2572 return TRUE;
2573 }
2487 }
2574
2575 if (logical) {
2576 if ((ccb_h->flags & CAM_DATA_PHYS) != 0)
2577 panic(KMSG_LEADING "physical address unsupported\n");
2578
2579 pSg->dSgAddress = (ULONG_PTR)csio->data_ptr;
2580 pSg->wSgSize = (USHORT)csio->dxfer_len;
2581 pSg->wSgFlag = SG_FLAG_EOT;
2582 return TRUE;
2583 }
2584
2585 KdPrint(("use sgl (physical) ...........\n"));
2586
2587 /*
2588 * XXX Hack to make this work with PAE. It will fail under
2589 * heavy load.
2590 */
2591 error = bus_dmamap_load(pAdapter->buf_dmat, prvCmd->buf_map,
2592 csio->data_ptr, csio->dxfer_len, hptmv_buffer_callback, &pSg,
2593 BUS_DMA_NOWAIT);
2594
2595 if (error) {
2596 printf("bus_dmamap_load failed error= %d\n", error);
2597 return FALSE;
2598 }
2599
2600/*#ifdef DEBUG
2601 do {
2602 int size, i = 0;
2603 KdPrintI(("sg[%d]:0x%lx %d\n", i++, pSg[i].dSgAddress,
2604 pSg[i].wSgSize));
2605 size = pSg->wSgSize;
2606 if (pSg[i].wSgFlag & SG_FLAG_EOT)
2607 break;
2608 } while (i<17);
2609#endif*/
2610
2611 if ((ccb_h->flags & CAM_DIR_MASK) == CAM_DIR_IN) {
2612 bus_dmamap_sync(pAdapter->buf_dmat, prvCmd->buf_map,
2613 BUS_DMASYNC_PREREAD);
2614 } else {
2615 bus_dmamap_sync(pAdapter->buf_dmat, prvCmd->buf_map,
2616 BUS_DMASYNC_PREWRITE);
2617 }
2618
2619 return TRUE;
2488
2489 /* since we have provided physical sg, nobody will ask us to build physical sg */
2490 HPT_ASSERT(0);
2491 return FALSE;
2620}
2621
2622/*******************************************************************************/
2623ULONG HPTLIBAPI
2624GetStamp(void)
2625{
2492}
2493
2494/*******************************************************************************/
2495ULONG HPTLIBAPI
2496GetStamp(void)
2497{
2626 ULONG stamp;
2627
2628 /*
2629 * the system variable, ticks, can't be used since it hasn't yet been active
2630 * when our driver starts (ticks==0, it's a invalid stamp value)
2631 */
2498 /*
2499 * the system variable, ticks, can't be used since it hasn't yet been active
2500 * when our driver starts (ticks==0, it's a invalid stamp value)
2501 */
2632 do {
2633 stamp = random();
2634 } while (stamp==0);
2635
2502 ULONG stamp;
2503 do { stamp = random(); } while (stamp==0);
2636 return stamp;
2637}
2638
2639
2640static void
2641SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev)
2642{
2643 int i;
2504 return stamp;
2505}
2506
2507
2508static void
2509SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev)
2510{
2511 int i;
2644 IDENTIFY_DATA2 *pIdentify;
2645
2646 pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice;
2512 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice;
2513
2647 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/
2648 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5);
2649#ifndef SERIAL_CMDS
2650 inquiryData->CommandQueue = 1;
2651#endif
2652
2653 switch(pVDev->VDeviceType) {
2654 case VD_SINGLE_DISK:
2655 case VD_ATAPI:
2656 case VD_REMOVABLE:
2657 /* Set the removable bit, if applicable. */
2514 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/
2515 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5);
2516#ifndef SERIAL_CMDS
2517 inquiryData->CommandQueue = 1;
2518#endif
2519
2520 switch(pVDev->VDeviceType) {
2521 case VD_SINGLE_DISK:
2522 case VD_ATAPI:
2523 case VD_REMOVABLE:
2524 /* Set the removable bit, if applicable. */
2658 if ((pVDev->u.disk.df_removable_drive) ||
2659 (pIdentify->GeneralConfiguration & 0x80))
2525 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80))
2660 inquiryData->RemovableMedia = 1;
2661
2662 /* Fill in vendor identification fields. */
2526 inquiryData->RemovableMedia = 1;
2527
2528 /* Fill in vendor identification fields. */
2663 for (i = 0; i < 16; i += 2) {
2664 inquiryData->VendorId[i] =
2665 ((PUCHAR)pIdentify->ModelNumber)[i + 1];
2666 inquiryData->VendorId[i+1] =
2667 ((PUCHAR)pIdentify->ModelNumber)[i];
2529 for (i = 0; i < 20; i += 2) {
2530 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1];
2531 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i];
2668
2669 }
2670
2671 /* Initialize unused portion of product id. */
2672 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' ';
2673
2674 /* firmware revision */
2532
2533 }
2534
2535 /* Initialize unused portion of product id. */
2536 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' ';
2537
2538 /* firmware revision */
2675 for (i = 0; i < 4; i += 2) {
2676 inquiryData->ProductRevisionLevel[i] =
2677 ((PUCHAR)pIdentify->FirmwareRevision)[i+1];
2678 inquiryData->ProductRevisionLevel[i+1] =
2679 ((PUCHAR)pIdentify->FirmwareRevision)[i];
2539 for (i = 0; i < 4; i += 2)
2540 {
2541 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1];
2542 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i];
2680 }
2681 break;
2682 default:
2683 memcpy(&inquiryData->VendorId, "RR182x ", 8);
2684#ifdef SUPPORT_ARRAY
2543 }
2544 break;
2545 default:
2546 memcpy(&inquiryData->VendorId, "RR182x ", 8);
2547#ifdef SUPPORT_ARRAY
2685 switch(pVDev->VDeviceType) {
2548 switch(pVDev->VDeviceType){
2686 case VD_RAID_0:
2549 case VD_RAID_0:
2687 if ((pVDev->u.array.pMember[0] &&
2688 mIsArray(pVDev->u.array.pMember[0])) ||
2689 (pVDev->u.array.pMember[1] &&
2690 mIsArray(pVDev->u.array.pMember[1])))
2691 memcpy(&inquiryData->ProductId,
2692 "RAID 1/0 Array ", 16);
2550 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2551 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2552 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16);
2693 else
2553 else
2694 memcpy(&inquiryData->ProductId,
2695 "RAID 0 Array ", 16);
2554 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16);
2696 break;
2697 case VD_RAID_1:
2555 break;
2556 case VD_RAID_1:
2698 if ((pVDev->u.array.pMember[0] &&
2699 mIsArray(pVDev->u.array.pMember[0])) ||
2700 (pVDev->u.array.pMember[1] &&
2701 mIsArray(pVDev->u.array.pMember[1])))
2702 memcpy(&inquiryData->ProductId,
2703 "RAID 0/1 Array ", 16);
2557 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2558 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2559 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16);
2704 else
2560 else
2705 memcpy(&inquiryData->ProductId,
2706 "RAID 1 Array ", 16);
2561 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16);
2707 break;
2708 case VD_RAID_5:
2709 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16);
2710 break;
2711 case VD_JBOD:
2712 memcpy(&inquiryData->ProductId, "JBOD Array ", 16);
2713 break;
2714 }
2715#endif
2716 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4);
2717 break;
2718 }
2719}
2720
2721static void
2722hpt_timeout(void *arg)
2723{
2562 break;
2563 case VD_RAID_5:
2564 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16);
2565 break;
2566 case VD_JBOD:
2567 memcpy(&inquiryData->ProductId, "JBOD Array ", 16);
2568 break;
2569 }
2570#endif
2571 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4);
2572 break;
2573 }
2574}
2575
2576static void
2577hpt_timeout(void *arg)
2578{
2724 _VBUS_INST(&((IAL_ADAPTER_T*)((union ccb *)arg)->ccb_adapter)->VBus)
2725 intrmask_t oldspl;
2726
2727 oldspl = lock_driver();
2579 _VBUS_INST(&((PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter)->pAdapter->VBus)
2580 intrmask_t oldspl = lock_driver();
2728 fResetVBus(_VBUS_P0);
2729 unlock_driver(oldspl);
2730}
2731
2581 fResetVBus(_VBUS_P0);
2582 unlock_driver(oldspl);
2583}
2584
2585static void
2586hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2587{
2588 PCommand pCmd = (PCommand)arg;
2589 union ccb *ccb = pCmd->pOrgCommand;
2590 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2591 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter;
2592 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2593 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2594 FPSCAT_GATH psg = pCmd->pSgTable;
2595 int idx;
2596 _VBUS_INST(pVDev->pVBus)
2597
2598 HPT_ASSERT(pCmd->cf_physical_sg);
2599
2600 if (error || nsegs == 0)
2601 panic("busdma error");
2602
2603 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS);
2604
2605 for (idx = 0; idx < nsegs; idx++, psg++) {
2606 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr;
2607 psg->wSgSize = segs[idx].ds_len;
2608 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0;
2609/* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */
2610 }
2611/* psg[-1].wSgFlag = SG_FLAG_EOT; */
2612
2613 if (pCmd->cf_data_in) {
2614 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREREAD);
2615 }
2616 else if (pCmd->cf_data_out) {
2617 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREWRITE);
2618 }
2619
2620 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz);
2621 pVDev->pfnSendCommand(_VBUS_P pCmd);
2622 CheckPendingCall(_VBUS_P0);
2623}
2624
2625
2626
2732static void HPTLIBAPI
2733OsSendCommand(_VBUS_ARG union ccb *ccb)
2734{
2627static void HPTLIBAPI
2628OsSendCommand(_VBUS_ARG union ccb *ccb)
2629{
2735 IAL_ADAPTER_T *pAdapter;
2736 struct ccb_hdr *ccb_h;
2737 struct ccb_scsiio *csio;
2738 PVDevice pVDev;
2739
2740 pAdapter = (IAL_ADAPTER_T *)ccb->ccb_adapter;
2741 ccb_h = &ccb->ccb_h;
2742 csio = &ccb->csio;
2743 pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2630 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2631 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2632 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2633 struct ccb_scsiio *csio = &ccb->csio;
2634 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2744
2635
2745 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n",
2636 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n",
2746 ccb,
2747 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0],
2748 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4],
2749 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8]
2750 ));
2751
2752 pAdapter->outstandingCommands++;
2753
2754 if (pVDev == NULL || pVDev->vf_online == 0) {
2755 ccb->ccb_h.status = CAM_REQ_INVALID;
2756 ccb_done(ccb);
2757 goto Command_Complished;
2758 }
2759
2760 switch(ccb->csio.cdb_io.cdb_bytes[0])
2761 {
2637 ccb,
2638 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0],
2639 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4],
2640 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8]
2641 ));
2642
2643 pAdapter->outstandingCommands++;
2644
2645 if (pVDev == NULL || pVDev->vf_online == 0) {
2646 ccb->ccb_h.status = CAM_REQ_INVALID;
2647 ccb_done(ccb);
2648 goto Command_Complished;
2649 }
2650
2651 switch(ccb->csio.cdb_io.cdb_bytes[0])
2652 {
2762 case TEST_UNIT_READY:
2763 case START_STOP_UNIT:
2764 case SYNCHRONIZE_CACHE:
2765 /* FALLTHROUGH */
2766 ccb->ccb_h.status = CAM_REQ_CMP;
2767 break;
2653 case TEST_UNIT_READY:
2654 case START_STOP_UNIT:
2655 case SYNCHRONIZE_CACHE:
2656 /* FALLTHROUGH */
2657 ccb->ccb_h.status = CAM_REQ_CMP;
2658 break;
2768
2659
2769 case INQUIRY:
2770 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len);
2771 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev);
2772 ccb_h->status = CAM_REQ_CMP;
2773 break;
2660 case INQUIRY:
2661 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len);
2662 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev);
2663 ccb_h->status = CAM_REQ_CMP;
2664 break;
2774
2665
2775 case READ_CAPACITY:
2776 {
2777 UCHAR swip[4];
2778 /* Claim 512 byte blocks (big-endian). */
2779 ((PREAD_CAPACITY_DATA)csio->data_ptr)->BytesPerBlock = 0x20000;
2780 *(ULONG*)swip = pVDev->VDeviceCapacity - 1;
2781 ((PREAD_CAPACITY_DATA)csio->data_ptr)->LogicalBlockAddress =
2782 (swip[0] << 24) | (swip[1] << 16) | (swip[2] << 8) | swip[3];
2783 ccb_h->status = CAM_REQ_CMP;
2784 break;
2785 }
2786
2787 case READ_6:
2788 case WRITE_6:
2789 case READ_10:
2790 case WRITE_10:
2791 case 0x13:
2792 case 0x2f:
2793 {
2794 UCHAR Cdb[16];
2795 UCHAR CdbLength;
2796 _VBUS_INST(pVDev->pVBus)
2797 PCommand pCmd;
2798
2799 pCmd = AllocateCommand(_VBUS_P0);
2800 HPT_ASSERT(pCmd);
2801
2802 CdbLength = csio->cdb_len;
2803 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) {
2804 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) {
2805 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength);
2806 } else {
2807 KdPrintE(("ERROR!!!\n"));
2808 ccb->ccb_h.status = CAM_REQ_INVALID;
2809 break;
2810 }
2811 } else {
2812 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength);
2813 }
2814
2815 pCmd->pOrgCommand = AllocPrivCommand(pAdapter);
2816 if (pCmd->pOrgCommand == NULL)
2817 panic("command leak!");
2818 ((pPrivCommand)(pCmd->pOrgCommand))->ccb = ccb;
2819 pCmd->pVDevice = pVDev;
2820 pCmd->pfnCompletion = fOsCommandDone;
2821 pCmd->pfnBuildSgl = fOsBuildSgl;
2822
2823 switch (Cdb[0]) {
2824 case READ_6:
2825 case WRITE_6:
2826 case 0x13:
2827 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) |
2828 ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3];
2829 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4];
2666 case READ_CAPACITY:
2667 {
2668 UCHAR swip[4];
2669 /* Claim 512 byte blocks (big-endian). */
2670 ((PREAD_CAPACITY_DATA)csio->data_ptr)->BytesPerBlock = 0x20000;
2671 *(ULONG*)swip = pVDev->VDeviceCapacity - 1;
2672 ((PREAD_CAPACITY_DATA)csio->data_ptr)->LogicalBlockAddress =
2673 (swip[0] << 24) | (swip[1] << 16) | (swip[2] << 8) | swip[3];
2674 ccb_h->status = CAM_REQ_CMP;
2830 break;
2675 break;
2831 default:
2832 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] |
2833 ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) |
2834 ((ULONG)Cdb[2] << 24);
2835 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] |
2836 ((USHORT)Cdb[7]<<8);
2837 break;
2838 }
2839
2676 }
2677
2840 switch (Cdb[0]) {
2841 case READ_6:
2678 case READ_6:
2842 case READ_10:
2843 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ;
2844 pCmd->cf_data_in = 1;
2845 break;
2846
2847 case WRITE_6:
2679 case WRITE_6:
2680 case READ_10:
2848 case WRITE_10:
2681 case WRITE_10:
2849 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE;
2850 pCmd->cf_data_out = 1;
2851 break;
2852 case 0x13:
2853 case 0x2f:
2682 case 0x13:
2683 case 0x2f:
2854 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY;
2855 break;
2856 }
2684 {
2685 UCHAR Cdb[16];
2686 UCHAR CdbLength;
2687 _VBUS_INST(pVDev->pVBus)
2688 PCommand pCmd = AllocateCommand(_VBUS_P0);
2689 HPT_ASSERT(pCmd);
2857
2690
2858 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz);
2691 CdbLength = csio->cdb_len;
2692 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0)
2693 {
2694 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0)
2695 {
2696 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength);
2697 }
2698 else
2699 {
2700 KdPrintE(("ERROR!!!\n"));
2701 ccb->ccb_h.status = CAM_REQ_INVALID;
2702 break;
2703 }
2704 }
2705 else
2706 {
2707 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength);
2708 }
2859
2709
2860 pVDev->pfnSendCommand(_VBUS_P pCmd);
2861 goto Command_Complished;
2862 }
2710 pCmd->pOrgCommand = ccb;
2711 pCmd->pVDevice = pVDev;
2712 pCmd->pfnCompletion = fOsCommandDone;
2713 pCmd->pfnBuildSgl = fOsBuildSgl;
2714 pCmd->pSgTable = pmap->psg;
2863
2715
2864 default:
2865 ccb->ccb_h.status = CAM_REQ_INVALID;
2866 break;
2716 switch (Cdb[0])
2717 {
2718 case READ_6:
2719 case WRITE_6:
2720 case 0x13:
2721 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3];
2722 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4];
2723 break;
2724
2725 default:
2726 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24);
2727 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8);
2728 break;
2729 }
2730
2731 switch (Cdb[0])
2732 {
2733 case READ_6:
2734 case READ_10:
2735 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ;
2736 pCmd->cf_data_in = 1;
2737 break;
2738
2739 case WRITE_6:
2740 case WRITE_10:
2741 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE;
2742 pCmd->cf_data_out = 1;
2743 break;
2744 case 0x13:
2745 case 0x2f:
2746 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY;
2747 break;
2748 }
2749/*///////////////////////// */
2750 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) {
2751 int idx;
2752 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr;
2753
2754 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS)
2755 pCmd->cf_physical_sg = 1;
2756
2757 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) {
2758 pCmd->pSgTable[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr;
2759 pCmd->pSgTable[idx].wSgSize = sgList[idx].ds_len;
2760 pCmd->pSgTable[idx].wSgFlag= (idx==ccb->csio.sglist_cnt-1)?SG_FLAG_EOT: 0;
2761 }
2762
2763 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz);
2764 pVDev->pfnSendCommand(_VBUS_P pCmd);
2765 }
2766 else {
2767 int error;
2768 pCmd->cf_physical_sg = 1;
2769 error = bus_dmamap_load(pAdapter->io_dma_parent,
2770 pmap->dma_map,
2771 ccb->csio.data_ptr, ccb->csio.dxfer_len,
2772 hpt_io_dmamap_callback, pCmd,
2773 BUS_DMA_WAITOK
2774 );
2775 KdPrint(("bus_dmamap_load return %d\n", error));
2776 if (error && error!=EINPROGRESS) {
2777 hpt_printk(("bus_dmamap_load error %d\n", error));
2778 FreeCommand(_VBUS_P pCmd);
2779 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
2780 dmamap_put(pmap);
2781 pAdapter->outstandingCommands--;
2782 xpt_done(ccb);
2783 }
2784 }
2785 goto Command_Complished;
2786 }
2787
2788 default:
2789 ccb->ccb_h.status = CAM_REQ_INVALID;
2790 break;
2867 }
2868 ccb_done(ccb);
2869Command_Complished:
2870 CheckPendingCall(_VBUS_P0);
2871 return;
2872}
2873
2791 }
2792 ccb_done(ccb);
2793Command_Complished:
2794 CheckPendingCall(_VBUS_P0);
2795 return;
2796}
2797
2874static void HPTLIBAPI
2798static void HPTLIBAPI
2875fOsCommandDone(_VBUS_ARG PCommand pCmd)
2876{
2799fOsCommandDone(_VBUS_ARG PCommand pCmd)
2800{
2877 IAL_ADAPTER_T *pAdapter;
2878 pPrivCommand prvCmd;
2879 union ccb *ccb;
2801 union ccb *ccb = pCmd->pOrgCommand;
2802 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2803 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2880
2804
2881 prvCmd = pCmd->pOrgCommand;
2882 pAdapter = prvCmd->pAdapter;
2883 ccb = prvCmd->ccb;
2884
2885 KdPrint(("fOsCommandDone(%p, %d)", pCmd, pCmd->Result));
2805 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result));
2886
2887 untimeout(hpt_timeout, (caddr_t)ccb, ccb->ccb_h.timeout_ch);
2888
2889 switch(pCmd->Result) {
2890 case RETURN_SUCCESS:
2891 ccb->ccb_h.status = CAM_REQ_CMP;
2892 break;
2893 case RETURN_BAD_DEVICE:

--- 11 unchanged lines hidden (view full) ---

2905 case RETURN_RETRY:
2906 ccb->ccb_h.status = CAM_BUSY;
2907 break;
2908 default:
2909 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2910 break;
2911 }
2912
2806
2807 untimeout(hpt_timeout, (caddr_t)ccb, ccb->ccb_h.timeout_ch);
2808
2809 switch(pCmd->Result) {
2810 case RETURN_SUCCESS:
2811 ccb->ccb_h.status = CAM_REQ_CMP;
2812 break;
2813 case RETURN_BAD_DEVICE:

--- 11 unchanged lines hidden (view full) ---

2825 case RETURN_RETRY:
2826 ccb->ccb_h.status = CAM_BUSY;
2827 break;
2828 default:
2829 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2830 break;
2831 }
2832
2913 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
2914 bus_dmamap_sync(pAdapter->buf_dmat, prvCmd->buf_map,
2915 BUS_DMASYNC_POSTREAD);
2916 } else {
2917 bus_dmamap_sync(pAdapter->buf_dmat, prvCmd->buf_map,
2918 BUS_DMASYNC_POSTWRITE);
2833 if (pCmd->cf_data_in) {
2834 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD);
2919 }
2835 }
2920 bus_dmamap_unload(pAdapter->buf_dmat, prvCmd->buf_map);
2836 else if (pCmd->cf_data_in) {
2837 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE);
2838 }
2839
2840 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map);
2921
2841
2922 FreePrivCommand(pAdapter, prvCmd);
2923 FreeCommand(_VBUS_P pCmd);
2924 ccb_done(ccb);
2925}
2926
2927int
2928hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags)
2929{
2930 int p;

--- 10 unchanged lines hidden (view full) ---

2941 DpcQueue[DpcQueue_Last].flags = flags;
2942 DpcQueue_Last = p;
2943
2944 return 0;
2945}
2946
2947#ifdef _RAID5N_
2948/*
2842 FreeCommand(_VBUS_P pCmd);
2843 ccb_done(ccb);
2844}
2845
2846int
2847hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags)
2848{
2849 int p;

--- 10 unchanged lines hidden (view full) ---

2860 DpcQueue[DpcQueue_Last].flags = flags;
2861 DpcQueue_Last = p;
2862
2863 return 0;
2864}
2865
2866#ifdef _RAID5N_
2867/*
2949 * Allocate memory above 16M, otherwise we may eat all low memory for ISA
2950 * devices.
2951 *
2952 * Busdma should be used here, not contigmalloc/free. However, this API
2953 * will need to be changed to use it effective.
2868 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices.
2869 * How about the memory for 5081 request/response array and PRD table?
2954 */
2955void
2956*os_alloc_page(_VBUS_ARG0)
2957{
2870 */
2871void
2872*os_alloc_page(_VBUS_ARG0)
2873{
2958 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000,
2959 0xffffffff, PAGE_SIZE, 0);
2874 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2960}
2875}
2876
2961void
2962*os_alloc_dma_page(_VBUS_ARG0)
2963{
2877void
2878*os_alloc_dma_page(_VBUS_ARG0)
2879{
2964 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000,
2965 0xffffffff, PAGE_SIZE, 0);
2880 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2966}
2967
2881}
2882
2968/*
2969 * The next two are not used right now.
2970 */
2971void
2883void
2972os_free_page(_VBUS_ARG void *p)
2973{
2974 contigfree(p, 0x1000, M_DEVBUF);
2884os_free_page(_VBUS_ARG void *p)
2885{
2886 contigfree(p, 0x1000, M_DEVBUF);
2975}
2976
2977void
2887}
2888
2889void
2978os_free_dma_page(_VBUS_ARG void *p)
2979{
2980 contigfree(p, 0x1000, M_DEVBUF);
2890os_free_dma_page(_VBUS_ARG void *p)
2891{
2892 contigfree(p, 0x1000, M_DEVBUF);
2981}
2982
2983void
2984DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes)
2985{
2986 UINT i;
2893}
2894
2895void
2896DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes)
2897{
2898 UINT i;
2987 for (i = 0; i < nBytes / 4; i++)
2988 *p0++ = *p1++ ^ *p2++;
2899 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++;
2989}
2990
2991void
2992DoXor2(ULONG *p0, ULONG *p2, UINT nBytes)
2993{
2994 UINT i;
2900}
2901
2902void
2903DoXor2(ULONG *p0, ULONG *p2, UINT nBytes)
2904{
2905 UINT i;
2995 for (i = 0; i < nBytes / 4; i++)
2996 *p0++ ^= *p2++;
2906 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++;
2997}
2998#endif
2907}
2908#endif