| if_gemvar.h (177560) | if_gemvar.h (194763) |
|---|---|
| 1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp 27 * | 1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp 27 * |
| 28 * $FreeBSD: head/sys/dev/gem/if_gemvar.h 177560 2008-03-24 17:23:53Z marius $ | 28 * $FreeBSD: head/sys/dev/gem/if_gemvar.h 194763 2009-06-23 20:36:59Z marius $ |
| 29 */ 30 31#ifndef _IF_GEMVAR_H 32#define _IF_GEMVAR_H 33 34#include <sys/queue.h> 35#include <sys/callout.h> 36 37/* | 29 */ 30 31#ifndef _IF_GEMVAR_H 32#define _IF_GEMVAR_H 33 34#include <sys/queue.h> 35#include <sys/callout.h> 36 37/* |
| 38 * Transmit descriptor list size. This is arbitrary, but allocate | 38 * Transmit descriptor ring size - this is arbitrary, but allocate |
| 39 * enough descriptors for 64 pending transmissions and 16 segments 40 * per packet. This limit is not actually enforced (packets with 41 * more segments can be sent, depending on the busdma backend); it 42 * is however used as an estimate for the TX window size. 43 */ 44#define GEM_NTXSEGS 16 45 46#define GEM_TXQUEUELEN 64 47#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS) 48#define GEM_MAXTXFREE (GEM_NTXDESC - 1) 49#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1) 50#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) 51 52/* | 39 * enough descriptors for 64 pending transmissions and 16 segments 40 * per packet. This limit is not actually enforced (packets with 41 * more segments can be sent, depending on the busdma backend); it 42 * is however used as an estimate for the TX window size. 43 */ 44#define GEM_NTXSEGS 16 45 46#define GEM_TXQUEUELEN 64 47#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS) 48#define GEM_MAXTXFREE (GEM_NTXDESC - 1) 49#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1) 50#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) 51 52/* |
| 53 * Receive descriptor list size. We have one RX buffer per incoming | 53 * Receive descriptor ring size - we have one RX buffer per incoming |
| 54 * packet, so this logic is a little simpler. 55 */ 56#define GEM_NRXDESC 256 57#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1) 58#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) 59 60/* 61 * How many ticks to wait until to retry on a RX descriptor that is 62 * still owned by the hardware. 63 */ 64#define GEM_RXOWN_TICKS (hz / 50) 65 66/* | 54 * packet, so this logic is a little simpler. 55 */ 56#define GEM_NRXDESC 256 57#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1) 58#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) 59 60/* 61 * How many ticks to wait until to retry on a RX descriptor that is 62 * still owned by the hardware. 63 */ 64#define GEM_RXOWN_TICKS (hz / 50) 65 66/* |
| 67 * Control structures are DMA'd to the GEM chip. We allocate them | 67 * Control structures are DMA'd to the chip. We allocate them |
| 68 * in a single clump that maps to a single DMA segment to make 69 * several things easier. 70 */ 71struct gem_control_data { 72 struct gem_desc gcd_txdescs[GEM_NTXDESC]; /* TX descriptors */ 73 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; /* RX descriptors */ 74}; 75 76#define GEM_CDOFF(x) offsetof(struct gem_control_data, x) 77#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)]) 78#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) 79 80/* 81 * software state for transmit job mbufs (may be elements of mbuf chains) 82 */ 83struct gem_txsoft { 84 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 85 bus_dmamap_t txs_dmamap; /* our DMA map */ | 68 * in a single clump that maps to a single DMA segment to make 69 * several things easier. 70 */ 71struct gem_control_data { 72 struct gem_desc gcd_txdescs[GEM_NTXDESC]; /* TX descriptors */ 73 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; /* RX descriptors */ 74}; 75 76#define GEM_CDOFF(x) offsetof(struct gem_control_data, x) 77#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)]) 78#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) 79 80/* 81 * software state for transmit job mbufs (may be elements of mbuf chains) 82 */ 83struct gem_txsoft { 84 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 85 bus_dmamap_t txs_dmamap; /* our DMA map */ |
| 86 int txs_firstdesc; /* first descriptor in packet */ 87 int txs_lastdesc; /* last descriptor in packet */ 88 int txs_ndescs; /* number of descriptors */ | 86 u_int txs_firstdesc; /* first descriptor in packet */ 87 u_int txs_lastdesc; /* last descriptor in packet */ 88 u_int txs_ndescs; /* number of descriptors */ |
| 89 STAILQ_ENTRY(gem_txsoft) txs_q; 90}; 91 92STAILQ_HEAD(gem_txsq, gem_txsoft); 93 94/* 95 * software state for receive jobs 96 */ --- 10 unchanged lines hidden (view full) --- 107 struct ifnet *sc_ifp; 108 struct mtx sc_mtx; 109 device_t sc_miibus; 110 struct mii_data *sc_mii; /* MII media control */ 111 device_t sc_dev; /* generic device information */ 112 u_char sc_enaddr[ETHER_ADDR_LEN]; 113 struct callout sc_tick_ch; /* tick callout */ 114 struct callout sc_rx_ch; /* delayed RX callout */ | 89 STAILQ_ENTRY(gem_txsoft) txs_q; 90}; 91 92STAILQ_HEAD(gem_txsq, gem_txsoft); 93 94/* 95 * software state for receive jobs 96 */ --- 10 unchanged lines hidden (view full) --- 107 struct ifnet *sc_ifp; 108 struct mtx sc_mtx; 109 device_t sc_miibus; 110 struct mii_data *sc_mii; /* MII media control */ 111 device_t sc_dev; /* generic device information */ 112 u_char sc_enaddr[ETHER_ADDR_LEN]; 113 struct callout sc_tick_ch; /* tick callout */ 114 struct callout sc_rx_ch; /* delayed RX callout */ |
| 115 int sc_wdog_timer; /* watchdog timer */ | 115 u_int sc_wdog_timer; /* watchdog timer */ |
| 116 117 void *sc_ih; 118 struct resource *sc_res[3]; 119#define GEM_RES_INTR 0 120#define GEM_RES_BANK1 1 121#define GEM_RES_BANK2 2 122 123 bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */ --- 12 unchanged lines hidden (view full) --- 136#define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */ 137 138#define GEM_IS_APPLE(sc) \ 139 ((sc)->sc_variant == GEM_APPLE_GMAC || \ 140 (sc)->sc_variant == GEM_APPLE_K2_GMAC) 141 142 u_int sc_flags; 143#define GEM_INITED (1 << 0) /* reset persistent regs init'ed */ | 116 117 void *sc_ih; 118 struct resource *sc_res[3]; 119#define GEM_RES_INTR 0 120#define GEM_RES_BANK1 1 121#define GEM_RES_BANK2 2 122 123 bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */ --- 12 unchanged lines hidden (view full) --- 136#define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */ 137 138#define GEM_IS_APPLE(sc) \ 139 ((sc)->sc_variant == GEM_APPLE_GMAC || \ 140 (sc)->sc_variant == GEM_APPLE_K2_GMAC) 141 142 u_int sc_flags; 143#define GEM_INITED (1 << 0) /* reset persistent regs init'ed */ |
| 144#define GEM_LINK (1 << 1) /* link is up */ 145#define GEM_PCI (1 << 2) /* PCI busses are little-endian */ 146#define GEM_SERDES (1 << 3) /* use the SERDES */ | 144#define GEM_DYING (1 << 1) /* detach initiated */ 145#define GEM_LINK (1 << 2) /* link is up */ 146#define GEM_PCI (1 << 3) /* PCI busses are little-endian */ 147#define GEM_PCI66 (1 << 4) /* PCI bus runs at 66MHz */ 148#define GEM_SERDES (1 << 5) /* use the SERDES */ |
| 147 148 /* 149 * ring buffer DMA stuff 150 */ | 149 150 /* 151 * ring buffer DMA stuff 152 */ |
| 151 bus_dma_segment_t sc_cdseg; /* control data memory */ 152 int sc_cdnseg; /* number of segments */ | |
| 153 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 154 bus_addr_t sc_cddma; 155 156 /* 157 * software state for transmit and receive descriptors 158 */ 159 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; 160 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; 161 162 /* 163 * control data structures 164 */ 165 struct gem_control_data *sc_control_data; 166#define sc_txdescs sc_control_data->gcd_txdescs 167#define sc_rxdescs sc_control_data->gcd_rxdescs 168 | 153 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 154 bus_addr_t sc_cddma; 155 156 /* 157 * software state for transmit and receive descriptors 158 */ 159 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; 160 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; 161 162 /* 163 * control data structures 164 */ 165 struct gem_control_data *sc_control_data; 166#define sc_txdescs sc_control_data->gcd_txdescs 167#define sc_rxdescs sc_control_data->gcd_rxdescs 168 |
| 169 int sc_txfree; /* number of free TX descriptors */ 170 int sc_txnext; /* next ready TX descriptor */ 171 int sc_txwin; /* TX desc. since last TX intr. */ | 169 u_int sc_txfree; /* number of free TX descriptors */ 170 u_int sc_txnext; /* next ready TX descriptor */ 171 u_int sc_txwin; /* TX desc. since last TX intr. */ |
| 172 173 struct gem_txsq sc_txfreeq; /* free TX descsofts */ 174 struct gem_txsq sc_txdirtyq; /* dirty TX descsofts */ 175 | 172 173 struct gem_txsq sc_txfreeq; /* free TX descsofts */ 174 struct gem_txsq sc_txdirtyq; /* dirty TX descsofts */ 175 |
| 176 int sc_rxptr; /* next ready RX desc./descsoft */ 177 int sc_rxfifosize; /* RX FIFO size (bytes) */ | 176 u_int sc_rxptr; /* next ready RX descriptor/state */ 177 u_int sc_rxfifosize; /* RX FIFO size (bytes) */ |
| 178 179 int sc_ifflags; | 178 179 int sc_ifflags; |
| 180 int sc_csum_features; | 180 u_long sc_csum_features; |
| 181}; 182 183#define GEM_BANKN_BARRIER(n, sc, offs, len, flags) \ 184 bus_barrier((sc)->sc_res[(n)], (offs), (len), (flags)) 185#define GEM_BANK1_BARRIER(sc, offs, len, flags) \ 186 GEM_BANKN_BARRIER(GEM_RES_BANK1, (sc), (offs), (len), (flags)) 187#define GEM_BANK2_BARRIER(sc, offs, len, flags) \ 188 GEM_BANKN_BARRIER(GEM_RES_BANK2, (sc), (offs), (len), (flags)) --- 44 unchanged lines hidden (view full) --- 233do { \ 234 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 235 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 236 struct mbuf *__m = __rxs->rxs_mbuf; \ 237 \ 238 __m->m_data = __m->m_ext.ext_buf; \ 239 __rxd->gd_addr = \ 240 GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \ | 181}; 182 183#define GEM_BANKN_BARRIER(n, sc, offs, len, flags) \ 184 bus_barrier((sc)->sc_res[(n)], (offs), (len), (flags)) 185#define GEM_BANK1_BARRIER(sc, offs, len, flags) \ 186 GEM_BANKN_BARRIER(GEM_RES_BANK1, (sc), (offs), (len), (flags)) 187#define GEM_BANK2_BARRIER(sc, offs, len, flags) \ 188 GEM_BANKN_BARRIER(GEM_RES_BANK2, (sc), (offs), (len), (flags)) --- 44 unchanged lines hidden (view full) --- 233do { \ 234 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 235 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 236 struct mbuf *__m = __rxs->rxs_mbuf; \ 237 \ 238 __m->m_data = __m->m_ext.ext_buf; \ 239 __rxd->gd_addr = \ 240 GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \ |
| 241 __rxd->gd_flags = \ 242 GEM_DMA_WRITE((sc), \ 243 (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) \ 244 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ | 241 __rxd->gd_flags = GEM_DMA_WRITE((sc), \ 242 (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) & \ 243 GEM_RD_BUFSIZE) | GEM_RD_OWN); \ |
| 245} while (0) 246 247#define GEM_UPDATE_RXDESC(sc, x) \ 248do { \ 249 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 250 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 251 struct mbuf *__m = __rxs->rxs_mbuf; \ 252 \ | 244} while (0) 245 246#define GEM_UPDATE_RXDESC(sc, x) \ 247do { \ 248 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 249 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 250 struct mbuf *__m = __rxs->rxs_mbuf; \ 251 \ |
| 253 __rxd->gd_flags = \ 254 GEM_DMA_WRITE((sc), \ 255 (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) \ 256 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ | 252 __rxd->gd_flags = GEM_DMA_WRITE((sc), \ 253 (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) & \ 254 GEM_RD_BUFSIZE) | GEM_RD_OWN); \ |
| 257} while (0) 258 259#define GEM_LOCK_INIT(_sc, _name) \ 260 mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 261#define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 262#define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 263#define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what)) 264#define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) --- 21 unchanged lines hidden --- | 255} while (0) 256 257#define GEM_LOCK_INIT(_sc, _name) \ 258 mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 259#define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 260#define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 261#define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what)) 262#define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) --- 21 unchanged lines hidden --- |