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if_gemvar.h (172334) if_gemvar.h (174987)
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp
27 *
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp
27 *
28 * $FreeBSD: head/sys/dev/gem/if_gemvar.h 172334 2007-09-26 21:14:18Z marius $
28 * $FreeBSD: head/sys/dev/gem/if_gemvar.h 174987 2007-12-30 01:32:03Z marius $
29 */
30
31#ifndef _IF_GEMVAR_H
32#define _IF_GEMVAR_H
33
29 */
30
31#ifndef _IF_GEMVAR_H
32#define _IF_GEMVAR_H
33
34
35#include <sys/queue.h>
36#include <sys/callout.h>
37
38/*
34#include <sys/queue.h>
35#include <sys/callout.h>
36
37/*
39 * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver.
40 */
41
42/*
43 * Transmit descriptor list size. This is arbitrary, but allocate
44 * enough descriptors for 64 pending transmissions and 16 segments
38 * Transmit descriptor list size. This is arbitrary, but allocate
39 * enough descriptors for 64 pending transmissions and 16 segments
45 * per packet. This limit is not actually enforced (packets with more segments
46 * can be sent, depending on the busdma backend); it is however used as an
47 * estimate for the tx window size.
40 * per packet. This limit is not actually enforced (packets with
41 * more segments can be sent, depending on the busdma backend); it
42 * is however used as an estimate for the TX window size.
48 */
49#define GEM_NTXSEGS 16
50
51#define GEM_TXQUEUELEN 64
52#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS)
53#define GEM_MAXTXFREE (GEM_NTXDESC - 1)
54#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1)
55#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
56
57/*
43 */
44#define GEM_NTXSEGS 16
45
46#define GEM_TXQUEUELEN 64
47#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS)
48#define GEM_MAXTXFREE (GEM_NTXDESC - 1)
49#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1)
50#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
51
52/*
58 * Receive descriptor list size. We have one Rx buffer per incoming
53 * Receive descriptor list size. We have one RX buffer per incoming
59 * packet, so this logic is a little simpler.
60 */
61#define GEM_NRXDESC 256
62#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
63#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
64
65/*
54 * packet, so this logic is a little simpler.
55 */
56#define GEM_NRXDESC 256
57#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
58#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
59
60/*
66 * How many ticks to wait until to retry on a RX descriptor that is still owned
67 * by the hardware.
61 * How many ticks to wait until to retry on a RX descriptor that is
62 * still owned by the hardware.
68 */
69#define GEM_RXOWN_TICKS (hz / 50)
70
71/*
63 */
64#define GEM_RXOWN_TICKS (hz / 50)
65
66/*
72 * Control structures are DMA'd to the GEM chip. We allocate them in
73 * a single clump that maps to a single DMA segment to make several things
74 * easier.
67 * Control structures are DMA'd to the GEM chip. We allocate them
68 * in a single clump that maps to a single DMA segment to make
69 * several things easier.
75 */
76struct gem_control_data {
70 */
71struct gem_control_data {
77 /*
78 * The transmit descriptors.
79 */
80 struct gem_desc gcd_txdescs[GEM_NTXDESC];
81
82 /*
83 * The receive descriptors.
84 */
85 struct gem_desc gcd_rxdescs[GEM_NRXDESC];
72 struct gem_desc gcd_txdescs[GEM_NTXDESC]; /* TX descriptors */
73 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; /* RX descriptors */
86};
87
88#define GEM_CDOFF(x) offsetof(struct gem_control_data, x)
89#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)])
90#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)])
91
92/*
74};
75
76#define GEM_CDOFF(x) offsetof(struct gem_control_data, x)
77#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)])
78#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)])
79
80/*
93 * Software state for transmit job mbufs (may be elements of mbuf chains).
81 * software state for transmit job mbufs (may be elements of mbuf chains)
94 */
95struct gem_txsoft {
96 struct mbuf *txs_mbuf; /* head of our mbuf chain */
97 bus_dmamap_t txs_dmamap; /* our DMA map */
98 int txs_firstdesc; /* first descriptor in packet */
99 int txs_lastdesc; /* last descriptor in packet */
100 int txs_ndescs; /* number of descriptors */
101 STAILQ_ENTRY(gem_txsoft) txs_q;
102};
103
104STAILQ_HEAD(gem_txsq, gem_txsoft);
105
106/*
82 */
83struct gem_txsoft {
84 struct mbuf *txs_mbuf; /* head of our mbuf chain */
85 bus_dmamap_t txs_dmamap; /* our DMA map */
86 int txs_firstdesc; /* first descriptor in packet */
87 int txs_lastdesc; /* last descriptor in packet */
88 int txs_ndescs; /* number of descriptors */
89 STAILQ_ENTRY(gem_txsoft) txs_q;
90};
91
92STAILQ_HEAD(gem_txsq, gem_txsoft);
93
94/*
107 * Software state for receive jobs.
95 * software state for receive jobs
108 */
109struct gem_rxsoft {
110 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
111 bus_dmamap_t rxs_dmamap; /* our DMA map */
112 bus_addr_t rxs_paddr; /* physical address of the segment */
113};
114
115/*
96 */
97struct gem_rxsoft {
98 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
99 bus_dmamap_t rxs_dmamap; /* our DMA map */
100 bus_addr_t rxs_paddr; /* physical address of the segment */
101};
102
103/*
116 * Software state per device.
104 * software state per device
117 */
118struct gem_softc {
119 struct ifnet *sc_ifp;
120 struct mtx sc_mtx;
121 device_t sc_miibus;
122 struct mii_data *sc_mii; /* MII media control */
123 device_t sc_dev; /* generic device information */
124 u_char sc_enaddr[ETHER_ADDR_LEN];
125 struct callout sc_tick_ch; /* tick callout */
105 */
106struct gem_softc {
107 struct ifnet *sc_ifp;
108 struct mtx sc_mtx;
109 device_t sc_miibus;
110 struct mii_data *sc_mii; /* MII media control */
111 device_t sc_dev; /* generic device information */
112 u_char sc_enaddr[ETHER_ADDR_LEN];
113 struct callout sc_tick_ch; /* tick callout */
126 struct callout sc_rx_ch; /* delayed rx callout */
114 struct callout sc_rx_ch; /* delayed RX callout */
127 int sc_wdog_timer; /* watchdog timer */
128
129 void *sc_ih;
130 struct resource *sc_res[2];
115 int sc_wdog_timer; /* watchdog timer */
116
117 void *sc_ih;
118 struct resource *sc_res[2];
131 bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */
132 bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */
133 bus_dma_tag_t sc_tdmatag; /* TX bus dma tag */
134 bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */
135 bus_dmamap_t sc_dmamap; /* bus dma handle */
119 bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */
120 bus_dma_tag_t sc_rdmatag; /* RX bus DMA tag */
121 bus_dma_tag_t sc_tdmatag; /* TX bus DMA tag */
122 bus_dma_tag_t sc_cdmatag; /* control data bus DMA tag */
123 bus_dmamap_t sc_dmamap; /* bus DMA handle */
136
124
137 int sc_phyad; /* addr. of PHY to use or -1 for any */
125 int sc_phyad; /* PHY to use or -1 for any */
138
126
139 u_int sc_variant; /* which GEM are we dealing with? */
127 u_int sc_variant;
140#define GEM_UNKNOWN 0 /* don't know */
141#define GEM_SUN_GEM 1 /* Sun GEM */
142#define GEM_SUN_ERI 2 /* Sun ERI */
143#define GEM_APPLE_GMAC 3 /* Apple GMAC */
144#define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */
145
146#define GEM_IS_APPLE(sc) \
147 ((sc)->sc_variant == GEM_APPLE_GMAC || \
148 (sc)->sc_variant == GEM_APPLE_K2_GMAC)
149
128#define GEM_UNKNOWN 0 /* don't know */
129#define GEM_SUN_GEM 1 /* Sun GEM */
130#define GEM_SUN_ERI 2 /* Sun ERI */
131#define GEM_APPLE_GMAC 3 /* Apple GMAC */
132#define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */
133
134#define GEM_IS_APPLE(sc) \
135 ((sc)->sc_variant == GEM_APPLE_GMAC || \
136 (sc)->sc_variant == GEM_APPLE_K2_GMAC)
137
150 u_int sc_flags; /* */
151#define GEM_INITED (1 << 0) /* reset persistent regs initialized */
138 u_int sc_flags;
139#define GEM_INITED (1 << 0) /* reset persistent regs init'ed */
152#define GEM_LINK (1 << 1) /* link is up */
140#define GEM_LINK (1 << 1) /* link is up */
153#define GEM_PCI (1 << 2) /* XXX PCI busses are little-endian */
141#define GEM_PCI (1 << 2) /* PCI busses are little-endian */
154#define GEM_SERDES (1 << 3) /* use the SERDES */
155
156 /*
142#define GEM_SERDES (1 << 3) /* use the SERDES */
143
144 /*
157 * Ring buffer DMA stuff.
145 * ring buffer DMA stuff
158 */
159 bus_dma_segment_t sc_cdseg; /* control data memory */
160 int sc_cdnseg; /* number of segments */
161 bus_dmamap_t sc_cddmamap; /* control data DMA map */
162 bus_addr_t sc_cddma;
163
164 /*
146 */
147 bus_dma_segment_t sc_cdseg; /* control data memory */
148 int sc_cdnseg; /* number of segments */
149 bus_dmamap_t sc_cddmamap; /* control data DMA map */
150 bus_addr_t sc_cddma;
151
152 /*
165 * Software state for transmit and receive descriptors.
153 * software state for transmit and receive descriptors
166 */
167 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
168 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
169
170 /*
154 */
155 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
156 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
157
158 /*
171 * Control data structures.
159 * control data structures
172 */
173 struct gem_control_data *sc_control_data;
174#define sc_txdescs sc_control_data->gcd_txdescs
175#define sc_rxdescs sc_control_data->gcd_rxdescs
176
160 */
161 struct gem_control_data *sc_control_data;
162#define sc_txdescs sc_control_data->gcd_txdescs
163#define sc_rxdescs sc_control_data->gcd_rxdescs
164
177 int sc_txfree; /* number of free Tx descriptors */
178 int sc_txnext; /* next ready Tx descriptor */
179 int sc_txwin; /* Tx descriptors since last Tx int */
165 int sc_txfree; /* number of free TX descriptors */
166 int sc_txnext; /* next ready TX descriptor */
167 int sc_txwin; /* TX desc. since last TX intr. */
180
168
181 struct gem_txsq sc_txfreeq; /* free Tx descsofts */
182 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */
169 struct gem_txsq sc_txfreeq; /* free TX descsofts */
170 struct gem_txsq sc_txdirtyq; /* dirty TX descsofts */
183
171
184 int sc_rxptr; /* next ready RX descriptor/descsoft */
185 int sc_rxfifosize; /* Rx FIFO size (bytes) */
172 int sc_rxptr; /* next ready RX desc./descsoft */
173 int sc_rxfifosize; /* RX FIFO size (bytes) */
186
174
187 /* ========== */
188 int sc_ifflags;
189 int sc_csum_features;
190};
191
175 int sc_ifflags;
176 int sc_csum_features;
177};
178
179/* XXX this should be handled by bus_dma(9). */
192#define GEM_DMA_READ(sc, v) \
193 ((((sc)->sc_flags & GEM_PCI) != 0) ? le64toh(v) : be64toh(v))
194#define GEM_DMA_WRITE(sc, v) \
195 ((((sc)->sc_flags & GEM_PCI) != 0) ? htole64(v) : htobe64(v))
196
197#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
198#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
199

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232#define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
233#define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
234#define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
235#define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
236
237#ifdef _KERNEL
238extern devclass_t gem_devclass;
239
180#define GEM_DMA_READ(sc, v) \
181 ((((sc)->sc_flags & GEM_PCI) != 0) ? le64toh(v) : be64toh(v))
182#define GEM_DMA_WRITE(sc, v) \
183 ((((sc)->sc_flags & GEM_PCI) != 0) ? htole64(v) : htobe64(v))
184
185#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
186#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
187

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220#define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
221#define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
222#define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
223#define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
224
225#ifdef _KERNEL
226extern devclass_t gem_devclass;
227
240int gem_attach(struct gem_softc *);
241void gem_detach(struct gem_softc *);
242void gem_suspend(struct gem_softc *);
243void gem_resume(struct gem_softc *);
244void gem_intr(void *);
228int gem_attach(struct gem_softc *sc);
229void gem_detach(struct gem_softc *sc);
230void gem_intr(void *v);
231void gem_resume(struct gem_softc *sc);
232void gem_suspend(struct gem_softc *sc);
245
233
246int gem_mediachange(struct ifnet *);
247void gem_mediastatus(struct ifnet *, struct ifmediareq *);
234int gem_mediachange(struct ifnet *ifp);
235void gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
248
249/* MII methods & callbacks */
236
237/* MII methods & callbacks */
250int gem_mii_readreg(device_t, int, int);
251int gem_mii_writereg(device_t, int, int, int);
252void gem_mii_statchg(device_t);
238int gem_mii_readreg(device_t dev, int phy, int reg);
239void gem_mii_statchg(device_t dev);
240int gem_mii_writereg(device_t dev, int phy, int reg, int val);
253
254#endif /* _KERNEL */
255
256#endif
241
242#endif /* _KERNEL */
243
244#endif