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if_gemvar.h (170273) if_gemvar.h (172334)
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp
27 *
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp
27 *
28 * $FreeBSD: head/sys/dev/gem/if_gemvar.h 170273 2007-06-04 06:01:04Z yongari $
28 * $FreeBSD: head/sys/dev/gem/if_gemvar.h 172334 2007-09-26 21:14:18Z marius $
29 */
30
31#ifndef _IF_GEMVAR_H
32#define _IF_GEMVAR_H
33
34
35#include <sys/queue.h>
36#include <sys/callout.h>

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53#define GEM_MAXTXFREE (GEM_NTXDESC - 1)
54#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1)
55#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
56
57/*
58 * Receive descriptor list size. We have one Rx buffer per incoming
59 * packet, so this logic is a little simpler.
60 */
29 */
30
31#ifndef _IF_GEMVAR_H
32#define _IF_GEMVAR_H
33
34
35#include <sys/queue.h>
36#include <sys/callout.h>

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53#define GEM_MAXTXFREE (GEM_NTXDESC - 1)
54#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1)
55#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
56
57/*
58 * Receive descriptor list size. We have one Rx buffer per incoming
59 * packet, so this logic is a little simpler.
60 */
61#define GEM_NRXDESC 128
61#define GEM_NRXDESC 256
62#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
62#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
63#define GEM_PREVRX(x) ((x - 1) & GEM_NRXDESC_MASK)
64#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
65
66/*
67 * How many ticks to wait until to retry on a RX descriptor that is still owned
68 * by the hardware.
69 */
70#define GEM_RXOWN_TICKS (hz / 50)
71

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113 bus_addr_t rxs_paddr; /* physical address of the segment */
114};
115
116/*
117 * Software state per device.
118 */
119struct gem_softc {
120 struct ifnet *sc_ifp;
63#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
64
65/*
66 * How many ticks to wait until to retry on a RX descriptor that is still owned
67 * by the hardware.
68 */
69#define GEM_RXOWN_TICKS (hz / 50)
70

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112 bus_addr_t rxs_paddr; /* physical address of the segment */
113};
114
115/*
116 * Software state per device.
117 */
118struct gem_softc {
119 struct ifnet *sc_ifp;
120 struct mtx sc_mtx;
121 device_t sc_miibus;
122 struct mii_data *sc_mii; /* MII media control */
123 device_t sc_dev; /* generic device information */
121 device_t sc_miibus;
122 struct mii_data *sc_mii; /* MII media control */
123 device_t sc_dev; /* generic device information */
124 u_char sc_enaddr[6];
124 u_char sc_enaddr[ETHER_ADDR_LEN];
125 struct callout sc_tick_ch; /* tick callout */
126 struct callout sc_rx_ch; /* delayed rx callout */
127 int sc_wdog_timer; /* watchdog timer */
128
125 struct callout sc_tick_ch; /* tick callout */
126 struct callout sc_rx_ch; /* delayed rx callout */
127 int sc_wdog_timer; /* watchdog timer */
128
129 /* The following bus handles are to be provided by the bus front-end */
130 void *sc_ih;
131 struct resource *sc_res[2];
132 bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */
133 bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */
134 bus_dma_tag_t sc_tdmatag; /* TX bus dma tag */
135 bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */
136 bus_dmamap_t sc_dmamap; /* bus dma handle */
137
129 void *sc_ih;
130 struct resource *sc_res[2];
131 bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */
132 bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */
133 bus_dma_tag_t sc_tdmatag; /* TX bus dma tag */
134 bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */
135 bus_dmamap_t sc_dmamap; /* bus dma handle */
136
138 int sc_phys[2]; /* MII instance -> PHY map */
137 int sc_phyad; /* addr. of PHY to use or -1 for any */
139
138
140 int sc_mif_config; /* Selected MII reg setting */
141
142 int sc_pci; /* XXXXX -- PCI buses are LE. */
143 u_int sc_variant; /* which GEM are we dealing with? */
144#define GEM_UNKNOWN 0 /* don't know */
139 u_int sc_variant; /* which GEM are we dealing with? */
140#define GEM_UNKNOWN 0 /* don't know */
145#define GEM_SUN_GEM 1 /* Sun GEM variant */
146#define GEM_APPLE_GMAC 2 /* Apple GMAC variant */
141#define GEM_SUN_GEM 1 /* Sun GEM */
142#define GEM_SUN_ERI 2 /* Sun ERI */
143#define GEM_APPLE_GMAC 3 /* Apple GMAC */
144#define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */
147
145
146#define GEM_IS_APPLE(sc) \
147 ((sc)->sc_variant == GEM_APPLE_GMAC || \
148 (sc)->sc_variant == GEM_APPLE_K2_GMAC)
149
148 u_int sc_flags; /* */
150 u_int sc_flags; /* */
149#define GEM_GIGABIT 0x0001 /* has a gigabit PHY */
151#define GEM_INITED (1 << 0) /* reset persistent regs initialized */
152#define GEM_LINK (1 << 1) /* link is up */
153#define GEM_PCI (1 << 2) /* XXX PCI busses are little-endian */
154#define GEM_SERDES (1 << 3) /* use the SERDES */
150
151 /*
152 * Ring buffer DMA stuff.
153 */
154 bus_dma_segment_t sc_cdseg; /* control data memory */
155 int sc_cdnseg; /* number of segments */
156 bus_dmamap_t sc_cddmamap; /* control data DMA map */
157 bus_addr_t sc_cddma;

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164
165 /*
166 * Control data structures.
167 */
168 struct gem_control_data *sc_control_data;
169#define sc_txdescs sc_control_data->gcd_txdescs
170#define sc_rxdescs sc_control_data->gcd_rxdescs
171
155
156 /*
157 * Ring buffer DMA stuff.
158 */
159 bus_dma_segment_t sc_cdseg; /* control data memory */
160 int sc_cdnseg; /* number of segments */
161 bus_dmamap_t sc_cddmamap; /* control data DMA map */
162 bus_addr_t sc_cddma;

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169
170 /*
171 * Control data structures.
172 */
173 struct gem_control_data *sc_control_data;
174#define sc_txdescs sc_control_data->gcd_txdescs
175#define sc_rxdescs sc_control_data->gcd_rxdescs
176
172 int sc_txfree; /* number of free Tx descriptors */
173 int sc_txnext; /* next ready Tx descriptor */
174 int sc_txwin; /* Tx descriptors since last Tx int */
177 int sc_txfree; /* number of free Tx descriptors */
178 int sc_txnext; /* next ready Tx descriptor */
179 int sc_txwin; /* Tx descriptors since last Tx int */
175
176 struct gem_txsq sc_txfreeq; /* free Tx descsofts */
177 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */
178
180
181 struct gem_txsq sc_txfreeq; /* free Tx descsofts */
182 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */
183
179 int sc_rxptr; /* next ready RX descriptor/descsoft */
180 int sc_rxfifosize; /* Rx FIFO size (bytes) */
184 int sc_rxptr; /* next ready RX descriptor/descsoft */
185 int sc_rxfifosize; /* Rx FIFO size (bytes) */
181
182 /* ========== */
186
187 /* ========== */
183 int sc_inited;
184 int sc_debug;
185 int sc_ifflags;
186 int sc_csum_features;
188 int sc_ifflags;
189 int sc_csum_features;
187
188 struct mtx sc_mtx;
189};
190
190};
191
191#define GEM_DMA_READ(sc, v) (((sc)->sc_pci) ? le64toh(v) : be64toh(v))
192#define GEM_DMA_WRITE(sc, v) (((sc)->sc_pci) ? htole64(v) : htobe64(v))
192#define GEM_DMA_READ(sc, v) \
193 ((((sc)->sc_flags & GEM_PCI) != 0) ? le64toh(v) : be64toh(v))
194#define GEM_DMA_WRITE(sc, v) \
195 ((((sc)->sc_flags & GEM_PCI) != 0) ? htole64(v) : htobe64(v))
193
194#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
195#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
196
197#define GEM_CDSYNC(sc, ops) \
196
197#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
198#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
199
200#define GEM_CDSYNC(sc, ops) \
198 bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops)); \
201 bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops));
199
200#define GEM_INIT_RXDESC(sc, x) \
201do { \
202 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
203 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
204 struct mbuf *__m = __rxs->rxs_mbuf; \
205 \
206 __m->m_data = __m->m_ext.ext_buf; \
207 __rxd->gd_addr = \
208 GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \
209 __rxd->gd_flags = \
210 GEM_DMA_WRITE((sc), \
202
203#define GEM_INIT_RXDESC(sc, x) \
204do { \
205 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
206 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
207 struct mbuf *__m = __rxs->rxs_mbuf; \
208 \
209 __m->m_data = __m->m_ext.ext_buf; \
210 __rxd->gd_addr = \
211 GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \
212 __rxd->gd_flags = \
213 GEM_DMA_WRITE((sc), \
211 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \
214 (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) \
212 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \
213} while (0)
214
215 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \
216} while (0)
217
218#define GEM_UPDATE_RXDESC(sc, x) \
219do { \
220 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
221 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
222 struct mbuf *__m = __rxs->rxs_mbuf; \
223 \
224 __rxd->gd_flags = \
225 GEM_DMA_WRITE((sc), \
226 (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) \
227 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \
228} while (0)
229
215#define GEM_LOCK_INIT(_sc, _name) \
216 mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
217#define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
218#define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
219#define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
220#define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
221
222#ifdef _KERNEL
223extern devclass_t gem_devclass;
224
225int gem_attach(struct gem_softc *);
226void gem_detach(struct gem_softc *);
227void gem_suspend(struct gem_softc *);
228void gem_resume(struct gem_softc *);
229void gem_intr(void *);
230
231int gem_mediachange(struct ifnet *);
232void gem_mediastatus(struct ifnet *, struct ifmediareq *);
233
230#define GEM_LOCK_INIT(_sc, _name) \
231 mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
232#define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
233#define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
234#define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
235#define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
236
237#ifdef _KERNEL
238extern devclass_t gem_devclass;
239
240int gem_attach(struct gem_softc *);
241void gem_detach(struct gem_softc *);
242void gem_suspend(struct gem_softc *);
243void gem_resume(struct gem_softc *);
244void gem_intr(void *);
245
246int gem_mediachange(struct ifnet *);
247void gem_mediastatus(struct ifnet *, struct ifmediareq *);
248
234void gem_reset(struct gem_softc *);
235
236/* MII methods & callbacks */
237int gem_mii_readreg(device_t, int, int);
238int gem_mii_writereg(device_t, int, int, int);
239void gem_mii_statchg(device_t);
240
241#endif /* _KERNEL */
242
249/* MII methods & callbacks */
250int gem_mii_readreg(device_t, int, int);
251int gem_mii_writereg(device_t, int, int, int);
252void gem_mii_statchg(device_t);
253
254#endif /* _KERNEL */
255
243
244#endif
256#endif