| if_gemreg.h (194763) | if_gemreg.h (223944) |
|---|---|
| 1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 12 unchanged lines hidden (view full) --- 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gemreg.h,v 1.9 2006/11/24 13:01:07 martin Exp 28 * | 1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 12 unchanged lines hidden (view full) --- 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gemreg.h,v 1.9 2006/11/24 13:01:07 martin Exp 28 * |
| 29 * $FreeBSD: head/sys/dev/gem/if_gemreg.h 194763 2009-06-23 20:36:59Z marius $ | 29 * $FreeBSD: head/sys/dev/gem/if_gemreg.h 223944 2011-07-12 08:20:15Z marius $ |
| 30 */ 31 32#ifndef _IF_GEMREG_H 33#define _IF_GEMREG_H 34 35/* register definitions for Apple GMAC, Sun ERI and Sun GEM */ 36 37/* | 30 */ 31 32#ifndef _IF_GEMREG_H 33#define _IF_GEMREG_H 34 35/* register definitions for Apple GMAC, Sun ERI and Sun GEM */ 36 37/* |
| 38 * First bank: this registers live at the start of the PCI | 38 * First bank: these registers live at the start of the PCI |
| 39 * mapping, and at the start of the second bank of the SBus 40 * version. 41 */ 42#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 43#define GEM_CONFIG 0x0004 /* config reg */ 44#define GEM_STATUS 0x000c /* status reg */ 45/* Note: Reading the status reg clears bits 0-6. */ 46#define GEM_INTMASK 0x0010 --- 41 unchanged lines hidden (view full) --- 88#define GEM_INTR_BERR 0x00040000 /* Bus error interrupt */ 89#define GEM_INTR_BITS "\177\020" \ 90 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 91 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 92 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \ 93 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0" 94 95/* | 39 * mapping, and at the start of the second bank of the SBus 40 * version. 41 */ 42#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 43#define GEM_CONFIG 0x0004 /* config reg */ 44#define GEM_STATUS 0x000c /* status reg */ 45/* Note: Reading the status reg clears bits 0-6. */ 46#define GEM_INTMASK 0x0010 --- 41 unchanged lines hidden (view full) --- 88#define GEM_INTR_BERR 0x00040000 /* Bus error interrupt */ 89#define GEM_INTR_BITS "\177\020" \ 90 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 91 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 92 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \ 93 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0" 94 95/* |
| 96 * Second bank: this registers live at offset 0x1000 of the PCI | 96 * Second bank: these registers live at offset 0x1000 of the PCI |
| 97 * mapping, and at the start of the first bank of the SBus 98 * version. 99 */ 100#define GEM_PCI_BANK2_OFFSET 0x1000 101#define GEM_PCI_BANK2_SIZE 0x14 102/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 103#define GEM_PCI_ERROR_STATUS 0x0000 /* PCI error status */ 104#define GEM_PCI_ERROR_MASK 0x0004 /* PCI error mask */ --- 18 unchanged lines hidden (view full) --- 123#define GEM_PCI_BIF_CNF_HOST_64 0x00000002 /* 64-bit host */ 124#define GEM_PCI_BIF_CNF_B64D_DS 0x00000004 /* no 64-bit data cycle */ 125#define GEM_PCI_BIF_CNF_M66EN 0x00000008 126#define GEM_PCI_BIF_CNF_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \ 127 "b\2B64DIS\0b\3M66EN\0\0" 128 129/* GEM_PCI_BIF_DIAG register bits */ 130#define GEN_PCI_BIF_DIAG_BC_SM 0x007f0000 /* burst ctrl. state machine */ | 97 * mapping, and at the start of the first bank of the SBus 98 * version. 99 */ 100#define GEM_PCI_BANK2_OFFSET 0x1000 101#define GEM_PCI_BANK2_SIZE 0x14 102/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 103#define GEM_PCI_ERROR_STATUS 0x0000 /* PCI error status */ 104#define GEM_PCI_ERROR_MASK 0x0004 /* PCI error mask */ --- 18 unchanged lines hidden (view full) --- 123#define GEM_PCI_BIF_CNF_HOST_64 0x00000002 /* 64-bit host */ 124#define GEM_PCI_BIF_CNF_B64D_DS 0x00000004 /* no 64-bit data cycle */ 125#define GEM_PCI_BIF_CNF_M66EN 0x00000008 126#define GEM_PCI_BIF_CNF_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \ 127 "b\2B64DIS\0b\3M66EN\0\0" 128 129/* GEM_PCI_BIF_DIAG register bits */ 130#define GEN_PCI_BIF_DIAG_BC_SM 0x007f0000 /* burst ctrl. state machine */ |
| 131#define GEN_PCI_BIF_DIAG_SM 0xff000000 /* BIF state machine */ | 131#define GEN_PCI_BIF_DIAG_SM 0xff000000 /* BIF state machine */ |
| 132 133/* Bits in GEM_SBUS_CONFIG register */ 134#define GEM_SBUS_CFG_BURST_32 0x00000001 /* 32 byte bursts */ 135#define GEM_SBUS_CFG_BURST_64 0x00000002 /* 64 byte bursts */ 136#define GEM_SBUS_CFG_BURST_128 0x00000004 /* 128 byte bursts */ 137#define GEM_SBUS_CFG_64BIT 0x00000008 /* extended transfer mode */ 138#define GEM_SBUS_CFG_PARITY 0x00000200 /* enable parity checking */ 139 140/* GEM_SBUS_STATUS register bits */ 141#define GEM_SBUS_STATUS_LERR 0x00000001 /* LERR from SBus slave */ 142#define GEM_SBUS_STATUS_SACK 0x00000002 /* size ack. error */ 143#define GEM_SBUS_STATUS_EACK 0x00000004 /* SBus ctrl. or slave error */ 144#define GEM_SBUS_STATUS_MPARITY 0x00000008 /* SBus master parity error */ 145 146/* GEM_RESET register bits -- TX and RX self clear when complete. */ 147#define GEM_RESET_TX 0x00000001 /* Reset TX half. */ 148#define GEM_RESET_RX 0x00000002 /* Reset RX half. */ 149#define GEM_RESET_PCI_RSTOUT 0x00000004 /* Force PCI RSTOUT#. */ | 132 133/* Bits in GEM_SBUS_CONFIG register */ 134#define GEM_SBUS_CFG_BURST_32 0x00000001 /* 32 byte bursts */ 135#define GEM_SBUS_CFG_BURST_64 0x00000002 /* 64 byte bursts */ 136#define GEM_SBUS_CFG_BURST_128 0x00000004 /* 128 byte bursts */ 137#define GEM_SBUS_CFG_64BIT 0x00000008 /* extended transfer mode */ 138#define GEM_SBUS_CFG_PARITY 0x00000200 /* enable parity checking */ 139 140/* GEM_SBUS_STATUS register bits */ 141#define GEM_SBUS_STATUS_LERR 0x00000001 /* LERR from SBus slave */ 142#define GEM_SBUS_STATUS_SACK 0x00000002 /* size ack. error */ 143#define GEM_SBUS_STATUS_EACK 0x00000004 /* SBus ctrl. or slave error */ 144#define GEM_SBUS_STATUS_MPARITY 0x00000008 /* SBus master parity error */ 145 146/* GEM_RESET register bits -- TX and RX self clear when complete. */ 147#define GEM_RESET_TX 0x00000001 /* Reset TX half. */ 148#define GEM_RESET_RX 0x00000002 /* Reset RX half. */ 149#define GEM_RESET_PCI_RSTOUT 0x00000004 /* Force PCI RSTOUT#. */ |
| 150#define GEM_RESET_CLSZ_MASK 0x00ff0000 /* ERI cache line size */ 151#define GEM_RESET_CLSZ_SHFT 16 |
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| 150 151/* The rest of the registers live in the first bank again. */ 152 153/* TX DMA registers */ 154#define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 155#define GEM_TX_CONFIG 0x2004 156#define GEM_TX_RING_PTR_LO 0x2008 157#define GEM_TX_RING_PTR_HI 0x200c --- 423 unchanged lines hidden (view full) --- 581 */ 582#define GEM_PCI_ROM_OFFSET 0x100000 583#define GEM_PCI_ROM_SIZE 0x10000 584 585/* Wired PHY addresses */ 586#define GEM_PHYAD_INTERNAL 1 587#define GEM_PHYAD_EXTERNAL 0 588 | 152 153/* The rest of the registers live in the first bank again. */ 154 155/* TX DMA registers */ 156#define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 157#define GEM_TX_CONFIG 0x2004 158#define GEM_TX_RING_PTR_LO 0x2008 159#define GEM_TX_RING_PTR_HI 0x200c --- 423 unchanged lines hidden (view full) --- 583 */ 584#define GEM_PCI_ROM_OFFSET 0x100000 585#define GEM_PCI_ROM_SIZE 0x10000 586 587/* Wired PHY addresses */ 588#define GEM_PHYAD_INTERNAL 1 589#define GEM_PHYAD_EXTERNAL 0 590 |
| 591/* Miscellaneous */ 592#define GEM_ERI_CACHE_LINE_SIZE 16 593#define GEM_ERI_LATENCY_TIMER 64 594 |
|
| 589/* 590 * descriptor table structures 591 */ 592struct gem_desc { 593 uint64_t gd_flags; 594 uint64_t gd_addr; 595}; 596 | 595/* 596 * descriptor table structures 597 */ 598struct gem_desc { 599 uint64_t gd_flags; 600 uint64_t gd_addr; 601}; 602 |
| 597/* Transmit flags */ | 603/* 604 * Transmit flags 605 * GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_START, GEM_TD_CXSUM_STUFF and 606 * GEM_TD_INTERRUPT_ME only need to be set in the first descriptor of a group. 607 */ |
| 598#define GEM_TD_BUFSIZE 0x0000000000007fffULL 599#define GEM_TD_CXSUM_START 0x00000000001f8000ULL /* Cxsum start offset */ 600#define GEM_TD_CXSUM_STARTSHFT 15 601#define GEM_TD_CXSUM_STUFF 0x000000001fe00000ULL /* Cxsum stuff offset */ 602#define GEM_TD_CXSUM_STUFFSHFT 21 603#define GEM_TD_CXSUM_ENABLE 0x0000000020000000ULL /* Cxsum generation enable */ 604#define GEM_TD_END_OF_PACKET 0x0000000040000000ULL 605#define GEM_TD_START_OF_PACKET 0x0000000080000000ULL 606#define GEM_TD_INTERRUPT_ME 0x0000000100000000ULL /* Interrupt me now */ 607#define GEM_TD_NO_CRC 0x0000000200000000ULL /* do not insert crc */ | 608#define GEM_TD_BUFSIZE 0x0000000000007fffULL 609#define GEM_TD_CXSUM_START 0x00000000001f8000ULL /* Cxsum start offset */ 610#define GEM_TD_CXSUM_STARTSHFT 15 611#define GEM_TD_CXSUM_STUFF 0x000000001fe00000ULL /* Cxsum stuff offset */ 612#define GEM_TD_CXSUM_STUFFSHFT 21 613#define GEM_TD_CXSUM_ENABLE 0x0000000020000000ULL /* Cxsum generation enable */ 614#define GEM_TD_END_OF_PACKET 0x0000000040000000ULL 615#define GEM_TD_START_OF_PACKET 0x0000000080000000ULL 616#define GEM_TD_INTERRUPT_ME 0x0000000100000000ULL /* Interrupt me now */ 617#define GEM_TD_NO_CRC 0x0000000200000000ULL /* do not insert crc */ |
| 608/* 609 * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF, 610 * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group. 611 */ | |
| 612 613/* Receive flags */ 614#define GEM_RD_CHECKSUM 0x000000000000ffffULL /* is the complement */ 615#define GEM_RD_BUFSIZE 0x000000007fff0000ULL 616#define GEM_RD_OWN 0x0000000080000000ULL /* 1 - owned by h/w */ 617#define GEM_RD_HASHVAL 0x0ffff00000000000ULL 618#define GEM_RD_HASH_PASS 0x1000000000000000ULL /* passed hash filter */ 619#define GEM_RD_ALTERNATE_MAC 0x2000000000000000ULL /* Alternate MAC adrs */ 620#define GEM_RD_BAD_CRC 0x4000000000000000ULL | 618 619/* Receive flags */ 620#define GEM_RD_CHECKSUM 0x000000000000ffffULL /* is the complement */ 621#define GEM_RD_BUFSIZE 0x000000007fff0000ULL 622#define GEM_RD_OWN 0x0000000080000000ULL /* 1 - owned by h/w */ 623#define GEM_RD_HASHVAL 0x0ffff00000000000ULL 624#define GEM_RD_HASH_PASS 0x1000000000000000ULL /* passed hash filter */ 625#define GEM_RD_ALTERNATE_MAC 0x2000000000000000ULL /* Alternate MAC adrs */ 626#define GEM_RD_BAD_CRC 0x4000000000000000ULL |
| 621 | |
| 622#define GEM_RD_BUFSHIFT 16 623#define GEM_RD_BUFLEN(x) (((x) & GEM_RD_BUFSIZE) >> GEM_RD_BUFSHIFT) 624 625#endif | 627#define GEM_RD_BUFSHIFT 16 628#define GEM_RD_BUFLEN(x) (((x) & GEM_RD_BUFSIZE) >> GEM_RD_BUFSHIFT) 629 630#endif |