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if_gemreg.h (177560) if_gemreg.h (194763)
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * All rights reserved.
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * from: NetBSD: gemreg.h,v 1.9 2006/11/24 13:01:07 martin Exp
28 *
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * All rights reserved.
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * from: NetBSD: gemreg.h,v 1.9 2006/11/24 13:01:07 martin Exp
28 *
29 * $FreeBSD: head/sys/dev/gem/if_gemreg.h 177560 2008-03-24 17:23:53Z marius $
29 * $FreeBSD: head/sys/dev/gem/if_gemreg.h 194763 2009-06-23 20:36:59Z marius $
30 */
31
32#ifndef _IF_GEMREG_H
33#define _IF_GEMREG_H
34
30 */
31
32#ifndef _IF_GEMREG_H
33#define _IF_GEMREG_H
34
35/* Register definitions for Sun GEM gigabit ethernet */
35/* register definitions for Apple GMAC, Sun ERI and Sun GEM */
36
37/*
38 * First bank: this registers live at the start of the PCI
39 * mapping, and at the start of the second bank of the SBus
40 * version.
41 */
42#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
43#define GEM_CONFIG 0x0004 /* config reg */
44#define GEM_STATUS 0x000c /* status reg */
45/* Note: Reading the status reg clears bits 0-6. */
46#define GEM_INTMASK 0x0010
47#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
48#define GEM_STATUS_ALIAS 0x001c
49
36
37/*
38 * First bank: this registers live at the start of the PCI
39 * mapping, and at the start of the second bank of the SBus
40 * version.
41 */
42#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
43#define GEM_CONFIG 0x0004 /* config reg */
44#define GEM_STATUS 0x000c /* status reg */
45/* Note: Reading the status reg clears bits 0-6. */
46#define GEM_INTMASK 0x0010
47#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
48#define GEM_STATUS_ALIAS 0x001c
49
50/*
51 * Second bank: this registers live at offset 0x1000 of the PCI
52 * mapping, and at the start of the first bank of the SBus
53 * version.
54 */
55#define GEM_PCI_BANK2_OFFSET 0x1000
56#define GEM_PCI_BANK2_SIZE 0x14
57/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */
58#define GEM_ERROR_STATUS 0x0000 /* PCI error status R/C */
59#define GEM_ERROR_MASK 0x0004
60#define GEM_SBUS_CONFIG 0x0004
61#define GEM_BIF_CONFIG 0x0008 /* BIF config reg */
62#define GEM_BIF_DIAG 0x000c
63#define GEM_RESET 0x0010 /* Software reset register */
64
65
66/* Bits in GEM_SEB register */
50/* Bits in GEM_SEB register */
67#define GEM_SEB_ARB 0x000000002 /* Arbitration status */
68#define GEM_SEB_RXWON 0x000000004
51#define GEM_SEB_ARB 0x00000002 /* Arbitration status */
52#define GEM_SEB_RXWON 0x00000004
69
53
70/* Bits in GEM_SBUS_CONFIG register */
71#define GEM_SBUS_CFG_BMODE64 0x00000008
72#define GEM_SBUS_CFG_PARITY 0x00000200
73
74/* Bits in GEM_CONFIG register */
54/* Bits in GEM_CONFIG register */
75#define GEM_CONFIG_BURST_64 0x000000000 /* maximum burst size 64KB */
76#define GEM_CONFIG_BURST_INF 0x000000001 /* infinite for entire packet */
77#define GEM_CONFIG_TXDMA_LIMIT 0x00000003e
78#define GEM_CONFIG_RXDMA_LIMIT 0x0000007c0
55#define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */
56#define GEM_CONFIG_BURST_INF 0x00000001 /* infinite for entire packet */
57#define GEM_CONFIG_TXDMA_LIMIT 0x0000003e
58#define GEM_CONFIG_RXDMA_LIMIT 0x000007c0
79/* GEM_CONFIG_RONPAULBIT and GEM_CONFIG_BUG2FIX are Apple only. */
59/* GEM_CONFIG_RONPAULBIT and GEM_CONFIG_BUG2FIX are Apple only. */
80#define GEM_CONFIG_RONPAULBIT 0x000000800 /* after infinite burst use */
60#define GEM_CONFIG_RONPAULBIT 0x00000800 /* after infinite burst use */
81 /* memory read multiple for */
82 /* PCI commands */
61 /* memory read multiple for */
62 /* PCI commands */
83#define GEM_CONFIG_BUG2FIX 0x000001000 /* fix RX hang after overflow */
63#define GEM_CONFIG_BUG2FIX 0x00001000 /* fix RX hang after overflow */
84
85#define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1
86#define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6
87
64
65#define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1
66#define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6
67
88
89/* Top part of GEM_STATUS has TX completion information */
68/* Top part of GEM_STATUS has TX completion information */
90#define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */
69#define GEM_STATUS_TX_COMPLETION_MASK 0xfff80000 /* TX completion reg. */
70#define GEM_STATUS_TX_COMPLETION_SHFT 19
91
71
92
93/*
94 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs
95 * Bits 0-6 auto-clear when read.
96 */
72/*
73 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs
74 * Bits 0-6 auto-clear when read.
75 */
97#define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */
98#define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */
99#define GEM_INTR_TX_DONE 0x000000004 /* TX complete */
100#define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */
101#define GEM_INTR_RX_NOBUF 0x000000020
102#define GEM_INTR_RX_TAG_ERR 0x000000040
103#define GEM_INTR_PERR 0x000000080 /* Parity error */
104#define GEM_INTR_PCS 0x000002000 /* Physical Code Sub-layer */
105#define GEM_INTR_TX_MAC 0x000004000
106#define GEM_INTR_RX_MAC 0x000008000
107#define GEM_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */
108#define GEM_INTR_MIF 0x000020000
109#define GEM_INTR_BERR 0x000040000 /* Bus error interrupt */
76#define GEM_INTR_TX_INTME 0x00000001 /* Frame w/INTME bit set sent */
77#define GEM_INTR_TX_EMPTY 0x00000002 /* TX ring empty */
78#define GEM_INTR_TX_DONE 0x00000004 /* TX complete */
79#define GEM_INTR_RX_DONE 0x00000010 /* Got a packet */
80#define GEM_INTR_RX_NOBUF 0x00000020
81#define GEM_INTR_RX_TAG_ERR 0x00000040
82#define GEM_INTR_PERR 0x00000080 /* Parity error */
83#define GEM_INTR_PCS 0x00002000 /* Physical Code Sub-layer */
84#define GEM_INTR_TX_MAC 0x00004000
85#define GEM_INTR_RX_MAC 0x00008000
86#define GEM_INTR_MAC_CONTROL 0x00010000 /* MAC control interrupt */
87#define GEM_INTR_MIF 0x00020000
88#define GEM_INTR_BERR 0x00040000 /* Bus error interrupt */
110#define GEM_INTR_BITS "\177\020" \
111 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \
112 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \
113 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \
114 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0"
115
89#define GEM_INTR_BITS "\177\020" \
90 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \
91 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \
92 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \
93 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0"
94
95/*
96 * Second bank: this registers live at offset 0x1000 of the PCI
97 * mapping, and at the start of the first bank of the SBus
98 * version.
99 */
100#define GEM_PCI_BANK2_OFFSET 0x1000
101#define GEM_PCI_BANK2_SIZE 0x14
102/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */
103#define GEM_PCI_ERROR_STATUS 0x0000 /* PCI error status */
104#define GEM_PCI_ERROR_MASK 0x0004 /* PCI error mask */
105#define GEM_PCI_BIF_CONFIG 0x0008 /* PCI BIF configuration */
106#define GEM_PCI_BIF_DIAG 0x000c /* PCI BIF diagnostic */
116
107
117/* GEM_ERROR_STATUS and GEM_ERROR_MASK PCI error bits */
118#define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */
119#define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */
120#define GEM_ERROR_STAT_OTHERS 0x000000004
121#define GEM_ERROR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0"
108#define GEM_SBUS_BIF_RESET 0x0000 /* SBus BIF only software reset */
109#define GEM_SBUS_CONFIG 0x0004 /* SBus IO configuration */
110#define GEM_SBUS_STATUS 0x0008 /* SBus IO status */
111#define GEM_SBUS_REVISION 0x000c /* SBus revision ID */
122
112
113#define GEM_RESET 0x0010 /* software reset */
123
114
124/* GEM_BIF_CONFIG register bits */
125#define GEM_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */
126#define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */
127#define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */
128#define GEM_BIF_CONFIG_M66EN 0x000000008
129#define GEM_BIF_CONFIG_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \
115/* GEM_PCI_ERROR_STATUS and GEM_PCI_ERROR_MASK error bits */
116#define GEM_PCI_ERR_STAT_BADACK 0x00000001 /* No ACK64# */
117#define GEM_PCI_ERR_STAT_DTRTO 0x00000002 /* Delayed xaction timeout */
118#define GEM_PCI_ERR_STAT_OTHERS 0x00000004
119#define GEM_PCI_ERR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0"
120
121/* GEM_PCI_BIF_CONFIG register bits */
122#define GEM_PCI_BIF_CNF_SLOWCLK 0x00000001 /* Parity error timing */
123#define GEM_PCI_BIF_CNF_HOST_64 0x00000002 /* 64-bit host */
124#define GEM_PCI_BIF_CNF_B64D_DS 0x00000004 /* no 64-bit data cycle */
125#define GEM_PCI_BIF_CNF_M66EN 0x00000008
126#define GEM_PCI_BIF_CNF_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \
130 "b\2B64DIS\0b\3M66EN\0\0"
131
127 "b\2B64DIS\0b\3M66EN\0\0"
128
129/* GEM_PCI_BIF_DIAG register bits */
130#define GEN_PCI_BIF_DIAG_BC_SM 0x007f0000 /* burst ctrl. state machine */
131#define GEN_PCI_BIF_DIAG_SM 0xff000000 /* BIF state machine */
132
132
133/* GEM_RESET register bits -- TX and RX self clear when complete. */
134#define GEM_RESET_TX 0x000000001 /* Reset TX half */
135#define GEM_RESET_RX 0x000000002 /* Reset RX half */
136#define GEM_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */
133/* Bits in GEM_SBUS_CONFIG register */
134#define GEM_SBUS_CFG_BURST_32 0x00000001 /* 32 byte bursts */
135#define GEM_SBUS_CFG_BURST_64 0x00000002 /* 64 byte bursts */
136#define GEM_SBUS_CFG_BURST_128 0x00000004 /* 128 byte bursts */
137#define GEM_SBUS_CFG_64BIT 0x00000008 /* extended transfer mode */
138#define GEM_SBUS_CFG_PARITY 0x00000200 /* enable parity checking */
137
139
140/* GEM_SBUS_STATUS register bits */
141#define GEM_SBUS_STATUS_LERR 0x00000001 /* LERR from SBus slave */
142#define GEM_SBUS_STATUS_SACK 0x00000002 /* size ack. error */
143#define GEM_SBUS_STATUS_EACK 0x00000004 /* SBus ctrl. or slave error */
144#define GEM_SBUS_STATUS_MPARITY 0x00000008 /* SBus master parity error */
138
145
146/* GEM_RESET register bits -- TX and RX self clear when complete. */
147#define GEM_RESET_TX 0x00000001 /* Reset TX half. */
148#define GEM_RESET_RX 0x00000002 /* Reset RX half. */
149#define GEM_RESET_PCI_RSTOUT 0x00000004 /* Force PCI RSTOUT#. */
150
139/* The rest of the registers live in the first bank again. */
151/* The rest of the registers live in the first bank again. */
140/* GEM TX DMA registers */
152
153/* TX DMA registers */
141#define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */
142#define GEM_TX_CONFIG 0x2004
143#define GEM_TX_RING_PTR_LO 0x2008
144#define GEM_TX_RING_PTR_HI 0x200c
145
146#define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */
147#define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */
148#define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */

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157#define GEM_TX_FIFO_ADDRESS 0x2104
158#define GEM_TX_FIFO_TAG 0x2108
159#define GEM_TX_FIFO_DATA_LO 0x210c
160#define GEM_TX_FIFO_DATA_HI_T1 0x2110
161#define GEM_TX_FIFO_DATA_HI_T0 0x2114
162#define GEM_TX_FIFO_SIZE 0x2118
163#define GEM_TX_DEBUG 0x3028
164
154#define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */
155#define GEM_TX_CONFIG 0x2004
156#define GEM_TX_RING_PTR_LO 0x2008
157#define GEM_TX_RING_PTR_HI 0x200c
158
159#define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */
160#define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */
161#define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */

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170#define GEM_TX_FIFO_ADDRESS 0x2104
171#define GEM_TX_FIFO_TAG 0x2108
172#define GEM_TX_FIFO_DATA_LO 0x210c
173#define GEM_TX_FIFO_DATA_HI_T1 0x2110
174#define GEM_TX_FIFO_DATA_HI_T0 0x2114
175#define GEM_TX_FIFO_SIZE 0x2118
176#define GEM_TX_DEBUG 0x3028
177
165
166/* GEM_TX_CONFIG register bits */
167#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */
168#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */
169#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */
170#define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */
171
172#define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */
173#define GEM_RING_SZ_64 (1<<1)
174#define GEM_RING_SZ_128 (2<<1)
175#define GEM_RING_SZ_256 (3<<1)
176#define GEM_RING_SZ_512 (4<<1)
177#define GEM_RING_SZ_1024 (5<<1)
178#define GEM_RING_SZ_2048 (6<<1)
179#define GEM_RING_SZ_4096 (7<<1)
180#define GEM_RING_SZ_8192 (8<<1)
181
178/* GEM_TX_CONFIG register bits */
179#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */
180#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */
181#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */
182#define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */
183
184#define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */
185#define GEM_RING_SZ_64 (1<<1)
186#define GEM_RING_SZ_128 (2<<1)
187#define GEM_RING_SZ_256 (3<<1)
188#define GEM_RING_SZ_512 (4<<1)
189#define GEM_RING_SZ_1024 (5<<1)
190#define GEM_RING_SZ_2048 (6<<1)
191#define GEM_RING_SZ_4096 (7<<1)
192#define GEM_RING_SZ_8192 (8<<1)
193
182
183/* GEM_TX_COMPLETION register bits */
184#define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */
185
194/* GEM_TX_COMPLETION register bits */
195#define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */
196
186
187/* GEM RX DMA registers */
197/* RX DMA registers */
188#define GEM_RX_CONFIG 0x4000
189#define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */
190#define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */
191
192#define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */
193#define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */
194#define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */
195#define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */

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206
207#define GEM_RX_FIFO_ADDRESS 0x410c
208#define GEM_RX_FIFO_TAG 0x4110
209#define GEM_RX_FIFO_DATA_LO 0x4114
210#define GEM_RX_FIFO_DATA_HI_T1 0x4118
211#define GEM_RX_FIFO_DATA_HI_T0 0x411c
212#define GEM_RX_FIFO_SIZE 0x4120
213
198#define GEM_RX_CONFIG 0x4000
199#define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */
200#define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */
201
202#define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */
203#define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */
204#define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */
205#define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */

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216
217#define GEM_RX_FIFO_ADDRESS 0x410c
218#define GEM_RX_FIFO_TAG 0x4110
219#define GEM_RX_FIFO_DATA_LO 0x4114
220#define GEM_RX_FIFO_DATA_HI_T1 0x4118
221#define GEM_RX_FIFO_DATA_HI_T0 0x411c
222#define GEM_RX_FIFO_SIZE 0x4120
223
214
215/* GEM_RX_CONFIG register bits */
216#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */
217#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */
218#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */
219#define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */
220#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */
221#define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */
222
223#define GEM_THRSH_64 0
224#define GEM_THRSH_128 1
225#define GEM_THRSH_256 2
226#define GEM_THRSH_512 3
227#define GEM_THRSH_1024 4
228#define GEM_THRSH_2048 5
229
230#define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24
231#define GEM_RX_CONFIG_FBOFF_SHFT 10
232#define GEM_RX_CONFIG_CXM_START_SHFT 13
233
224/* GEM_RX_CONFIG register bits */
225#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */
226#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */
227#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */
228#define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */
229#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */
230#define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */
231
232#define GEM_THRSH_64 0
233#define GEM_THRSH_128 1
234#define GEM_THRSH_256 2
235#define GEM_THRSH_512 3
236#define GEM_THRSH_1024 4
237#define GEM_THRSH_2048 5
238
239#define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24
240#define GEM_RX_CONFIG_FBOFF_SHFT 10
241#define GEM_RX_CONFIG_CXM_START_SHFT 13
242
234
235/* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */
236#define GEM_RX_PTH_XOFF_THRESH 0x000001ff
237#define GEM_RX_PTH_XON_THRESH 0x001ff000
238
243/* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */
244#define GEM_RX_PTH_XOFF_THRESH 0x000001ff
245#define GEM_RX_PTH_XON_THRESH 0x001ff000
246
239
240/* GEM_RX_BLANKING register bits */
241#define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */
242#define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */
243#define GEM_RX_BLANKING_TIME_SHIFT 12
244/* One tick is 2048 PCI clocks, or 16us at 66MHz */
245
247/* GEM_RX_BLANKING register bits */
248#define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */
249#define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */
250#define GEM_RX_BLANKING_TIME_SHIFT 12
251/* One tick is 2048 PCI clocks, or 16us at 66MHz */
252
246
247/* GEM_MAC registers */
248#define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */
249#define GEM_MAC_RXRESET 0x6004 /* ditto */
250#define GEM_MAC_SEND_PAUSE_CMD 0x6008
251#define GEM_MAC_TX_STATUS 0x6010
252#define GEM_MAC_RX_STATUS 0x6014
253#define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */
254#define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */

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311#define GEM_MAC_RX_FRAME_COUNT 0x6118
312#define GEM_MAC_RX_LEN_ERR_CNT 0x611c
313#define GEM_MAC_RX_ALIGN_ERR 0x6120
314#define GEM_MAC_RX_CRC_ERR_CNT 0x6124
315#define GEM_MAC_RX_CODE_VIOL 0x6128
316#define GEM_MAC_RANDOM_SEED 0x6130
317#define GEM_MAC_MAC_STATE 0x6134 /* MAC state machine reg */
318
253/* GEM_MAC registers */
254#define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */
255#define GEM_MAC_RXRESET 0x6004 /* ditto */
256#define GEM_MAC_SEND_PAUSE_CMD 0x6008
257#define GEM_MAC_TX_STATUS 0x6010
258#define GEM_MAC_RX_STATUS 0x6014
259#define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */
260#define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */

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317#define GEM_MAC_RX_FRAME_COUNT 0x6118
318#define GEM_MAC_RX_LEN_ERR_CNT 0x611c
319#define GEM_MAC_RX_ALIGN_ERR 0x6120
320#define GEM_MAC_RX_CRC_ERR_CNT 0x6124
321#define GEM_MAC_RX_CODE_VIOL 0x6128
322#define GEM_MAC_RANDOM_SEED 0x6130
323#define GEM_MAC_MAC_STATE 0x6134 /* MAC state machine reg */
324
319
320/* GEM_MAC_SEND_PAUSE_CMD register bits */
321#define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff
322#define GEM_MAC_PAUSE_CMD_SEND 0x00010000
323
325/* GEM_MAC_SEND_PAUSE_CMD register bits */
326#define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff
327#define GEM_MAC_PAUSE_CMD_SEND 0x00010000
328
324
325/* GEM_MAC_TX_STATUS and _MASK register bits */
326#define GEM_MAC_TX_XMIT_DONE 0x00000001
327#define GEM_MAC_TX_UNDERRUN 0x00000002
328#define GEM_MAC_TX_PKT_TOO_LONG 0x00000004
329#define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */
330#define GEM_MAC_TX_ECC_EXP 0x00000010
331#define GEM_MAC_TX_LCC_EXP 0x00000020
332#define GEM_MAC_TX_FCC_EXP 0x00000040
333#define GEM_MAC_TX_DEFER_EXP 0x00000080
334#define GEM_MAC_TX_PEAK_EXP 0x00000100
335
329/* GEM_MAC_TX_STATUS and _MASK register bits */
330#define GEM_MAC_TX_XMIT_DONE 0x00000001
331#define GEM_MAC_TX_UNDERRUN 0x00000002
332#define GEM_MAC_TX_PKT_TOO_LONG 0x00000004
333#define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */
334#define GEM_MAC_TX_ECC_EXP 0x00000010
335#define GEM_MAC_TX_LCC_EXP 0x00000020
336#define GEM_MAC_TX_FCC_EXP 0x00000040
337#define GEM_MAC_TX_DEFER_EXP 0x00000080
338#define GEM_MAC_TX_PEAK_EXP 0x00000100
339
336
337/* GEM_MAC_RX_STATUS and _MASK register bits */
338#define GEM_MAC_RX_DONE 0x00000001
339#define GEM_MAC_RX_OVERFLOW 0x00000002
340#define GEM_MAC_RX_FRAME_CNT 0x00000004
341#define GEM_MAC_RX_ALIGN_EXP 0x00000008
342#define GEM_MAC_RX_CRC_EXP 0x00000010
343#define GEM_MAC_RX_LEN_EXP 0x00000020
344#define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */
345
340/* GEM_MAC_RX_STATUS and _MASK register bits */
341#define GEM_MAC_RX_DONE 0x00000001
342#define GEM_MAC_RX_OVERFLOW 0x00000002
343#define GEM_MAC_RX_FRAME_CNT 0x00000004
344#define GEM_MAC_RX_ALIGN_EXP 0x00000008
345#define GEM_MAC_RX_CRC_EXP 0x00000010
346#define GEM_MAC_RX_LEN_EXP 0x00000020
347#define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */
348
346
347/* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */
348#define GEM_MAC_PAUSED 0x00000001 /* Pause received */
349#define GEM_MAC_PAUSE 0x00000002 /* enter pause state */
350#define GEM_MAC_RESUME 0x00000004 /* exit pause state */
351#define GEM_MAC_PAUSE_TIME_SLTS 0xffff0000 /* pause time in slots */
352#define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0"
353
354#define GEM_MAC_PAUSE_TIME_SHFT 16

--- 26 unchanged lines hidden (view full) ---

381#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */
382#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */
383#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */
384#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */
385#define GEM_MAC_TX_NO_BACKOFF 0x00000040
386#define GEM_MAC_TX_SLOWDOWN 0x00000080
387#define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */
388#define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */
349/* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */
350#define GEM_MAC_PAUSED 0x00000001 /* Pause received */
351#define GEM_MAC_PAUSE 0x00000002 /* enter pause state */
352#define GEM_MAC_RESUME 0x00000004 /* exit pause state */
353#define GEM_MAC_PAUSE_TIME_SLTS 0xffff0000 /* pause time in slots */
354#define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0"
355
356#define GEM_MAC_PAUSE_TIME_SHFT 16

--- 26 unchanged lines hidden (view full) ---

383#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */
384#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */
385#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */
386#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */
387#define GEM_MAC_TX_NO_BACKOFF 0x00000040
388#define GEM_MAC_TX_SLOWDOWN 0x00000080
389#define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */
390#define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */
389/* Carrier Extension is required for half duplex Gbps operation */
391/* Carrier Extension is required for half duplex Gbps operation. */
390#define GEM_MAC_TX_CONFIG_BITS "\177\020" \
391 "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \
392 "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \
393 "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \
394 "b\x9TXCARREXT\0\0"
395
392#define GEM_MAC_TX_CONFIG_BITS "\177\020" \
393 "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \
394 "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \
395 "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \
396 "b\x9TXCARREXT\0\0"
397
396
397/* GEM_MAC_RX_CONFIG register bits */
398#define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */
399#define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */
400#define GEM_MAC_RX_STRIP_CRC 0x00000004
401#define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */
402#define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */
403#define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */
404#define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */
405#define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */
406#define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */
407/*
408 * Carrier Extension enables reception of packet bursts generated by
409 * senders with carrier extension enabled.
410 */
411#define GEM_MAC_RX_CONFIG_BITS "\177\020" \
412 "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \
413 "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \
414 "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0"
415
398/* GEM_MAC_RX_CONFIG register bits */
399#define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */
400#define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */
401#define GEM_MAC_RX_STRIP_CRC 0x00000004
402#define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */
403#define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */
404#define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */
405#define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */
406#define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */
407#define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */
408/*
409 * Carrier Extension enables reception of packet bursts generated by
410 * senders with carrier extension enabled.
411 */
412#define GEM_MAC_RX_CONFIG_BITS "\177\020" \
413 "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \
414 "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \
415 "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0"
416
416
417/* GEM_MAC_CONTROL_CONFIG bits */
418#define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */
419#define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */
420#define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */
421#define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0"
422
417/* GEM_MAC_CONTROL_CONFIG bits */
418#define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */
419#define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */
420#define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */
421#define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0"
422
423
424/* GEM MIF registers */
425/* Bit bang registers use low bit only. */
423/*
424 * MIF registers
425 * Bit bang registers use low bit only.
426 */
426#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */
427#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */
428#define GEM_MIF_BB_OUTPUT_ENAB 0x6208
429#define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */
430#define GEM_MIF_CONFIG 0x6210
427#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */
428#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */
429#define GEM_MIF_BB_OUTPUT_ENAB 0x6208
430#define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */
431#define GEM_MIF_CONFIG 0x6210
431#define GEM_MIF_INTERRUPT_MASK 0x6214
432#define GEM_MIF_BASIC_STATUS 0x6218
432#define GEM_MIF_MASK 0x6214
433#define GEM_MIF_STATUS 0x6218
433#define GEM_MIF_STATE_MACHINE 0x621c
434
434#define GEM_MIF_STATE_MACHINE 0x621c
435
435
436/* GEM_MIF_FRAME bits */
437#define GEM_MIF_FRAME_DATA 0x0000ffff
436/* GEM_MIF_FRAME bits */
437#define GEM_MIF_FRAME_DATA 0x0000ffff
438#define GEM_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */
439#define GEM_MIF_FRAME_TA1 0x00020000 /* TA bits */
438#define GEM_MIF_FRAME_TA0 0x00010000 /* TA LSB, 1 for completion */
439#define GEM_MIF_FRAME_TA1 0x00020000 /* TA MSB, 1 for instruction */
440#define GEM_MIF_FRAME_REG_ADDR 0x007c0000
440#define GEM_MIF_FRAME_REG_ADDR 0x007c0000
441#define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* phy address, should be 0 */
441#define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* PHY address */
442#define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */
443#define GEM_MIF_FRAME_START 0xc0000000 /* START bits */
444
445#define GEM_MIF_FRAME_READ 0x60020000
446#define GEM_MIF_FRAME_WRITE 0x50020000
447
448#define GEM_MIF_REG_SHIFT 18
449#define GEM_MIF_PHY_SHIFT 23
450
442#define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */
443#define GEM_MIF_FRAME_START 0xc0000000 /* START bits */
444
445#define GEM_MIF_FRAME_READ 0x60020000
446#define GEM_MIF_FRAME_WRITE 0x50020000
447
448#define GEM_MIF_REG_SHIFT 18
449#define GEM_MIF_PHY_SHIFT 23
450
451
452/* GEM_MIF_CONFIG register bits */
451/* GEM_MIF_CONFIG register bits */
453#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0=MDIO0 */
452#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0: MDIO_0 */
454#define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */
455#define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */
456#define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */
453#define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */
454#define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */
455#define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */
457#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */
458#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */
456#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 attached/data */
457#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 attached/data */
459#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */
460/* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */
461#define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \
462 "b\x8MDIO0\0b\x9MDIO1\0\0"
463
458#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */
459/* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */
460#define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \
461 "b\x8MDIO0\0b\x9MDIO1\0\0"
462
464
465/* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */
466#define GEM_MIF_STATUS 0x0000ffff
467#define GEM_MIF_BASIC 0xffff0000
463/* GEM_MIF_STATUS and GEM_MIF_MASK bits */
464#define GEM_MIF_POLL_STATUS_MASK 0x0000ffff /* polling status */
465#define GEM_MIF_POLL_STATUS_SHFT 0
466#define GEM_MIF_POLL_DATA_MASK 0xffff0000 /* polling data */
467#define GEM_MIF_POLL_DATA_SHFT 8
468/*
469 * The Basic part is the last value read in the POLL field of the config
470 * register.
468/*
469 * The Basic part is the last value read in the POLL field of the config
470 * register.
471 *
472 * The status part indicates the bits that have changed.
473 */
474
471 * The status part indicates the bits that have changed.
472 */
473
475
476/* GEM PCS/Serial link registers */
477/* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */
478#define GEM_MII_CONTROL 0x9000
479#define GEM_MII_STATUS 0x9004
480#define GEM_MII_ANAR 0x9008 /* MII advertisement reg */
481#define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */
482#define GEM_MII_CONFIG 0x9010
483#define GEM_MII_STATE_MACHINE 0x9014
484#define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */
485#define GEM_MII_DATAPATH_MODE 0x9050
486#define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */
487#define GEM_MII_OUTPUT_SELECT 0x9058
474/* GEM PCS/Serial link registers */
475/* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */
476#define GEM_MII_CONTROL 0x9000
477#define GEM_MII_STATUS 0x9004
478#define GEM_MII_ANAR 0x9008 /* MII advertisement reg */
479#define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */
480#define GEM_MII_CONFIG 0x9010
481#define GEM_MII_STATE_MACHINE 0x9014
482#define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */
483#define GEM_MII_DATAPATH_MODE 0x9050
484#define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */
485#define GEM_MII_OUTPUT_SELECT 0x9058
488#define GEM_MII_SLINK_STATUS 0x905c /* serial link status */
486#define GEM_MII_SLINK_STATUS 0x905c /* Serialink status */
489
487
490
491/* GEM_MII_CONTROL bits - PCS "BMCR" (Basic Mode Control Reg) */
488/* GEM_MII_CONTROL bits - PCS "BMCR" (Basic Mode Control Reg) */
492#define GEM_MII_CONTROL_RESET 0x00008000
493#define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */
494#define GEM_MII_CONTROL_1000M 0x00002000 /* speed select, always 0 */
495#define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */
496#define GEM_MII_CONTROL_POWERDN 0x00000800
497#define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate phy from mii */
498#define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotiation */
499#define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */
489#define GEM_MII_CONTROL_1000M 0x00000040 /* 1000Mbps speed select */
500#define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */
490#define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */
491#define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full-duplex, always 0 */
492#define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto-negotiation */
493#define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate PHY from MII */
494#define GEM_MII_CONTROL_POWERDN 0x00000800 /* power down */
495#define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto-negotiation enable */
496#define GEM_MII_CONTROL_10_100M 0x00002000 /* 10/100Mbps speed select */
497#define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */
498#define GEM_MII_CONTROL_RESET 0x00008000 /* Reset PCS. */
501#define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \
502 "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \
503 "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0"
504
499#define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \
500 "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \
501 "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0"
502
505
506/* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */
503/* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */
507#define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */
508#define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */
509#define GEM_MII_STATUS_UNK 0x00000100
510#define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate compete */
511#define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */
512#define GEM_MII_STATUS_ACFG 0x00000008 /* can auto negotiate */
513#define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */
504#define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended capability */
514#define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */
505#define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */
515#define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended register capability */
506#define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */
507#define GEM_MII_STATUS_ACFG 0x00000008 /* can auto-negotiate */
508#define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */
509#define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */
510#define GEM_MII_STATUS_EXTENDED 0x00000100 /* extended status */
516#define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \
511#define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \
517 "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0b\x9GBHDX\0" \
518 "b\xaGBFDX\0\0"
512 "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0\0"
519
513
520
521/* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */
514/* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */
522#define GEM_MII_ANEG_NP 0x00008000 /* next page bit */
523#define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of */
524 /* Link Partner Capability */
525#define GEM_MII_ANEG_RF 0x00003000 /* advertise remote fault cap */
526#define GEM_MII_ANEG_ASYM_PAUSE 0x00000100 /* asymmetric pause */
527#define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* symmetric pause */
528#define GEM_MII_ANEG_HLF_DUPLX 0x00000040
529#define GEM_MII_ANEG_FUL_DUPLX 0x00000020
515#define GEM_MII_ANEG_FDUPLX 0x00000020 /* full-duplex */
516#define GEM_MII_ANEG_HDUPLX 0x00000040 /* half-duplex */
517#define GEM_MII_ANEG_PAUSE 0x00000080 /* symmetric PAUSE */
518#define GEM_MII_ANEG_ASM_DIR 0x00000100 /* asymmetric PAUSE */
519#define GEM_MII_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */
520#define GEM_MII_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */
521#define GEM_MII_ANEG_RFLT_MASK \
522(CAS_PCS_ANEG_RFLT_FAIL | CAS_PCS_ANEG_RFLT_OFF)
523#define GEM_MII_ANEG_ACK 0x00004000 /* acknowledge */
524#define GEM_MII_ANEG_NP 0x00008000 /* next page */
530#define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \
531 "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \
532 "\b\xfNPBIT\0\0"
533
525#define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \
526 "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \
527 "\b\xfNPBIT\0\0"
528
534
535/* GEM_MII_CONFIG reg */
529/* GEM_MII_CONFIG reg */
536#define GEM_MII_CONFIG_TIMER 0x0000000e /* link monitor timer values */
537#define GEM_MII_CONFIG_ANTO 0x00000020 /* 10ms ANEG timer override */
538#define GEM_MII_CONFIG_JS 0x00000018 /* Jitter Study, 0 normal
539 * 1 high freq, 2 low freq */
540#define GEM_MII_CONFIG_SDL 0x00000004 /* Signal Detect active low */
541#define GEM_MII_CONFIG_SDO 0x00000002 /* Signal Detect Override */
542#define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */
530#define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS. */
531#define GEM_MII_CONFIG_SDO 0x00000002 /* signal detect override */
532#define GEM_MII_CONFIG_SDL 0x00000004 /* signal detect active-low */
533#define GEM_MII_CONFIG_JS_NORM 0x00000000 /* jitter study - normal op. */
534#define GEM_MII_CONFIG_JS_HF 0x00000008 /* jitter study - HF test */
535#define GEM_MII_CONFIG_JS_LF 0x00000010 /* jitter study - LF test */
536#define GEM_MII_CONFIG_JS_MASK \
537 (GEM_MII_CONFIG_JS_HF | GEM_MII_CONFIG_JS_LF)
538#define GEM_MII_CONFIG_ANTO 0x00000020 /* auto-neg. timer override */
543#define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0"
544
539#define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0"
540
545
546/*
541/*
547 * GEM_MII_STATE_MACHINE
548 * XXX These are best guesses from observed behavior.
549 */
550#define GEM_MII_FSM_STOP 0x00000000 /* stopped */
551#define GEM_MII_FSM_RUN 0x00000001 /* running */
552#define GEM_MII_FSM_UNKWN 0x00000100 /* unknown */
553#define GEM_MII_FSM_DONE 0x00000101 /* complete */
554
555
556/*
557 * GEM_MII_INTERRUP_STATUS reg
558 * No mask register; mask with the global interrupt mask register.
559 */
560#define GEM_MII_INTERRUP_LINK 0x00000004 /* PCS link status change */
561
542 * GEM_MII_INTERRUP_STATUS reg
543 * No mask register; mask with the global interrupt mask register.
544 */
545#define GEM_MII_INTERRUP_LINK 0x00000004 /* PCS link status change */
546
562
563/* GEM_MII_DATAPATH_MODE reg */
547/* GEM_MII_DATAPATH_MODE reg */
564#define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serial link */
565#define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */
566#define GEM_MII_DATAPATH_MII 0x00000004 /* Use {G}MII, not PCS */
567#define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */
548#define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serialink */
549#define GEM_MII_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */
550#define GEM_MII_DATAPATH_MII 0x00000004 /* GMII/MII */
551#define GEM_MII_DATAPATH_GMIIOE 0x00000008 /* serial output on GMII en. */
568#define GEM_MII_DATAPATH_BITS "\177\020" \
552#define GEM_MII_DATAPATH_BITS "\177\020" \
569 "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3MIIOUT\0\0"
553 "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3GMIIOE\0\0"
570
554
571
572/* GEM_MII_SLINK_CONTROL reg */
555/* GEM_MII_SLINK_CONTROL reg */
573#define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at sl, logic
556#define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at SL, logic
574 * reversed for SERDES */
575#define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */
557 * reversed for SERDES */
558#define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */
576#define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */
577#define GEM_MII_SLINK_EMPHASIS 0x00000008 /* enable emphasis */
578#define GEM_MII_SLINK_SELFTEST 0x000001c0
579#define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down serial link */
559#define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock to reference clock */
560#define GEM_MII_SLINK_EMPHASIS 0x00000018 /* enable emphasis */
561#define GEM_MII_SLINK_SELFTEST 0x000001c0 /* self-test */
562#define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down Serialink. */
563#define GEM_MII_SLINK_RX_ZERO 0x00000c00 /* PLL input to Serialink. */
564#define GEM_MII_SLINK_RX_POLE 0x00003000 /* PLL input to Serialink. */
565#define GEM_MII_SLINK_TX_ZERO 0x0000c000 /* PLL input to Serialink. */
566#define GEM_MII_SLINK_TX_POLE 0x00030000 /* PLL input to Serialink. */
580#define GEM_MII_SLINK_CONTROL_BITS \
581 "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \
582 "\0b\3EMPHASIS\0b\x9PWRDWN\0\0"
583
567#define GEM_MII_SLINK_CONTROL_BITS \
568 "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \
569 "\0b\3EMPHASIS\0b\x9PWRDWN\0\0"
570
584
585/* GEM_MII_SLINK_STATUS reg */
586#define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */
571/* GEM_MII_SLINK_STATUS reg */
572#define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */
587#define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */
573#define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us w/ lockrefn */
588#define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */
589#define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */
590
591/*
592 * PCI Expansion ROM runtime access
593 * Sun GEMs map a 1MB space for the PCI Expansion ROM as the second half
594 * of the first register bank, although they only support up to 64KB ROMs.
595 */
596#define GEM_PCI_ROM_OFFSET 0x100000
597#define GEM_PCI_ROM_SIZE 0x10000
598
574#define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */
575#define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */
576
577/*
578 * PCI Expansion ROM runtime access
579 * Sun GEMs map a 1MB space for the PCI Expansion ROM as the second half
580 * of the first register bank, although they only support up to 64KB ROMs.
581 */
582#define GEM_PCI_ROM_OFFSET 0x100000
583#define GEM_PCI_ROM_SIZE 0x10000
584
599/* Wired GEM PHY addresses */
585/* Wired PHY addresses */
600#define GEM_PHYAD_INTERNAL 1
601#define GEM_PHYAD_EXTERNAL 0
602
603/*
586#define GEM_PHYAD_INTERNAL 1
587#define GEM_PHYAD_EXTERNAL 0
588
589/*
604 * GEM descriptor table structures
590 * descriptor table structures
605 */
606struct gem_desc {
607 uint64_t gd_flags;
608 uint64_t gd_addr;
609};
610
611/* Transmit flags */
591 */
592struct gem_desc {
593 uint64_t gd_flags;
594 uint64_t gd_addr;
595};
596
597/* Transmit flags */
612#define GEM_TD_BUFSIZE 0x0000000000007fffLL
613#define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */
598#define GEM_TD_BUFSIZE 0x0000000000007fffULL
599#define GEM_TD_CXSUM_START 0x00000000001f8000ULL /* Cxsum start offset */
614#define GEM_TD_CXSUM_STARTSHFT 15
600#define GEM_TD_CXSUM_STARTSHFT 15
615#define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */
601#define GEM_TD_CXSUM_STUFF 0x000000001fe00000ULL /* Cxsum stuff offset */
616#define GEM_TD_CXSUM_STUFFSHFT 21
602#define GEM_TD_CXSUM_STUFFSHFT 21
617#define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */
618#define GEM_TD_END_OF_PACKET 0x0000000040000000LL
619#define GEM_TD_START_OF_PACKET 0x0000000080000000LL
620#define GEM_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */
621#define GEM_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */
603#define GEM_TD_CXSUM_ENABLE 0x0000000020000000ULL /* Cxsum generation enable */
604#define GEM_TD_END_OF_PACKET 0x0000000040000000ULL
605#define GEM_TD_START_OF_PACKET 0x0000000080000000ULL
606#define GEM_TD_INTERRUPT_ME 0x0000000100000000ULL /* Interrupt me now */
607#define GEM_TD_NO_CRC 0x0000000200000000ULL /* do not insert crc */
622/*
623 * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF,
624 * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group.
625 */
626
627/* Receive flags */
608/*
609 * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF,
610 * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group.
611 */
612
613/* Receive flags */
628#define GEM_RD_CHECKSUM 0x000000000000ffffLL /* is the complement */
629#define GEM_RD_BUFSIZE 0x000000007fff0000LL
630#define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */
631#define GEM_RD_HASHVAL 0x0ffff00000000000LL
632#define GEM_RD_HASH_PASS 0x1000000000000000LL /* passed hash filter */
633#define GEM_RD_ALTERNATE_MAC 0x2000000000000000LL /* Alternate MAC adrs */
634#define GEM_RD_BAD_CRC 0x4000000000000000LL
614#define GEM_RD_CHECKSUM 0x000000000000ffffULL /* is the complement */
615#define GEM_RD_BUFSIZE 0x000000007fff0000ULL
616#define GEM_RD_OWN 0x0000000080000000ULL /* 1 - owned by h/w */
617#define GEM_RD_HASHVAL 0x0ffff00000000000ULL
618#define GEM_RD_HASH_PASS 0x1000000000000000ULL /* passed hash filter */
619#define GEM_RD_ALTERNATE_MAC 0x2000000000000000ULL /* Alternate MAC adrs */
620#define GEM_RD_BAD_CRC 0x4000000000000000ULL
635
636#define GEM_RD_BUFSHIFT 16
637#define GEM_RD_BUFLEN(x) (((x) & GEM_RD_BUFSIZE) >> GEM_RD_BUFSHIFT)
638
639#endif
621
622#define GEM_RD_BUFSHIFT 16
623#define GEM_RD_BUFLEN(x) (((x) & GEM_RD_BUFSIZE) >> GEM_RD_BUFSHIFT)
624
625#endif