| if_gemreg.h (172334) | if_gemreg.h (174987) |
|---|---|
| 1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 12 unchanged lines hidden (view full) --- 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gemreg.h,v 1.8 2005/12/11 12:21:26 christos Exp 28 * | 1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 12 unchanged lines hidden (view full) --- 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gemreg.h,v 1.8 2005/12/11 12:21:26 christos Exp 28 * |
| 29 * $FreeBSD: head/sys/dev/gem/if_gemreg.h 172334 2007-09-26 21:14:18Z marius $ | 29 * $FreeBSD: head/sys/dev/gem/if_gemreg.h 174987 2007-12-30 01:32:03Z marius $ |
| 30 */ 31 32#ifndef _IF_GEMREG_H 33#define _IF_GEMREG_H 34 35/* Register definitions for Sun GEM gigabit ethernet */ 36 37#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 38#define GEM_CONFIG 0x0004 /* config reg */ 39#define GEM_STATUS 0x000c /* status reg */ | 30 */ 31 32#ifndef _IF_GEMREG_H 33#define _IF_GEMREG_H 34 35/* Register definitions for Sun GEM gigabit ethernet */ 36 37#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 38#define GEM_CONFIG 0x0004 /* config reg */ 39#define GEM_STATUS 0x000c /* status reg */ |
| 40/* Note: Reading the status reg clears bits 0-6 */ | 40/* Note: Reading the status reg clears bits 0-6. */ |
| 41#define GEM_INTMASK 0x0010 42#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 43#define GEM_STATUS_ALIAS 0x001c 44/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 45#define GEM_ERROR_STATUS 0x1000 /* PCI error status R/C */ 46#define GEM_ERROR_MASK 0x1004 47#define GEM_BIF_CONFIG 0x1008 /* BIF config reg */ 48#define GEM_BIF_DIAG 0x100c --- 20 unchanged lines hidden (view full) --- 69#define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 70 71 72/* Top part of GEM_STATUS has TX completion information */ 73#define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */ 74 75 76/* | 41#define GEM_INTMASK 0x0010 42#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 43#define GEM_STATUS_ALIAS 0x001c 44/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 45#define GEM_ERROR_STATUS 0x1000 /* PCI error status R/C */ 46#define GEM_ERROR_MASK 0x1004 47#define GEM_BIF_CONFIG 0x1008 /* BIF config reg */ 48#define GEM_BIF_DIAG 0x100c --- 20 unchanged lines hidden (view full) --- 69#define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 70 71 72/* Top part of GEM_STATUS has TX completion information */ 73#define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */ 74 75 76/* |
| 77 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs. | 77 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs |
| 78 * Bits 0-6 auto-clear when read. 79 */ 80#define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */ 81#define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */ 82#define GEM_INTR_TX_DONE 0x000000004 /* TX complete */ 83#define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */ 84#define GEM_INTR_RX_NOBUF 0x000000020 85#define GEM_INTR_RX_TAG_ERR 0x000000040 --- 54 unchanged lines hidden (view full) --- 140#define GEM_TX_FIFO_TAG 0x2108 141#define GEM_TX_FIFO_DATA_LO 0x210c 142#define GEM_TX_FIFO_DATA_HI_T1 0x2110 143#define GEM_TX_FIFO_DATA_HI_T0 0x2114 144#define GEM_TX_FIFO_SIZE 0x2118 145#define GEM_TX_DEBUG 0x3028 146 147 | 78 * Bits 0-6 auto-clear when read. 79 */ 80#define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */ 81#define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */ 82#define GEM_INTR_TX_DONE 0x000000004 /* TX complete */ 83#define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */ 84#define GEM_INTR_RX_NOBUF 0x000000020 85#define GEM_INTR_RX_TAG_ERR 0x000000040 --- 54 unchanged lines hidden (view full) --- 140#define GEM_TX_FIFO_TAG 0x2108 141#define GEM_TX_FIFO_DATA_LO 0x210c 142#define GEM_TX_FIFO_DATA_HI_T1 0x2110 143#define GEM_TX_FIFO_DATA_HI_T0 0x2114 144#define GEM_TX_FIFO_SIZE 0x2118 145#define GEM_TX_DEBUG 0x3028 146 147 |
| 148/* GEM_TX_CONFIG register bits. */ | 148/* GEM_TX_CONFIG register bits */ |
| 149#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 150#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 151#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 152#define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 153 154#define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 155#define GEM_RING_SZ_64 (1<<1) 156#define GEM_RING_SZ_128 (2<<1) --- 32 unchanged lines hidden (view full) --- 189#define GEM_RX_FIFO_ADDRESS 0x410c 190#define GEM_RX_FIFO_TAG 0x4110 191#define GEM_RX_FIFO_DATA_LO 0x4114 192#define GEM_RX_FIFO_DATA_HI_T1 0x4118 193#define GEM_RX_FIFO_DATA_HI_T0 0x411c 194#define GEM_RX_FIFO_SIZE 0x4120 195 196 | 149#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 150#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 151#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 152#define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 153 154#define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 155#define GEM_RING_SZ_64 (1<<1) 156#define GEM_RING_SZ_128 (2<<1) --- 32 unchanged lines hidden (view full) --- 189#define GEM_RX_FIFO_ADDRESS 0x410c 190#define GEM_RX_FIFO_TAG 0x4110 191#define GEM_RX_FIFO_DATA_LO 0x4114 192#define GEM_RX_FIFO_DATA_HI_T1 0x4118 193#define GEM_RX_FIFO_DATA_HI_T0 0x411c 194#define GEM_RX_FIFO_SIZE 0x4120 195 196 |
| 197/* GEM_RX_CONFIG register bits. */ | 197/* GEM_RX_CONFIG register bits */ |
| 198#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 199#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 200#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 201#define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 202#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ 203#define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 204 205#define GEM_THRSH_64 0 --- 150 unchanged lines hidden (view full) --- 356 */ 357#define GEM_MAC_SLOT_TIME_CARR_EXTEND 0x200 358#define GEM_MAC_SLOT_TIME_NORMAL 0x40 359 360/* GEM_MAC_TX_CONFIG register bits */ 361#define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 362#define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 363#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ | 198#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 199#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 200#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 201#define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 202#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ 203#define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 204 205#define GEM_THRSH_64 0 --- 150 unchanged lines hidden (view full) --- 356 */ 357#define GEM_MAC_SLOT_TIME_CARR_EXTEND 0x200 358#define GEM_MAC_SLOT_TIME_NORMAL 0x40 359 360/* GEM_MAC_TX_CONFIG register bits */ 361#define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 362#define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 363#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ |
| 364#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */ | 364#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */ |
| 365#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 366#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 367#define GEM_MAC_TX_NO_BACKOFF 0x00000040 368#define GEM_MAC_TX_SLOWDOWN 0x00000080 369#define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 370#define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 371/* Carrier Extension is required for half duplex Gbps operation */ 372#define GEM_MAC_TX_CONFIG_BITS "\177\020" \ --- 26 unchanged lines hidden (view full) --- 399/* GEM_MAC_CONTROL_CONFIG bits */ 400#define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 401#define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 402#define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 403#define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0" 404 405 406/* GEM MIF registers */ | 365#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 366#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 367#define GEM_MAC_TX_NO_BACKOFF 0x00000040 368#define GEM_MAC_TX_SLOWDOWN 0x00000080 369#define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 370#define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 371/* Carrier Extension is required for half duplex Gbps operation */ 372#define GEM_MAC_TX_CONFIG_BITS "\177\020" \ --- 26 unchanged lines hidden (view full) --- 399/* GEM_MAC_CONTROL_CONFIG bits */ 400#define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 401#define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 402#define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 403#define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0" 404 405 406/* GEM MIF registers */ |
| 407/* Bit bang registers use low bit only */ | 407/* Bit bang registers use low bit only. */ |
| 408#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 409#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 410#define GEM_MIF_BB_OUTPUT_ENAB 0x6208 411#define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 412#define GEM_MIF_CONFIG 0x6210 413#define GEM_MIF_INTERRUPT_MASK 0x6214 414#define GEM_MIF_BASIC_STATUS 0x6218 415#define GEM_MIF_STATE_MACHINE 0x621c --- 18 unchanged lines hidden (view full) --- 434/* GEM_MIF_CONFIG register bits */ 435#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0=MDIO0 */ 436#define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 437#define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 438#define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 439#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */ 440#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */ 441#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ | 408#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 409#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 410#define GEM_MIF_BB_OUTPUT_ENAB 0x6208 411#define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 412#define GEM_MIF_CONFIG 0x6210 413#define GEM_MIF_INTERRUPT_MASK 0x6214 414#define GEM_MIF_BASIC_STATUS 0x6218 415#define GEM_MIF_STATE_MACHINE 0x621c --- 18 unchanged lines hidden (view full) --- 434/* GEM_MIF_CONFIG register bits */ 435#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0=MDIO0 */ 436#define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 437#define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 438#define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 439#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */ 440#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */ 441#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ |
| 442/* MDI0 is onboard transceiver MDI1 is external, PHYAD for both is 0 */ | 442/* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */ |
| 443#define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ 444 "b\x8MDIO0\0b\x9MDIO1\0\0" 445 446 447/* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */ 448#define GEM_MIF_STATUS 0x0000ffff 449#define GEM_MIF_BASIC 0xffff0000 450/* 451 * The Basic part is the last value read in the POLL field of the config 452 * register. 453 * 454 * The status part indicates the bits that have changed. 455 */ 456 457 | 443#define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ 444 "b\x8MDIO0\0b\x9MDIO1\0\0" 445 446 447/* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */ 448#define GEM_MIF_STATUS 0x0000ffff 449#define GEM_MIF_BASIC 0xffff0000 450/* 451 * The Basic part is the last value read in the POLL field of the config 452 * register. 453 * 454 * The status part indicates the bits that have changed. 455 */ 456 457 |
| 458/* The GEM PCS/Serial link registers. */ | 458/* GEM PCS/Serial link registers */ |
| 459/* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */ 460#define GEM_MII_CONTROL 0x9000 461#define GEM_MII_STATUS 0x9004 462#define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 463#define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */ 464#define GEM_MII_CONFIG 0x9010 465#define GEM_MII_STATE_MACHINE 0x9014 466#define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */ --- 111 unchanged lines hidden (view full) --- 578#define GEM_PCI_ROM_OFFSET 0x100000 579#define GEM_PCI_ROM_SIZE 0x10000 580 581/* Wired GEM PHY addresses */ 582#define GEM_PHYAD_INTERNAL 1 583#define GEM_PHYAD_EXTERNAL 0 584 585/* | 459/* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */ 460#define GEM_MII_CONTROL 0x9000 461#define GEM_MII_STATUS 0x9004 462#define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 463#define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */ 464#define GEM_MII_CONFIG 0x9010 465#define GEM_MII_STATE_MACHINE 0x9014 466#define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */ --- 111 unchanged lines hidden (view full) --- 578#define GEM_PCI_ROM_OFFSET 0x100000 579#define GEM_PCI_ROM_SIZE 0x10000 580 581/* Wired GEM PHY addresses */ 582#define GEM_PHYAD_INTERNAL 1 583#define GEM_PHYAD_EXTERNAL 0 584 585/* |
| 586 * GEM descriptor table structures. | 586 * GEM descriptor table structures |
| 587 */ 588struct gem_desc { 589 uint64_t gd_flags; 590 uint64_t gd_addr; 591}; 592 593/* Transmit flags */ 594#define GEM_TD_BUFSIZE 0x0000000000007fffLL --- 27 unchanged lines hidden --- | 587 */ 588struct gem_desc { 589 uint64_t gd_flags; 590 uint64_t gd_addr; 591}; 592 593/* Transmit flags */ 594#define GEM_TD_BUFSIZE 0x0000000000007fffLL --- 27 unchanged lines hidden --- |