if_gem.c (182060) | if_gem.c (194763) |
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1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 15 unchanged lines hidden (view full) --- 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29 */ 30 31#include <sys/cdefs.h> | 1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 15 unchanged lines hidden (view full) --- 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29 */ 30 31#include <sys/cdefs.h> |
32__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 182060 2008-08-23 15:03:26Z marius $"); | 32__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 194763 2009-06-23 20:36:59Z marius $"); |
33 34/* 35 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 36 */ 37 38#if 0 39#define GEM_DEBUG 40#endif --- 38 unchanged lines hidden (view full) --- 79#include <dev/mii/miivar.h> 80 81#include <dev/gem/if_gemreg.h> 82#include <dev/gem/if_gemvar.h> 83 84CTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); 85CTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); 86 | 33 34/* 35 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 36 */ 37 38#if 0 39#define GEM_DEBUG 40#endif --- 38 unchanged lines hidden (view full) --- 79#include <dev/mii/miivar.h> 80 81#include <dev/gem/if_gemreg.h> 82#include <dev/gem/if_gemvar.h> 83 84CTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); 85CTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); 86 |
87#define TRIES 10000 | 87#define GEM_TRIES 10000 |
88 89/* 90 * The hardware supports basic TCP/UDP checksum offloading. However, 91 * the hardware doesn't compensate the checksum for UDP datagram which 92 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled 93 * by default. It can be reactivated by setting special link option 94 * link0 with ifconfig(8). 95 */ --- 18 unchanged lines hidden (view full) --- 114static int gem_reset_rx(struct gem_softc *sc); 115static void gem_reset_rxdma(struct gem_softc *sc); 116static int gem_reset_tx(struct gem_softc *sc); 117static u_int gem_ringsize(u_int sz); 118static void gem_rint(struct gem_softc *sc); 119#ifdef GEM_RINT_TIMEOUT 120static void gem_rint_timeout(void *arg); 121#endif | 88 89/* 90 * The hardware supports basic TCP/UDP checksum offloading. However, 91 * the hardware doesn't compensate the checksum for UDP datagram which 92 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled 93 * by default. It can be reactivated by setting special link option 94 * link0 with ifconfig(8). 95 */ --- 18 unchanged lines hidden (view full) --- 114static int gem_reset_rx(struct gem_softc *sc); 115static void gem_reset_rxdma(struct gem_softc *sc); 116static int gem_reset_tx(struct gem_softc *sc); 117static u_int gem_ringsize(u_int sz); 118static void gem_rint(struct gem_softc *sc); 119#ifdef GEM_RINT_TIMEOUT 120static void gem_rint_timeout(void *arg); 121#endif |
122static __inline void gem_rxcksum(struct mbuf *m, uint64_t flags); | 122static inline void gem_rxcksum(struct mbuf *m, uint64_t flags); |
123static void gem_rxdrain(struct gem_softc *sc); 124static void gem_setladrf(struct gem_softc *sc); 125static void gem_start(struct ifnet *ifp); 126static void gem_start_locked(struct ifnet *ifp); 127static void gem_stop(struct ifnet *ifp, int disable); 128static void gem_tick(void *arg); 129static void gem_tint(struct gem_softc *sc); | 123static void gem_rxdrain(struct gem_softc *sc); 124static void gem_setladrf(struct gem_softc *sc); 125static void gem_start(struct ifnet *ifp); 126static void gem_start_locked(struct ifnet *ifp); 127static void gem_stop(struct ifnet *ifp, int disable); 128static void gem_tick(void *arg); 129static void gem_tint(struct gem_softc *sc); |
130static inline void gem_txkick(struct gem_softc *sc); |
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130static int gem_watchdog(struct gem_softc *sc); 131 132devclass_t gem_devclass; 133DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 134MODULE_DEPEND(gem, miibus, 1, 1, 1); 135 136#ifdef GEM_DEBUG 137#include <sys/ktr.h> --- 8 unchanged lines hidden (view full) --- 146int 147gem_attach(struct gem_softc *sc) 148{ 149 struct gem_txsoft *txs; 150 struct ifnet *ifp; 151 int error, i; 152 uint32_t v; 153 | 131static int gem_watchdog(struct gem_softc *sc); 132 133devclass_t gem_devclass; 134DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 135MODULE_DEPEND(gem, miibus, 1, 1, 1); 136 137#ifdef GEM_DEBUG 138#include <sys/ktr.h> --- 8 unchanged lines hidden (view full) --- 147int 148gem_attach(struct gem_softc *sc) 149{ 150 struct gem_txsoft *txs; 151 struct ifnet *ifp; 152 int error, i; 153 uint32_t v; 154 |
155 if (bootverbose) 156 device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags); 157 158 /* Set up ifnet structure. */ |
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154 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 155 if (ifp == NULL) 156 return (ENOSPC); | 159 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 160 if (ifp == NULL) 161 return (ENOSPC); |
162 sc->sc_csum_features = GEM_CSUM_FEATURES; 163 ifp->if_softc = sc; 164 if_initname(ifp, device_get_name(sc->sc_dev), 165 device_get_unit(sc->sc_dev)); 166 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 167 ifp->if_start = gem_start; 168 ifp->if_ioctl = gem_ioctl; 169 ifp->if_init = gem_init; 170 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN); 171 ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN; 172 IFQ_SET_READY(&ifp->if_snd); |
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157 158 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 159#ifdef GEM_RINT_TIMEOUT 160 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 161#endif 162 163 /* Make sure the chip is stopped. */ | 173 174 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 175#ifdef GEM_RINT_TIMEOUT 176 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 177#endif 178 179 /* Make sure the chip is stopped. */ |
164 ifp->if_softc = sc; | |
165 gem_reset(sc); 166 167 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 168 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 169 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 170 NULL, &sc->sc_pdmatag); | 180 gem_reset(sc); 181 182 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 183 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 184 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 185 NULL, &sc->sc_pdmatag); |
171 if (error) | 186 if (error != 0) |
172 goto fail_ifnet; 173 174 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 175 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 176 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag); | 187 goto fail_ifnet; 188 189 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 190 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 191 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag); |
177 if (error) | 192 if (error != 0) |
178 goto fail_ptag; 179 180 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 181 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 182 MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES, 183 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); | 193 goto fail_ptag; 194 195 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 196 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 197 MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES, 198 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); |
184 if (error) | 199 if (error != 0) |
185 goto fail_rtag; 186 187 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 188 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 189 sizeof(struct gem_control_data), 1, 190 sizeof(struct gem_control_data), 0, 191 NULL, NULL, &sc->sc_cdmatag); | 200 goto fail_rtag; 201 202 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 203 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 204 sizeof(struct gem_control_data), 1, 205 sizeof(struct gem_control_data), 0, 206 NULL, NULL, &sc->sc_cdmatag); |
192 if (error) | 207 if (error != 0) |
193 goto fail_ttag; 194 195 /* 196 * Allocate the control data structures, create and load the 197 * DMA map for it. 198 */ 199 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 200 (void **)&sc->sc_control_data, 201 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, | 208 goto fail_ttag; 209 210 /* 211 * Allocate the control data structures, create and load the 212 * DMA map for it. 213 */ 214 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 215 (void **)&sc->sc_control_data, 216 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, |
202 &sc->sc_cddmamap))) { | 217 &sc->sc_cddmamap)) != 0) { |
203 device_printf(sc->sc_dev, 204 "unable to allocate control data, error = %d\n", error); 205 goto fail_ctag; 206 } 207 208 sc->sc_cddma = 0; 209 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 210 sc->sc_control_data, sizeof(struct gem_control_data), --- 122 unchanged lines hidden (view full) --- 333 sc->sc_rxfifosize = 64 * 334 GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE); 335 336 /* Get TX FIFO size. */ 337 v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE); 338 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 339 sc->sc_rxfifosize / 1024, v / 16); 340 | 218 device_printf(sc->sc_dev, 219 "unable to allocate control data, error = %d\n", error); 220 goto fail_ctag; 221 } 222 223 sc->sc_cddma = 0; 224 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 225 sc->sc_control_data, sizeof(struct gem_control_data), --- 122 unchanged lines hidden (view full) --- 348 sc->sc_rxfifosize = 64 * 349 GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE); 350 351 /* Get TX FIFO size. */ 352 v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE); 353 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 354 sc->sc_rxfifosize / 1024, v / 16); 355 |
341 sc->sc_csum_features = GEM_CSUM_FEATURES; 342 /* Initialize ifnet structure. */ 343 ifp->if_softc = sc; 344 if_initname(ifp, device_get_name(sc->sc_dev), 345 device_get_unit(sc->sc_dev)); 346 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 347 ifp->if_start = gem_start; 348 ifp->if_ioctl = gem_ioctl; 349 ifp->if_init = gem_init; 350 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN); 351 ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN; 352 IFQ_SET_READY(&ifp->if_snd); 353 | |
354 /* Attach the interface. */ 355 ether_ifattach(ifp, sc->sc_enaddr); 356 357 /* 358 * Tell the upper layer(s) we support long frames/checksum offloads. 359 */ 360 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 361 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; --- 35 unchanged lines hidden (view full) --- 397 398void 399gem_detach(struct gem_softc *sc) 400{ 401 struct ifnet *ifp = sc->sc_ifp; 402 int i; 403 404 GEM_LOCK(sc); | 356 /* Attach the interface. */ 357 ether_ifattach(ifp, sc->sc_enaddr); 358 359 /* 360 * Tell the upper layer(s) we support long frames/checksum offloads. 361 */ 362 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 363 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; --- 35 unchanged lines hidden (view full) --- 399 400void 401gem_detach(struct gem_softc *sc) 402{ 403 struct ifnet *ifp = sc->sc_ifp; 404 int i; 405 406 GEM_LOCK(sc); |
407 sc->sc_flags |= GEM_DYING; |
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405 gem_stop(ifp, 1); 406 GEM_UNLOCK(sc); 407 callout_drain(&sc->sc_tick_ch); 408#ifdef GEM_RINT_TIMEOUT 409 callout_drain(&sc->sc_rx_ch); 410#endif 411 ether_ifdetach(ifp); 412 if_free(ifp); --- 38 unchanged lines hidden (view full) --- 451 * after power-on. 452 */ 453 sc->sc_flags &= ~GEM_INITED; 454 if (ifp->if_flags & IFF_UP) 455 gem_init_locked(sc); 456 GEM_UNLOCK(sc); 457} 458 | 408 gem_stop(ifp, 1); 409 GEM_UNLOCK(sc); 410 callout_drain(&sc->sc_tick_ch); 411#ifdef GEM_RINT_TIMEOUT 412 callout_drain(&sc->sc_rx_ch); 413#endif 414 ether_ifdetach(ifp); 415 if_free(ifp); --- 38 unchanged lines hidden (view full) --- 454 * after power-on. 455 */ 456 sc->sc_flags &= ~GEM_INITED; 457 if (ifp->if_flags & IFF_UP) 458 gem_init_locked(sc); 459 GEM_UNLOCK(sc); 460} 461 |
459static __inline void | 462static inline void |
460gem_rxcksum(struct mbuf *m, uint64_t flags) 461{ 462 struct ether_header *eh; 463 struct ip *ip; 464 struct udphdr *uh; 465 uint16_t *opts; 466 int32_t hlen, len, pktlen; 467 uint32_t temp32; --- 62 unchanged lines hidden (view full) --- 530 panic("%s: bad control buffer segment count", __func__); 531 sc->sc_cddma = segs[0].ds_addr; 532} 533 534static void 535gem_tick(void *arg) 536{ 537 struct gem_softc *sc = arg; | 463gem_rxcksum(struct mbuf *m, uint64_t flags) 464{ 465 struct ether_header *eh; 466 struct ip *ip; 467 struct udphdr *uh; 468 uint16_t *opts; 469 int32_t hlen, len, pktlen; 470 uint32_t temp32; --- 62 unchanged lines hidden (view full) --- 533 panic("%s: bad control buffer segment count", __func__); 534 sc->sc_cddma = segs[0].ds_addr; 535} 536 537static void 538gem_tick(void *arg) 539{ 540 struct gem_softc *sc = arg; |
538 struct ifnet *ifp; | 541 struct ifnet *ifp = sc->sc_ifp; |
539 uint32_t v; 540 541 GEM_LOCK_ASSERT(sc, MA_OWNED); 542 | 542 uint32_t v; 543 544 GEM_LOCK_ASSERT(sc, MA_OWNED); 545 |
543 ifp = sc->sc_ifp; | |
544 /* 545 * Unload collision and error counters. 546 */ 547 ifp->if_collisions += 548 GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) + 549 GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT); 550 v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) + 551 GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT); --- 27 unchanged lines hidden (view full) --- 579 580static int 581gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr, 582 uint32_t set) 583{ 584 int i; 585 uint32_t reg; 586 | 546 /* 547 * Unload collision and error counters. 548 */ 549 ifp->if_collisions += 550 GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) + 551 GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT); 552 v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) + 553 GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT); --- 27 unchanged lines hidden (view full) --- 581 582static int 583gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr, 584 uint32_t set) 585{ 586 int i; 587 uint32_t reg; 588 |
587 for (i = TRIES; i--; DELAY(100)) { | 589 for (i = GEM_TRIES; i--; DELAY(100)) { |
588 reg = GEM_BANKN_READ_M(bank, 4, sc, r); 589 if ((reg & clr) == 0 && (reg & set) == set) 590 return (1); 591 } 592 return (0); 593} 594 595static void | 590 reg = GEM_BANKN_READ_M(bank, 4, sc, r); 591 if ((reg & clr) == 0 && (reg & set) == set) 592 return (1); 593 } 594 return (0); 595} 596 597static void |
596gem_reset(sc) 597 struct gem_softc *sc; | 598gem_reset(struct gem_softc *sc) |
598{ 599 600#ifdef GEM_DEBUG 601 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 602#endif 603 gem_reset_rx(sc); 604 gem_reset_tx(sc); 605 --- 33 unchanged lines hidden (view full) --- 639 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 640#endif 641 642 callout_stop(&sc->sc_tick_ch); 643#ifdef GEM_RINT_TIMEOUT 644 callout_stop(&sc->sc_rx_ch); 645#endif 646 | 599{ 600 601#ifdef GEM_DEBUG 602 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 603#endif 604 gem_reset_rx(sc); 605 gem_reset_tx(sc); 606 --- 33 unchanged lines hidden (view full) --- 640 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 641#endif 642 643 callout_stop(&sc->sc_tick_ch); 644#ifdef GEM_RINT_TIMEOUT 645 callout_stop(&sc->sc_rx_ch); 646#endif 647 |
647 /* XXX should we reset these instead? */ 648 gem_disable_tx(sc); 649 gem_disable_rx(sc); | 648 gem_reset_tx(sc); 649 gem_reset_rx(sc); |
650 651 /* 652 * Release any queued transmit buffers. 653 */ 654 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 655 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 656 if (txs->txs_ndescs != 0) { 657 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, --- 58 unchanged lines hidden (view full) --- 716 int i; 717 718 if (gem_reset_rx(sc) != 0) 719 return (gem_init_locked(sc)); 720 for (i = 0; i < GEM_NRXDESC; i++) 721 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 722 GEM_UPDATE_RXDESC(sc, i); 723 sc->sc_rxptr = 0; | 650 651 /* 652 * Release any queued transmit buffers. 653 */ 654 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 655 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 656 if (txs->txs_ndescs != 0) { 657 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, --- 58 unchanged lines hidden (view full) --- 716 int i; 717 718 if (gem_reset_rx(sc) != 0) 719 return (gem_init_locked(sc)); 720 for (i = 0; i < GEM_NRXDESC; i++) 721 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 722 GEM_UPDATE_RXDESC(sc, i); 723 sc->sc_rxptr = 0; |
724 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | 724 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); |
725 726 /* NOTE: we use only 32-bit DMA addresses here. */ 727 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 728 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 729 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 730 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 731 gem_ringsize(GEM_NRXDESC /* XXX */) | 732 ((ETHER_HDR_LEN + sizeof(struct ip)) << 733 GEM_RX_CONFIG_CXM_START_SHFT) | 734 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | | 725 726 /* NOTE: we use only 32-bit DMA addresses here. */ 727 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 728 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 729 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 730 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 731 gem_ringsize(GEM_NRXDESC /* XXX */) | 732 ((ETHER_HDR_LEN + sizeof(struct ip)) << 733 GEM_RX_CONFIG_CXM_START_SHFT) | 734 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | |
735 (2 << GEM_RX_CONFIG_FBOFF_SHFT)); | 735 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT)); 736 /* Adjust for the SBus clock probably isn't worth the fuzz. */ |
736 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, | 737 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, |
737 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); | 738 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 739 GEM_RX_BLANKING_TIME_SHIFT) | 6); |
738 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 739 (3 * sc->sc_rxfifosize / 256) | 740 ((sc->sc_rxfifosize / 256) << 12)); 741 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 742 GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); 743 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 744 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 745 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, --- 47 unchanged lines hidden (view full) --- 793 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE); 794 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 795 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 796 return (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 797 0)); 798} 799 800static int | 740 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 741 (3 * sc->sc_rxfifosize / 256) | 742 ((sc->sc_rxfifosize / 256) << 12)); 743 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 744 GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); 745 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 746 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 747 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, --- 47 unchanged lines hidden (view full) --- 795 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE); 796 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 797 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 798 return (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 799 0)); 800} 801 802static int |
801gem_meminit(sc) 802 struct gem_softc *sc; | 803gem_meminit(struct gem_softc *sc) |
803{ 804 struct gem_rxsoft *rxs; 805 int error, i; 806 | 804{ 805 struct gem_rxsoft *rxs; 806 int error, i; 807 |
808 GEM_LOCK_ASSERT(sc, MA_OWNED); 809 |
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807 /* 808 * Initialize the transmit descriptor ring. 809 */ 810 for (i = 0; i < GEM_NTXDESC; i++) { 811 sc->sc_txdescs[i].gd_flags = 0; 812 sc->sc_txdescs[i].gd_addr = 0; 813 } 814 sc->sc_txfree = GEM_MAXTXFREE; --- 17 unchanged lines hidden (view full) --- 832 */ 833 gem_rxdrain(sc); 834 return (1); 835 } 836 } else 837 GEM_INIT_RXDESC(sc, i); 838 } 839 sc->sc_rxptr = 0; | 810 /* 811 * Initialize the transmit descriptor ring. 812 */ 813 for (i = 0; i < GEM_NTXDESC; i++) { 814 sc->sc_txdescs[i].gd_flags = 0; 815 sc->sc_txdescs[i].gd_addr = 0; 816 } 817 sc->sc_txfree = GEM_MAXTXFREE; --- 17 unchanged lines hidden (view full) --- 835 */ 836 gem_rxdrain(sc); 837 return (1); 838 } 839 } else 840 GEM_INIT_RXDESC(sc, i); 841 } 842 sc->sc_rxptr = 0; |
840 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | |
841 | 843 |
844 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 845 |
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842 return (0); 843} 844 845static u_int 846gem_ringsize(u_int sz) 847{ 848 849 switch (sz) { --- 83 unchanged lines hidden (view full) --- 933 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 934 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 935#ifdef GEM_DEBUG 936 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", 937 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 938#endif 939 940 /* step 8. Global Configuration & Interrupt Mask */ | 846 return (0); 847} 848 849static u_int 850gem_ringsize(u_int sz) 851{ 852 853 switch (sz) { --- 83 unchanged lines hidden (view full) --- 937 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 938 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 939#ifdef GEM_DEBUG 940 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", 941 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 942#endif 943 944 /* step 8. Global Configuration & Interrupt Mask */ |
945 946 /* 947 * Set the internal arbitration to "infinite" bursts of the 948 * maximum length of 31 * 64 bytes so DMA transfers aren't 949 * split up in cache line size chunks. This greatly improves 950 * RX performance. 951 * Enable silicon bug workarounds for the Apple variants. 952 */ 953 GEM_BANK1_WRITE_4(sc, GEM_CONFIG, 954 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 955 ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF : 956 GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 957 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 958 |
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941 GEM_BANK1_WRITE_4(sc, GEM_INTMASK, 942 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | 943 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | 944 GEM_INTR_BERR 945#ifdef GEM_DEBUG 946 | GEM_INTR_PCS | GEM_INTR_MIF 947#endif 948 )); 949 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 950 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 951 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK, | 959 GEM_BANK1_WRITE_4(sc, GEM_INTMASK, 960 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | 961 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | 962 GEM_INTR_BERR 963#ifdef GEM_DEBUG 964 | GEM_INTR_PCS | GEM_INTR_MIF 965#endif 966 )); 967 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 968 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 969 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK, |
952 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP); | 970 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 971 GEM_MAC_TX_PEAK_EXP); |
953#ifdef GEM_DEBUG 954 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 955 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME)); 956#else 957 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 958 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 959#endif 960 961 /* step 9. ETX Configuration: use mostly default values. */ 962 963 /* Enable DMA. */ | 972#ifdef GEM_DEBUG 973 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 974 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME)); 975#else 976 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 977 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 978#endif 979 980 /* step 9. ETX Configuration: use mostly default values. */ 981 982 /* Enable DMA. */ |
964 v = gem_ringsize(GEM_NTXDESC /* XXX */); | 983 v = gem_ringsize(GEM_NTXDESC); 984 /* Set TX FIFO threshold and enable DMA. */ |
965 v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) & 966 GEM_TX_CONFIG_TXFIFO_TH; 967 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 968 969 /* step 10. ERX Configuration */ 970 971 /* Encode Receive Descriptor ring size. */ 972 v = gem_ringsize(GEM_NRXDESC /* XXX */); 973 /* RX TCP/UDP checksum offset */ 974 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << 975 GEM_RX_CONFIG_CXM_START_SHFT); | 985 v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) & 986 GEM_TX_CONFIG_TXFIFO_TH; 987 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 988 989 /* step 10. ERX Configuration */ 990 991 /* Encode Receive Descriptor ring size. */ 992 v = gem_ringsize(GEM_NRXDESC /* XXX */); 993 /* RX TCP/UDP checksum offset */ 994 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << 995 GEM_RX_CONFIG_CXM_START_SHFT); |
976 977 /* Enable DMA. */ | 996 /* Set RX FIFO threshold, set first byte offset and enable DMA. */ |
978 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 979 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | | 997 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 998 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | |
980 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); | 999 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) | 1000 GEM_RX_CONFIG_RXDMA_EN); |
981 | 1001 |
1002 /* Adjust for the SBus clock probably isn't worth the fuzz. */ |
|
982 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, | 1003 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, |
983 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); | 1004 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 1005 GEM_RX_BLANKING_TIME_SHIFT) | 6); |
984 985 /* 986 * The following value is for an OFF Threshold of about 3/4 full 987 * and an ON Threshold of 1/4 full. 988 */ 989 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 990 (3 * sc->sc_rxfifosize / 256) | 991 ((sc->sc_rxfifosize / 256) << 12)); --- 5 unchanged lines hidden (view full) --- 997 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 998 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 999 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 1000 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1001 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 1002 device_printf(sc->sc_dev, "cannot configure RX MAC\n"); 1003 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 1004 | 1006 1007 /* 1008 * The following value is for an OFF Threshold of about 3/4 full 1009 * and an ON Threshold of 1/4 full. 1010 */ 1011 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 1012 (3 * sc->sc_rxfifosize / 256) | 1013 ((sc->sc_rxfifosize / 256) << 12)); --- 5 unchanged lines hidden (view full) --- 1019 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1020 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 1021 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 1022 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1023 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 1024 device_printf(sc->sc_dev, "cannot configure RX MAC\n"); 1025 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 1026 |
1005 /* step 13. TX_MAC Configuration Register */ | 1027 /* step 13. TX_MAC Configuration Register */ |
1006 v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG); 1007 v |= GEM_MAC_TX_ENABLE; 1008 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 1009 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 1010 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1011 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 1012 device_printf(sc->sc_dev, "cannot configure TX MAC\n"); 1013 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v); --- 18 unchanged lines hidden (view full) --- 1032{ 1033 bus_dma_segment_t txsegs[GEM_NTXSEGS]; 1034 struct gem_txsoft *txs; 1035 struct ip *ip; 1036 struct mbuf *m; 1037 uint64_t cflags, flags; 1038 int error, nexttx, nsegs, offset, seg; 1039 | 1028 v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG); 1029 v |= GEM_MAC_TX_ENABLE; 1030 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 1031 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 1032 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1033 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 1034 device_printf(sc->sc_dev, "cannot configure TX MAC\n"); 1035 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v); --- 18 unchanged lines hidden (view full) --- 1054{ 1055 bus_dma_segment_t txsegs[GEM_NTXSEGS]; 1056 struct gem_txsoft *txs; 1057 struct ip *ip; 1058 struct mbuf *m; 1059 uint64_t cflags, flags; 1060 int error, nexttx, nsegs, offset, seg; 1061 |
1062 GEM_LOCK_ASSERT(sc, MA_OWNED); 1063 |
|
1040 /* Get a work queue entry. */ 1041 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1042 /* Ran out of descriptors. */ 1043 return (ENOBUFS); 1044 } 1045 1046 cflags = 0; 1047 if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) { --- 90 unchanged lines hidden (view full) --- 1138 1139 /* Lastly set SOP on the first descriptor. */ 1140#ifdef GEM_DEBUG 1141 CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", 1142 __func__, seg, nexttx); 1143#endif 1144 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1145 sc->sc_txwin = 0; | 1064 /* Get a work queue entry. */ 1065 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1066 /* Ran out of descriptors. */ 1067 return (ENOBUFS); 1068 } 1069 1070 cflags = 0; 1071 if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) { --- 90 unchanged lines hidden (view full) --- 1162 1163 /* Lastly set SOP on the first descriptor. */ 1164#ifdef GEM_DEBUG 1165 CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", 1166 __func__, seg, nexttx); 1167#endif 1168 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1169 sc->sc_txwin = 0; |
1146 flags |= GEM_TD_INTERRUPT_ME; | |
1147 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1148 GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME | 1149 GEM_TD_START_OF_PACKET); 1150 } else 1151 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1152 GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); 1153 1154 /* Sync the DMA map. */ --- 15 unchanged lines hidden (view full) --- 1170 return (0); 1171} 1172 1173static void 1174gem_init_regs(struct gem_softc *sc) 1175{ 1176 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1177 | 1170 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1171 GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME | 1172 GEM_TD_START_OF_PACKET); 1173 } else 1174 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1175 GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); 1176 1177 /* Sync the DMA map. */ --- 15 unchanged lines hidden (view full) --- 1193 return (0); 1194} 1195 1196static void 1197gem_init_regs(struct gem_softc *sc) 1198{ 1199 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1200 |
1201 GEM_LOCK_ASSERT(sc, MA_OWNED); 1202 |
|
1178 /* These registers are not cleared on reset. */ 1179 if ((sc->sc_flags & GEM_INITED) == 0) { 1180 /* magic values */ 1181 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0); 1182 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8); 1183 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4); 1184 | 1203 /* These registers are not cleared on reset. */ 1204 if ((sc->sc_flags & GEM_INITED) == 0) { 1205 /* magic values */ 1206 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0); 1207 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8); 1208 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4); 1209 |
1210 /* min frame length */ |
|
1185 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); | 1211 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); |
1186 /* max frame and max burst size */ | 1212 /* max frame length and max burst size */ |
1187 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME, 1188 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 1189 | 1213 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME, 1214 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 1215 |
1216 /* more magic values */ |
|
1190 GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7); 1191 GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4); 1192 GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10); | 1217 GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7); 1218 GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4); 1219 GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10); |
1193 /* dunno... */ | |
1194 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8088); | 1220 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8088); |
1221 1222 /* random number seed */ |
|
1195 GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED, 1196 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1197 1198 /* secondary MAC address: 0:0:0:0:0:0 */ 1199 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0); 1200 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0); 1201 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0); 1202 1203 /* MAC control address: 01:80:c2:00:00:01 */ 1204 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001); 1205 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200); 1206 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180); 1207 1208 /* MAC filter address: 0:0:0:0:0:0 */ 1209 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0); 1210 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0); 1211 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0); | 1223 GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED, 1224 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1225 1226 /* secondary MAC address: 0:0:0:0:0:0 */ 1227 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0); 1228 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0); 1229 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0); 1230 1231 /* MAC control address: 01:80:c2:00:00:01 */ 1232 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001); 1233 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200); 1234 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180); 1235 1236 /* MAC filter address: 0:0:0:0:0:0 */ 1237 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0); 1238 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0); 1239 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0); |
1212 | |
1213 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0); 1214 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0); 1215 1216 sc->sc_flags |= GEM_INITED; 1217 } 1218 1219 /* Counters need to be zeroed. */ 1220 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); --- 6 unchanged lines hidden (view full) --- 1227 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 1228 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 1229 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 1230 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 1231 1232 /* Set XOFF PAUSE time. */ 1233 GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1234 | 1240 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0); 1241 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0); 1242 1243 sc->sc_flags |= GEM_INITED; 1244 } 1245 1246 /* Counters need to be zeroed. */ 1247 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); --- 6 unchanged lines hidden (view full) --- 1254 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 1255 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 1256 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 1257 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 1258 1259 /* Set XOFF PAUSE time. */ 1260 GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1261 |
1235 /* 1236 * Set the internal arbitration to "infinite" bursts of the 1237 * maximum length of 31 * 64 bytes so DMA transfers aren't 1238 * split up in cache line size chunks. This greatly improves 1239 * especially RX performance. 1240 * Enable silicon bug workarounds for the Apple variants. 1241 */ 1242 GEM_BANK1_WRITE_4(sc, GEM_CONFIG, 1243 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1244 GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ? 1245 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1246 | |
1247 /* Set the station address. */ 1248 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1249 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1250 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1251 1252 /* Enable MII outputs. */ 1253 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); 1254} 1255 1256static void 1257gem_start(struct ifnet *ifp) 1258{ 1259 struct gem_softc *sc = ifp->if_softc; 1260 1261 GEM_LOCK(sc); 1262 gem_start_locked(ifp); 1263 GEM_UNLOCK(sc); 1264} 1265 | 1262 /* Set the station address. */ 1263 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1264 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1265 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1266 1267 /* Enable MII outputs. */ 1268 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); 1269} 1270 1271static void 1272gem_start(struct ifnet *ifp) 1273{ 1274 struct gem_softc *sc = ifp->if_softc; 1275 1276 GEM_LOCK(sc); 1277 gem_start_locked(ifp); 1278 GEM_UNLOCK(sc); 1279} 1280 |
1281static inline void 1282gem_txkick(struct gem_softc *sc) 1283{ 1284 1285 /* 1286 * Update the TX kick register. This register has to point to the 1287 * descriptor after the last valid one and for optimum performance 1288 * should be incremented in multiples of 4 (the DMA engine fetches/ 1289 * updates descriptors in batches of 4). 1290 */ 1291#ifdef GEM_DEBUG 1292 CTR3(KTR_GEM, "%s: %s: kicking TX %d", 1293 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1294#endif 1295 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1296 GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext); 1297} 1298 |
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1266static void 1267gem_start_locked(struct ifnet *ifp) 1268{ 1269 struct gem_softc *sc = ifp->if_softc; 1270 struct mbuf *m; | 1299static void 1300gem_start_locked(struct ifnet *ifp) 1301{ 1302 struct gem_softc *sc = ifp->if_softc; 1303 struct mbuf *m; |
1271 int ntx; | 1304 int kicked, ntx; |
1272 | 1305 |
1306 GEM_LOCK_ASSERT(sc, MA_OWNED); 1307 |
|
1273 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1274 IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) 1275 return; 1276 1277#ifdef GEM_DEBUG 1278 CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d", 1279 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1280 sc->sc_txnext); 1281#endif 1282 ntx = 0; | 1308 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1309 IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) 1310 return; 1311 1312#ifdef GEM_DEBUG 1313 CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d", 1314 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1315 sc->sc_txnext); 1316#endif 1317 ntx = 0; |
1318 kicked = 0; |
|
1283 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1284 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1285 if (m == NULL) 1286 break; 1287 if (gem_load_txmbuf(sc, &m) != 0) { 1288 if (m == NULL) 1289 break; 1290 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1291 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1292 break; 1293 } | 1319 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1320 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1321 if (m == NULL) 1322 break; 1323 if (gem_load_txmbuf(sc, &m) != 0) { 1324 if (m == NULL) 1325 break; 1326 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1327 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1328 break; 1329 } |
1330 if ((sc->sc_txnext % 4) == 0) { 1331 gem_txkick(sc); 1332 kicked = 1; 1333 } else 1334 kicked = 0; |
|
1294 ntx++; | 1335 ntx++; |
1295 /* Kick the transmitter. */ 1296#ifdef GEM_DEBUG 1297 CTR3(KTR_GEM, "%s: %s: kicking TX %d", 1298 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1299#endif 1300 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1301 GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext); 1302 | |
1303 BPF_MTAP(ifp, m); 1304 } 1305 1306 if (ntx > 0) { | 1336 BPF_MTAP(ifp, m); 1337 } 1338 1339 if (ntx > 0) { |
1340 if (kicked == 0) 1341 gem_txkick(sc); |
|
1307#ifdef GEM_DEBUG 1308 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1309 device_get_name(sc->sc_dev), sc->sc_txnext); 1310#endif 1311 1312 /* Set a watchdog timer in case the chip flakes out. */ 1313 sc->sc_wdog_timer = 5; 1314#ifdef GEM_DEBUG --- 4 unchanged lines hidden (view full) --- 1319 } 1320} 1321 1322static void 1323gem_tint(struct gem_softc *sc) 1324{ 1325 struct ifnet *ifp = sc->sc_ifp; 1326 struct gem_txsoft *txs; | 1342#ifdef GEM_DEBUG 1343 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1344 device_get_name(sc->sc_dev), sc->sc_txnext); 1345#endif 1346 1347 /* Set a watchdog timer in case the chip flakes out. */ 1348 sc->sc_wdog_timer = 5; 1349#ifdef GEM_DEBUG --- 4 unchanged lines hidden (view full) --- 1354 } 1355} 1356 1357static void 1358gem_tint(struct gem_softc *sc) 1359{ 1360 struct ifnet *ifp = sc->sc_ifp; 1361 struct gem_txsoft *txs; |
1327 int txlast, progress; | 1362 int progress; 1363 uint32_t txlast; |
1328#ifdef GEM_DEBUG 1329 int i; 1330 | 1364#ifdef GEM_DEBUG 1365 int i; 1366 |
1367 GEM_LOCK_ASSERT(sc, MA_OWNED); 1368 |
|
1331 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1332#endif 1333 1334 /* 1335 * Go through our TX list and free mbufs for those 1336 * frames that have been transmitted. 1337 */ 1338 progress = 0; 1339 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1340 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { | 1369 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1370#endif 1371 1372 /* 1373 * Go through our TX list and free mbufs for those 1374 * frames that have been transmitted. 1375 */ 1376 progress = 0; 1377 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1378 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { |
1341 | |
1342#ifdef GEM_DEBUG 1343 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1344 printf(" txsoft %p transmit chain:\n", txs); 1345 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1346 printf("descriptor %d: ", i); 1347 printf("gd_flags: 0x%016llx\t", 1348 (long long)GEM_DMA_READ(sc, 1349 sc->sc_txdescs[i].gd_flags)); --- 64 unchanged lines hidden (view full) --- 1414 if (sc->sc_txfree == GEM_NTXDESC - 1) 1415 sc->sc_txwin = 0; 1416 1417 /* 1418 * We freed some descriptors, so reset IFF_DRV_OACTIVE 1419 * and restart. 1420 */ 1421 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; | 1379#ifdef GEM_DEBUG 1380 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1381 printf(" txsoft %p transmit chain:\n", txs); 1382 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1383 printf("descriptor %d: ", i); 1384 printf("gd_flags: 0x%016llx\t", 1385 (long long)GEM_DMA_READ(sc, 1386 sc->sc_txdescs[i].gd_flags)); --- 64 unchanged lines hidden (view full) --- 1451 if (sc->sc_txfree == GEM_NTXDESC - 1) 1452 sc->sc_txwin = 0; 1453 1454 /* 1455 * We freed some descriptors, so reset IFF_DRV_OACTIVE 1456 * and restart. 1457 */ 1458 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; |
1422 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1423 | 1459 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1460 sc->sc_wdog_timer = 0; |
1424 gem_start_locked(ifp); 1425 } 1426 1427#ifdef GEM_DEBUG 1428 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1429 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1430#endif 1431} 1432 1433#ifdef GEM_RINT_TIMEOUT 1434static void 1435gem_rint_timeout(void *arg) 1436{ 1437 struct gem_softc *sc = arg; 1438 1439 GEM_LOCK_ASSERT(sc, MA_OWNED); | 1461 gem_start_locked(ifp); 1462 } 1463 1464#ifdef GEM_DEBUG 1465 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1466 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1467#endif 1468} 1469 1470#ifdef GEM_RINT_TIMEOUT 1471static void 1472gem_rint_timeout(void *arg) 1473{ 1474 struct gem_softc *sc = arg; 1475 1476 GEM_LOCK_ASSERT(sc, MA_OWNED); |
1477 |
|
1440 gem_rint(sc); 1441} 1442#endif 1443 1444static void 1445gem_rint(struct gem_softc *sc) 1446{ 1447 struct ifnet *ifp = sc->sc_ifp; 1448 struct mbuf *m; 1449 uint64_t rxstat; 1450 uint32_t rxcomp; 1451 | 1478 gem_rint(sc); 1479} 1480#endif 1481 1482static void 1483gem_rint(struct gem_softc *sc) 1484{ 1485 struct ifnet *ifp = sc->sc_ifp; 1486 struct mbuf *m; 1487 uint64_t rxstat; 1488 uint32_t rxcomp; 1489 |
1490 GEM_LOCK_ASSERT(sc, MA_OWNED); 1491 |
|
1452#ifdef GEM_RINT_TIMEOUT 1453 callout_stop(&sc->sc_rx_ch); 1454#endif 1455#ifdef GEM_DEBUG 1456 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1457#endif 1458 1459 /* 1460 * Read the completion register once. This limits 1461 * how long the following loop can execute. 1462 */ 1463 rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION); | 1492#ifdef GEM_RINT_TIMEOUT 1493 callout_stop(&sc->sc_rx_ch); 1494#endif 1495#ifdef GEM_DEBUG 1496 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1497#endif 1498 1499 /* 1500 * Read the completion register once. This limits 1501 * how long the following loop can execute. 1502 */ 1503 rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION); |
1464 | |
1465#ifdef GEM_DEBUG | 1504#ifdef GEM_DEBUG |
1466 CTR3(KTR_GEM, "%s: sc->rxptr %d, complete %d", | 1505 CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d", |
1467 __func__, sc->sc_rxptr, rxcomp); 1468#endif | 1506 __func__, sc->sc_rxptr, rxcomp); 1507#endif |
1469 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); | 1508 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); |
1470 for (; sc->sc_rxptr != rxcomp;) { 1471 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf; 1472 rxstat = GEM_DMA_READ(sc, 1473 sc->sc_rxdescs[sc->sc_rxptr].gd_flags); 1474 1475 if (rxstat & GEM_RD_OWN) { 1476#ifdef GEM_RINT_TIMEOUT 1477 /* --- 42 unchanged lines hidden (view full) --- 1520 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1521 m = NULL; 1522 } 1523 1524 kickit: 1525 /* 1526 * Update the RX kick register. This register has to point 1527 * to the descriptor after the last valid one (before the | 1509 for (; sc->sc_rxptr != rxcomp;) { 1510 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf; 1511 rxstat = GEM_DMA_READ(sc, 1512 sc->sc_rxdescs[sc->sc_rxptr].gd_flags); 1513 1514 if (rxstat & GEM_RD_OWN) { 1515#ifdef GEM_RINT_TIMEOUT 1516 /* --- 42 unchanged lines hidden (view full) --- 1559 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1560 m = NULL; 1561 } 1562 1563 kickit: 1564 /* 1565 * Update the RX kick register. This register has to point 1566 * to the descriptor after the last valid one (before the |
1528 * current batch) and must be incremented in multiples of 1529 * 4 (because the DMA engine fetches/updates descriptors 1530 * in batches of 4). | 1567 * current batch) and for optimum performance should be 1568 * incremented in multiples of 4 (the DMA engine fetches/ 1569 * updates descriptors in batches of 4). |
1531 */ 1532 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr); 1533 if ((sc->sc_rxptr % 4) == 0) { 1534 GEM_CDSYNC(sc, 1535 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1536 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, 1537 (sc->sc_rxptr + GEM_NRXDESC - 4) & 1538 GEM_NRXDESC_MASK); 1539 } 1540 1541 if (m == NULL) { 1542 if (rxstat & GEM_RD_OWN) 1543 break; 1544 continue; 1545 } 1546 1547 ifp->if_ipackets++; | 1570 */ 1571 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr); 1572 if ((sc->sc_rxptr % 4) == 0) { 1573 GEM_CDSYNC(sc, 1574 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1575 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, 1576 (sc->sc_rxptr + GEM_NRXDESC - 4) & 1577 GEM_NRXDESC_MASK); 1578 } 1579 1580 if (m == NULL) { 1581 if (rxstat & GEM_RD_OWN) 1582 break; 1583 continue; 1584 } 1585 1586 ifp->if_ipackets++; |
1548 m->m_data += 2; /* We're already off by two */ | 1587 m->m_data += ETHER_ALIGN; /* first byte offset */ |
1549 m->m_pkthdr.rcvif = ifp; 1550 m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat); 1551 1552 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1553 gem_rxcksum(m, rxstat); 1554 1555 /* Pass it on. */ 1556 GEM_UNLOCK(sc); 1557 (*ifp->if_input)(ifp, m); 1558 GEM_LOCK(sc); 1559 } 1560 1561#ifdef GEM_DEBUG | 1588 m->m_pkthdr.rcvif = ifp; 1589 m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat); 1590 1591 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1592 gem_rxcksum(m, rxstat); 1593 1594 /* Pass it on. */ 1595 GEM_UNLOCK(sc); 1596 (*ifp->if_input)(ifp, m); 1597 GEM_LOCK(sc); 1598 } 1599 1600#ifdef GEM_DEBUG |
1562 CTR3(KTR_GEM, "%s: done sc->rxptr %d, complete %d", __func__, | 1601 CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__, |
1563 sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION)); 1564#endif 1565} 1566 1567static int 1568gem_add_rxbuf(struct gem_softc *sc, int idx) 1569{ 1570 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1571 struct mbuf *m; 1572 bus_dma_segment_t segs[1]; 1573 int error, nsegs; 1574 | 1602 sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION)); 1603#endif 1604} 1605 1606static int 1607gem_add_rxbuf(struct gem_softc *sc, int idx) 1608{ 1609 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1610 struct mbuf *m; 1611 bus_dma_segment_t segs[1]; 1612 int error, nsegs; 1613 |
1614 GEM_LOCK_ASSERT(sc, MA_OWNED); 1615 |
|
1575 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1576 if (m == NULL) 1577 return (ENOBUFS); 1578 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1579 1580#ifdef GEM_DEBUG 1581 /* Bzero the packet to check DMA. */ 1582 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); --- 32 unchanged lines hidden (view full) --- 1615{ 1616 1617 sc->sc_ifp->if_ierrors++; 1618 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1619 gem_reset_rxdma(sc); 1620 return; 1621 } 1622 | 1616 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1617 if (m == NULL) 1618 return (ENOBUFS); 1619 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1620 1621#ifdef GEM_DEBUG 1622 /* Bzero the packet to check DMA. */ 1623 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); --- 32 unchanged lines hidden (view full) --- 1656{ 1657 1658 sc->sc_ifp->if_ierrors++; 1659 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1660 gem_reset_rxdma(sc); 1661 return; 1662 } 1663 |
1623 device_printf(sc->sc_dev, "%s: status=%x\n", __func__, status); | 1664 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1665 if ((status & GEM_INTR_BERR) != 0) { 1666 if ((sc->sc_flags & GEM_PCI) != 0) 1667 printf(", PCI bus error 0x%x\n", 1668 GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS)); 1669 else 1670 printf(", SBus error 0x%x\n", 1671 GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS)); 1672 } |
1624} 1625 1626void 1627gem_intr(void *v) 1628{ 1629 struct gem_softc *sc = v; 1630 uint32_t status, status2; 1631 1632 GEM_LOCK(sc); 1633 status = GEM_BANK1_READ_4(sc, GEM_STATUS); 1634 1635#ifdef GEM_DEBUG 1636 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", | 1673} 1674 1675void 1676gem_intr(void *v) 1677{ 1678 struct gem_softc *sc = v; 1679 uint32_t status, status2; 1680 1681 GEM_LOCK(sc); 1682 status = GEM_BANK1_READ_4(sc, GEM_STATUS); 1683 1684#ifdef GEM_DEBUG 1685 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", |
1637 device_get_name(sc->sc_dev), __func__, (status >> 19), 1638 (u_int)status); | 1686 device_get_name(sc->sc_dev), __func__, 1687 (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status); |
1639 1640 /* 1641 * PCS interrupts must be cleared, otherwise no traffic is passed! 1642 */ 1643 if ((status & GEM_INTR_PCS) != 0) { 1644 status2 = 1645 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) | 1646 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS); --- 13 unchanged lines hidden (view full) --- 1660 if ((status2 & GEM_MAC_RESUME) != 0) 1661 device_printf(sc->sc_dev, 1662 "%s: transited to non-PAUSE state\n", __func__); 1663 } 1664 if ((status & GEM_INTR_MIF) != 0) 1665 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 1666#endif 1667 | 1688 1689 /* 1690 * PCS interrupts must be cleared, otherwise no traffic is passed! 1691 */ 1692 if ((status & GEM_INTR_PCS) != 0) { 1693 status2 = 1694 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) | 1695 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS); --- 13 unchanged lines hidden (view full) --- 1709 if ((status2 & GEM_MAC_RESUME) != 0) 1710 device_printf(sc->sc_dev, 1711 "%s: transited to non-PAUSE state\n", __func__); 1712 } 1713 if ((status & GEM_INTR_MIF) != 0) 1714 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 1715#endif 1716 |
1668 if ((status & | 1717 if (__predict_false(status & |
1669 (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0) 1670 gem_eint(sc, status); 1671 1672 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1673 gem_rint(sc); 1674 1675 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1676 gem_tint(sc); 1677 | 1718 (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0) 1719 gem_eint(sc, status); 1720 1721 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1722 gem_rint(sc); 1723 1724 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1725 gem_tint(sc); 1726 |
1678 if (status & GEM_INTR_TX_MAC) { | 1727 if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) { |
1679 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS); 1680 if ((status2 & | 1728 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS); 1729 if ((status2 & |
1681 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP)) != 0) | 1730 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 1731 GEM_MAC_TX_PEAK_EXP)) != 0) |
1682 device_printf(sc->sc_dev, 1683 "MAC TX fault, status %x\n", status2); 1684 if ((status2 & | 1732 device_printf(sc->sc_dev, 1733 "MAC TX fault, status %x\n", status2); 1734 if ((status2 & |
1685 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) | 1735 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) { 1736 sc->sc_ifp->if_oerrors++; |
1686 gem_init_locked(sc); | 1737 gem_init_locked(sc); |
1738 } |
|
1687 } | 1739 } |
1688 if (status & GEM_INTR_RX_MAC) { | 1740 if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) { |
1689 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS); 1690 /* 1691 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 1692 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 1693 * silicon bug so handle them silently. Moreover, it's 1694 * likely that the receiver has hung so we reset it. 1695 */ 1696 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { --- 204 unchanged lines hidden (view full) --- 1901gem_mii_statchg(device_t dev) 1902{ 1903 struct gem_softc *sc; 1904 int gigabit; 1905 uint32_t rxcfg, txcfg, v; 1906 1907 sc = device_get_softc(dev); 1908 | 1741 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS); 1742 /* 1743 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 1744 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 1745 * silicon bug so handle them silently. Moreover, it's 1746 * likely that the receiver has hung so we reset it. 1747 */ 1748 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { --- 204 unchanged lines hidden (view full) --- 1953gem_mii_statchg(device_t dev) 1954{ 1955 struct gem_softc *sc; 1956 int gigabit; 1957 uint32_t rxcfg, txcfg, v; 1958 1959 sc = device_get_softc(dev); 1960 |
1961 GEM_LOCK_ASSERT(sc, MA_OWNED); 1962 |
|
1909#ifdef GEM_DEBUG 1910 if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) 1911 device_printf(sc->sc_dev, "%s: status change: PHY = %d\n", 1912 __func__, sc->sc_phyad); 1913#endif 1914 1915 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 1916 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) --- 63 unchanged lines hidden (view full) --- 1980 1981 /* XIF Configuration */ 1982 v = GEM_MAC_XIF_LINK_LED; 1983 v |= GEM_MAC_XIF_TX_MII_ENA; 1984 if ((sc->sc_flags & GEM_SERDES) == 0) { 1985 if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & 1986 GEM_MIF_CONFIG_PHY_SEL) != 0) { 1987 /* External MII needs echo disable if half duplex. */ | 1963#ifdef GEM_DEBUG 1964 if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) 1965 device_printf(sc->sc_dev, "%s: status change: PHY = %d\n", 1966 __func__, sc->sc_phyad); 1967#endif 1968 1969 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 1970 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) --- 63 unchanged lines hidden (view full) --- 2034 2035 /* XIF Configuration */ 2036 v = GEM_MAC_XIF_LINK_LED; 2037 v |= GEM_MAC_XIF_TX_MII_ENA; 2038 if ((sc->sc_flags & GEM_SERDES) == 0) { 2039 if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & 2040 GEM_MIF_CONFIG_PHY_SEL) != 0) { 2041 /* External MII needs echo disable if half duplex. */ |
1988 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & | 2042 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & |
1989 IFM_FDX) == 0) 1990 v |= GEM_MAC_XIF_ECHO_DISABL; 1991 } else 1992 /* 1993 * Internal MII needs buffer enable. 1994 * XXX buffer enable makes only sense for an 1995 * external PHY. 1996 */ --- 51 unchanged lines hidden (view full) --- 2048 struct gem_softc *sc = ifp->if_softc; 2049 struct ifreq *ifr = (struct ifreq *)data; 2050 int error; 2051 2052 error = 0; 2053 switch (cmd) { 2054 case SIOCSIFFLAGS: 2055 GEM_LOCK(sc); | 2043 IFM_FDX) == 0) 2044 v |= GEM_MAC_XIF_ECHO_DISABL; 2045 } else 2046 /* 2047 * Internal MII needs buffer enable. 2048 * XXX buffer enable makes only sense for an 2049 * external PHY. 2050 */ --- 51 unchanged lines hidden (view full) --- 2102 struct gem_softc *sc = ifp->if_softc; 2103 struct ifreq *ifr = (struct ifreq *)data; 2104 int error; 2105 2106 error = 0; 2107 switch (cmd) { 2108 case SIOCSIFFLAGS: 2109 GEM_LOCK(sc); |
2110 if ((sc->sc_flags & GEM_DYING) != 0) { 2111 error = EINVAL; 2112 GEM_UNLOCK(sc); 2113 break; 2114 } |
|
2056 if ((ifp->if_flags & IFF_UP) != 0) { 2057 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2058 ((ifp->if_flags ^ sc->sc_ifflags) & 2059 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2060 gem_setladrf(sc); 2061 else 2062 gem_init_locked(sc); 2063 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) --- 113 unchanged lines hidden --- | 2115 if ((ifp->if_flags & IFF_UP) != 0) { 2116 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2117 ((ifp->if_flags ^ sc->sc_ifflags) & 2118 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2119 gem_setladrf(sc); 2120 else 2121 gem_init_locked(sc); 2122 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) --- 113 unchanged lines hidden --- |