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if_gem.c (176996) if_gem.c (177560)
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 15 unchanged lines hidden (view full) ---

24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
29 */
30
31#include <sys/cdefs.h>
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 15 unchanged lines hidden (view full) ---

24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 176996 2008-03-09 17:55:19Z marius $");
32__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 177560 2008-03-24 17:23:53Z marius $");
33
34/*
35 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers
36 */
37
38#if 0
39#define GEM_DEBUG
40#endif

--- 50 unchanged lines hidden (view full) ---

91 * the hardware doesn't compensate the checksum for UDP datagram which
92 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled
93 * by default. It can be reactivated by setting special link option
94 * link0 with ifconfig(8).
95 */
96#define GEM_CSUM_FEATURES (CSUM_TCP)
97
98static int gem_add_rxbuf(struct gem_softc *sc, int idx);
33
34/*
35 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers
36 */
37
38#if 0
39#define GEM_DEBUG
40#endif

--- 50 unchanged lines hidden (view full) ---

91 * the hardware doesn't compensate the checksum for UDP datagram which
92 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled
93 * by default. It can be reactivated by setting special link option
94 * link0 with ifconfig(8).
95 */
96#define GEM_CSUM_FEATURES (CSUM_TCP)
97
98static int gem_add_rxbuf(struct gem_softc *sc, int idx);
99static int gem_bitwait(struct gem_softc *sc, bus_addr_t r, uint32_t clr,
100 uint32_t set);
99static int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r,
100 uint32_t clr, uint32_t set);
101static void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs,
102 int nsegs, int error);
103static int gem_disable_rx(struct gem_softc *sc);
104static int gem_disable_tx(struct gem_softc *sc);
105static void gem_eint(struct gem_softc *sc, u_int status);
106static void gem_init(void *xsc);
107static void gem_init_locked(struct gem_softc *sc);
108static void gem_init_regs(struct gem_softc *sc);

--- 26 unchanged lines hidden (view full) ---

135DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0);
136MODULE_DEPEND(gem, miibus, 1, 1, 1);
137
138#ifdef GEM_DEBUG
139#include <sys/ktr.h>
140#define KTR_GEM KTR_CT2
141#endif
142
101static void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs,
102 int nsegs, int error);
103static int gem_disable_rx(struct gem_softc *sc);
104static int gem_disable_tx(struct gem_softc *sc);
105static void gem_eint(struct gem_softc *sc, u_int status);
106static void gem_init(void *xsc);
107static void gem_init_locked(struct gem_softc *sc);
108static void gem_init_regs(struct gem_softc *sc);

--- 26 unchanged lines hidden (view full) ---

135DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0);
136MODULE_DEPEND(gem, miibus, 1, 1, 1);
137
138#ifdef GEM_DEBUG
139#include <sys/ktr.h>
140#define KTR_GEM KTR_CT2
141#endif
142
143#define GEM_BANK1_BITWAIT(sc, r, clr, set) \
144 gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set))
145#define GEM_BANK2_BITWAIT(sc, r, clr, set) \
146 gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set))
147
143int
144gem_attach(struct gem_softc *sc)
145{
146 struct gem_txsoft *txs;
147 struct ifnet *ifp;
148 int error, i;
149 uint32_t v;
150

--- 96 unchanged lines hidden (view full) ---

247 i, error);
248 goto fail_rxd;
249 }
250 sc->sc_rxsoft[i].rxs_mbuf = NULL;
251 }
252
253 /* Bad things will happen when touching this register on ERI. */
254 if (sc->sc_variant != GEM_SUN_ERI)
148int
149gem_attach(struct gem_softc *sc)
150{
151 struct gem_txsoft *txs;
152 struct ifnet *ifp;
153 int error, i;
154 uint32_t v;
155

--- 96 unchanged lines hidden (view full) ---

252 i, error);
253 goto fail_rxd;
254 }
255 sc->sc_rxsoft[i].rxs_mbuf = NULL;
256 }
257
258 /* Bad things will happen when touching this register on ERI. */
259 if (sc->sc_variant != GEM_SUN_ERI)
255 bus_write_4(sc->sc_res[0], GEM_MII_DATAPATH_MODE,
260 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE,
256 GEM_MII_DATAPATH_MII);
257
258 gem_mifinit(sc);
259
260 /*
261 * Look for an external PHY.
262 */
263 error = ENXIO;
261 GEM_MII_DATAPATH_MII);
262
263 gem_mifinit(sc);
264
265 /*
266 * Look for an external PHY.
267 */
268 error = ENXIO;
264 v = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
269 v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG);
265 if ((v & GEM_MIF_CONFIG_MDI1) != 0) {
266 v |= GEM_MIF_CONFIG_PHY_SEL;
270 if ((v & GEM_MIF_CONFIG_MDI1) != 0) {
271 v |= GEM_MIF_CONFIG_PHY_SEL;
267 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
272 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v);
268 switch (sc->sc_variant) {
269 case GEM_SUN_ERI:
270 sc->sc_phyad = GEM_PHYAD_EXTERNAL;
271 break;
272 default:
273 sc->sc_phyad = -1;
274 break;
275 }
276 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus,
277 gem_mediachange, gem_mediastatus);
278 }
279
280 /*
281 * Fall back on an internal PHY if no external PHY was found.
282 */
283 if (error != 0 && (v & GEM_MIF_CONFIG_MDI0) != 0) {
284 v &= ~GEM_MIF_CONFIG_PHY_SEL;
273 switch (sc->sc_variant) {
274 case GEM_SUN_ERI:
275 sc->sc_phyad = GEM_PHYAD_EXTERNAL;
276 break;
277 default:
278 sc->sc_phyad = -1;
279 break;
280 }
281 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus,
282 gem_mediachange, gem_mediastatus);
283 }
284
285 /*
286 * Fall back on an internal PHY if no external PHY was found.
287 */
288 if (error != 0 && (v & GEM_MIF_CONFIG_MDI0) != 0) {
289 v &= ~GEM_MIF_CONFIG_PHY_SEL;
285 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
290 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v);
286 switch (sc->sc_variant) {
287 case GEM_SUN_ERI:
288 case GEM_APPLE_K2_GMAC:
289 sc->sc_phyad = GEM_PHYAD_INTERNAL;
290 break;
291 case GEM_APPLE_GMAC:
292 sc->sc_phyad = GEM_PHYAD_EXTERNAL;
293 break;

--- 4 unchanged lines hidden (view full) ---

298 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus,
299 gem_mediachange, gem_mediastatus);
300 }
301
302 /*
303 * Try the external PCS SERDES if we didn't find any PHYs.
304 */
305 if (error != 0 && sc->sc_variant == GEM_SUN_GEM) {
291 switch (sc->sc_variant) {
292 case GEM_SUN_ERI:
293 case GEM_APPLE_K2_GMAC:
294 sc->sc_phyad = GEM_PHYAD_INTERNAL;
295 break;
296 case GEM_APPLE_GMAC:
297 sc->sc_phyad = GEM_PHYAD_EXTERNAL;
298 break;

--- 4 unchanged lines hidden (view full) ---

303 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus,
304 gem_mediachange, gem_mediastatus);
305 }
306
307 /*
308 * Try the external PCS SERDES if we didn't find any PHYs.
309 */
310 if (error != 0 && sc->sc_variant == GEM_SUN_GEM) {
306 bus_write_4(sc->sc_res[0], GEM_MII_DATAPATH_MODE,
311 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE,
307 GEM_MII_DATAPATH_SERDES);
312 GEM_MII_DATAPATH_SERDES);
308 bus_write_4(sc->sc_res[0], GEM_MII_SLINK_CONTROL,
313 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL,
309 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
314 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
310 bus_write_4(sc->sc_res[0], GEM_MII_CONFIG,
311 GEM_MII_CONFIG_ENABLE);
315 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE);
312 sc->sc_flags |= GEM_SERDES;
313 sc->sc_phyad = GEM_PHYAD_EXTERNAL;
314 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus,
315 gem_mediachange, gem_mediastatus);
316 }
317
318 if (error != 0) {
319 device_printf(sc->sc_dev, "PHY probe failed: %d\n", error);

--- 4 unchanged lines hidden (view full) ---

324 /*
325 * From this point forward, the attachment cannot fail. A failure
326 * before this point releases all resources that may have been
327 * allocated.
328 */
329
330 /* Get RX FIFO size. */
331 sc->sc_rxfifosize = 64 *
316 sc->sc_flags |= GEM_SERDES;
317 sc->sc_phyad = GEM_PHYAD_EXTERNAL;
318 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus,
319 gem_mediachange, gem_mediastatus);
320 }
321
322 if (error != 0) {
323 device_printf(sc->sc_dev, "PHY probe failed: %d\n", error);

--- 4 unchanged lines hidden (view full) ---

328 /*
329 * From this point forward, the attachment cannot fail. A failure
330 * before this point releases all resources that may have been
331 * allocated.
332 */
333
334 /* Get RX FIFO size. */
335 sc->sc_rxfifosize = 64 *
332 bus_read_4(sc->sc_res[0], GEM_RX_FIFO_SIZE);
336 GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE);
333
334 /* Get TX FIFO size. */
337
338 /* Get TX FIFO size. */
335 v = bus_read_4(sc->sc_res[0], GEM_TX_FIFO_SIZE);
339 v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE);
336 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
337 sc->sc_rxfifosize / 1024, v / 16);
338
339 sc->sc_csum_features = GEM_CSUM_FEATURES;
340 /* Initialize ifnet structure. */
341 ifp->if_softc = sc;
342 if_initname(ifp, device_get_name(sc->sc_dev),
343 device_get_unit(sc->sc_dev));

--- 243 unchanged lines hidden (view full) ---

587
588 GEM_LOCK_ASSERT(sc, MA_OWNED);
589
590 ifp = sc->sc_ifp;
591 /*
592 * Unload collision counters.
593 */
594 ifp->if_collisions +=
340 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
341 sc->sc_rxfifosize / 1024, v / 16);
342
343 sc->sc_csum_features = GEM_CSUM_FEATURES;
344 /* Initialize ifnet structure. */
345 ifp->if_softc = sc;
346 if_initname(ifp, device_get_name(sc->sc_dev),
347 device_get_unit(sc->sc_dev));

--- 243 unchanged lines hidden (view full) ---

591
592 GEM_LOCK_ASSERT(sc, MA_OWNED);
593
594 ifp = sc->sc_ifp;
595 /*
596 * Unload collision counters.
597 */
598 ifp->if_collisions +=
595 bus_read_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT) +
596 bus_read_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT) +
597 bus_read_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT) +
598 bus_read_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT);
599 GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) +
600 GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT) +
601 GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) +
602 GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT);
599
600 /*
601 * Then clear the hardware counters.
602 */
603
604 /*
605 * Then clear the hardware counters.
606 */
603 bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0);
604 bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0);
605 bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0);
606 bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0);
607 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0);
608 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0);
609 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0);
610 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0);
607
608 mii_tick(sc->sc_mii);
609
610 if (gem_watchdog(sc) == EJUSTRETURN)
611 return;
612
613 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
614}
615
616static int
611
612 mii_tick(sc->sc_mii);
613
614 if (gem_watchdog(sc) == EJUSTRETURN)
615 return;
616
617 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
618}
619
620static int
617gem_bitwait(struct gem_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set)
621gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr,
622 uint32_t set)
618{
619 int i;
620 uint32_t reg;
621
622 for (i = TRIES; i--; DELAY(100)) {
623{
624 int i;
625 uint32_t reg;
626
627 for (i = TRIES; i--; DELAY(100)) {
623 reg = bus_read_4(sc->sc_res[0], r);
628 reg = GEM_BANKN_READ_M(bank, 4, sc, r);
624 if ((reg & clr) == 0 && (reg & set) == set)
625 return (1);
626 }
627 return (0);
628}
629
630static void
631gem_reset(sc)
632 struct gem_softc *sc;
633{
634
635#ifdef GEM_DEBUG
636 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
637#endif
638 gem_reset_rx(sc);
639 gem_reset_tx(sc);
640
641 /* Do a full reset. */
629 if ((reg & clr) == 0 && (reg & set) == set)
630 return (1);
631 }
632 return (0);
633}
634
635static void
636gem_reset(sc)
637 struct gem_softc *sc;
638{
639
640#ifdef GEM_DEBUG
641 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
642#endif
643 gem_reset_rx(sc);
644 gem_reset_tx(sc);
645
646 /* Do a full reset. */
642 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
643 bus_barrier(sc->sc_res[0], GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
644 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
647 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
648 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
649 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
645 device_printf(sc->sc_dev, "cannot reset device\n");
646}
647
648static void
649gem_rxdrain(struct gem_softc *sc)
650{
651 struct gem_rxsoft *rxs;
652 int i;

--- 61 unchanged lines hidden (view full) ---

714gem_reset_rx(struct gem_softc *sc)
715{
716
717 /*
718 * Resetting while DMA is in progress can cause a bus hang, so we
719 * disable DMA first.
720 */
721 gem_disable_rx(sc);
650 device_printf(sc->sc_dev, "cannot reset device\n");
651}
652
653static void
654gem_rxdrain(struct gem_softc *sc)
655{
656 struct gem_rxsoft *rxs;
657 int i;

--- 61 unchanged lines hidden (view full) ---

719gem_reset_rx(struct gem_softc *sc)
720{
721
722 /*
723 * Resetting while DMA is in progress can cause a bus hang, so we
724 * disable DMA first.
725 */
726 gem_disable_rx(sc);
722 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG, 0);
723 bus_barrier(sc->sc_res[0], GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
724 if (!gem_bitwait(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0))
727 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0);
728 GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
729 if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0))
725 device_printf(sc->sc_dev, "cannot disable RX DMA\n");
726
727 /* Finally, reset the ERX. */
730 device_printf(sc->sc_dev, "cannot disable RX DMA\n");
731
732 /* Finally, reset the ERX. */
728 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX);
729 bus_barrier(sc->sc_res[0], GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
730 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) {
733 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX);
734 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
735 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX,
736 0)) {
731 device_printf(sc->sc_dev, "cannot reset receiver\n");
732 return (1);
733 }
734 return (0);
735}
736
737/*
738 * Reset the receiver DMA engine.

--- 12 unchanged lines hidden (view full) ---

751 for (i = 0; i < GEM_NRXDESC; i++)
752 if (sc->sc_rxsoft[i].rxs_mbuf != NULL)
753 GEM_UPDATE_RXDESC(sc, i);
754 sc->sc_rxptr = 0;
755 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
756 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
757
758 /* NOTE: we use only 32-bit DMA addresses here. */
737 device_printf(sc->sc_dev, "cannot reset receiver\n");
738 return (1);
739 }
740 return (0);
741}
742
743/*
744 * Reset the receiver DMA engine.

--- 12 unchanged lines hidden (view full) ---

757 for (i = 0; i < GEM_NRXDESC; i++)
758 if (sc->sc_rxsoft[i].rxs_mbuf != NULL)
759 GEM_UPDATE_RXDESC(sc, i);
760 sc->sc_rxptr = 0;
761 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
762 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
763
764 /* NOTE: we use only 32-bit DMA addresses here. */
759 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_HI, 0);
760 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
761 bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC - 4);
762 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
765 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0);
766 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
767 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4);
768 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
763 gem_ringsize(GEM_NRXDESC /* XXX */) |
764 ((ETHER_HDR_LEN + sizeof(struct ip)) <<
765 GEM_RX_CONFIG_CXM_START_SHFT) |
766 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
767 (2 << GEM_RX_CONFIG_FBOFF_SHFT));
769 gem_ringsize(GEM_NRXDESC /* XXX */) |
770 ((ETHER_HDR_LEN + sizeof(struct ip)) <<
771 GEM_RX_CONFIG_CXM_START_SHFT) |
772 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
773 (2 << GEM_RX_CONFIG_FBOFF_SHFT));
768 bus_write_4(sc->sc_res[0], GEM_RX_BLANKING,
774 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING,
769 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6);
775 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6);
770 bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH,
776 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH,
771 (3 * sc->sc_rxfifosize / 256) |
772 ((sc->sc_rxfifosize / 256) << 12));
777 (3 * sc->sc_rxfifosize / 256) |
778 ((sc->sc_rxfifosize / 256) << 12));
773 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
774 bus_read_4(sc->sc_res[0], GEM_RX_CONFIG) |
775 GEM_RX_CONFIG_RXDMA_EN);
776 bus_write_4(sc->sc_res[0], GEM_MAC_RX_MASK,
779 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
780 GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN);
781 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK,
777 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
782 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
778 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG,
779 bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG) |
780 GEM_MAC_RX_ENABLE);
783 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG,
784 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) | GEM_MAC_RX_ENABLE);
781}
782
783static int
784gem_reset_tx(struct gem_softc *sc)
785{
786
787 /*
788 * Resetting while DMA is in progress can cause a bus hang, so we
789 * disable DMA first.
790 */
791 gem_disable_tx(sc);
785}
786
787static int
788gem_reset_tx(struct gem_softc *sc)
789{
790
791 /*
792 * Resetting while DMA is in progress can cause a bus hang, so we
793 * disable DMA first.
794 */
795 gem_disable_tx(sc);
792 bus_write_4(sc->sc_res[0], GEM_TX_CONFIG, 0);
793 bus_barrier(sc->sc_res[0], GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
794 if (!gem_bitwait(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0))
796 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0);
797 GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
798 if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0))
795 device_printf(sc->sc_dev, "cannot disable TX DMA\n");
796
797 /* Finally, reset the ETX. */
799 device_printf(sc->sc_dev, "cannot disable TX DMA\n");
800
801 /* Finally, reset the ETX. */
798 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_TX);
799 bus_barrier(sc->sc_res[0], GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
800 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) {
802 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX);
803 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
804 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX,
805 0)) {
801 device_printf(sc->sc_dev, "cannot reset transmitter\n");
802 return (1);
803 }
804 return (0);
805}
806
807static int
808gem_disable_rx(struct gem_softc *sc)
809{
806 device_printf(sc->sc_dev, "cannot reset transmitter\n");
807 return (1);
808 }
809 return (0);
810}
811
812static int
813gem_disable_rx(struct gem_softc *sc)
814{
810 uint32_t cfg;
811
815
812 cfg = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
813 cfg &= ~GEM_MAC_RX_ENABLE;
814 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, cfg);
815 bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
816 BUS_SPACE_BARRIER_WRITE);
817 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
816 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG,
817 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE);
818 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
819 return (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE,
820 0));
818}
819
820static int
821gem_disable_tx(struct gem_softc *sc)
822{
821}
822
823static int
824gem_disable_tx(struct gem_softc *sc)
825{
823 uint32_t cfg;
824
826
825 cfg = bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG);
826 cfg &= ~GEM_MAC_TX_ENABLE;
827 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, cfg);
828 bus_barrier(sc->sc_res[0], GEM_MAC_TX_CONFIG, 4,
829 BUS_SPACE_BARRIER_WRITE);
830 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
827 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG,
828 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE);
829 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
830 return (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE,
831 0));
831}
832
833static int
834gem_meminit(sc)
835 struct gem_softc *sc;
836{
837 struct gem_rxsoft *rxs;
838 int error, i;

--- 117 unchanged lines hidden (view full) ---

956 /* step 4. TX MAC registers & counters */
957 gem_init_regs(sc);
958
959 /* step 5. RX MAC registers & counters */
960 gem_setladrf(sc);
961
962 /* step 6 & 7. Program Descriptor Ring Base Addresses. */
963 /* NOTE: we use only 32-bit DMA addresses here. */
832}
833
834static int
835gem_meminit(sc)
836 struct gem_softc *sc;
837{
838 struct gem_rxsoft *rxs;
839 int error, i;

--- 117 unchanged lines hidden (view full) ---

957 /* step 4. TX MAC registers & counters */
958 gem_init_regs(sc);
959
960 /* step 5. RX MAC registers & counters */
961 gem_setladrf(sc);
962
963 /* step 6 & 7. Program Descriptor Ring Base Addresses. */
964 /* NOTE: we use only 32-bit DMA addresses here. */
964 bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_HI, 0);
965 bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
965 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0);
966 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
966
967
967 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_HI, 0);
968 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
968 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0);
969 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
969#ifdef GEM_DEBUG
970 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx",
971 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
972#endif
973
974 /* step 8. Global Configuration & Interrupt Mask */
970#ifdef GEM_DEBUG
971 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx",
972 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
973#endif
974
975 /* step 8. Global Configuration & Interrupt Mask */
975 bus_write_4(sc->sc_res[0], GEM_INTMASK,
976 GEM_BANK1_WRITE_4(sc, GEM_INTMASK,
976 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE |
977 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR |
978 GEM_INTR_BERR
979#ifdef GEM_DEBUG
980 | GEM_INTR_PCS | GEM_INTR_MIF
981#endif
982 ));
977 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE |
978 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR |
979 GEM_INTR_BERR
980#ifdef GEM_DEBUG
981 | GEM_INTR_PCS | GEM_INTR_MIF
982#endif
983 ));
983 bus_write_4(sc->sc_res[0], GEM_MAC_RX_MASK,
984 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK,
984 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
985 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
985 bus_write_4(sc->sc_res[0], GEM_MAC_TX_MASK,
986 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK,
986 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP);
987#ifdef GEM_DEBUG
987 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP);
988#ifdef GEM_DEBUG
988 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_MASK,
989 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK,
989 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME));
990#else
990 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME));
991#else
991 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_MASK,
992 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK,
992 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME);
993#endif
994
995 /* step 9. ETX Configuration: use mostly default values. */
996
997 /* Enable DMA. */
998 v = gem_ringsize(GEM_NTXDESC /* XXX */);
993 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME);
994#endif
995
996 /* step 9. ETX Configuration: use mostly default values. */
997
998 /* Enable DMA. */
999 v = gem_ringsize(GEM_NTXDESC /* XXX */);
999 bus_write_4(sc->sc_res[0], GEM_TX_CONFIG,
1000 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG,
1000 v | GEM_TX_CONFIG_TXDMA_EN |
1001 ((0x400 << 10) & GEM_TX_CONFIG_TXFIFO_TH));
1002
1003 /* step 10. ERX Configuration */
1004
1005 /* Encode Receive Descriptor ring size. */
1006 v = gem_ringsize(GEM_NRXDESC /* XXX */);
1007 /* RX TCP/UDP checksum offset */
1008 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) <<
1009 GEM_RX_CONFIG_CXM_START_SHFT);
1010
1011 /* Enable DMA. */
1001 v | GEM_TX_CONFIG_TXDMA_EN |
1002 ((0x400 << 10) & GEM_TX_CONFIG_TXFIFO_TH));
1003
1004 /* step 10. ERX Configuration */
1005
1006 /* Encode Receive Descriptor ring size. */
1007 v = gem_ringsize(GEM_NRXDESC /* XXX */);
1008 /* RX TCP/UDP checksum offset */
1009 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) <<
1010 GEM_RX_CONFIG_CXM_START_SHFT);
1011
1012 /* Enable DMA. */
1012 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
1013 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
1013 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
1014 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN);
1015
1014 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
1015 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN);
1016
1016 bus_write_4(sc->sc_res[0], GEM_RX_BLANKING,
1017 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING,
1017 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6);
1018
1019 /*
1020 * The following value is for an OFF Threshold of about 3/4 full
1021 * and an ON Threshold of 1/4 full.
1022 */
1018 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6);
1019
1020 /*
1021 * The following value is for an OFF Threshold of about 3/4 full
1022 * and an ON Threshold of 1/4 full.
1023 */
1023 bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH,
1024 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH,
1024 (3 * sc->sc_rxfifosize / 256) |
1025 ((sc->sc_rxfifosize / 256) << 12));
1026
1027 /* step 11. Configure Media. */
1028
1029 /* step 12. RX_MAC Configuration Register */
1025 (3 * sc->sc_rxfifosize / 256) |
1026 ((sc->sc_rxfifosize / 256) << 12));
1027
1028 /* step 11. Configure Media. */
1029
1030 /* step 12. RX_MAC Configuration Register */
1030 v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
1031 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG);
1031 v |= GEM_MAC_RX_STRIP_CRC;
1032 v |= GEM_MAC_RX_STRIP_CRC;
1032 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, 0);
1033 bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
1034 BUS_SPACE_BARRIER_WRITE);
1035 if (!gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
1033 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0);
1034 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
1035 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
1036 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
1036 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
1037 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
1037 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v);
1038
1039 /* step 14. Issue Transmit Pending command. */
1040
1041 /* step 15. Give the reciever a swift kick. */
1038
1039 /* step 14. Issue Transmit Pending command. */
1040
1041 /* step 15. Give the reciever a swift kick. */
1042 bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC - 4);
1042 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4);
1043
1044 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1045 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1046 sc->sc_ifflags = ifp->if_flags;
1047
1048 sc->sc_flags &= ~GEM_LINK;
1049 mii_mediachg(sc->sc_mii);
1050

--- 127 unchanged lines hidden (view full) ---

1178static void
1179gem_init_regs(struct gem_softc *sc)
1180{
1181 const u_char *laddr = IF_LLADDR(sc->sc_ifp);
1182
1183 /* These registers are not cleared on reset. */
1184 if ((sc->sc_flags & GEM_INITED) == 0) {
1185 /* magic values */
1043
1044 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1045 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1046 sc->sc_ifflags = ifp->if_flags;
1047
1048 sc->sc_flags &= ~GEM_LINK;
1049 mii_mediachg(sc->sc_mii);
1050

--- 127 unchanged lines hidden (view full) ---

1178static void
1179gem_init_regs(struct gem_softc *sc)
1180{
1181 const u_char *laddr = IF_LLADDR(sc->sc_ifp);
1182
1183 /* These registers are not cleared on reset. */
1184 if ((sc->sc_flags & GEM_INITED) == 0) {
1185 /* magic values */
1186 bus_write_4(sc->sc_res[0], GEM_MAC_IPG0, 0);
1187 bus_write_4(sc->sc_res[0], GEM_MAC_IPG1, 8);
1188 bus_write_4(sc->sc_res[0], GEM_MAC_IPG2, 4);
1186 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0);
1187 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8);
1188 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4);
1189
1189
1190 bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MIN_FRAME,
1191 ETHER_MIN_LEN);
1190 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1192 /* max frame and max burst size */
1191 /* max frame and max burst size */
1193 bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MAX_FRAME,
1192 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME,
1194 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16));
1195
1193 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16));
1194
1196 bus_write_4(sc->sc_res[0], GEM_MAC_PREAMBLE_LEN, 0x7);
1197 bus_write_4(sc->sc_res[0], GEM_MAC_JAM_SIZE, 0x4);
1198 bus_write_4(sc->sc_res[0], GEM_MAC_ATTEMPT_LIMIT, 0x10);
1195 GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7);
1196 GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4);
1197 GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10);
1199 /* dunno... */
1198 /* dunno... */
1200 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_TYPE, 0x8088);
1201 bus_write_4(sc->sc_res[0], GEM_MAC_RANDOM_SEED,
1199 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8088);
1200 GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED,
1202 ((laddr[5] << 8) | laddr[4]) & 0x3ff);
1203
1204 /* secondary MAC address: 0:0:0:0:0:0 */
1201 ((laddr[5] << 8) | laddr[4]) & 0x3ff);
1202
1203 /* secondary MAC address: 0:0:0:0:0:0 */
1205 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR3, 0);
1206 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR4, 0);
1207 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR5, 0);
1204 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0);
1205 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0);
1206 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0);
1208
1209 /* MAC control address: 01:80:c2:00:00:01 */
1207
1208 /* MAC control address: 01:80:c2:00:00:01 */
1210 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR6, 0x0001);
1211 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR7, 0xc200);
1212 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR8, 0x0180);
1209 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001);
1210 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200);
1211 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180);
1213
1214 /* MAC filter address: 0:0:0:0:0:0 */
1212
1213 /* MAC filter address: 0:0:0:0:0:0 */
1215 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER0, 0);
1216 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER1, 0);
1217 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER2, 0);
1214 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0);
1215 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0);
1216 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0);
1218
1217
1219 bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK1_2, 0);
1220 bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK0, 0);
1218 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0);
1219 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0);
1221
1222 sc->sc_flags |= GEM_INITED;
1223 }
1224
1225 /* Counters need to be zeroed. */
1220
1221 sc->sc_flags |= GEM_INITED;
1222 }
1223
1224 /* Counters need to be zeroed. */
1226 bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0);
1227 bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0);
1228 bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0);
1229 bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0);
1230 bus_write_4(sc->sc_res[0], GEM_MAC_DEFER_TMR_CNT, 0);
1231 bus_write_4(sc->sc_res[0], GEM_MAC_PEAK_ATTEMPTS, 0);
1232 bus_write_4(sc->sc_res[0], GEM_MAC_RX_FRAME_COUNT, 0);
1233 bus_write_4(sc->sc_res[0], GEM_MAC_RX_LEN_ERR_CNT, 0);
1234 bus_write_4(sc->sc_res[0], GEM_MAC_RX_ALIGN_ERR, 0);
1235 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CRC_ERR_CNT, 0);
1236 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CODE_VIOL, 0);
1225 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0);
1226 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0);
1227 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0);
1228 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0);
1229 GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0);
1230 GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0);
1231 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0);
1232 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0);
1233 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0);
1234 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0);
1235 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0);
1237
1238 /* Set XOFF PAUSE time. */
1236
1237 /* Set XOFF PAUSE time. */
1239 bus_write_4(sc->sc_res[0], GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1238 GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1240
1241 /*
1242 * Set the internal arbitration to "infinite" bursts of the
1243 * maximum length of 31 * 64 bytes so DMA transfers aren't
1244 * split up in cache line size chunks. This greatly improves
1245 * especially RX performance.
1246 * Enable silicon bug workarounds for the Apple variants.
1247 */
1239
1240 /*
1241 * Set the internal arbitration to "infinite" bursts of the
1242 * maximum length of 31 * 64 bytes so DMA transfers aren't
1243 * split up in cache line size chunks. This greatly improves
1244 * especially RX performance.
1245 * Enable silicon bug workarounds for the Apple variants.
1246 */
1248 bus_write_4(sc->sc_res[0], GEM_CONFIG,
1247 GEM_BANK1_WRITE_4(sc, GEM_CONFIG,
1249 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT |
1250 GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ?
1251 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0));
1252
1253 /* Set the station address. */
1248 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT |
1249 GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ?
1250 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0));
1251
1252 /* Set the station address. */
1254 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR0,
1255 (laddr[4] << 8) | laddr[5]);
1256 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR1,
1257 (laddr[2] << 8) | laddr[3]);
1258 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR2,
1259 (laddr[0] << 8) | laddr[1]);
1253 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
1254 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
1255 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
1260
1261 /* Enable MII outputs. */
1256
1257 /* Enable MII outputs. */
1262 bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG,
1263 GEM_MAC_XIF_TX_MII_ENA);
1258 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA);
1264}
1265
1266static void
1267gem_start(struct ifnet *ifp)
1268{
1269 struct gem_softc *sc = ifp->if_softc;
1270
1271 GEM_LOCK(sc);

--- 31 unchanged lines hidden (view full) ---

1303 }
1304 ntx++;
1305 /* Kick the transmitter. */
1306#ifdef GEM_DEBUG
1307 CTR3(KTR_GEM, "%s: %s: kicking TX %d",
1308 device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
1309#endif
1310 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1259}
1260
1261static void
1262gem_start(struct ifnet *ifp)
1263{
1264 struct gem_softc *sc = ifp->if_softc;
1265
1266 GEM_LOCK(sc);

--- 31 unchanged lines hidden (view full) ---

1298 }
1299 ntx++;
1300 /* Kick the transmitter. */
1301#ifdef GEM_DEBUG
1302 CTR3(KTR_GEM, "%s: %s: kicking TX %d",
1303 device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
1304#endif
1305 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1311 bus_write_4(sc->sc_res[0], GEM_TX_KICK, sc->sc_txnext);
1306 GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext);
1312
1313 BPF_MTAP(ifp, m);
1314 }
1315
1316 if (ntx > 0) {
1317#ifdef GEM_DEBUG
1318 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
1319 device_get_name(sc->sc_dev), sc->sc_txnext);

--- 48 unchanged lines hidden (view full) ---

1368
1369 /*
1370 * In theory, we could harvest some descriptors before
1371 * the ring is empty, but that's a bit complicated.
1372 *
1373 * GEM_TX_COMPLETION points to the last descriptor
1374 * processed + 1.
1375 */
1307
1308 BPF_MTAP(ifp, m);
1309 }
1310
1311 if (ntx > 0) {
1312#ifdef GEM_DEBUG
1313 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
1314 device_get_name(sc->sc_dev), sc->sc_txnext);

--- 48 unchanged lines hidden (view full) ---

1363
1364 /*
1365 * In theory, we could harvest some descriptors before
1366 * the ring is empty, but that's a bit complicated.
1367 *
1368 * GEM_TX_COMPLETION points to the last descriptor
1369 * processed + 1.
1370 */
1376 txlast = bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION);
1371 txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION);
1377#ifdef GEM_DEBUG
1378 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, "
1379 "txs->txs_lastdesc = %d, txlast = %d",
1380 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1381#endif
1382 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1383 if ((txlast >= txs->txs_firstdesc) &&
1384 (txlast <= txs->txs_lastdesc))

--- 24 unchanged lines hidden (view full) ---

1409
1410 ifp->if_opackets++;
1411 progress = 1;
1412 }
1413
1414#ifdef GEM_DEBUG
1415 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx "
1416 "GEM_TX_COMPLETION %x",
1372#ifdef GEM_DEBUG
1373 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, "
1374 "txs->txs_lastdesc = %d, txlast = %d",
1375 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1376#endif
1377 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1378 if ((txlast >= txs->txs_firstdesc) &&
1379 (txlast <= txs->txs_lastdesc))

--- 24 unchanged lines hidden (view full) ---

1404
1405 ifp->if_opackets++;
1406 progress = 1;
1407 }
1408
1409#ifdef GEM_DEBUG
1410 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx "
1411 "GEM_TX_COMPLETION %x",
1417 __func__, bus_read_4(sc->sc_res[0], GEM_TX_STATE_MACHINE),
1418 ((long long)bus_read_4(sc->sc_res[0],
1419 GEM_TX_DATA_PTR_HI) << 32) |
1420 bus_read_4(sc->sc_res[0], GEM_TX_DATA_PTR_LO),
1421 bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION));
1412 __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE),
1413 ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) |
1414 GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO),
1415 GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION));
1422#endif
1423
1424 if (progress) {
1425 if (sc->sc_txfree == GEM_NTXDESC - 1)
1426 sc->sc_txwin = 0;
1427
1428 /*
1429 * We freed some descriptors, so reset IFF_DRV_OACTIVE

--- 38 unchanged lines hidden (view full) ---

1468#ifdef GEM_DEBUG
1469 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
1470#endif
1471
1472 /*
1473 * Read the completion register once. This limits
1474 * how long the following loop can execute.
1475 */
1416#endif
1417
1418 if (progress) {
1419 if (sc->sc_txfree == GEM_NTXDESC - 1)
1420 sc->sc_txwin = 0;
1421
1422 /*
1423 * We freed some descriptors, so reset IFF_DRV_OACTIVE

--- 38 unchanged lines hidden (view full) ---

1462#ifdef GEM_DEBUG
1463 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
1464#endif
1465
1466 /*
1467 * Read the completion register once. This limits
1468 * how long the following loop can execute.
1469 */
1476 rxcomp = bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION);
1470 rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION);
1477
1478#ifdef GEM_DEBUG
1479 CTR3(KTR_GEM, "%s: sc->rxptr %d, complete %d",
1480 __func__, sc->sc_rxptr, rxcomp);
1481#endif
1482 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1483 for (; sc->sc_rxptr != rxcomp;) {
1484 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf;

--- 55 unchanged lines hidden (view full) ---

1540 * to the descriptor after the last valid one (before the
1541 * current batch) and must be incremented in multiples of
1542 * 4 (because the DMA engine fetches/updates descriptors
1543 * in batches of 4).
1544 */
1545 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr);
1546 if ((sc->sc_rxptr % 4) == 0) {
1547 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1471
1472#ifdef GEM_DEBUG
1473 CTR3(KTR_GEM, "%s: sc->rxptr %d, complete %d",
1474 __func__, sc->sc_rxptr, rxcomp);
1475#endif
1476 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1477 for (; sc->sc_rxptr != rxcomp;) {
1478 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf;

--- 55 unchanged lines hidden (view full) ---

1534 * to the descriptor after the last valid one (before the
1535 * current batch) and must be incremented in multiples of
1536 * 4 (because the DMA engine fetches/updates descriptors
1537 * in batches of 4).
1538 */
1539 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr);
1540 if ((sc->sc_rxptr % 4) == 0) {
1541 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1548 bus_write_4(sc->sc_res[0], GEM_RX_KICK,
1542 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK,
1549 (sc->sc_rxptr + GEM_NRXDESC - 4) &
1550 GEM_NRXDESC_MASK);
1551 }
1552
1553 if (m == NULL) {
1554 if (rxstat & GEM_RD_OWN)
1555 break;
1556 continue;

--- 10 unchanged lines hidden (view full) ---

1567 /* Pass it on. */
1568 GEM_UNLOCK(sc);
1569 (*ifp->if_input)(ifp, m);
1570 GEM_LOCK(sc);
1571 }
1572
1573#ifdef GEM_DEBUG
1574 CTR3(KTR_GEM, "%s: done sc->rxptr %d, complete %d", __func__,
1543 (sc->sc_rxptr + GEM_NRXDESC - 4) &
1544 GEM_NRXDESC_MASK);
1545 }
1546
1547 if (m == NULL) {
1548 if (rxstat & GEM_RD_OWN)
1549 break;
1550 continue;

--- 10 unchanged lines hidden (view full) ---

1561 /* Pass it on. */
1562 GEM_UNLOCK(sc);
1563 (*ifp->if_input)(ifp, m);
1564 GEM_LOCK(sc);
1565 }
1566
1567#ifdef GEM_DEBUG
1568 CTR3(KTR_GEM, "%s: done sc->rxptr %d, complete %d", __func__,
1575 sc->sc_rxptr, bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION));
1569 sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION));
1576#endif
1577}
1578
1579static int
1580gem_add_rxbuf(struct gem_softc *sc, int idx)
1581{
1582 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
1583 struct mbuf *m;

--- 53 unchanged lines hidden (view full) ---

1637
1638void
1639gem_intr(void *v)
1640{
1641 struct gem_softc *sc = v;
1642 uint32_t status, status2;
1643
1644 GEM_LOCK(sc);
1570#endif
1571}
1572
1573static int
1574gem_add_rxbuf(struct gem_softc *sc, int idx)
1575{
1576 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
1577 struct mbuf *m;

--- 53 unchanged lines hidden (view full) ---

1631
1632void
1633gem_intr(void *v)
1634{
1635 struct gem_softc *sc = v;
1636 uint32_t status, status2;
1637
1638 GEM_LOCK(sc);
1645 status = bus_read_4(sc->sc_res[0], GEM_STATUS);
1639 status = GEM_BANK1_READ_4(sc, GEM_STATUS);
1646
1647#ifdef GEM_DEBUG
1648 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x",
1649 device_get_name(sc->sc_dev), __func__, (status >> 19),
1650 (u_int)status);
1651
1652 /*
1653 * PCS interrupts must be cleared, otherwise no traffic is passed!
1654 */
1655 if ((status & GEM_INTR_PCS) != 0) {
1656 status2 =
1640
1641#ifdef GEM_DEBUG
1642 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x",
1643 device_get_name(sc->sc_dev), __func__, (status >> 19),
1644 (u_int)status);
1645
1646 /*
1647 * PCS interrupts must be cleared, otherwise no traffic is passed!
1648 */
1649 if ((status & GEM_INTR_PCS) != 0) {
1650 status2 =
1657 bus_read_4(sc->sc_res[0], GEM_MII_INTERRUP_STATUS) |
1658 bus_read_4(sc->sc_res[0], GEM_MII_INTERRUP_STATUS);
1651 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) |
1652 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS);
1659 if ((status2 & GEM_MII_INTERRUP_LINK) != 0)
1660 device_printf(sc->sc_dev,
1661 "%s: PCS link status changed\n", __func__);
1662 }
1663 if ((status & GEM_MAC_CONTROL_STATUS) != 0) {
1653 if ((status2 & GEM_MII_INTERRUP_LINK) != 0)
1654 device_printf(sc->sc_dev,
1655 "%s: PCS link status changed\n", __func__);
1656 }
1657 if ((status & GEM_MAC_CONTROL_STATUS) != 0) {
1664 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS);
1658 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS);
1665 if ((status2 & GEM_MAC_PAUSED) != 0)
1666 device_printf(sc->sc_dev,
1667 "%s: PAUSE received (PAUSE time %d slots)\n",
1668 __func__, GEM_MAC_PAUSE_TIME(status2));
1669 if ((status2 & GEM_MAC_PAUSE) != 0)
1670 device_printf(sc->sc_dev,
1671 "%s: transited to PAUSE state\n", __func__);
1672 if ((status2 & GEM_MAC_RESUME) != 0)

--- 10 unchanged lines hidden (view full) ---

1683
1684 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1685 gem_rint(sc);
1686
1687 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1688 gem_tint(sc);
1689
1690 if (status & GEM_INTR_TX_MAC) {
1659 if ((status2 & GEM_MAC_PAUSED) != 0)
1660 device_printf(sc->sc_dev,
1661 "%s: PAUSE received (PAUSE time %d slots)\n",
1662 __func__, GEM_MAC_PAUSE_TIME(status2));
1663 if ((status2 & GEM_MAC_PAUSE) != 0)
1664 device_printf(sc->sc_dev,
1665 "%s: transited to PAUSE state\n", __func__);
1666 if ((status2 & GEM_MAC_RESUME) != 0)

--- 10 unchanged lines hidden (view full) ---

1677
1678 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1679 gem_rint(sc);
1680
1681 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1682 gem_tint(sc);
1683
1684 if (status & GEM_INTR_TX_MAC) {
1691 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS);
1685 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS);
1692 if ((status2 &
1693 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP)) != 0)
1694 device_printf(sc->sc_dev,
1695 "MAC TX fault, status %x\n", status2);
1696 if ((status2 &
1697 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0)
1698 gem_init_locked(sc);
1699 }
1700 if (status & GEM_INTR_RX_MAC) {
1686 if ((status2 &
1687 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP)) != 0)
1688 device_printf(sc->sc_dev,
1689 "MAC TX fault, status %x\n", status2);
1690 if ((status2 &
1691 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0)
1692 gem_init_locked(sc);
1693 }
1694 if (status & GEM_INTR_RX_MAC) {
1701 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS);
1695 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS);
1702 /*
1703 * At least with GEM_SUN_GEM and some GEM_SUN_ERI
1704 * revisions GEM_MAC_RX_OVERFLOW happen often due to a
1705 * silicon bug so handle them silently. Moreover, it's
1706 * likely that the receiver has hung so we reset it.
1707 */
1708 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) {
1709 sc->sc_ifp->if_ierrors++;

--- 10 unchanged lines hidden (view full) ---

1720gem_watchdog(struct gem_softc *sc)
1721{
1722
1723 GEM_LOCK_ASSERT(sc, MA_OWNED);
1724
1725#ifdef GEM_DEBUG
1726 CTR4(KTR_GEM,
1727 "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x",
1696 /*
1697 * At least with GEM_SUN_GEM and some GEM_SUN_ERI
1698 * revisions GEM_MAC_RX_OVERFLOW happen often due to a
1699 * silicon bug so handle them silently. Moreover, it's
1700 * likely that the receiver has hung so we reset it.
1701 */
1702 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) {
1703 sc->sc_ifp->if_ierrors++;

--- 10 unchanged lines hidden (view full) ---

1714gem_watchdog(struct gem_softc *sc)
1715{
1716
1717 GEM_LOCK_ASSERT(sc, MA_OWNED);
1718
1719#ifdef GEM_DEBUG
1720 CTR4(KTR_GEM,
1721 "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x",
1728 __func__, bus_read_4(sc->sc_res[0], GEM_RX_CONFIG),
1729 bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS),
1730 bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG));
1722 __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG),
1723 GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS),
1724 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG));
1731 CTR4(KTR_GEM,
1732 "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x",
1725 CTR4(KTR_GEM,
1726 "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x",
1733 __func__, bus_read_4(sc->sc_res[0], GEM_TX_CONFIG),
1734 bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS),
1735 bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG));
1727 __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG),
1728 GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS),
1729 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG));
1736#endif
1737
1738 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
1739 return (0);
1740
1741 if ((sc->sc_flags & GEM_LINK) != 0)
1742 device_printf(sc->sc_dev, "device timeout\n");
1743 else if (bootverbose)

--- 5 unchanged lines hidden (view full) ---

1749 return (EJUSTRETURN);
1750}
1751
1752static void
1753gem_mifinit(struct gem_softc *sc)
1754{
1755
1756 /* Configure the MIF in frame mode. */
1730#endif
1731
1732 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
1733 return (0);
1734
1735 if ((sc->sc_flags & GEM_LINK) != 0)
1736 device_printf(sc->sc_dev, "device timeout\n");
1737 else if (bootverbose)

--- 5 unchanged lines hidden (view full) ---

1743 return (EJUSTRETURN);
1744}
1745
1746static void
1747gem_mifinit(struct gem_softc *sc)
1748{
1749
1750 /* Configure the MIF in frame mode. */
1757 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, bus_read_4(sc->sc_res[0],
1758 GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA);
1751 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG,
1752 GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA);
1759}
1760
1761/*
1762 * MII interface
1763 *
1764 * The GEM MII interface supports at least three different operating modes:
1765 *
1766 * Bitbang mode is implemented using data, clock and output enable registers.

--- 39 unchanged lines hidden (view full) ---

1806 break;
1807 case MII_EXTSR:
1808 return (EXTSR_1000XFDX | EXTSR_1000XHDX);
1809 default:
1810 device_printf(sc->sc_dev,
1811 "%s: unhandled register %d\n", __func__, reg);
1812 return (0);
1813 }
1753}
1754
1755/*
1756 * MII interface
1757 *
1758 * The GEM MII interface supports at least three different operating modes:
1759 *
1760 * Bitbang mode is implemented using data, clock and output enable registers.

--- 39 unchanged lines hidden (view full) ---

1800 break;
1801 case MII_EXTSR:
1802 return (EXTSR_1000XFDX | EXTSR_1000XHDX);
1803 default:
1804 device_printf(sc->sc_dev,
1805 "%s: unhandled register %d\n", __func__, reg);
1806 return (0);
1807 }
1814 return (bus_read_4(sc->sc_res[0], reg));
1808 return (GEM_BANK1_READ_4(sc, reg));
1815 }
1816
1817 /* Construct the frame command. */
1818 v = GEM_MIF_FRAME_READ |
1819 (phy << GEM_MIF_PHY_SHIFT) |
1820 (reg << GEM_MIF_REG_SHIFT);
1821
1809 }
1810
1811 /* Construct the frame command. */
1812 v = GEM_MIF_FRAME_READ |
1813 (phy << GEM_MIF_PHY_SHIFT) |
1814 (reg << GEM_MIF_REG_SHIFT);
1815
1822 bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
1816 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v);
1823 for (n = 0; n < 100; n++) {
1824 DELAY(1);
1817 for (n = 0; n < 100; n++) {
1818 DELAY(1);
1825 v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
1819 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME);
1826 if (v & GEM_MIF_FRAME_TA0)
1827 return (v & GEM_MIF_FRAME_DATA);
1828 }
1829
1830 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
1831 return (0);
1832}
1833

--- 16 unchanged lines hidden (view full) ---

1850 switch (reg) {
1851 case MII_BMCR:
1852 reg = GEM_MII_CONTROL;
1853 break;
1854 case MII_BMSR:
1855 reg = GEM_MII_STATUS;
1856 break;
1857 case MII_ANAR:
1820 if (v & GEM_MIF_FRAME_TA0)
1821 return (v & GEM_MIF_FRAME_DATA);
1822 }
1823
1824 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
1825 return (0);
1826}
1827

--- 16 unchanged lines hidden (view full) ---

1844 switch (reg) {
1845 case MII_BMCR:
1846 reg = GEM_MII_CONTROL;
1847 break;
1848 case MII_BMSR:
1849 reg = GEM_MII_STATUS;
1850 break;
1851 case MII_ANAR:
1858 bus_write_4(sc->sc_res[0], GEM_MII_CONFIG, 0);
1859 bus_barrier(sc->sc_res[0], GEM_MII_CONFIG, 4,
1852 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0);
1853 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4,
1860 BUS_SPACE_BARRIER_WRITE);
1854 BUS_SPACE_BARRIER_WRITE);
1861 bus_write_4(sc->sc_res[0], GEM_MII_ANAR, val);
1862 bus_write_4(sc->sc_res[0], GEM_MII_SLINK_CONTROL,
1855 GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val);
1856 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL,
1863 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
1857 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
1864 bus_write_4(sc->sc_res[0], GEM_MII_CONFIG,
1858 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG,
1865 GEM_MII_CONFIG_ENABLE);
1866 return (0);
1867 case MII_ANLPAR:
1868 reg = GEM_MII_ANLPAR;
1869 break;
1870 default:
1871 device_printf(sc->sc_dev,
1872 "%s: unhandled register %d\n", __func__, reg);
1873 return (0);
1874 }
1859 GEM_MII_CONFIG_ENABLE);
1860 return (0);
1861 case MII_ANLPAR:
1862 reg = GEM_MII_ANLPAR;
1863 break;
1864 default:
1865 device_printf(sc->sc_dev,
1866 "%s: unhandled register %d\n", __func__, reg);
1867 return (0);
1868 }
1875 bus_write_4(sc->sc_res[0], reg, val);
1869 GEM_BANK1_WRITE_4(sc, reg, val);
1876 return (0);
1877 }
1878
1879 /* Construct the frame command. */
1880 v = GEM_MIF_FRAME_WRITE |
1881 (phy << GEM_MIF_PHY_SHIFT) |
1882 (reg << GEM_MIF_REG_SHIFT) |
1883 (val & GEM_MIF_FRAME_DATA);
1884
1870 return (0);
1871 }
1872
1873 /* Construct the frame command. */
1874 v = GEM_MIF_FRAME_WRITE |
1875 (phy << GEM_MIF_PHY_SHIFT) |
1876 (reg << GEM_MIF_REG_SHIFT) |
1877 (val & GEM_MIF_FRAME_DATA);
1878
1885 bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
1879 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v);
1886 for (n = 0; n < 100; n++) {
1887 DELAY(1);
1880 for (n = 0; n < 100; n++) {
1881 DELAY(1);
1888 v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
1882 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME);
1889 if (v & GEM_MIF_FRAME_TA0)
1890 return (1);
1891 }
1892
1893 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
1894 return (0);
1895}
1896

--- 31 unchanged lines hidden (view full) ---

1928
1929 /*
1930 * The configuration done here corresponds to the steps F) and
1931 * G) and as far as enabling of RX and TX MAC goes also step H)
1932 * of the initialization sequence outlined in section 3.2.1 of
1933 * the GEM Gigabit Ethernet ASIC Specification.
1934 */
1935
1883 if (v & GEM_MIF_FRAME_TA0)
1884 return (1);
1885 }
1886
1887 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
1888 return (0);
1889}
1890

--- 31 unchanged lines hidden (view full) ---

1922
1923 /*
1924 * The configuration done here corresponds to the steps F) and
1925 * G) and as far as enabling of RX and TX MAC goes also step H)
1926 * of the initialization sequence outlined in section 3.2.1 of
1927 * the GEM Gigabit Ethernet ASIC Specification.
1928 */
1929
1936 rxcfg = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
1930 rxcfg = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG);
1937 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE);
1938 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT;
1939 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
1940 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS;
1941 else if (gigabit != 0) {
1942 rxcfg |= GEM_MAC_RX_CARR_EXTEND;
1943 txcfg |= GEM_MAC_TX_CARR_EXTEND;
1944 }
1931 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE);
1932 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT;
1933 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
1934 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS;
1935 else if (gigabit != 0) {
1936 rxcfg |= GEM_MAC_RX_CARR_EXTEND;
1937 txcfg |= GEM_MAC_TX_CARR_EXTEND;
1938 }
1945 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, 0);
1946 bus_barrier(sc->sc_res[0], GEM_MAC_TX_CONFIG, 4,
1947 BUS_SPACE_BARRIER_WRITE);
1948 if (!gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0))
1939 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0);
1940 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
1941 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0))
1949 device_printf(sc->sc_dev, "cannot disable TX MAC\n");
1942 device_printf(sc->sc_dev, "cannot disable TX MAC\n");
1950 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, txcfg);
1951 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, 0);
1952 bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
1953 BUS_SPACE_BARRIER_WRITE);
1954 if (!gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
1943 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg);
1944 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0);
1945 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
1946 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
1955 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
1947 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
1956 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, rxcfg);
1948 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg);
1957
1949
1958 v = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_CONFIG) &
1950 v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) &
1959 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE);
1960#ifdef notyet
1961 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
1962 IFM_ETH_RXPAUSE) != 0)
1963 v |= GEM_MAC_CC_RX_PAUSE;
1964 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
1965 IFM_ETH_TXPAUSE) != 0)
1966 v |= GEM_MAC_CC_TX_PAUSE;
1967#endif
1951 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE);
1952#ifdef notyet
1953 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
1954 IFM_ETH_RXPAUSE) != 0)
1955 v |= GEM_MAC_CC_RX_PAUSE;
1956 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
1957 IFM_ETH_TXPAUSE) != 0)
1958 v |= GEM_MAC_CC_TX_PAUSE;
1959#endif
1968 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_CONFIG, v);
1960 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v);
1969
1970 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 &&
1971 gigabit != 0)
1961
1962 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 &&
1963 gigabit != 0)
1972 bus_write_4(sc->sc_res[0], GEM_MAC_SLOT_TIME,
1964 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME,
1973 GEM_MAC_SLOT_TIME_CARR_EXTEND);
1974 else
1965 GEM_MAC_SLOT_TIME_CARR_EXTEND);
1966 else
1975 bus_write_4(sc->sc_res[0], GEM_MAC_SLOT_TIME,
1967 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME,
1976 GEM_MAC_SLOT_TIME_NORMAL);
1977
1978 /* XIF Configuration */
1979 v = GEM_MAC_XIF_LINK_LED;
1980 v |= GEM_MAC_XIF_TX_MII_ENA;
1981 if ((sc->sc_flags & GEM_SERDES) == 0) {
1968 GEM_MAC_SLOT_TIME_NORMAL);
1969
1970 /* XIF Configuration */
1971 v = GEM_MAC_XIF_LINK_LED;
1972 v |= GEM_MAC_XIF_TX_MII_ENA;
1973 if ((sc->sc_flags & GEM_SERDES) == 0) {
1982 if ((bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG) &
1974 if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) &
1983 GEM_MIF_CONFIG_PHY_SEL) != 0 &&
1984 (IFM_OPTIONS(sc->sc_mii->mii_media_active) &
1985 IFM_FDX) == 0)
1986 /* External MII needs echo disable if half duplex. */
1987 v |= GEM_MAC_XIF_ECHO_DISABL;
1988 else
1989 /*
1990 * Internal MII needs buffer enable.
1991 * XXX buffer enable makes only sense for an
1992 * external PHY.
1993 */
1994 v |= GEM_MAC_XIF_MII_BUF_ENA;
1995 }
1996 if (gigabit != 0)
1997 v |= GEM_MAC_XIF_GMII_MODE;
1998 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
1999 v |= GEM_MAC_XIF_FDPLX_LED;
1975 GEM_MIF_CONFIG_PHY_SEL) != 0 &&
1976 (IFM_OPTIONS(sc->sc_mii->mii_media_active) &
1977 IFM_FDX) == 0)
1978 /* External MII needs echo disable if half duplex. */
1979 v |= GEM_MAC_XIF_ECHO_DISABL;
1980 else
1981 /*
1982 * Internal MII needs buffer enable.
1983 * XXX buffer enable makes only sense for an
1984 * external PHY.
1985 */
1986 v |= GEM_MAC_XIF_MII_BUF_ENA;
1987 }
1988 if (gigabit != 0)
1989 v |= GEM_MAC_XIF_GMII_MODE;
1990 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
1991 v |= GEM_MAC_XIF_FDPLX_LED;
2000 bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, v);
1992 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v);
2001
2002 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2003 (sc->sc_flags & GEM_LINK) != 0) {
1993
1994 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1995 (sc->sc_flags & GEM_LINK) != 0) {
2004 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG,
1996 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG,
2005 txcfg | GEM_MAC_TX_ENABLE);
1997 txcfg | GEM_MAC_TX_ENABLE);
2006 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG,
1998 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG,
2007 rxcfg | GEM_MAC_RX_ENABLE);
2008 }
2009}
2010
2011int
2012gem_mediachange(struct ifnet *ifp)
2013{
2014 struct gem_softc *sc = ifp->if_softc;

--- 87 unchanged lines hidden (view full) ---

2102 struct ifmultiaddr *inm;
2103 int i;
2104 uint32_t hash[16];
2105 uint32_t crc, v;
2106
2107 GEM_LOCK_ASSERT(sc, MA_OWNED);
2108
2109 /* Get the current RX configuration. */
1999 rxcfg | GEM_MAC_RX_ENABLE);
2000 }
2001}
2002
2003int
2004gem_mediachange(struct ifnet *ifp)
2005{
2006 struct gem_softc *sc = ifp->if_softc;

--- 87 unchanged lines hidden (view full) ---

2094 struct ifmultiaddr *inm;
2095 int i;
2096 uint32_t hash[16];
2097 uint32_t crc, v;
2098
2099 GEM_LOCK_ASSERT(sc, MA_OWNED);
2100
2101 /* Get the current RX configuration. */
2110 v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
2102 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG);
2111
2112 /*
2113 * Turn off promiscuous mode, promiscuous group mode (all multicast),
2114 * and hash filter. Depending on the case, the right bit will be
2115 * enabled.
2116 */
2117 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER |
2118 GEM_MAC_RX_PROMISC_GRP);
2119
2103
2104 /*
2105 * Turn off promiscuous mode, promiscuous group mode (all multicast),
2106 * and hash filter. Depending on the case, the right bit will be
2107 * enabled.
2108 */
2109 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER |
2110 GEM_MAC_RX_PROMISC_GRP);
2111
2120 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
2121 bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
2122 BUS_SPACE_BARRIER_WRITE);
2123 if (!gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER, 0))
2112 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v);
2113 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
2114 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER,
2115 0))
2124 device_printf(sc->sc_dev, "cannot disable RX hash filter\n");
2125
2126 if ((ifp->if_flags & IFF_PROMISC) != 0) {
2127 v |= GEM_MAC_RX_PROMISCUOUS;
2128 goto chipit;
2129 }
2130 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
2131 v |= GEM_MAC_RX_PROMISC_GRP;

--- 26 unchanged lines hidden (view full) ---

2158 hash[crc >> 4] |= 1 << (15 - (crc & 15));
2159 }
2160 IF_ADDR_UNLOCK(ifp);
2161
2162 v |= GEM_MAC_RX_HASH_FILTER;
2163
2164 /* Now load the hash table into the chip (if we are using it). */
2165 for (i = 0; i < 16; i++)
2116 device_printf(sc->sc_dev, "cannot disable RX hash filter\n");
2117
2118 if ((ifp->if_flags & IFF_PROMISC) != 0) {
2119 v |= GEM_MAC_RX_PROMISCUOUS;
2120 goto chipit;
2121 }
2122 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
2123 v |= GEM_MAC_RX_PROMISC_GRP;

--- 26 unchanged lines hidden (view full) ---

2150 hash[crc >> 4] |= 1 << (15 - (crc & 15));
2151 }
2152 IF_ADDR_UNLOCK(ifp);
2153
2154 v |= GEM_MAC_RX_HASH_FILTER;
2155
2156 /* Now load the hash table into the chip (if we are using it). */
2157 for (i = 0; i < 16; i++)
2166 bus_write_4(sc->sc_res[0],
2158 GEM_BANK1_WRITE_4(sc,
2167 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0),
2168 hash[i]);
2169
2170 chipit:
2159 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0),
2160 hash[i]);
2161
2162 chipit:
2171 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
2163 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v);
2172}
2164}