Deleted Added
sdiff udiff text old ( 170847 ) new ( 172334 )
full compact
if_gem.c (170847) if_gem.c (172334)
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 14 unchanged lines hidden (view full) ---

23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
28 */
29
30#include <sys/cdefs.h>
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 14 unchanged lines hidden (view full) ---

23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 170847 2007-06-16 23:27:59Z marius $");
31__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 172334 2007-09-26 21:14:18Z marius $");
32
33/*
32
33/*
34 * Driver for Sun GEM ethernet controllers.
34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers
35 */
36
37#if 0
38#define GEM_DEBUG
39#endif
40
41#if 0 /* XXX: In case of emergency, re-enable this. */
42#define GEM_RINT_TIMEOUT

--- 32 unchanged lines hidden (view full) ---

75#include <machine/bus.h>
76
77#include <dev/mii/mii.h>
78#include <dev/mii/miivar.h>
79
80#include <dev/gem/if_gemreg.h>
81#include <dev/gem/if_gemvar.h>
82
35 */
36
37#if 0
38#define GEM_DEBUG
39#endif
40
41#if 0 /* XXX: In case of emergency, re-enable this. */
42#define GEM_RINT_TIMEOUT

--- 32 unchanged lines hidden (view full) ---

75#include <machine/bus.h>
76
77#include <dev/mii/mii.h>
78#include <dev/mii/miivar.h>
79
80#include <dev/gem/if_gemreg.h>
81#include <dev/gem/if_gemvar.h>
82
83CTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192);
84CTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192);
85
83#define TRIES 10000
86#define TRIES 10000
87
84/*
85 * The GEM hardware support basic TCP/UDP checksum offloading. However,
86 * the hardware doesn't compensate the checksum for UDP datagram which
87 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled
88 * by default. It can be reactivated by setting special link option
89 * link0 with ifconfig(8).
90 */
91#define GEM_CSUM_FEATURES (CSUM_TCP)

--- 5 unchanged lines hidden (view full) ---

97static void gem_cddma_callback(void *, bus_dma_segment_t *, int, int);
98static __inline void gem_txcksum(struct gem_softc *, struct mbuf *, uint64_t *);
99static __inline void gem_rxcksum(struct mbuf *, uint64_t);
100static void gem_tick(void *);
101static int gem_watchdog(struct gem_softc *);
102static void gem_init(void *);
103static void gem_init_locked(struct gem_softc *);
104static void gem_init_regs(struct gem_softc *);
88/*
89 * The GEM hardware support basic TCP/UDP checksum offloading. However,
90 * the hardware doesn't compensate the checksum for UDP datagram which
91 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled
92 * by default. It can be reactivated by setting special link option
93 * link0 with ifconfig(8).
94 */
95#define GEM_CSUM_FEATURES (CSUM_TCP)

--- 5 unchanged lines hidden (view full) ---

101static void gem_cddma_callback(void *, bus_dma_segment_t *, int, int);
102static __inline void gem_txcksum(struct gem_softc *, struct mbuf *, uint64_t *);
103static __inline void gem_rxcksum(struct mbuf *, uint64_t);
104static void gem_tick(void *);
105static int gem_watchdog(struct gem_softc *);
106static void gem_init(void *);
107static void gem_init_locked(struct gem_softc *);
108static void gem_init_regs(struct gem_softc *);
105static int gem_ringsize(int sz);
109static u_int gem_ringsize(u_int);
106static int gem_meminit(struct gem_softc *);
107static struct mbuf *gem_defrag(struct mbuf *, int, int);
108static int gem_load_txmbuf(struct gem_softc *, struct mbuf **);
109static void gem_mifinit(struct gem_softc *);
110static int gem_bitwait(struct gem_softc *, bus_addr_t, u_int32_t,
111 u_int32_t);
110static int gem_meminit(struct gem_softc *);
111static struct mbuf *gem_defrag(struct mbuf *, int, int);
112static int gem_load_txmbuf(struct gem_softc *, struct mbuf **);
113static void gem_mifinit(struct gem_softc *);
114static int gem_bitwait(struct gem_softc *, bus_addr_t, u_int32_t,
115 u_int32_t);
116static void gem_reset(struct gem_softc *);
112static int gem_reset_rx(struct gem_softc *);
117static int gem_reset_rx(struct gem_softc *);
118static void gem_reset_rxdma(struct gem_softc *sc);
113static int gem_reset_tx(struct gem_softc *);
114static int gem_disable_rx(struct gem_softc *);
115static int gem_disable_tx(struct gem_softc *);
116static void gem_rxdrain(struct gem_softc *);
117static int gem_add_rxbuf(struct gem_softc *, int);
118static void gem_setladrf(struct gem_softc *);
119
120struct mbuf *gem_get(struct gem_softc *, int, int);
121static void gem_eint(struct gem_softc *, u_int);
122static void gem_rint(struct gem_softc *);
123#ifdef GEM_RINT_TIMEOUT
124static void gem_rint_timeout(void *);
125#endif
126static void gem_tint(struct gem_softc *);
119static int gem_reset_tx(struct gem_softc *);
120static int gem_disable_rx(struct gem_softc *);
121static int gem_disable_tx(struct gem_softc *);
122static void gem_rxdrain(struct gem_softc *);
123static int gem_add_rxbuf(struct gem_softc *, int);
124static void gem_setladrf(struct gem_softc *);
125
126struct mbuf *gem_get(struct gem_softc *, int, int);
127static void gem_eint(struct gem_softc *, u_int);
128static void gem_rint(struct gem_softc *);
129#ifdef GEM_RINT_TIMEOUT
130static void gem_rint_timeout(void *);
131#endif
132static void gem_tint(struct gem_softc *);
127#ifdef notyet
128static void gem_power(int, void *);
129#endif
130
131devclass_t gem_devclass;
132DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0);
133MODULE_DEPEND(gem, miibus, 1, 1, 1);
134
135#ifdef GEM_DEBUG
136#include <sys/ktr.h>
137#define KTR_GEM KTR_CT2

--- 6 unchanged lines hidden (view full) ---

144 *
145 * Attach a Gem interface to the system.
146 */
147int
148gem_attach(sc)
149 struct gem_softc *sc;
150{
151 struct ifnet *ifp;
133
134devclass_t gem_devclass;
135DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0);
136MODULE_DEPEND(gem, miibus, 1, 1, 1);
137
138#ifdef GEM_DEBUG
139#include <sys/ktr.h>
140#define KTR_GEM KTR_CT2

--- 6 unchanged lines hidden (view full) ---

147 *
148 * Attach a Gem interface to the system.
149 */
150int
151gem_attach(sc)
152 struct gem_softc *sc;
153{
154 struct ifnet *ifp;
152 struct mii_softc *child;
153 int i, error;
154 u_int32_t v;
155
156 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
157 if (ifp == NULL)
158 return (ENOSPC);
159
160 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
161#ifdef GEM_RINT_TIMEOUT
162 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0);
163#endif
164
165 /* Make sure the chip is stopped. */
166 ifp->if_softc = sc;
155 int i, error;
156 u_int32_t v;
157
158 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
159 if (ifp == NULL)
160 return (ENOSPC);
161
162 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
163#ifdef GEM_RINT_TIMEOUT
164 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0);
165#endif
166
167 /* Make sure the chip is stopped. */
168 ifp->if_softc = sc;
167 GEM_LOCK(sc);
168 gem_stop(ifp, 0);
169 gem_reset(sc);
169 gem_reset(sc);
170 GEM_UNLOCK(sc);
171
172 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
173 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
174 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
175 &sc->sc_pdmatag);
176 if (error)
177 goto fail_ifnet;
178

--- 73 unchanged lines hidden (view full) ---

252 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
253 device_printf(sc->sc_dev, "unable to create rx DMA map "
254 "%d, error = %d\n", i, error);
255 goto fail_rxd;
256 }
257 sc->sc_rxsoft[i].rxs_mbuf = NULL;
258 }
259
170
171 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
172 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
173 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
174 &sc->sc_pdmatag);
175 if (error)
176 goto fail_ifnet;
177

--- 73 unchanged lines hidden (view full) ---

251 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
252 device_printf(sc->sc_dev, "unable to create rx DMA map "
253 "%d, error = %d\n", i, error);
254 goto fail_rxd;
255 }
256 sc->sc_rxsoft[i].rxs_mbuf = NULL;
257 }
258
259 /* Bad things will happen when touching this register on ERI. */
260 if (sc->sc_variant != GEM_SUN_ERI)
261 bus_write_4(sc->sc_res[0], GEM_MII_DATAPATH_MODE,
262 GEM_MII_DATAPATH_MII);
263
260 gem_mifinit(sc);
261
264 gem_mifinit(sc);
265
262 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange,
263 gem_mediastatus)) != 0) {
264 device_printf(sc->sc_dev, "phy probe failed: %d\n", error);
266 /*
267 * Look for an external PHY.
268 */
269 error = ENXIO;
270 v = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
271 if ((v & GEM_MIF_CONFIG_MDI1) != 0) {
272 v |= GEM_MIF_CONFIG_PHY_SEL;
273 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
274 switch (sc->sc_variant) {
275 case GEM_SUN_ERI:
276 sc->sc_phyad = GEM_PHYAD_EXTERNAL;
277 break;
278 default:
279 sc->sc_phyad = -1;
280 break;
281 }
282 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus,
283 gem_mediachange, gem_mediastatus);
284 }
285
286 /*
287 * Fall back on an internal PHY if no external PHY was found.
288 */
289 if (error != 0 && (v & GEM_MIF_CONFIG_MDI0) != 0) {
290 v &= ~GEM_MIF_CONFIG_PHY_SEL;
291 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
292 switch (sc->sc_variant) {
293 case GEM_SUN_ERI:
294 case GEM_APPLE_K2_GMAC:
295 sc->sc_phyad = GEM_PHYAD_INTERNAL;
296 break;
297 case GEM_APPLE_GMAC:
298 sc->sc_phyad = GEM_PHYAD_EXTERNAL;
299 break;
300 default:
301 sc->sc_phyad = -1;
302 break;
303 }
304 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus,
305 gem_mediachange, gem_mediastatus);
306 }
307
308 /*
309 * Try the external PCS SERDES if we didn't find any PHYs.
310 */
311 if (error != 0 && sc->sc_variant == GEM_SUN_GEM) {
312 bus_write_4(sc->sc_res[0], GEM_MII_DATAPATH_MODE,
313 GEM_MII_DATAPATH_SERDES);
314 bus_write_4(sc->sc_res[0], GEM_MII_SLINK_CONTROL,
315 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
316 bus_write_4(sc->sc_res[0], GEM_MII_CONFIG,
317 GEM_MII_CONFIG_ENABLE);
318 sc->sc_flags |= GEM_SERDES;
319 sc->sc_phyad = GEM_PHYAD_EXTERNAL;
320 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus,
321 gem_mediachange, gem_mediastatus);
322 }
323
324 if (error != 0) {
325 device_printf(sc->sc_dev, "PHY probe failed: %d\n", error);
265 goto fail_rxd;
266 }
267 sc->sc_mii = device_get_softc(sc->sc_miibus);
268
269 /*
270 * From this point forward, the attachment cannot fail. A failure
271 * before this point releases all resources that may have been
272 * allocated.

--- 15 unchanged lines hidden (view full) ---

288 device_get_unit(sc->sc_dev));
289 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
290 ifp->if_start = gem_start;
291 ifp->if_ioctl = gem_ioctl;
292 ifp->if_init = gem_init;
293 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN);
294 ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN;
295 IFQ_SET_READY(&ifp->if_snd);
326 goto fail_rxd;
327 }
328 sc->sc_mii = device_get_softc(sc->sc_miibus);
329
330 /*
331 * From this point forward, the attachment cannot fail. A failure
332 * before this point releases all resources that may have been
333 * allocated.

--- 15 unchanged lines hidden (view full) ---

349 device_get_unit(sc->sc_dev));
350 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
351 ifp->if_start = gem_start;
352 ifp->if_ioctl = gem_ioctl;
353 ifp->if_init = gem_init;
354 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN);
355 ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN;
356 IFQ_SET_READY(&ifp->if_snd);
296 /*
297 * Walk along the list of attached MII devices and
298 * establish an `MII instance' to `phy number'
299 * mapping. We'll use this mapping in media change
300 * requests to determine which phy to use to program
301 * the MIF configuration register.
302 */
303 for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL;
304 child = LIST_NEXT(child, mii_list)) {
305 /*
306 * Note: we support just two PHYs: the built-in
307 * internal device and an external on the MII
308 * connector.
309 */
310 if (child->mii_phy > 1 || child->mii_inst > 1) {
311 device_printf(sc->sc_dev, "cannot accomodate "
312 "MII device %s at phy %d, instance %d\n",
313 device_get_name(child->mii_dev),
314 child->mii_phy, child->mii_inst);
315 continue;
316 }
317
357
318 sc->sc_phys[child->mii_inst] = child->mii_phy;
319 }
320
321 /*
322 * Now select and activate the PHY we will use.
323 *
324 * The order of preference is External (MDI1),
325 * Internal (MDI0), Serial Link (no MII).
326 */
327 if (sc->sc_phys[1]) {
328#ifdef GEM_DEBUG
329 printf("using external phy\n");
330#endif
331 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
332 } else {
333#ifdef GEM_DEBUG
334 printf("using internal phy\n");
335#endif
336 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
337 }
338 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG,
339 sc->sc_mif_config);
340 /* Attach the interface. */
341 ether_ifattach(ifp, sc->sc_enaddr);
342
358 /* Attach the interface. */
359 ether_ifattach(ifp, sc->sc_enaddr);
360
343#ifdef notyet
344 /*
361 /*
345 * Add a suspend hook to make sure we come back up after a
346 * resume.
347 */
348 sc->sc_powerhook = powerhook_establish(gem_power, sc);
349 if (sc->sc_powerhook == NULL)
350 device_printf(sc->sc_dev, "WARNING: unable to establish power "
351 "hook\n");
352#endif
353
354 /*
355 * Tell the upper layer(s) we support long frames/checksum offloads.
356 */
357 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
358 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM;
359 ifp->if_hwassist |= sc->sc_csum_features;
360 ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM;
361
362 return (0);

--- 87 unchanged lines hidden (view full) ---

450{
451 struct ifnet *ifp = sc->sc_ifp;
452
453 GEM_LOCK(sc);
454 /*
455 * On resume all registers have to be initialized again like
456 * after power-on.
457 */
362 * Tell the upper layer(s) we support long frames/checksum offloads.
363 */
364 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
365 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM;
366 ifp->if_hwassist |= sc->sc_csum_features;
367 ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM;
368
369 return (0);

--- 87 unchanged lines hidden (view full) ---

457{
458 struct ifnet *ifp = sc->sc_ifp;
459
460 GEM_LOCK(sc);
461 /*
462 * On resume all registers have to be initialized again like
463 * after power-on.
464 */
458 sc->sc_inited = 0;
465 sc->sc_flags &= ~GEM_INITED;
459 if (ifp->if_flags & IFF_UP)
460 gem_init_locked(sc);
461 GEM_UNLOCK(sc);
462}
463
464static __inline void
465gem_txcksum(struct gem_softc *sc, struct mbuf *m, uint64_t *cflags)
466{

--- 108 unchanged lines hidden (view full) ---

575 int error;
576{
577 struct gem_softc *sc = (struct gem_softc *)xsc;
578
579 if (error != 0)
580 return;
581 if (nsegs != 1) {
582 /* can't happen... */
466 if (ifp->if_flags & IFF_UP)
467 gem_init_locked(sc);
468 GEM_UNLOCK(sc);
469}
470
471static __inline void
472gem_txcksum(struct gem_softc *sc, struct mbuf *m, uint64_t *cflags)
473{

--- 108 unchanged lines hidden (view full) ---

582 int error;
583{
584 struct gem_softc *sc = (struct gem_softc *)xsc;
585
586 if (error != 0)
587 return;
588 if (nsegs != 1) {
589 /* can't happen... */
583 panic("gem_cddma_callback: bad control buffer segment count");
590 panic("%s: bad control buffer segment count", __func__);
584 }
585 sc->sc_cddma = segs[0].ds_addr;
586}
587
588static void
589gem_tick(arg)
590 void *arg;
591{

--- 41 unchanged lines hidden (view full) ---

633 for (i = TRIES; i--; DELAY(100)) {
634 reg = bus_read_4(sc->sc_res[0], r);
635 if ((reg & clr) == 0 && (reg & set) == set)
636 return (1);
637 }
638 return (0);
639}
640
591 }
592 sc->sc_cddma = segs[0].ds_addr;
593}
594
595static void
596gem_tick(arg)
597 void *arg;
598{

--- 41 unchanged lines hidden (view full) ---

640 for (i = TRIES; i--; DELAY(100)) {
641 reg = bus_read_4(sc->sc_res[0], r);
642 if ((reg & clr) == 0 && (reg & set) == set)
643 return (1);
644 }
645 return (0);
646}
647
641void
648static void
642gem_reset(sc)
643 struct gem_softc *sc;
644{
645
646#ifdef GEM_DEBUG
647 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
648#endif
649 gem_reset_rx(sc);
650 gem_reset_tx(sc);
651
652 /* Do a full reset */
653 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
649gem_reset(sc)
650 struct gem_softc *sc;
651{
652
653#ifdef GEM_DEBUG
654 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
655#endif
656 gem_reset_rx(sc);
657 gem_reset_tx(sc);
658
659 /* Do a full reset */
660 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
661 bus_barrier(sc->sc_res[0], GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
654 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
655 device_printf(sc->sc_dev, "cannot reset device\n");
656}
657
662 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
663 device_printf(sc->sc_dev, "cannot reset device\n");
664}
665
658
659/*
660 * gem_rxdrain:
661 *
662 * Drain the receive queue.
663 */
664static void
665gem_rxdrain(sc)
666 struct gem_softc *sc;

--- 26 unchanged lines hidden (view full) ---

693
694#ifdef GEM_DEBUG
695 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
696#endif
697
698 callout_stop(&sc->sc_tick_ch);
699#ifdef GEM_RINT_TIMEOUT
700 callout_stop(&sc->sc_rx_ch);
666/*
667 * gem_rxdrain:
668 *
669 * Drain the receive queue.
670 */
671static void
672gem_rxdrain(sc)
673 struct gem_softc *sc;

--- 26 unchanged lines hidden (view full) ---

700
701#ifdef GEM_DEBUG
702 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
703#endif
704
705 callout_stop(&sc->sc_tick_ch);
706#ifdef GEM_RINT_TIMEOUT
707 callout_stop(&sc->sc_rx_ch);
701#endif
708#endif
702
703 /* XXX - Should we reset these instead? */
704 gem_disable_tx(sc);
705 gem_disable_rx(sc);
706
707 /*
708 * Release any queued transmit buffers.
709 */

--- 13 unchanged lines hidden (view full) ---

723
724 if (disable)
725 gem_rxdrain(sc);
726
727 /*
728 * Mark the interface down and cancel the watchdog timer.
729 */
730 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
709
710 /* XXX - Should we reset these instead? */
711 gem_disable_tx(sc);
712 gem_disable_rx(sc);
713
714 /*
715 * Release any queued transmit buffers.
716 */

--- 13 unchanged lines hidden (view full) ---

730
731 if (disable)
732 gem_rxdrain(sc);
733
734 /*
735 * Mark the interface down and cancel the watchdog timer.
736 */
737 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
738 sc->sc_flags &= ~GEM_LINK;
731 sc->sc_wdog_timer = 0;
732}
733
734/*
735 * Reset the receiver
736 */
739 sc->sc_wdog_timer = 0;
740}
741
742/*
743 * Reset the receiver
744 */
737int
745static int
738gem_reset_rx(sc)
739 struct gem_softc *sc;
740{
741
742 /*
743 * Resetting while DMA is in progress can cause a bus hang, so we
744 * disable DMA first.
745 */
746 gem_disable_rx(sc);
747 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG, 0);
746gem_reset_rx(sc)
747 struct gem_softc *sc;
748{
749
750 /*
751 * Resetting while DMA is in progress can cause a bus hang, so we
752 * disable DMA first.
753 */
754 gem_disable_rx(sc);
755 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG, 0);
748 /* Wait till it finishes */
749 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0))
750 device_printf(sc->sc_dev, "cannot disable read dma\n");
756 bus_barrier(sc->sc_res[0], GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
757 if (!gem_bitwait(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0))
758 device_printf(sc->sc_dev, "cannot disable RX DMA\n");
751
759
752 /* Wait 5ms extra. */
753 DELAY(5000);
754
755 /* Finally, reset the ERX */
756 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX);
760 /* Finally, reset the ERX */
761 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX);
757 /* Wait till it finishes */
758 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX, 0)) {
762 bus_barrier(sc->sc_res[0], GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
763 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) {
759 device_printf(sc->sc_dev, "cannot reset receiver\n");
760 return (1);
761 }
762 return (0);
763}
764
764 device_printf(sc->sc_dev, "cannot reset receiver\n");
765 return (1);
766 }
767 return (0);
768}
769
770/*
771 * Reset the receiver DMA engine.
772 *
773 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW
774 * etc in order to reset the receiver DMA engine only and not do a full
775 * reset which amongst others also downs the link and clears the FIFOs.
776 */
777static void
778gem_reset_rxdma(struct gem_softc *sc)
779{
780 int i;
765
781
782 if (gem_reset_rx(sc) != 0)
783 return (gem_init_locked(sc));
784 for (i = 0; i < GEM_NRXDESC; i++)
785 if (sc->sc_rxsoft[i].rxs_mbuf != NULL)
786 GEM_UPDATE_RXDESC(sc, i);
787 sc->sc_rxptr = 0;
788 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
789 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
790
791 /* NOTE: we use only 32-bit DMA addresses here. */
792 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_HI, 0);
793 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
794 bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC - 4);
795 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
796 gem_ringsize(GEM_NRXDESC /*XXX*/) |
797 ((ETHER_HDR_LEN + sizeof(struct ip)) <<
798 GEM_RX_CONFIG_CXM_START_SHFT) |
799 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
800 (2 << GEM_RX_CONFIG_FBOFF_SHFT));
801 bus_write_4(sc->sc_res[0], GEM_RX_BLANKING,
802 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6);
803 bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH,
804 (3 * sc->sc_rxfifosize / 256) | ((sc->sc_rxfifosize / 256) << 12));
805 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
806 bus_read_4(sc->sc_res[0], GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN);
807 bus_write_4(sc->sc_res[0], GEM_MAC_RX_MASK,
808 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
809 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG,
810 bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG) | GEM_MAC_RX_ENABLE);
811}
812
766/*
767 * Reset the transmitter
768 */
769static int
770gem_reset_tx(sc)
771 struct gem_softc *sc;
772{
813/*
814 * Reset the transmitter
815 */
816static int
817gem_reset_tx(sc)
818 struct gem_softc *sc;
819{
773 int i;
774
775 /*
776 * Resetting while DMA is in progress can cause a bus hang, so we
777 * disable DMA first.
778 */
779 gem_disable_tx(sc);
780 bus_write_4(sc->sc_res[0], GEM_TX_CONFIG, 0);
820
821 /*
822 * Resetting while DMA is in progress can cause a bus hang, so we
823 * disable DMA first.
824 */
825 gem_disable_tx(sc);
826 bus_write_4(sc->sc_res[0], GEM_TX_CONFIG, 0);
781 /* Wait till it finishes */
782 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0))
783 device_printf(sc->sc_dev, "cannot disable read dma\n");
827 bus_barrier(sc->sc_res[0], GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
828 if (!gem_bitwait(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0))
829 device_printf(sc->sc_dev, "cannot disable TX DMA\n");
784
830
785 /* Wait 5ms extra. */
786 DELAY(5000);
787
788 /* Finally, reset the ETX */
789 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_TX);
831 /* Finally, reset the ETX */
832 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_TX);
790 /* Wait till it finishes */
791 for (i = TRIES; i--; DELAY(100))
792 if ((bus_read_4(sc->sc_res[0], GEM_RESET) & GEM_RESET_TX) == 0)
793 break;
794 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
795 device_printf(sc->sc_dev, "cannot reset receiver\n");
833 bus_barrier(sc->sc_res[0], GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
834 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) {
835 device_printf(sc->sc_dev, "cannot reset transmitter\n");
796 return (1);
797 }
798 return (0);
799}
800
801/*
802 * disable receiver.
803 */
804static int
805gem_disable_rx(sc)
806 struct gem_softc *sc;
807{
808 u_int32_t cfg;
809
810 /* Flip the enable bit */
811 cfg = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
812 cfg &= ~GEM_MAC_RX_ENABLE;
813 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, cfg);
836 return (1);
837 }
838 return (0);
839}
840
841/*
842 * disable receiver.
843 */
844static int
845gem_disable_rx(sc)
846 struct gem_softc *sc;
847{
848 u_int32_t cfg;
849
850 /* Flip the enable bit */
851 cfg = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
852 cfg &= ~GEM_MAC_RX_ENABLE;
853 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, cfg);
814
815 /* Wait for it to finish */
854 bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
855 BUS_SPACE_BARRIER_WRITE);
816 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
817}
818
819/*
820 * disable transmitter.
821 */
822static int
823gem_disable_tx(sc)
824 struct gem_softc *sc;
825{
826 u_int32_t cfg;
827
828 /* Flip the enable bit */
829 cfg = bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG);
830 cfg &= ~GEM_MAC_TX_ENABLE;
831 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, cfg);
856 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
857}
858
859/*
860 * disable transmitter.
861 */
862static int
863gem_disable_tx(sc)
864 struct gem_softc *sc;
865{
866 u_int32_t cfg;
867
868 /* Flip the enable bit */
869 cfg = bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG);
870 cfg &= ~GEM_MAC_TX_ENABLE;
871 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, cfg);
832
833 /* Wait for it to finish */
872 bus_barrier(sc->sc_res[0], GEM_MAC_TX_CONFIG, 4,
873 BUS_SPACE_BARRIER_WRITE);
834 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
835}
836
837/*
838 * Initialize interface.
839 */
840static int
841gem_meminit(sc)

--- 36 unchanged lines hidden (view full) ---

878 }
879 sc->sc_rxptr = 0;
880 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
881 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
882
883 return (0);
884}
885
874 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
875}
876
877/*
878 * Initialize interface.
879 */
880static int
881gem_meminit(sc)

--- 36 unchanged lines hidden (view full) ---

918 }
919 sc->sc_rxptr = 0;
920 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
921 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
922
923 return (0);
924}
925
886static int
926static u_int
887gem_ringsize(sz)
927gem_ringsize(sz)
888 int sz;
928 u_int sz;
889{
929{
890 int v = 0;
891
892 switch (sz) {
893 case 32:
930
931 switch (sz) {
932 case 32:
894 v = GEM_RING_SZ_32;
895 break;
933 return (GEM_RING_SZ_32);
896 case 64:
934 case 64:
897 v = GEM_RING_SZ_64;
898 break;
935 return (GEM_RING_SZ_64);
899 case 128:
936 case 128:
900 v = GEM_RING_SZ_128;
901 break;
937 return (GEM_RING_SZ_128);
902 case 256:
938 case 256:
903 v = GEM_RING_SZ_256;
904 break;
939 return (GEM_RING_SZ_256);
905 case 512:
940 case 512:
906 v = GEM_RING_SZ_512;
907 break;
941 return (GEM_RING_SZ_512);
908 case 1024:
942 case 1024:
909 v = GEM_RING_SZ_1024;
910 break;
943 return (GEM_RING_SZ_1024);
911 case 2048:
944 case 2048:
912 v = GEM_RING_SZ_2048;
913 break;
945 return (GEM_RING_SZ_2048);
914 case 4096:
946 case 4096:
915 v = GEM_RING_SZ_4096;
916 break;
947 return (GEM_RING_SZ_4096);
917 case 8192:
948 case 8192:
918 v = GEM_RING_SZ_8192;
919 break;
949 return (GEM_RING_SZ_8192);
920 default:
950 default:
921 printf("gem: invalid Receive Descriptor ring size\n");
922 break;
951 printf("%s: invalid ring size %d\n", __func__, sz);
952 return (GEM_RING_SZ_32);
923 }
953 }
924 return (v);
925}
926
927static void
928gem_init(xsc)
929 void *xsc;
930{
931 struct gem_softc *sc = (struct gem_softc *)xsc;
932

--- 33 unchanged lines hidden (view full) ---

966 CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev),
967 __func__);
968#endif
969
970 /* Re-initialize the MIF */
971 gem_mifinit(sc);
972
973 /* step 3. Setup data structures in host memory */
954}
955
956static void
957gem_init(xsc)
958 void *xsc;
959{
960 struct gem_softc *sc = (struct gem_softc *)xsc;
961

--- 33 unchanged lines hidden (view full) ---

995 CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev),
996 __func__);
997#endif
998
999 /* Re-initialize the MIF */
1000 gem_mifinit(sc);
1001
1002 /* step 3. Setup data structures in host memory */
974 gem_meminit(sc);
1003 if (gem_meminit(sc) != 0)
1004 return;
975
976 /* step 4. TX MAC registers & counters */
977 gem_init_regs(sc);
978
979 /* step 5. RX MAC registers & counters */
980 gem_setladrf(sc);
981
982 /* step 6 & 7. Program Descriptor Ring Base Addresses */

--- 5 unchanged lines hidden (view full) ---

988 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
989#ifdef GEM_DEBUG
990 CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx",
991 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
992#endif
993
994 /* step 8. Global Configuration & Interrupt Mask */
995 bus_write_4(sc->sc_res[0], GEM_INTMASK,
1005
1006 /* step 4. TX MAC registers & counters */
1007 gem_init_regs(sc);
1008
1009 /* step 5. RX MAC registers & counters */
1010 gem_setladrf(sc);
1011
1012 /* step 6 & 7. Program Descriptor Ring Base Addresses */

--- 5 unchanged lines hidden (view full) ---

1018 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
1019#ifdef GEM_DEBUG
1020 CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx",
1021 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
1022#endif
1023
1024 /* step 8. Global Configuration & Interrupt Mask */
1025 bus_write_4(sc->sc_res[0], GEM_INTMASK,
996 ~(GEM_INTR_TX_INTME|
997 GEM_INTR_TX_EMPTY|
998 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF|
999 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS|
1000 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF|
1001 GEM_INTR_BERR));
1026 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE |
1027 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR |
1028 GEM_INTR_BERR
1029#ifdef GEM_DEBUG
1030 | GEM_INTR_PCS | GEM_INTR_MIF
1031#endif
1032 ));
1002 bus_write_4(sc->sc_res[0], GEM_MAC_RX_MASK,
1033 bus_write_4(sc->sc_res[0], GEM_MAC_RX_MASK,
1003 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT);
1004 bus_write_4(sc->sc_res[0], GEM_MAC_TX_MASK, 0xffff); /* XXXX */
1005 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_MASK, 0); /* XXXX */
1034 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
1035 bus_write_4(sc->sc_res[0], GEM_MAC_TX_MASK,
1036 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP);
1037#ifdef GEM_DEBUG
1038 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_MASK,
1039 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME));
1040#else
1041 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_MASK,
1042 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME);
1043#endif
1006
1007 /* step 9. ETX Configuration: use mostly default values */
1008
1009 /* Enable DMA */
1010 v = gem_ringsize(GEM_NTXDESC /*XXX*/);
1011 bus_write_4(sc->sc_res[0], GEM_TX_CONFIG,
1012 v|GEM_TX_CONFIG_TXDMA_EN|
1013 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH));
1014
1015 /* step 10. ERX Configuration */
1016
1044
1045 /* step 9. ETX Configuration: use mostly default values */
1046
1047 /* Enable DMA */
1048 v = gem_ringsize(GEM_NTXDESC /*XXX*/);
1049 bus_write_4(sc->sc_res[0], GEM_TX_CONFIG,
1050 v|GEM_TX_CONFIG_TXDMA_EN|
1051 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH));
1052
1053 /* step 10. ERX Configuration */
1054
1017 /* Encode Receive Descriptor ring size: four possible values */
1055 /* Encode Receive Descriptor ring size. */
1018 v = gem_ringsize(GEM_NRXDESC /*XXX*/);
1019 /* Rx TCP/UDP checksum offset */
1020 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) <<
1021 GEM_RX_CONFIG_CXM_START_SHFT);
1022
1023 /* Enable DMA */
1024 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
1025 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)|
1026 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN);
1056 v = gem_ringsize(GEM_NRXDESC /*XXX*/);
1057 /* Rx TCP/UDP checksum offset */
1058 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) <<
1059 GEM_RX_CONFIG_CXM_START_SHFT);
1060
1061 /* Enable DMA */
1062 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
1063 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)|
1064 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN);
1065
1066 bus_write_4(sc->sc_res[0], GEM_RX_BLANKING,
1067 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6);
1068
1027 /*
1028 * The following value is for an OFF Threshold of about 3/4 full
1029 * and an ON Threshold of 1/4 full.
1030 */
1031 bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH,
1032 (3 * sc->sc_rxfifosize / 256) |
1033 ( (sc->sc_rxfifosize / 256) << 12));
1069 /*
1070 * The following value is for an OFF Threshold of about 3/4 full
1071 * and an ON Threshold of 1/4 full.
1072 */
1073 bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH,
1074 (3 * sc->sc_rxfifosize / 256) |
1075 ( (sc->sc_rxfifosize / 256) << 12));
1034 bus_write_4(sc->sc_res[0], GEM_RX_BLANKING, (6<<12)|6);
1035
1036 /* step 11. Configure Media */
1076
1077 /* step 11. Configure Media */
1037 mii_mediachg(sc->sc_mii);
1038
1039 /* step 12. RX_MAC Configuration Register */
1040 v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
1078
1079 /* step 12. RX_MAC Configuration Register */
1080 v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
1041 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC;
1081 v |= GEM_MAC_RX_STRIP_CRC;
1082 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, 0);
1083 bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
1084 BUS_SPACE_BARRIER_WRITE);
1085 if (!gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
1086 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
1042 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
1043
1044 /* step 14. Issue Transmit Pending command */
1045
1046 /* step 15. Give the reciever a swift kick */
1047 bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC-4);
1048
1087 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
1088
1089 /* step 14. Issue Transmit Pending command */
1090
1091 /* step 15. Give the reciever a swift kick */
1092 bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC-4);
1093
1049 /* Start the one second timer. */
1050 sc->sc_wdog_timer = 0;
1051 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
1052
1053 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1054 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1055 sc->sc_ifflags = ifp->if_flags;
1094 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1095 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1096 sc->sc_ifflags = ifp->if_flags;
1097
1098 sc->sc_flags &= ~GEM_LINK;
1099 mii_mediachg(sc->sc_mii);
1100
1101 /* Start the one second timer. */
1102 sc->sc_wdog_timer = 0;
1103 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
1056}
1057
1058/*
1059 * It's copy of ath_defrag(ath(4)).
1060 *
1061 * Defragment an mbuf chain, returning at most maxfrags separate
1062 * mbufs+clusters. If this is not possible NULL is returned and
1063 * the original mbuf chain is left in it's present (potentially

--- 136 unchanged lines hidden (view full) ---

1200 flags = cflags = 0;
1201 if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0)
1202 gem_txcksum(sc, *m_head, &cflags);
1203
1204 txs->txs_ndescs = nsegs;
1205 txs->txs_firstdesc = sc->sc_txnext;
1206 nexttx = txs->txs_firstdesc;
1207 for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) {
1104}
1105
1106/*
1107 * It's copy of ath_defrag(ath(4)).
1108 *
1109 * Defragment an mbuf chain, returning at most maxfrags separate
1110 * mbufs+clusters. If this is not possible NULL is returned and
1111 * the original mbuf chain is left in it's present (potentially

--- 136 unchanged lines hidden (view full) ---

1248 flags = cflags = 0;
1249 if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0)
1250 gem_txcksum(sc, *m_head, &cflags);
1251
1252 txs->txs_ndescs = nsegs;
1253 txs->txs_firstdesc = sc->sc_txnext;
1254 nexttx = txs->txs_firstdesc;
1255 for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) {
1208#ifdef GEM_DEBUG
1256#ifdef GEM_DEBUG
1209 CTR6(KTR_GEM, "%s: mapping seg %d (txd %d), len "
1210 "%lx, addr %#lx (%#lx)", __func__, seg, nexttx,
1211 txsegs[seg].ds_len, txsegs[seg].ds_addr,
1212 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr));
1213#endif
1214 sc->sc_txdescs[nexttx].gd_addr =
1215 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr);
1216 KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE,
1217 ("%s: segment size too large!", __func__));
1218 flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE;
1219 sc->sc_txdescs[nexttx].gd_flags =
1220 GEM_DMA_WRITE(sc, flags | cflags);
1221 txs->txs_lastdesc = nexttx;
1222 }
1223
1224 /* set EOP on the last descriptor */
1257 CTR6(KTR_GEM, "%s: mapping seg %d (txd %d), len "
1258 "%lx, addr %#lx (%#lx)", __func__, seg, nexttx,
1259 txsegs[seg].ds_len, txsegs[seg].ds_addr,
1260 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr));
1261#endif
1262 sc->sc_txdescs[nexttx].gd_addr =
1263 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr);
1264 KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE,
1265 ("%s: segment size too large!", __func__));
1266 flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE;
1267 sc->sc_txdescs[nexttx].gd_flags =
1268 GEM_DMA_WRITE(sc, flags | cflags);
1269 txs->txs_lastdesc = nexttx;
1270 }
1271
1272 /* set EOP on the last descriptor */
1225#ifdef GEM_DEBUG
1273#ifdef GEM_DEBUG
1226 CTR3(KTR_GEM, "%s: end of packet at seg %d, tx %d", __func__, seg,
1227 nexttx);
1228#endif
1229 sc->sc_txdescs[txs->txs_lastdesc].gd_flags |=
1230 GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET);
1231
1232 /* Lastly set SOP on the first descriptor */
1274 CTR3(KTR_GEM, "%s: end of packet at seg %d, tx %d", __func__, seg,
1275 nexttx);
1276#endif
1277 sc->sc_txdescs[txs->txs_lastdesc].gd_flags |=
1278 GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET);
1279
1280 /* Lastly set SOP on the first descriptor */
1233#ifdef GEM_DEBUG
1281#ifdef GEM_DEBUG
1234 CTR3(KTR_GEM, "%s: start of packet at seg %d, tx %d", __func__, seg,
1235 nexttx);
1236#endif
1237 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
1238 sc->sc_txwin = 0;
1239 flags |= GEM_TD_INTERRUPT_ME;
1240 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |=
1241 GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME |

--- 19 unchanged lines hidden (view full) ---

1261 return (0);
1262}
1263
1264static void
1265gem_init_regs(sc)
1266 struct gem_softc *sc;
1267{
1268 const u_char *laddr = IF_LLADDR(sc->sc_ifp);
1282 CTR3(KTR_GEM, "%s: start of packet at seg %d, tx %d", __func__, seg,
1283 nexttx);
1284#endif
1285 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
1286 sc->sc_txwin = 0;
1287 flags |= GEM_TD_INTERRUPT_ME;
1288 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |=
1289 GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME |

--- 19 unchanged lines hidden (view full) ---

1309 return (0);
1310}
1311
1312static void
1313gem_init_regs(sc)
1314 struct gem_softc *sc;
1315{
1316 const u_char *laddr = IF_LLADDR(sc->sc_ifp);
1269 u_int32_t v;
1270
1271 /* These regs are not cleared on reset */
1317
1318 /* These regs are not cleared on reset */
1272 if (!sc->sc_inited) {
1273
1319 if ((sc->sc_flags & GEM_INITED) == 0) {
1274 /* Wooo. Magic values. */
1275 bus_write_4(sc->sc_res[0], GEM_MAC_IPG0, 0);
1276 bus_write_4(sc->sc_res[0], GEM_MAC_IPG1, 8);
1277 bus_write_4(sc->sc_res[0], GEM_MAC_IPG2, 4);
1278
1279 bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1280 /* Max frame and max burst size */
1281 bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MAX_FRAME,
1320 /* Wooo. Magic values. */
1321 bus_write_4(sc->sc_res[0], GEM_MAC_IPG0, 0);
1322 bus_write_4(sc->sc_res[0], GEM_MAC_IPG1, 8);
1323 bus_write_4(sc->sc_res[0], GEM_MAC_IPG2, 4);
1324
1325 bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1326 /* Max frame and max burst size */
1327 bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MAX_FRAME,
1282 (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) |
1283 (0x2000 << 16));
1328 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16));
1284
1285 bus_write_4(sc->sc_res[0], GEM_MAC_PREAMBLE_LEN, 0x7);
1286 bus_write_4(sc->sc_res[0], GEM_MAC_JAM_SIZE, 0x4);
1287 bus_write_4(sc->sc_res[0], GEM_MAC_ATTEMPT_LIMIT, 0x10);
1288 /* Dunno.... */
1289 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_TYPE, 0x8088);
1290 bus_write_4(sc->sc_res[0], GEM_MAC_RANDOM_SEED,
1291 ((laddr[5]<<8)|laddr[4])&0x3ff);

--- 11 unchanged lines hidden (view full) ---

1303 /* MAC filter addr set to 0:0:0:0:0:0 */
1304 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER0, 0);
1305 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER1, 0);
1306 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER2, 0);
1307
1308 bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK1_2, 0);
1309 bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK0, 0);
1310
1329
1330 bus_write_4(sc->sc_res[0], GEM_MAC_PREAMBLE_LEN, 0x7);
1331 bus_write_4(sc->sc_res[0], GEM_MAC_JAM_SIZE, 0x4);
1332 bus_write_4(sc->sc_res[0], GEM_MAC_ATTEMPT_LIMIT, 0x10);
1333 /* Dunno.... */
1334 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_TYPE, 0x8088);
1335 bus_write_4(sc->sc_res[0], GEM_MAC_RANDOM_SEED,
1336 ((laddr[5]<<8)|laddr[4])&0x3ff);

--- 11 unchanged lines hidden (view full) ---

1348 /* MAC filter addr set to 0:0:0:0:0:0 */
1349 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER0, 0);
1350 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER1, 0);
1351 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER2, 0);
1352
1353 bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK1_2, 0);
1354 bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK0, 0);
1355
1311 sc->sc_inited = 1;
1356 sc->sc_flags |= GEM_INITED;
1312 }
1313
1314 /* Counters need to be zeroed */
1315 bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0);
1316 bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0);
1317 bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0);
1318 bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0);
1319 bus_write_4(sc->sc_res[0], GEM_MAC_DEFER_TMR_CNT, 0);
1320 bus_write_4(sc->sc_res[0], GEM_MAC_PEAK_ATTEMPTS, 0);
1321 bus_write_4(sc->sc_res[0], GEM_MAC_RX_FRAME_COUNT, 0);
1322 bus_write_4(sc->sc_res[0], GEM_MAC_RX_LEN_ERR_CNT, 0);
1323 bus_write_4(sc->sc_res[0], GEM_MAC_RX_ALIGN_ERR, 0);
1324 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CRC_ERR_CNT, 0);
1325 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CODE_VIOL, 0);
1326
1357 }
1358
1359 /* Counters need to be zeroed */
1360 bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0);
1361 bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0);
1362 bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0);
1363 bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0);
1364 bus_write_4(sc->sc_res[0], GEM_MAC_DEFER_TMR_CNT, 0);
1365 bus_write_4(sc->sc_res[0], GEM_MAC_PEAK_ATTEMPTS, 0);
1366 bus_write_4(sc->sc_res[0], GEM_MAC_RX_FRAME_COUNT, 0);
1367 bus_write_4(sc->sc_res[0], GEM_MAC_RX_LEN_ERR_CNT, 0);
1368 bus_write_4(sc->sc_res[0], GEM_MAC_RX_ALIGN_ERR, 0);
1369 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CRC_ERR_CNT, 0);
1370 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CODE_VIOL, 0);
1371
1327 /* Un-pause stuff */
1328#if 0
1372 /* Set XOFF PAUSE time. */
1329 bus_write_4(sc->sc_res[0], GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1373 bus_write_4(sc->sc_res[0], GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1330#else
1331 bus_write_4(sc->sc_res[0], GEM_MAC_SEND_PAUSE_CMD, 0);
1332#endif
1333
1334 /*
1374
1375 /*
1376 * Set the internal arbitration to "infinite" bursts of the
1377 * maximum length of 31 * 64 bytes so DMA transfers aren't
1378 * split up in cache line size chunks. This greatly improves
1379 * especially RX performance.
1380 * Enable silicon bug workarounds for the Apple variants.
1381 */
1382 bus_write_4(sc->sc_res[0], GEM_CONFIG,
1383 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT |
1384 GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ?
1385 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0));
1386
1387 /*
1335 * Set the station address.
1336 */
1337 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
1338 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
1339 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
1340
1388 * Set the station address.
1389 */
1390 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
1391 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
1392 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
1393
1341 /*
1342 * Enable MII outputs. Enable GMII if there is a gigabit PHY.
1343 */
1344 sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
1345 v = GEM_MAC_XIF_TX_MII_ENA;
1346 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
1347 v |= GEM_MAC_XIF_FDPLX_LED;
1348 if (sc->sc_flags & GEM_GIGABIT)
1349 v |= GEM_MAC_XIF_GMII_MODE;
1350 }
1351 bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, v);
1394 /* Enable MII outputs. */
1395 bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA);
1352}
1353
1354static void
1355gem_start(ifp)
1356 struct ifnet *ifp;
1357{
1358 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1359
1360 GEM_LOCK(sc);
1361 gem_start_locked(ifp);
1362 GEM_UNLOCK(sc);
1363}
1364
1365static void
1366gem_start_locked(ifp)
1367 struct ifnet *ifp;
1368{
1369 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1370 struct mbuf *m;
1396}
1397
1398static void
1399gem_start(ifp)
1400 struct ifnet *ifp;
1401{
1402 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1403
1404 GEM_LOCK(sc);
1405 gem_start_locked(ifp);
1406 GEM_UNLOCK(sc);
1407}
1408
1409static void
1410gem_start_locked(ifp)
1411 struct ifnet *ifp;
1412{
1413 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1414 struct mbuf *m;
1371 int firsttx, ntx = 0, txmfail;
1415 int ntx = 0;
1372
1373 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1416
1417 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1374 IFF_DRV_RUNNING)
1418 IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0)
1375 return;
1376
1419 return;
1420
1377 firsttx = sc->sc_txnext;
1378#ifdef GEM_DEBUG
1379 CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d",
1421#ifdef GEM_DEBUG
1422 CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d",
1380 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, firsttx);
1423 device_get_name(sc->sc_dev), __func__, sc->sc_txfree,
1424 sc->sc_txnext);
1381#endif
1382 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) {
1383 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1384 if (m == NULL)
1385 break;
1425#endif
1426 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) {
1427 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1428 if (m == NULL)
1429 break;
1386 txmfail = gem_load_txmbuf(sc, &m);
1387 if (txmfail != 0) {
1430 if (gem_load_txmbuf(sc, &m) != 0) {
1388 if (m == NULL)
1389 break;
1390 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1391 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1392 break;
1393 }
1394 ntx++;
1395 /* Kick the transmitter. */
1431 if (m == NULL)
1432 break;
1433 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1434 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1435 break;
1436 }
1437 ntx++;
1438 /* Kick the transmitter. */
1396#ifdef GEM_DEBUG
1439#ifdef GEM_DEBUG
1397 CTR3(KTR_GEM, "%s: %s: kicking tx %d",
1398 device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
1399#endif
1440 CTR3(KTR_GEM, "%s: %s: kicking tx %d",
1441 device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
1442#endif
1443 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1400 bus_write_4(sc->sc_res[0], GEM_TX_KICK,
1401 sc->sc_txnext);
1402
1403 BPF_MTAP(ifp, m);
1404 }
1405
1406 if (ntx > 0) {
1444 bus_write_4(sc->sc_res[0], GEM_TX_KICK,
1445 sc->sc_txnext);
1446
1447 BPF_MTAP(ifp, m);
1448 }
1449
1450 if (ntx > 0) {
1407 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1408
1409#ifdef GEM_DEBUG
1410 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
1451#ifdef GEM_DEBUG
1452 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
1411 device_get_name(sc->sc_dev), firsttx);
1453 device_get_name(sc->sc_dev), sc->sc_txnext);
1412#endif
1413
1414 /* Set a watchdog timer in case the chip flakes out. */
1415 sc->sc_wdog_timer = 5;
1416#ifdef GEM_DEBUG
1417 CTR3(KTR_GEM, "%s: %s: watchdog %d",
1418 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer);
1419#endif

--- 7 unchanged lines hidden (view full) ---

1427gem_tint(sc)
1428 struct gem_softc *sc;
1429{
1430 struct ifnet *ifp = sc->sc_ifp;
1431 struct gem_txsoft *txs;
1432 int txlast;
1433 int progress = 0;
1434
1454#endif
1455
1456 /* Set a watchdog timer in case the chip flakes out. */
1457 sc->sc_wdog_timer = 5;
1458#ifdef GEM_DEBUG
1459 CTR3(KTR_GEM, "%s: %s: watchdog %d",
1460 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer);
1461#endif

--- 7 unchanged lines hidden (view full) ---

1469gem_tint(sc)
1470 struct gem_softc *sc;
1471{
1472 struct ifnet *ifp = sc->sc_ifp;
1473 struct gem_txsoft *txs;
1474 int txlast;
1475 int progress = 0;
1476
1435
1436#ifdef GEM_DEBUG
1437 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
1438#endif
1439
1440 /*
1441 * Go through our Tx list and free mbufs for those
1442 * frames that have been transmitted.
1443 */

--- 12 unchanged lines hidden (view full) ---

1456 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr));
1457 if (i == txs->txs_lastdesc)
1458 break;
1459 }
1460 }
1461#endif
1462
1463 /*
1477#ifdef GEM_DEBUG
1478 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
1479#endif
1480
1481 /*
1482 * Go through our Tx list and free mbufs for those
1483 * frames that have been transmitted.
1484 */

--- 12 unchanged lines hidden (view full) ---

1497 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr));
1498 if (i == txs->txs_lastdesc)
1499 break;
1500 }
1501 }
1502#endif
1503
1504 /*
1464 * In theory, we could harveast some descriptors before
1505 * In theory, we could harvest some descriptors before
1465 * the ring is empty, but that's a bit complicated.
1466 *
1467 * GEM_TX_COMPLETION points to the last descriptor
1468 * processed +1.
1469 */
1470 txlast = bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION);
1471#ifdef GEM_DEBUG
1472 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, "

--- 29 unchanged lines hidden (view full) ---

1502 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1503
1504 ifp->if_opackets++;
1505 progress = 1;
1506 }
1507
1508#ifdef GEM_DEBUG
1509 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x "
1506 * the ring is empty, but that's a bit complicated.
1507 *
1508 * GEM_TX_COMPLETION points to the last descriptor
1509 * processed +1.
1510 */
1511 txlast = bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION);
1512#ifdef GEM_DEBUG
1513 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, "

--- 29 unchanged lines hidden (view full) ---

1543 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1544
1545 ifp->if_opackets++;
1546 progress = 1;
1547 }
1548
1549#ifdef GEM_DEBUG
1550 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x "
1510 "GEM_TX_DATA_PTR %llx "
1511 "GEM_TX_COMPLETION %x",
1512 __func__,
1513 bus_space_read_4(sc->sc_res[0], sc->sc_h, GEM_TX_STATE_MACHINE),
1514 ((long long) bus_4(sc->sc_res[0],
1515 GEM_TX_DATA_PTR_HI) << 32) |
1516 bus_read_4(sc->sc_res[0],
1517 GEM_TX_DATA_PTR_LO),
1518 bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION));
1551 "GEM_TX_DATA_PTR %llx "
1552 "GEM_TX_COMPLETION %x",
1553 __func__,
1554 bus_read_4(sc->sc_res[0], GEM_TX_STATE_MACHINE),
1555 ((long long) bus_read_4(sc->sc_res[0], GEM_TX_DATA_PTR_HI) << 32) |
1556 bus_read_4(sc->sc_res[0], GEM_TX_DATA_PTR_LO),
1557 bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION));
1519#endif
1520
1521 if (progress) {
1522 if (sc->sc_txfree == GEM_NTXDESC - 1)
1523 sc->sc_txwin = 0;
1524
1525 /* Freed some descriptors, so reset IFF_DRV_OACTIVE and restart. */
1526 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;

--- 25 unchanged lines hidden (view full) ---

1552/*
1553 * Receive interrupt.
1554 */
1555static void
1556gem_rint(sc)
1557 struct gem_softc *sc;
1558{
1559 struct ifnet *ifp = sc->sc_ifp;
1558#endif
1559
1560 if (progress) {
1561 if (sc->sc_txfree == GEM_NTXDESC - 1)
1562 sc->sc_txwin = 0;
1563
1564 /* Freed some descriptors, so reset IFF_DRV_OACTIVE and restart. */
1565 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;

--- 25 unchanged lines hidden (view full) ---

1591/*
1592 * Receive interrupt.
1593 */
1594static void
1595gem_rint(sc)
1596 struct gem_softc *sc;
1597{
1598 struct ifnet *ifp = sc->sc_ifp;
1560 struct gem_rxsoft *rxs;
1561 struct mbuf *m;
1562 u_int64_t rxstat;
1563 u_int32_t rxcomp;
1599 struct mbuf *m;
1600 u_int64_t rxstat;
1601 u_int32_t rxcomp;
1564 int i, len, progress = 0;
1565
1566#ifdef GEM_RINT_TIMEOUT
1567 callout_stop(&sc->sc_rx_ch);
1568#endif
1569#ifdef GEM_DEBUG
1570 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
1571#endif
1572
1573 /*
1574 * Read the completion register once. This limits
1575 * how long the following loop can execute.
1576 */
1577 rxcomp = bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION);
1578
1579#ifdef GEM_DEBUG
1580 CTR3(KTR_GEM, "%s: sc->rxptr %d, complete %d",
1581 __func__, sc->sc_rxptr, rxcomp);
1582#endif
1583 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1602
1603#ifdef GEM_RINT_TIMEOUT
1604 callout_stop(&sc->sc_rx_ch);
1605#endif
1606#ifdef GEM_DEBUG
1607 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
1608#endif
1609
1610 /*
1611 * Read the completion register once. This limits
1612 * how long the following loop can execute.
1613 */
1614 rxcomp = bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION);
1615
1616#ifdef GEM_DEBUG
1617 CTR3(KTR_GEM, "%s: sc->rxptr %d, complete %d",
1618 __func__, sc->sc_rxptr, rxcomp);
1619#endif
1620 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1584 for (i = sc->sc_rxptr; i != rxcomp;
1585 i = GEM_NEXTRX(i)) {
1586 rxs = &sc->sc_rxsoft[i];
1621 for (; sc->sc_rxptr != rxcomp;) {
1622 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf;
1623 rxstat = GEM_DMA_READ(sc,
1624 sc->sc_rxdescs[sc->sc_rxptr].gd_flags);
1587
1625
1588 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
1589
1590 if (rxstat & GEM_RD_OWN) {
1591#ifdef GEM_RINT_TIMEOUT
1592 /*
1593 * The descriptor is still marked as owned, although
1594 * it is supposed to have completed. This has been
1595 * observed on some machines. Just exiting here
1596 * might leave the packet sitting around until another
1597 * one arrives to trigger a new interrupt, which is
1598 * generally undesirable, so set up a timeout.
1599 */
1600 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS,
1601 gem_rint_timeout, sc);
1602#endif
1626 if (rxstat & GEM_RD_OWN) {
1627#ifdef GEM_RINT_TIMEOUT
1628 /*
1629 * The descriptor is still marked as owned, although
1630 * it is supposed to have completed. This has been
1631 * observed on some machines. Just exiting here
1632 * might leave the packet sitting around until another
1633 * one arrives to trigger a new interrupt, which is
1634 * generally undesirable, so set up a timeout.
1635 */
1636 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS,
1637 gem_rint_timeout, sc);
1638#endif
1603 break;
1639 m = NULL;
1640 goto kickit;
1604 }
1605
1641 }
1642
1606 progress++;
1607 ifp->if_ipackets++;
1608
1609 if (rxstat & GEM_RD_BAD_CRC) {
1610 ifp->if_ierrors++;
1611 device_printf(sc->sc_dev, "receive error: CRC error\n");
1643 if (rxstat & GEM_RD_BAD_CRC) {
1644 ifp->if_ierrors++;
1645 device_printf(sc->sc_dev, "receive error: CRC error\n");
1612 GEM_INIT_RXDESC(sc, i);
1613 continue;
1646 GEM_INIT_RXDESC(sc, sc->sc_rxptr);
1647 m = NULL;
1648 goto kickit;
1614 }
1615
1616#ifdef GEM_DEBUG
1617 if (ifp->if_flags & IFF_DEBUG) {
1649 }
1650
1651#ifdef GEM_DEBUG
1652 if (ifp->if_flags & IFF_DEBUG) {
1618 printf(" rxsoft %p descriptor %d: ", rxs, i);
1653 printf(" rxsoft %p descriptor %d: ",
1654 &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr);
1619 printf("gd_flags: 0x%016llx\t", (long long)
1655 printf("gd_flags: 0x%016llx\t", (long long)
1620 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
1656 GEM_DMA_READ(sc, sc->sc_rxdescs[
1657 sc->sc_rxptr].gd_flags));
1621 printf("gd_addr: 0x%016llx\n", (long long)
1658 printf("gd_addr: 0x%016llx\n", (long long)
1622 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
1659 GEM_DMA_READ(sc, sc->sc_rxdescs[
1660 sc->sc_rxptr].gd_addr));
1623 }
1624#endif
1625
1626 /*
1661 }
1662#endif
1663
1664 /*
1627 * No errors; receive the packet.
1628 */
1629 len = GEM_RD_BUFLEN(rxstat);
1630
1631 /*
1632 * Allocate a new mbuf cluster. If that fails, we are
1633 * out of memory, and must drop the packet and recycle
1634 * the buffer that's already attached to this descriptor.
1635 */
1665 * Allocate a new mbuf cluster. If that fails, we are
1666 * out of memory, and must drop the packet and recycle
1667 * the buffer that's already attached to this descriptor.
1668 */
1636 m = rxs->rxs_mbuf;
1637 if (gem_add_rxbuf(sc, i) != 0) {
1669 if (gem_add_rxbuf(sc, sc->sc_rxptr) != 0) {
1638 ifp->if_ierrors++;
1670 ifp->if_ierrors++;
1639 GEM_INIT_RXDESC(sc, i);
1671 GEM_INIT_RXDESC(sc, sc->sc_rxptr);
1672 m = NULL;
1673 }
1674
1675kickit:
1676 /*
1677 * Update the RX kick register. This register has to point
1678 * to the descriptor after the last valid one (before the
1679 * current batch) and must be incremented in multiples of
1680 * 4 (because the DMA engine fetches/updates descriptors
1681 * in batches of 4).
1682 */
1683 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr);
1684 if ((sc->sc_rxptr % 4) == 0) {
1685 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1686 bus_write_4(sc->sc_res[0], GEM_RX_KICK,
1687 (sc->sc_rxptr + GEM_NRXDESC - 4) &
1688 GEM_NRXDESC_MASK);
1689 }
1690
1691 if (m == NULL) {
1692 if (rxstat & GEM_RD_OWN)
1693 break;
1640 continue;
1641 }
1694 continue;
1695 }
1642 m->m_data += 2; /* We're already off by two */
1643
1696
1697 ifp->if_ipackets++;
1698 m->m_data += 2; /* We're already off by two */
1644 m->m_pkthdr.rcvif = ifp;
1699 m->m_pkthdr.rcvif = ifp;
1645 m->m_pkthdr.len = m->m_len = len;
1700 m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat);
1646
1647 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1648 gem_rxcksum(m, rxstat);
1649
1650 /* Pass it on. */
1651 GEM_UNLOCK(sc);
1652 (*ifp->if_input)(ifp, m);
1653 GEM_LOCK(sc);
1654 }
1655
1701
1702 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1703 gem_rxcksum(m, rxstat);
1704
1705 /* Pass it on. */
1706 GEM_UNLOCK(sc);
1707 (*ifp->if_input)(ifp, m);
1708 GEM_LOCK(sc);
1709 }
1710
1656 if (progress) {
1657 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1658 /* Update the receive pointer. */
1659 if (i == sc->sc_rxptr) {
1660 device_printf(sc->sc_dev, "rint: ring wrap\n");
1661 }
1662 sc->sc_rxptr = i;
1663 bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_PREVRX(i));
1664 }
1665
1666#ifdef GEM_DEBUG
1667 CTR3(KTR_GEM, "%s: done sc->rxptr %d, complete %d", __func__,
1668 sc->sc_rxptr, bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION));
1669#endif
1670}
1671
1711#ifdef GEM_DEBUG
1712 CTR3(KTR_GEM, "%s: done sc->rxptr %d, complete %d", __func__,
1713 sc->sc_rxptr, bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION));
1714#endif
1715}
1716
1672
1673/*
1674 * gem_add_rxbuf:
1675 *
1676 * Add a receive buffer to the indicated descriptor.
1677 */
1678static int
1679gem_add_rxbuf(sc, idx)
1680 struct gem_softc *sc;

--- 15 unchanged lines hidden (view full) ---

1696#endif
1697
1698 if (rxs->rxs_mbuf != NULL) {
1699 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
1700 BUS_DMASYNC_POSTREAD);
1701 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
1702 }
1703
1717/*
1718 * gem_add_rxbuf:
1719 *
1720 * Add a receive buffer to the indicated descriptor.
1721 */
1722static int
1723gem_add_rxbuf(sc, idx)
1724 struct gem_softc *sc;

--- 15 unchanged lines hidden (view full) ---

1740#endif
1741
1742 if (rxs->rxs_mbuf != NULL) {
1743 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
1744 BUS_DMASYNC_POSTREAD);
1745 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
1746 }
1747
1704 rxs->rxs_mbuf = m;
1705
1706 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap,
1707 m, segs, &nsegs, BUS_DMA_NOWAIT);
1708 /* If nsegs is wrong then the stack is corrupt. */
1709 KASSERT(nsegs == 1, ("Too many segments returned!"));
1710 if (error != 0) {
1711 device_printf(sc->sc_dev, "can't load rx DMA map %d, error = "
1712 "%d\n", idx, error);
1713 m_freem(m);
1748 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap,
1749 m, segs, &nsegs, BUS_DMA_NOWAIT);
1750 /* If nsegs is wrong then the stack is corrupt. */
1751 KASSERT(nsegs == 1, ("Too many segments returned!"));
1752 if (error != 0) {
1753 device_printf(sc->sc_dev, "can't load rx DMA map %d, error = "
1754 "%d\n", idx, error);
1755 m_freem(m);
1714 return (ENOBUFS);
1756 return (error);
1715 }
1757 }
1758 rxs->rxs_mbuf = m;
1716 rxs->rxs_paddr = segs[0].ds_addr;
1717
1718 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
1719
1720 GEM_INIT_RXDESC(sc, idx);
1721
1722 return (0);
1723}
1724
1759 rxs->rxs_paddr = segs[0].ds_addr;
1760
1761 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
1762
1763 GEM_INIT_RXDESC(sc, idx);
1764
1765 return (0);
1766}
1767
1725
1726static void
1727gem_eint(sc, status)
1728 struct gem_softc *sc;
1729 u_int status;
1730{
1731
1768static void
1769gem_eint(sc, status)
1770 struct gem_softc *sc;
1771 u_int status;
1772{
1773
1732 if ((status & GEM_INTR_MIF) != 0) {
1733 device_printf(sc->sc_dev, "XXXlink status changed\n");
1774 sc->sc_ifp->if_ierrors++;
1775 if ((status & GEM_INTR_RX_TAG_ERR) != 0) {
1776 gem_reset_rxdma(sc);
1734 return;
1735 }
1736
1777 return;
1778 }
1779
1737 device_printf(sc->sc_dev, "status=%x\n", status);
1780 device_printf(sc->sc_dev, "%s: status=%x\n", __func__, status);
1738}
1739
1781}
1782
1740
1741void
1742gem_intr(v)
1743 void *v;
1744{
1745 struct gem_softc *sc = (struct gem_softc *)v;
1783void
1784gem_intr(v)
1785 void *v;
1786{
1787 struct gem_softc *sc = (struct gem_softc *)v;
1746 u_int32_t status;
1788 uint32_t status, status2;
1747
1748 GEM_LOCK(sc);
1749 status = bus_read_4(sc->sc_res[0], GEM_STATUS);
1789
1790 GEM_LOCK(sc);
1791 status = bus_read_4(sc->sc_res[0], GEM_STATUS);
1792
1750#ifdef GEM_DEBUG
1751 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x",
1752 device_get_name(sc->sc_dev), __func__, (status>>19),
1753 (u_int)status);
1793#ifdef GEM_DEBUG
1794 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x",
1795 device_get_name(sc->sc_dev), __func__, (status>>19),
1796 (u_int)status);
1797
1798 /*
1799 * PCS interrupts must be cleared, otherwise no traffic is passed!
1800 */
1801 if ((status & GEM_INTR_PCS) != 0) {
1802 status2 = bus_read_4(sc->sc_res[0], GEM_MII_INTERRUP_STATUS) |
1803 bus_read_4(sc->sc_res[0], GEM_MII_INTERRUP_STATUS);
1804 if ((status2 & GEM_MII_INTERRUP_LINK) != 0)
1805 device_printf(sc->sc_dev,
1806 "%s: PCS link status changed\n", __func__);
1807 }
1808 if ((status & GEM_MAC_CONTROL_STATUS) != 0) {
1809 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS);
1810 if ((status2 & GEM_MAC_PAUSED) != 0)
1811 device_printf(sc->sc_dev,
1812 "%s: PAUSE received (PAUSE time %d slots)\n",
1813 __func__, GEM_MAC_PAUSE_TIME(status2));
1814 if ((status2 & GEM_MAC_PAUSE) != 0)
1815 device_printf(sc->sc_dev,
1816 "%s: transited to PAUSE state\n", __func__);
1817 if ((status2 & GEM_MAC_RESUME) != 0)
1818 device_printf(sc->sc_dev,
1819 "%s: transited to non-PAUSE state\n", __func__);
1820 }
1821 if ((status & GEM_INTR_MIF) != 0)
1822 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__);
1754#endif
1755
1823#endif
1824
1756 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
1825 if ((status &
1826 (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0)
1757 gem_eint(sc, status);
1758
1827 gem_eint(sc, status);
1828
1759 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1760 gem_tint(sc);
1761
1762 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1763 gem_rint(sc);
1764
1829 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1830 gem_rint(sc);
1831
1765 /* We should eventually do more than just print out error stats. */
1832 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1833 gem_tint(sc);
1834
1766 if (status & GEM_INTR_TX_MAC) {
1835 if (status & GEM_INTR_TX_MAC) {
1767 int txstat = bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS);
1768 if (txstat & ~GEM_MAC_TX_XMIT_DONE)
1836 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS);
1837 if (status2 & ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP))
1769 device_printf(sc->sc_dev, "MAC tx fault, status %x\n",
1838 device_printf(sc->sc_dev, "MAC tx fault, status %x\n",
1770 txstat);
1771 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
1839 status2);
1840 if (status2 & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
1772 gem_init_locked(sc);
1773 }
1774 if (status & GEM_INTR_RX_MAC) {
1841 gem_init_locked(sc);
1842 }
1843 if (status & GEM_INTR_RX_MAC) {
1775 int rxstat = bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS);
1844 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS);
1776 /*
1845 /*
1777 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often
1778 * due to a silicon bug so handle them silently.
1846 * At least with GEM_SUN_GEM and some GEM_SUN_ERI
1847 * revisions GEM_MAC_RX_OVERFLOW happen often due to a
1848 * silicon bug so handle them silently. Moreover, it's
1849 * likely that the receiver has hung so we reset it.
1779 */
1850 */
1780 if (rxstat & GEM_MAC_RX_OVERFLOW)
1781 gem_init_locked(sc);
1782 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
1851 if (status2 & GEM_MAC_RX_OVERFLOW) {
1852 sc->sc_ifp->if_ierrors++;
1853 gem_reset_rxdma(sc);
1854 } else if (status2 & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
1783 device_printf(sc->sc_dev, "MAC rx fault, status %x\n",
1855 device_printf(sc->sc_dev, "MAC rx fault, status %x\n",
1784 rxstat);
1856 status2);
1785 }
1786 GEM_UNLOCK(sc);
1787}
1788
1789static int
1790gem_watchdog(sc)
1791 struct gem_softc *sc;
1792{

--- 11 unchanged lines hidden (view full) ---

1804 bus_read_4(sc->sc_res[0], GEM_TX_CONFIG),
1805 bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS),
1806 bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG));
1807#endif
1808
1809 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
1810 return (0);
1811
1857 }
1858 GEM_UNLOCK(sc);
1859}
1860
1861static int
1862gem_watchdog(sc)
1863 struct gem_softc *sc;
1864{

--- 11 unchanged lines hidden (view full) ---

1876 bus_read_4(sc->sc_res[0], GEM_TX_CONFIG),
1877 bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS),
1878 bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG));
1879#endif
1880
1881 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
1882 return (0);
1883
1812 device_printf(sc->sc_dev, "device timeout\n");
1884 if ((sc->sc_flags & GEM_LINK) != 0)
1885 device_printf(sc->sc_dev, "device timeout\n");
1886 else if (bootverbose)
1887 device_printf(sc->sc_dev, "device timeout (no link)\n");
1813 ++sc->sc_ifp->if_oerrors;
1814
1815 /* Try to get more packets going. */
1816 gem_init_locked(sc);
1817 return (EJUSTRETURN);
1818}
1819
1820/*
1821 * Initialize the MII Management Interface
1822 */
1823static void
1824gem_mifinit(sc)
1825 struct gem_softc *sc;
1826{
1827
1828 /* Configure the MIF in frame mode */
1888 ++sc->sc_ifp->if_oerrors;
1889
1890 /* Try to get more packets going. */
1891 gem_init_locked(sc);
1892 return (EJUSTRETURN);
1893}
1894
1895/*
1896 * Initialize the MII Management Interface
1897 */
1898static void
1899gem_mifinit(sc)
1900 struct gem_softc *sc;
1901{
1902
1903 /* Configure the MIF in frame mode */
1829 sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
1830 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
1831 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, sc->sc_mif_config);
1904 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, bus_read_4(sc->sc_res[0],
1905 GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA);
1832}
1833
1834/*
1835 * MII interface
1836 *
1837 * The GEM MII interface supports at least three different operating modes:
1838 *
1839 * Bitbang mode is implemented using data, clock and output enable registers.

--- 10 unchanged lines hidden (view full) ---

1850 device_t dev;
1851 int phy, reg;
1852{
1853 struct gem_softc *sc = device_get_softc(dev);
1854 int n;
1855 u_int32_t v;
1856
1857#ifdef GEM_DEBUG_PHY
1906}
1907
1908/*
1909 * MII interface
1910 *
1911 * The GEM MII interface supports at least three different operating modes:
1912 *
1913 * Bitbang mode is implemented using data, clock and output enable registers.

--- 10 unchanged lines hidden (view full) ---

1924 device_t dev;
1925 int phy, reg;
1926{
1927 struct gem_softc *sc = device_get_softc(dev);
1928 int n;
1929 u_int32_t v;
1930
1931#ifdef GEM_DEBUG_PHY
1858 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
1932 printf("%s: phy %d reg %d\n", __func__, phy, reg);
1859#endif
1860
1933#endif
1934
1861#if 0
1862 /* Select the desired PHY in the MIF configuration register */
1863 v = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
1864 /* Clear PHY select bit */
1865 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1866 if (phy == GEM_PHYAD_EXTERNAL)
1867 /* Set PHY select bit to get at external device */
1868 v |= GEM_MIF_CONFIG_PHY_SEL;
1869 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
1870#endif
1935 if (sc->sc_phyad != -1 && phy != sc->sc_phyad)
1936 return (0);
1871
1937
1938 if ((sc->sc_flags & GEM_SERDES) != 0) {
1939 switch (reg) {
1940 case MII_BMCR:
1941 reg = GEM_MII_CONTROL;
1942 break;
1943 case MII_BMSR:
1944 reg = GEM_MII_STATUS;
1945 break;
1946 case MII_PHYIDR1:
1947 case MII_PHYIDR2:
1948 return (0);
1949 case MII_ANAR:
1950 reg = GEM_MII_ANAR;
1951 break;
1952 case MII_ANLPAR:
1953 reg = GEM_MII_ANLPAR;
1954 break;
1955 case MII_EXTSR:
1956 return (EXTSR_1000XFDX | EXTSR_1000XHDX);
1957 default:
1958 device_printf(sc->sc_dev,
1959 "%s: unhandled register %d\n", __func__, reg);
1960 return (0);
1961 }
1962 return (bus_read_4(sc->sc_res[0], reg));
1963 }
1964
1872 /* Construct the frame command */
1965 /* Construct the frame command */
1873 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |
1874 GEM_MIF_FRAME_READ;
1966 v = GEM_MIF_FRAME_READ |
1967 (phy << GEM_MIF_PHY_SHIFT) |
1968 (reg << GEM_MIF_REG_SHIFT);
1875
1876 bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
1877 for (n = 0; n < 100; n++) {
1878 DELAY(1);
1879 v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
1880 if (v & GEM_MIF_FRAME_TA0)
1881 return (v & GEM_MIF_FRAME_DATA);
1882 }

--- 7 unchanged lines hidden (view full) ---

1890 device_t dev;
1891 int phy, reg, val;
1892{
1893 struct gem_softc *sc = device_get_softc(dev);
1894 int n;
1895 u_int32_t v;
1896
1897#ifdef GEM_DEBUG_PHY
1969
1970 bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
1971 for (n = 0; n < 100; n++) {
1972 DELAY(1);
1973 v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
1974 if (v & GEM_MIF_FRAME_TA0)
1975 return (v & GEM_MIF_FRAME_DATA);
1976 }

--- 7 unchanged lines hidden (view full) ---

1984 device_t dev;
1985 int phy, reg, val;
1986{
1987 struct gem_softc *sc = device_get_softc(dev);
1988 int n;
1989 u_int32_t v;
1990
1991#ifdef GEM_DEBUG_PHY
1898 printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val);
1992 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__);
1899#endif
1900
1993#endif
1994
1901#if 0
1902 /* Select the desired PHY in the MIF configuration register */
1903 v = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
1904 /* Clear PHY select bit */
1905 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1906 if (phy == GEM_PHYAD_EXTERNAL)
1907 /* Set PHY select bit to get at external device */
1908 v |= GEM_MIF_CONFIG_PHY_SEL;
1909 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
1910#endif
1995 if (sc->sc_phyad != -1 && phy != sc->sc_phyad)
1996 return (0);
1997
1998 if ((sc->sc_flags & GEM_SERDES) != 0) {
1999 switch (reg) {
2000 case MII_BMCR:
2001 reg = GEM_MII_CONTROL;
2002 break;
2003 case MII_BMSR:
2004 reg = GEM_MII_STATUS;
2005 break;
2006 case MII_ANAR:
2007 bus_write_4(sc->sc_res[0], GEM_MII_CONFIG, 0);
2008 bus_barrier(sc->sc_res[0], GEM_MII_CONFIG, 4,
2009 BUS_SPACE_BARRIER_WRITE);
2010 bus_write_4(sc->sc_res[0], GEM_MII_ANAR, val);
2011 bus_write_4(sc->sc_res[0], GEM_MII_SLINK_CONTROL,
2012 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
2013 bus_write_4(sc->sc_res[0], GEM_MII_CONFIG,
2014 GEM_MII_CONFIG_ENABLE);
2015 return (0);
2016 case MII_ANLPAR:
2017 reg = GEM_MII_ANLPAR;
2018 break;
2019 default:
2020 device_printf(sc->sc_dev,
2021 "%s: unhandled register %d\n", __func__, reg);
2022 return (0);
2023 }
2024 bus_write_4(sc->sc_res[0], reg, val);
2025 return (0);
2026 }
2027
1911 /* Construct the frame command */
2028 /* Construct the frame command */
1912 v = GEM_MIF_FRAME_WRITE |
1913 (phy << GEM_MIF_PHY_SHIFT) |
1914 (reg << GEM_MIF_REG_SHIFT) |
2029 v = GEM_MIF_FRAME_WRITE |
2030 (phy << GEM_MIF_PHY_SHIFT) |
2031 (reg << GEM_MIF_REG_SHIFT) |
1915 (val & GEM_MIF_FRAME_DATA);
1916
1917 bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
1918 for (n = 0; n < 100; n++) {
1919 DELAY(1);
1920 v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
1921 if (v & GEM_MIF_FRAME_TA0)
1922 return (1);
1923 }
1924
1925 device_printf(sc->sc_dev, "mii_write timeout\n");
1926 return (0);
1927}
1928
1929void
1930gem_mii_statchg(dev)
1931 device_t dev;
1932{
1933 struct gem_softc *sc = device_get_softc(dev);
2032 (val & GEM_MIF_FRAME_DATA);
2033
2034 bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
2035 for (n = 0; n < 100; n++) {
2036 DELAY(1);
2037 v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
2038 if (v & GEM_MIF_FRAME_TA0)
2039 return (1);
2040 }
2041
2042 device_printf(sc->sc_dev, "mii_write timeout\n");
2043 return (0);
2044}
2045
2046void
2047gem_mii_statchg(dev)
2048 device_t dev;
2049{
2050 struct gem_softc *sc = device_get_softc(dev);
1934#ifdef GEM_DEBUG
1935 int instance;
1936#endif
1937 u_int32_t v;
2051 int gigabit;
2052 uint32_t rxcfg, txcfg, v;
1938
1939#ifdef GEM_DEBUG
2053
2054#ifdef GEM_DEBUG
1940 instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media);
1941 if (sc->sc_debug)
1942 printf("gem_mii_statchg: status change: phy = %d\n",
1943 sc->sc_phys[instance]);
2055 if ((sc->sc_ifflags & IFF_DEBUG) != 0)
2056 device_printf(sc->sc_dev, "%s: status change: PHY = %d\n",
2057 __func__, sc->sc_phyad);
1944#endif
1945
2058#endif
2059
1946 /* Set tx full duplex options */
1947 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, 0);
1948 DELAY(10000); /* reg must be cleared and delay before changing. */
1949 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT|
1950 GEM_MAC_TX_ENABLE;
1951 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) {
1952 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS;
2060 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 &&
2061 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE)
2062 sc->sc_flags |= GEM_LINK;
2063 else
2064 sc->sc_flags &= ~GEM_LINK;
2065
2066 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) {
2067 case IFM_1000_SX:
2068 case IFM_1000_LX:
2069 case IFM_1000_CX:
2070 case IFM_1000_T:
2071 gigabit = 1;
2072 break;
2073 default:
2074 gigabit = 0;
1953 }
2075 }
1954 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, v);
1955
2076
2077 /*
2078 * The configuration done here corresponds to the steps F) and
2079 * G) and as far as enabling of RX and TX MAC goes also step H)
2080 * of the initialization sequence outlined in section 3.2.1 of
2081 * the GEM Gigabit Ethernet ASIC Specification.
2082 */
2083
2084 rxcfg = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
2085 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE);
2086 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT;
2087 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2088 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS;
2089 else if (gigabit != 0) {
2090 rxcfg |= GEM_MAC_RX_CARR_EXTEND;
2091 txcfg |= GEM_MAC_TX_CARR_EXTEND;
2092 }
2093 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, 0);
2094 bus_barrier(sc->sc_res[0], GEM_MAC_TX_CONFIG, 4,
2095 BUS_SPACE_BARRIER_WRITE);
2096 if (!gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0))
2097 device_printf(sc->sc_dev, "cannot disable TX MAC\n");
2098 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, txcfg);
2099 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, 0);
2100 bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
2101 BUS_SPACE_BARRIER_WRITE);
2102 if (!gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
2103 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
2104 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, rxcfg);
2105
2106 v = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_CONFIG) &
2107 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE);
2108#ifdef notyet
2109 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2110 v |= GEM_MAC_CC_RX_PAUSE;
2111 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2112 v |= GEM_MAC_CC_TX_PAUSE;
2113#endif
2114 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_CONFIG, v);
2115
2116 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 &&
2117 gigabit != 0)
2118 bus_write_4(sc->sc_res[0], GEM_MAC_SLOT_TIME,
2119 GEM_MAC_SLOT_TIME_CARR_EXTEND);
2120 else
2121 bus_write_4(sc->sc_res[0], GEM_MAC_SLOT_TIME,
2122 GEM_MAC_SLOT_TIME_NORMAL);
2123
1956 /* XIF Configuration */
1957 v = GEM_MAC_XIF_LINK_LED;
1958 v |= GEM_MAC_XIF_TX_MII_ENA;
2124 /* XIF Configuration */
2125 v = GEM_MAC_XIF_LINK_LED;
2126 v |= GEM_MAC_XIF_TX_MII_ENA;
1959
1960 /* If an external transceiver is connected, enable its MII drivers */
1961 sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
1962 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
1963 /* External MII needs echo disable if half duplex. */
1964 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
1965 /* turn on full duplex LED */
1966 v |= GEM_MAC_XIF_FDPLX_LED;
2127 if ((sc->sc_flags & GEM_SERDES) == 0) {
2128 if ((bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG) &
2129 GEM_MIF_CONFIG_PHY_SEL) != 0 &&
2130 (IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0)
2131 /* External MII needs echo disable if half duplex. */
2132 v |= GEM_MAC_XIF_ECHO_DISABL;
1967 else
2133 else
1968 /* half duplex -- disable echo */
1969 v |= GEM_MAC_XIF_ECHO_DISABL;
1970
1971 if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T)
1972 v |= GEM_MAC_XIF_GMII_MODE;
1973 else
1974 v &= ~GEM_MAC_XIF_GMII_MODE;
1975 } else {
1976 /* Internal MII needs buf enable */
1977 v |= GEM_MAC_XIF_MII_BUF_ENA;
2134 /*
2135 * Internal MII needs buffer enable.
2136 * XXX buffer enable makes only sense for an
2137 * external PHY.
2138 */
2139 v |= GEM_MAC_XIF_MII_BUF_ENA;
1978 }
2140 }
2141 if (gigabit != 0)
2142 v |= GEM_MAC_XIF_GMII_MODE;
2143 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2144 v |= GEM_MAC_XIF_FDPLX_LED;
1979 bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, v);
2145 bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, v);
2146
2147 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2148 (sc->sc_flags & GEM_LINK) != 0) {
2149 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG,
2150 txcfg | GEM_MAC_TX_ENABLE);
2151 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG,
2152 rxcfg | GEM_MAC_RX_ENABLE);
2153 }
1980}
1981
1982int
1983gem_mediachange(ifp)
1984 struct ifnet *ifp;
1985{
1986 struct gem_softc *sc = ifp->if_softc;
1987 int error;

--- 37 unchanged lines hidden (view full) ---

2025 struct gem_softc *sc = ifp->if_softc;
2026 struct ifreq *ifr = (struct ifreq *)data;
2027 int error = 0;
2028
2029 switch (cmd) {
2030 case SIOCSIFFLAGS:
2031 GEM_LOCK(sc);
2032 if (ifp->if_flags & IFF_UP) {
2154}
2155
2156int
2157gem_mediachange(ifp)
2158 struct ifnet *ifp;
2159{
2160 struct gem_softc *sc = ifp->if_softc;
2161 int error;

--- 37 unchanged lines hidden (view full) ---

2199 struct gem_softc *sc = ifp->if_softc;
2200 struct ifreq *ifr = (struct ifreq *)data;
2201 int error = 0;
2202
2203 switch (cmd) {
2204 case SIOCSIFFLAGS:
2205 GEM_LOCK(sc);
2206 if (ifp->if_flags & IFF_UP) {
2033 if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC)
2207 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2208 ((ifp->if_flags ^ sc->sc_ifflags) &
2209 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
2034 gem_setladrf(sc);
2035 else
2036 gem_init_locked(sc);
2037 } else {
2038 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2039 gem_stop(ifp, 0);
2040 }
2041 if ((ifp->if_flags & IFF_LINK0) != 0)

--- 54 unchanged lines hidden (view full) ---

2096 /*
2097 * Turn off promiscuous mode, promiscuous group mode (all multicast),
2098 * and hash filter. Depending on the case, the right bit will be
2099 * enabled.
2100 */
2101 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
2102 GEM_MAC_RX_PROMISC_GRP);
2103
2210 gem_setladrf(sc);
2211 else
2212 gem_init_locked(sc);
2213 } else {
2214 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2215 gem_stop(ifp, 0);
2216 }
2217 if ((ifp->if_flags & IFF_LINK0) != 0)

--- 54 unchanged lines hidden (view full) ---

2272 /*
2273 * Turn off promiscuous mode, promiscuous group mode (all multicast),
2274 * and hash filter. Depending on the case, the right bit will be
2275 * enabled.
2276 */
2277 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
2278 GEM_MAC_RX_PROMISC_GRP);
2279
2280 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
2281 bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
2282 BUS_SPACE_BARRIER_WRITE);
2283 if (!gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER, 0))
2284 device_printf(sc->sc_dev, "cannot disable RX hash filter\n");
2285
2104 if ((ifp->if_flags & IFF_PROMISC) != 0) {
2286 if ((ifp->if_flags & IFF_PROMISC) != 0) {
2105 /* Turn on promiscuous mode */
2106 v |= GEM_MAC_RX_PROMISCUOUS;
2107 goto chipit;
2108 }
2109 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
2287 v |= GEM_MAC_RX_PROMISCUOUS;
2288 goto chipit;
2289 }
2290 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
2110 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
2111 ifp->if_flags |= IFF_ALLMULTI;
2112 v |= GEM_MAC_RX_PROMISC_GRP;
2113 goto chipit;
2114 }
2115
2116 /*
2117 * Set up multicast address filter by passing all multicast addresses
2118 * through a crc generator, and then using the high order 8 bits as an
2119 * index into the 256 bit logical address filter. The high order 4

--- 15 unchanged lines hidden (view full) ---

2135 crc >>= 24;
2136
2137 /* Set the corresponding bit in the filter. */
2138 hash[crc >> 4] |= 1 << (15 - (crc & 15));
2139 }
2140 IF_ADDR_UNLOCK(ifp);
2141
2142 v |= GEM_MAC_RX_HASH_FILTER;
2291 v |= GEM_MAC_RX_PROMISC_GRP;
2292 goto chipit;
2293 }
2294
2295 /*
2296 * Set up multicast address filter by passing all multicast addresses
2297 * through a crc generator, and then using the high order 8 bits as an
2298 * index into the 256 bit logical address filter. The high order 4

--- 15 unchanged lines hidden (view full) ---

2314 crc >>= 24;
2315
2316 /* Set the corresponding bit in the filter. */
2317 hash[crc >> 4] |= 1 << (15 - (crc & 15));
2318 }
2319 IF_ADDR_UNLOCK(ifp);
2320
2321 v |= GEM_MAC_RX_HASH_FILTER;
2143 ifp->if_flags &= ~IFF_ALLMULTI;
2144
2145 /* Now load the hash table into the chip (if we are using it) */
2146 for (i = 0; i < 16; i++) {
2147 bus_write_4(sc->sc_res[0],
2148 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
2149 hash[i]);
2150 }
2151
2152chipit:
2153 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
2154}
2322
2323 /* Now load the hash table into the chip (if we are using it) */
2324 for (i = 0; i < 16; i++) {
2325 bus_write_4(sc->sc_res[0],
2326 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
2327 hash[i]);
2328 }
2329
2330chipit:
2331 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
2332}