| mb86960.h (8027) | mb86960.h (21694) |
|---|---|
| 1/* 2 * All Rights Reserved, Copyright (C) Fujitsu Limited 1995 3 * 4 * This software may be used, modified, copied, distributed, and sold, in 5 * both source and binary form provided that the above copyright, these 6 * terms and the following disclaimer are retained. The name of the author 7 * and/or the contributor may not be used to endorse or promote products 8 * derived from this software without specific prior written permission. --- 6 unchanged lines hidden (view full) --- 15 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 16 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 19 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 20 * SUCH DAMAGE. 21 */ 22 | 1/* 2 * All Rights Reserved, Copyright (C) Fujitsu Limited 1995 3 * 4 * This software may be used, modified, copied, distributed, and sold, in 5 * both source and binary form provided that the above copyright, these 6 * terms and the following disclaimer are retained. The name of the author 7 * and/or the contributor may not be used to endorse or promote products 8 * derived from this software without specific prior written permission. --- 6 unchanged lines hidden (view full) --- 15 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 16 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 19 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 20 * SUCH DAMAGE. 21 */ 22 |
| 23#define FE_MB86960_H_VERSION "mb86960.h ver. 0.8" 24 | |
| 25/* | 23/* |
| 26 * Registers of Fujitsu MB86960A/MB86965A Ethernet controller. | 24 * Registers of Fujitsu MB86960A/MB86965A series Ethernet controllers. |
| 27 * Written and contributed by M.S. <seki@sysrap.cs.fujitsu.co.jp> 28 */ 29 30/* 31 * Notes on register naming: 32 * 33 * Fujitsu documents for MB86960A/MB86965A uses no mnemorable names 34 * for their registers. They defined only three names for 32 --- 44 unchanged lines hidden (view full) --- 79#define FE_BMPR9 9 80#define FE_BMPR10 10 81#define FE_BMPR11 11 82#define FE_BMPR12 12 83#define FE_BMPR13 13 84#define FE_BMPR14 14 85#define FE_BMPR15 15 86 | 25 * Written and contributed by M.S. <seki@sysrap.cs.fujitsu.co.jp> 26 */ 27 28/* 29 * Notes on register naming: 30 * 31 * Fujitsu documents for MB86960A/MB86965A uses no mnemorable names 32 * for their registers. They defined only three names for 32 --- 44 unchanged lines hidden (view full) --- 77#define FE_BMPR9 9 78#define FE_BMPR10 10 79#define FE_BMPR11 11 80#define FE_BMPR12 12 81#define FE_BMPR13 13 82#define FE_BMPR14 14 83#define FE_BMPR15 15 84 |
| 87/* More BMPRs, only on MB86965A, accessible only when JLI mode. */ | 85/* More BMPRs, only on 86965, accessible only when JLI mode. */ |
| 88#define FE_BMPR16 16 89#define FE_BMPR17 17 90#define FE_BMPR18 18 91#define FE_BMPR19 19 92 93/* 94 * Definitions of registers. 95 * I don't have Fujitsu documents of MB86960A/MB86965A, so I don't 96 * know the official names for each flags and fields. The following 97 * names are assigned by me (the author of this file,) since I cannot 98 * mnemorize hexadecimal constants for all of these functions. | 86#define FE_BMPR16 16 87#define FE_BMPR17 17 88#define FE_BMPR18 18 89#define FE_BMPR19 19 90 91/* 92 * Definitions of registers. 93 * I don't have Fujitsu documents of MB86960A/MB86965A, so I don't 94 * know the official names for each flags and fields. The following 95 * names are assigned by me (the author of this file,) since I cannot 96 * mnemorize hexadecimal constants for all of these functions. |
| 99 * Comments? FIXME. | 97 * Comments? 98 * 99 * I've got documents from Fujitsu web site, recently. However, it's 100 * too late. Names for some fields (bits) are kept different from 101 * those used in the Fujitsu documents... |
| 100 */ 101 102/* DLCR0 -- transmitter status */ | 102 */ 103 104/* DLCR0 -- transmitter status */ |
| 103#define FE_D0_BUSERR 0x01 /* Bus write error */ | 105#define FE_D0_BUSERR 0x01 /* Bus write error? */ |
| 104#define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */ 105#define FE_D0_COLLID 0x04 /* Collision on last transmission */ 106#define FE_D0_JABBER 0x08 /* Jabber */ 107#define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */ | 106#define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */ 107#define FE_D0_COLLID 0x04 /* Collision on last transmission */ 108#define FE_D0_JABBER 0x08 /* Jabber */ 109#define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */ |
| 108#define FE_D0_PKTRCD 0x20 /* No corrision on last transmission */ | 110#define FE_D0_PKTRCD 0x20 /* Last packet looped back correctly */ |
| 109#define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */ 110#define FE_D0_TXDONE 0x80 /* Transmission complete */ 111 112/* DLCR1 -- receiver status */ 113#define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */ 114#define FE_D1_CRCERR 0x02 /* CRC error on last packet */ 115#define FE_D1_ALGERR 0x04 /* Alignment error on last packet */ 116#define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */ --- 19 unchanged lines hidden (view full) --- 136#define FE_D3_RMTRST FE_D1_RMTRST 137#define FE_D3_DMAEOP FE_D1_DMAEOP 138#define FE_D3_BUSERR FE_D1_BUSERR 139#define FE_D3_PKTRDY FE_D1_PKTRDY 140 141/* DLCR4 -- transmitter operation mode */ 142#define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */ 143#define FE_D4_LBC 0x02 /* Loop back test control */ | 111#define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */ 112#define FE_D0_TXDONE 0x80 /* Transmission complete */ 113 114/* DLCR1 -- receiver status */ 115#define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */ 116#define FE_D1_CRCERR 0x02 /* CRC error on last packet */ 117#define FE_D1_ALGERR 0x04 /* Alignment error on last packet */ 118#define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */ --- 19 unchanged lines hidden (view full) --- 138#define FE_D3_RMTRST FE_D1_RMTRST 139#define FE_D3_DMAEOP FE_D1_DMAEOP 140#define FE_D3_BUSERR FE_D1_BUSERR 141#define FE_D3_PKTRDY FE_D1_PKTRDY 142 143/* DLCR4 -- transmitter operation mode */ 144#define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */ 145#define FE_D4_LBC 0x02 /* Loop back test control */ |
| 144#define FE_D4_CNTRL 0x04 /* - ??? */ | 146#define FE_D4_CNTRL 0x04 /* - tied to CNTRL pin of the chip */ |
| 145#define FE_D4_TEST1 0x08 /* Test output #1 */ 146#define FE_D4_COL 0xF0 /* Collision counter */ 147 148#define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */ 149#define FE_D4_LBC_DISABLE 0x02 /* Normal operation */ 150 151#define FE_D4_COL_SHIFT 4 152 --- 50 unchanged lines hidden (view full) --- 203 204#define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */ 205#define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */ 206#define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */ 207 208#define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */ 209#define FE_D7_POWER_UP 0x20 /* Normal operation */ 210 | 147#define FE_D4_TEST1 0x08 /* Test output #1 */ 148#define FE_D4_COL 0xF0 /* Collision counter */ 149 150#define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */ 151#define FE_D4_LBC_DISABLE 0x02 /* Normal operation */ 152 153#define FE_D4_COL_SHIFT 4 154 --- 50 unchanged lines hidden (view full) --- 205 206#define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */ 207#define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */ 208#define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */ 209 210#define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */ 211#define FE_D7_POWER_UP 0x20 /* Normal operation */ 212 |
| 211#define FE_D7_IDENT_NICE 0x80 212#define FE_D7_IDENT_EC 0xC0 | 213#define FE_D7_IDENT_TDK 0x00 /* TDK chips? */ 214#define FE_D7_IDENT_NICE 0x80 /* Fujitsu NICE (86960) */ 215#define FE_D7_IDENT_EC 0xC0 /* Fujitsu EtherCoupler (86965) */ |
| 213 214/* DLCR8 thru DLCR13 are for Ethernet station address. */ 215 | 216 217/* DLCR8 thru DLCR13 are for Ethernet station address. */ 218 |
| 216/* DLCR14 and DLCR15 are for TDR. (BTW, what is TDR? FIXME.) */ | 219/* DLCR14 and DLCR15 are for TDR. (TDR is used for cable diagnostic.) */ |
| 217 218/* MAR8 thru MAR15 are for Multicast address filter. */ 219 220/* BMPR8 and BMPR9 are for packet data. */ 221 222/* BMPR10 -- transmitter start trigger */ 223#define FE_B10_START 0x80 /* Start transmitter */ 224#define FE_B10_COUNT 0x7F /* Packet count */ --- 11 unchanged lines hidden (view full) --- 236#define FE_B12_RXDMA 0x02 /* Enable receiver DMA */ 237 238/* BMPR13 -- DMA control */ 239#define FE_B13_BSTCTL 0x03 /* DMA burst mode control */ 240#define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */ 241#define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */ 242#define FE_B13_LNKTST 0x20 /* Link test enable */ 243#define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */ | 220 221/* MAR8 thru MAR15 are for Multicast address filter. */ 222 223/* BMPR8 and BMPR9 are for packet data. */ 224 225/* BMPR10 -- transmitter start trigger */ 226#define FE_B10_START 0x80 /* Start transmitter */ 227#define FE_B10_COUNT 0x7F /* Packet count */ --- 11 unchanged lines hidden (view full) --- 239#define FE_B12_RXDMA 0x02 /* Enable receiver DMA */ 240 241/* BMPR13 -- DMA control */ 242#define FE_B13_BSTCTL 0x03 /* DMA burst mode control */ 243#define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */ 244#define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */ 245#define FE_B13_LNKTST 0x20 /* Link test enable */ 246#define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */ |
| 244#define FE_B13_IOUNLK 0x80 /* Change I/O base address */ | 247#define FE_B13_IOUNLK 0x80 /* Change I/O base address, on JLI mode */ |
| 245 246#define FE_B13_BSTCTL_1 0x00 247#define FE_B13_BSTCTL_4 0x01 248#define FE_B13_BSTCTL_8 0x02 249#define FE_B13_BSTCLT_12 0x03 250 251#define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */ 252#define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */ --- 22 unchanged lines hidden (view full) --- 275#define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */ 276#define FE_B16_SELECT 0x20 /* EEPROM chip select */ 277#define FE_B16_CLOCK 0x40 /* EEPROM shift clock */ 278#define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */ 279 280/* BMPR17 -- EEPROM data */ 281#define FE_B17_DATA 0x80 /* EEPROM data bit */ 282 | 248 249#define FE_B13_BSTCTL_1 0x00 250#define FE_B13_BSTCTL_4 0x01 251#define FE_B13_BSTCTL_8 0x02 252#define FE_B13_BSTCLT_12 0x03 253 254#define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */ 255#define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */ --- 22 unchanged lines hidden (view full) --- 278#define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */ 279#define FE_B16_SELECT 0x20 /* EEPROM chip select */ 280#define FE_B16_CLOCK 0x40 /* EEPROM shift clock */ 281#define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */ 282 283/* BMPR17 -- EEPROM data */ 284#define FE_B17_DATA 0x80 /* EEPROM data bit */ 285 |
| 283/* BMPR18 ??? */ | 286/* BMPR18 -- cycle I/O address setting in JLI mode */ |
| 284 | 287 |
| 285/* BMPR19 -- ISA interface configuration */ | 288/* BMPR19 -- ISA interface configuration in JLI mode */ |
| 286#define FE_B19_IRQ 0xC0 287#define FE_B19_IRQ_SHIFT 6 288 289#define FE_B19_ROM 0x38 290#define FE_B19_ROM_SHIFT 3 291 292#define FE_B19_ADDR 0x07 293#define FE_B19_ADDR_SHIFT 0 294 295/* | 289#define FE_B19_IRQ 0xC0 290#define FE_B19_IRQ_SHIFT 6 291 292#define FE_B19_ROM 0x38 293#define FE_B19_ROM_SHIFT 3 294 295#define FE_B19_ADDR 0x07 296#define FE_B19_ADDR_SHIFT 0 297 298/* |
| 299 * An extra I/O port address to reset 86965. This location is called 300 * "ID ROM area" by Fujitsu document. 301 */ 302 303/* 304 * Flags in Receive Packet Header... Basically same layout as DLCR1. 305 */ 306#define FE_RPH_OVRFLO FE_D1_OVRFLO 307#define FE_RPH_CRCERR FE_D1_CRCERR 308#define FE_RPH_ALGERR FE_D1_ALGERR 309#define FE_RPH_SRTPKT FE_D1_SRTPKT 310#define FE_RPH_RMTRST FE_D1_RMTRST 311#define FE_RPH_GOOD 0x20 /* Good packet follows */ 312 313/* |
|
| 296 * EEPROM specification (of JLI mode). 297 */ 298 299/* Number of bytes in an EEPROM accessible through 86965. */ 300#define FE_EEPROM_SIZE 32 301 302/* Offset for JLI config; automatically copied into BMPR19 at startup. */ 303#define FE_EEPROM_CONF 0 304 305/* | 314 * EEPROM specification (of JLI mode). 315 */ 316 317/* Number of bytes in an EEPROM accessible through 86965. */ 318#define FE_EEPROM_SIZE 32 319 320/* Offset for JLI config; automatically copied into BMPR19 at startup. */ 321#define FE_EEPROM_CONF 0 322 323/* |
| 306 * Some 86960 specific constants. | 324 * Some 8696x specific constants. |
| 307 */ 308 309/* Length (in bytes) of a Multicast Address Filter. */ 310#define FE_FILTER_LEN 8 311 312/* How many packets we can put in the transmission buffer on NIC memory. */ 313#define FE_QUEUEING_MAX 127 314 315/* Length (in bytes) of a "packet length" word in transmission buffer. */ 316#define FE_DATA_LEN_LEN 2 317 318/* Special Multicast Address Filter value. */ 319#define FE_FILTER_NOTHING { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } 320#define FE_FILTER_ALL { 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF } | 325 */ 326 327/* Length (in bytes) of a Multicast Address Filter. */ 328#define FE_FILTER_LEN 8 329 330/* How many packets we can put in the transmission buffer on NIC memory. */ 331#define FE_QUEUEING_MAX 127 332 333/* Length (in bytes) of a "packet length" word in transmission buffer. */ 334#define FE_DATA_LEN_LEN 2 335 336/* Special Multicast Address Filter value. */ 337#define FE_FILTER_NOTHING { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } 338#define FE_FILTER_ALL { 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF } |