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if_fatmvar.h (116735) if_fatmvar.h (118208)
1/*
2 * Copyright (c) 2001-2003
3 * Fraunhofer Institute for Open Communication Systems (FhG Fokus).
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Author: Hartmut Brandt <harti@freebsd.org>
28 *
1/*
2 * Copyright (c) 2001-2003
3 * Fraunhofer Institute for Open Communication Systems (FhG Fokus).
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Author: Hartmut Brandt <harti@freebsd.org>
28 *
29 * $FreeBSD: head/sys/dev/fatm/if_fatmvar.h 116735 2003-06-23 14:46:12Z harti $
29 * $FreeBSD: head/sys/dev/fatm/if_fatmvar.h 118208 2003-07-30 14:20:00Z harti $
30 *
31 * Fore PCA200E driver definitions.
32 */
33/*
34 * Debug statistics of the PCA200 driver
35 */
36struct istats {
37 uint32_t cmd_queue_full;
38 uint32_t get_stat_errors;
39 uint32_t clr_stat_errors;
40 uint32_t get_prom_errors;
41 uint32_t suni_reg_errors;
42 uint32_t tx_queue_full;
43 uint32_t tx_queue_almost_full;
44 uint32_t tx_pdu2big;
45 uint32_t tx_too_many_segs;
46 uint32_t tx_retry;
47 uint32_t fix_empty;
48 uint32_t fix_addr_copy;
49 uint32_t fix_addr_noext;
50 uint32_t fix_addr_ext;
51 uint32_t fix_len_noext;
52 uint32_t fix_len_copy;
53 uint32_t fix_len;
54 uint32_t rx_badvc;
55 uint32_t rx_closed;
56};
57
58/*
59 * Addresses on the on-board RAM are expressed as offsets to the
60 * start of that RAM.
61 */
62typedef uint32_t cardoff_t;
63
64/*
65 * The card uses a number of queues for communication with the host.
66 * Parts of the queue are located on the card (pointers to the status
67 * word and the ioblk and the command blocks), the rest in host memory.
68 * Each of these queues forms a ring, where the head and tail pointers are
69 * managed * either by the card or the host. For the receive queue the
70 * head is managed by the card (and not used altogether by the host) and the
71 * tail by the host - for all other queues its the other way around.
72 * The host resident parts of the queue entries contain pointers to
73 * the host resident status and the host resident ioblk (the latter not for
74 * the command queue) as well as DMA addresses for supply to the card.
75 */
76struct fqelem {
77 cardoff_t card; /* corresponding element on card */
78 bus_addr_t card_ioblk; /* ioblk address to supply to card */
79 volatile uint32_t *statp; /* host status pointer */
80 void *ioblk; /* host ioblk (not for commands) */
81};
82
83struct fqueue {
84 struct fqelem *chunk; /* pointer to the element array */
85 int head; /* queue head */
86 int tail; /* queue tail */
87};
88
89/*
90 * Queue manipulation macros
91 */
92#define NEXT_QUEUE_ENTRY(HEAD,LEN) ((HEAD) = ((HEAD) + 1) % LEN)
93#define GET_QUEUE(Q,TYPE,IDX) (&((TYPE *)(Q).chunk)[(IDX)])
94
95/*
96 * Now define structures for the different queues. Each of these structures
97 * must start with a struct fqelem.
98 */
99struct txqueue { /* transmit queue element */
100 struct fqelem q;
101 struct mbuf *m; /* the chain we are transmitting */
102 bus_dmamap_t map; /* map for the packet */
103};
104
105struct rxqueue { /* receive queue element */
106 struct fqelem q;
107};
108
109struct supqueue { /* supply queue element */
110 struct fqelem q;
111};
112
113struct cmdqueue;
114struct fatm_softc;
115
116typedef void (*completion_cb)(struct fatm_softc *, struct cmdqueue *);
117
118struct cmdqueue { /* command queue element */
119 struct fqelem q;
120 completion_cb cb; /* call on command completion */
121 int error; /* set if error occured */
122};
123
124/*
125 * Card-DMA-able memory is managed by means of the bus_dma* functions.
126 * To allocate a chunk of memory with a specific size and alignment one
127 * has to:
128 * 1. create a DMA tag
129 * 2. allocate the memory
130 * 3. load the memory into a map.
131 * This finally gives the physical address that can be given to the card.
132 * The card can DMA the entire 32-bit space without boundaries. We assume,
133 * that all the allocations can be mapped in one contiguous segment. This
134 * may be wrong in the future if we have more than 32 bit addresses.
135 * Allocation is done at attach time and managed by the following structure.
136 *
137 * This could be done easier with the NetBSD bus_dma* functions. They appear
138 * to be more useful and consistent.
139 */
140struct fatm_mem {
141 u_int size; /* size */
142 u_int align; /* alignment */
143 bus_dma_tag_t dmat; /* DMA tag */
144 void *mem; /* memory block */
145 bus_addr_t paddr; /* pysical address */
146 bus_dmamap_t map; /* map */
147};
148
149/*
150 * Each of these structures describes one receive buffer while the buffer
151 * is on the card or in the receive return queue. These structures are
152 * allocated at initialisation time together with the DMA maps. The handle that
153 * is given to the card is the index into the array of these structures.
154 */
155struct rbuf {
156 struct mbuf *m; /* the mbuf while we are on the card */
157 bus_dmamap_t map; /* the map */
158 LIST_ENTRY(rbuf) link; /* the free list link */
159};
160LIST_HEAD(rbuf_list, rbuf);
161
162/*
163 * The driver maintains a list of all open VCCs. Because we
164 * use only VPI=0 and a maximum VCI of 1024, the list is rather an array
165 * than a list. We also store the atm pseudoheader flags here and the
166 * rxhand (aka. protocol block).
167 */
168struct card_vcc {
30 *
31 * Fore PCA200E driver definitions.
32 */
33/*
34 * Debug statistics of the PCA200 driver
35 */
36struct istats {
37 uint32_t cmd_queue_full;
38 uint32_t get_stat_errors;
39 uint32_t clr_stat_errors;
40 uint32_t get_prom_errors;
41 uint32_t suni_reg_errors;
42 uint32_t tx_queue_full;
43 uint32_t tx_queue_almost_full;
44 uint32_t tx_pdu2big;
45 uint32_t tx_too_many_segs;
46 uint32_t tx_retry;
47 uint32_t fix_empty;
48 uint32_t fix_addr_copy;
49 uint32_t fix_addr_noext;
50 uint32_t fix_addr_ext;
51 uint32_t fix_len_noext;
52 uint32_t fix_len_copy;
53 uint32_t fix_len;
54 uint32_t rx_badvc;
55 uint32_t rx_closed;
56};
57
58/*
59 * Addresses on the on-board RAM are expressed as offsets to the
60 * start of that RAM.
61 */
62typedef uint32_t cardoff_t;
63
64/*
65 * The card uses a number of queues for communication with the host.
66 * Parts of the queue are located on the card (pointers to the status
67 * word and the ioblk and the command blocks), the rest in host memory.
68 * Each of these queues forms a ring, where the head and tail pointers are
69 * managed * either by the card or the host. For the receive queue the
70 * head is managed by the card (and not used altogether by the host) and the
71 * tail by the host - for all other queues its the other way around.
72 * The host resident parts of the queue entries contain pointers to
73 * the host resident status and the host resident ioblk (the latter not for
74 * the command queue) as well as DMA addresses for supply to the card.
75 */
76struct fqelem {
77 cardoff_t card; /* corresponding element on card */
78 bus_addr_t card_ioblk; /* ioblk address to supply to card */
79 volatile uint32_t *statp; /* host status pointer */
80 void *ioblk; /* host ioblk (not for commands) */
81};
82
83struct fqueue {
84 struct fqelem *chunk; /* pointer to the element array */
85 int head; /* queue head */
86 int tail; /* queue tail */
87};
88
89/*
90 * Queue manipulation macros
91 */
92#define NEXT_QUEUE_ENTRY(HEAD,LEN) ((HEAD) = ((HEAD) + 1) % LEN)
93#define GET_QUEUE(Q,TYPE,IDX) (&((TYPE *)(Q).chunk)[(IDX)])
94
95/*
96 * Now define structures for the different queues. Each of these structures
97 * must start with a struct fqelem.
98 */
99struct txqueue { /* transmit queue element */
100 struct fqelem q;
101 struct mbuf *m; /* the chain we are transmitting */
102 bus_dmamap_t map; /* map for the packet */
103};
104
105struct rxqueue { /* receive queue element */
106 struct fqelem q;
107};
108
109struct supqueue { /* supply queue element */
110 struct fqelem q;
111};
112
113struct cmdqueue;
114struct fatm_softc;
115
116typedef void (*completion_cb)(struct fatm_softc *, struct cmdqueue *);
117
118struct cmdqueue { /* command queue element */
119 struct fqelem q;
120 completion_cb cb; /* call on command completion */
121 int error; /* set if error occured */
122};
123
124/*
125 * Card-DMA-able memory is managed by means of the bus_dma* functions.
126 * To allocate a chunk of memory with a specific size and alignment one
127 * has to:
128 * 1. create a DMA tag
129 * 2. allocate the memory
130 * 3. load the memory into a map.
131 * This finally gives the physical address that can be given to the card.
132 * The card can DMA the entire 32-bit space without boundaries. We assume,
133 * that all the allocations can be mapped in one contiguous segment. This
134 * may be wrong in the future if we have more than 32 bit addresses.
135 * Allocation is done at attach time and managed by the following structure.
136 *
137 * This could be done easier with the NetBSD bus_dma* functions. They appear
138 * to be more useful and consistent.
139 */
140struct fatm_mem {
141 u_int size; /* size */
142 u_int align; /* alignment */
143 bus_dma_tag_t dmat; /* DMA tag */
144 void *mem; /* memory block */
145 bus_addr_t paddr; /* pysical address */
146 bus_dmamap_t map; /* map */
147};
148
149/*
150 * Each of these structures describes one receive buffer while the buffer
151 * is on the card or in the receive return queue. These structures are
152 * allocated at initialisation time together with the DMA maps. The handle that
153 * is given to the card is the index into the array of these structures.
154 */
155struct rbuf {
156 struct mbuf *m; /* the mbuf while we are on the card */
157 bus_dmamap_t map; /* the map */
158 LIST_ENTRY(rbuf) link; /* the free list link */
159};
160LIST_HEAD(rbuf_list, rbuf);
161
162/*
163 * The driver maintains a list of all open VCCs. Because we
164 * use only VPI=0 and a maximum VCI of 1024, the list is rather an array
165 * than a list. We also store the atm pseudoheader flags here and the
166 * rxhand (aka. protocol block).
167 */
168struct card_vcc {
169 struct atmio_vcc param; /* traffic parameters */
169 void *rxhand;
170 void *rxhand;
170 uint32_t pcr;
171 uint32_t flags;
172 uint8_t aal;
173 uint8_t traffic;
171 uint vflags;
172 uint32_t ipackets;
173 uint32_t opackets;
174 uint32_t ibytes;
175 uint32_t obytes;
174};
175
176#define FATM_VCC_OPEN 0x00010000 /* is open */
177#define FATM_VCC_TRY_OPEN 0x00020000 /* is currently opening */
178#define FATM_VCC_TRY_CLOSE 0x00040000 /* is currently closing */
179#define FATM_VCC_BUSY 0x00070000 /* one of the above */
180
181/*
182 * Finally the softc structure
183 */
184struct fatm_softc {
185 struct ifatm ifatm; /* common part */
186 struct mtx mtx; /* lock this structure */
187 struct ifmedia media; /* media */
188
189 int init_state; /* initialisation step */
190 int memid; /* resource id for card memory */
191 struct resource *memres; /* resource for card memory */
192 bus_space_handle_t memh; /* handle for card memory */
193 bus_space_tag_t memt; /* tag for card memory */
194 int irqid; /* resource id for interrupt */
195 struct resource *irqres; /* resource for interrupt */
196 void *ih; /* interrupt handler */
197
198 bus_dma_tag_t parent_dmat; /* parent DMA tag */
199 struct fatm_mem stat_mem; /* memory for status blocks */
200 struct fatm_mem txq_mem; /* TX descriptor queue */
201 struct fatm_mem rxq_mem; /* RX descriptor queue */
202 struct fatm_mem s1q_mem; /* Small buffer 1 queue */
203 struct fatm_mem l1q_mem; /* Large buffer 1 queue */
204 struct fatm_mem prom_mem; /* PROM memory */
205
206 struct fqueue txqueue; /* transmission queue */
207 struct fqueue rxqueue; /* receive queue */
208 struct fqueue s1queue; /* SMALL S1 queue */
209 struct fqueue l1queue; /* LARGE S1 queue */
210 struct fqueue cmdqueue; /* command queue */
211
212 /* fields for access to the SUNI registers */
213 struct fatm_mem reg_mem; /* DMAable memory for readregs */
214 struct cv cv_regs; /* to serialize access to reg_mem */
215
216 /* fields for access to statistics */
217 struct fatm_mem sadi_mem; /* sadistics memory */
218 struct cv cv_stat; /* to serialize access to sadi_mem */
219
220 u_int flags;
221#define FATM_STAT_INUSE 0x0001
222#define FATM_REGS_INUSE 0x0002
223 u_int txcnt; /* number of used transmit desc */
224 int retry_tx; /* keep mbufs in queue if full */
225
176};
177
178#define FATM_VCC_OPEN 0x00010000 /* is open */
179#define FATM_VCC_TRY_OPEN 0x00020000 /* is currently opening */
180#define FATM_VCC_TRY_CLOSE 0x00040000 /* is currently closing */
181#define FATM_VCC_BUSY 0x00070000 /* one of the above */
182
183/*
184 * Finally the softc structure
185 */
186struct fatm_softc {
187 struct ifatm ifatm; /* common part */
188 struct mtx mtx; /* lock this structure */
189 struct ifmedia media; /* media */
190
191 int init_state; /* initialisation step */
192 int memid; /* resource id for card memory */
193 struct resource *memres; /* resource for card memory */
194 bus_space_handle_t memh; /* handle for card memory */
195 bus_space_tag_t memt; /* tag for card memory */
196 int irqid; /* resource id for interrupt */
197 struct resource *irqres; /* resource for interrupt */
198 void *ih; /* interrupt handler */
199
200 bus_dma_tag_t parent_dmat; /* parent DMA tag */
201 struct fatm_mem stat_mem; /* memory for status blocks */
202 struct fatm_mem txq_mem; /* TX descriptor queue */
203 struct fatm_mem rxq_mem; /* RX descriptor queue */
204 struct fatm_mem s1q_mem; /* Small buffer 1 queue */
205 struct fatm_mem l1q_mem; /* Large buffer 1 queue */
206 struct fatm_mem prom_mem; /* PROM memory */
207
208 struct fqueue txqueue; /* transmission queue */
209 struct fqueue rxqueue; /* receive queue */
210 struct fqueue s1queue; /* SMALL S1 queue */
211 struct fqueue l1queue; /* LARGE S1 queue */
212 struct fqueue cmdqueue; /* command queue */
213
214 /* fields for access to the SUNI registers */
215 struct fatm_mem reg_mem; /* DMAable memory for readregs */
216 struct cv cv_regs; /* to serialize access to reg_mem */
217
218 /* fields for access to statistics */
219 struct fatm_mem sadi_mem; /* sadistics memory */
220 struct cv cv_stat; /* to serialize access to sadi_mem */
221
222 u_int flags;
223#define FATM_STAT_INUSE 0x0001
224#define FATM_REGS_INUSE 0x0002
225 u_int txcnt; /* number of used transmit desc */
226 int retry_tx; /* keep mbufs in queue if full */
227
226 struct card_vcc *vccs; /* table of vccs */
228 struct card_vcc **vccs; /* table of vccs */
227 int open_vccs; /* number of vccs in use */
228 int small_cnt; /* number of buffers owned by card */
229 int large_cnt; /* number of buffers owned by card */
229 int open_vccs; /* number of vccs in use */
230 int small_cnt; /* number of buffers owned by card */
231 int large_cnt; /* number of buffers owned by card */
232 uma_zone_t vcc_zone; /* allocator for VCCs */
230
231 /* receiving */
232 struct rbuf *rbufs; /* rbuf array */
233 struct rbuf_list rbuf_free; /* free rbufs list */
234 struct rbuf_list rbuf_used; /* used rbufs list */
235 u_int rbuf_total; /* total number of buffs */
236 bus_dma_tag_t rbuf_tag; /* tag for rbuf mapping */
237
238 /* transmission */
239 bus_dma_tag_t tx_tag; /* transmission tag */
240
241 uint32_t heartbeat; /* last heartbeat */
242 u_int stop_cnt; /* how many times checked */
243
244 struct istats istats; /* internal statistics */
245
246 /* SUNI state */
247 struct utopia utopia;
248
249 /* sysctl support */
250 struct sysctl_ctx_list sysctl_ctx;
251 struct sysctl_oid *sysctl_tree;
252
253#ifdef FATM_DEBUG
254 /* debugging */
255 u_int debug;
256#endif
257};
258
259#ifndef FATM_DEBUG
260#define FATM_LOCK(SC) mtx_lock(&(SC)->mtx)
261#define FATM_UNLOCK(SC) mtx_unlock(&(SC)->mtx)
262#else
263#define FATM_LOCK(SC) do { \
264 DBG(SC, LOCK, ("locking in line %d", __LINE__)); \
265 mtx_lock(&(SC)->mtx); \
266 } while (0)
267#define FATM_UNLOCK(SC) do { \
268 DBG(SC, LOCK, ("unlocking in line %d", __LINE__)); \
269 mtx_unlock(&(SC)->mtx); \
270 } while (0)
271#endif
272#define FATM_CHECKLOCK(SC) mtx_assert(&sc->mtx, MA_OWNED)
273
274/*
275 * Macros to access host memory fields that are also access by the card.
276 * These fields need to little-endian always.
277 */
278#define H_GETSTAT(STATP) (le32toh(*(STATP)))
279#define H_SETSTAT(STATP, S) do { *(STATP) = htole32(S); } while (0)
280#define H_SETDESC(DESC, D) do { (DESC) = htole32(D); } while (0)
281
282#ifdef notyet
283#define H_SYNCSTAT_POSTREAD(SC, P) \
284 bus_dmamap_sync_size((SC)->stat_mem.dmat, \
285 (SC)->stat_mem.map, \
286 (volatile char *)(P) - (volatile char *)(SC)->stat_mem.mem, \
287 sizeof(volatile uint32_t), BUS_DMASYNC_POSTREAD)
288
289#define H_SYNCSTAT_PREWRITE(SC, P) \
290 bus_dmamap_sync_size((SC)->stat_mem.dmat, \
291 (SC)->stat_mem.map, \
292 (volatile char *)(P) - (volatile char *)(SC)->stat_mem.mem, \
293 sizeof(volatile uint32_t), BUS_DMASYNC_PREWRITE)
294
295#define H_SYNCQ_PREWRITE(M, P, SZ) \
296 bus_dmamap_sync_size((M)->dmat, (M)->map, \
297 (volatile char *)(P) - (volatile char *)(M)->mem, (SZ), \
298 BUS_DMASYNC_PREWRITE)
299
300#define H_SYNCQ_POSTREAD(M, P, SZ) \
301 bus_dmamap_sync_size((M)->dmat, (M)->map, \
302 (volatile char *)(P) - (volatile char *)(M)->mem, (SZ), \
303 BUS_DMASYNC_POSTREAD)
304#else
305#define H_SYNCSTAT_POSTREAD(SC, P) do { } while (0)
306#define H_SYNCSTAT_PREWRITE(SC, P) do { } while (0)
307#define H_SYNCQ_PREWRITE(M, P, SZ) do { } while (0)
308#define H_SYNCQ_POSTREAD(M, P, SZ) do { } while (0)
309#endif
310
311/*
312 * Macros to manipulate VPVCs
313 */
314#define MKVPVC(VPI,VCI) (((VPI) << 16) | (VCI))
315#define GETVPI(VPVC) (((VPVC) >> 16) & 0xff)
316#define GETVCI(VPVC) ((VPVC) & 0xffff)
317
318/*
319 * These macros encapsulate the bus_space functions for better readabiliy.
320 */
321#define WRITE4(SC, OFF, VAL) bus_space_write_4(SC->memt, SC->memh, OFF, VAL)
322#define WRITE1(SC, OFF, VAL) bus_space_write_1(SC->memt, SC->memh, OFF, VAL)
323
324#define READ4(SC, OFF) bus_space_read_4(SC->memt, SC->memh, OFF)
325#define READ1(SC, OFF) bus_space_read_1(SC->memt, SC->memh, OFF)
326
327#define BARRIER_R(SC) \
328 bus_space_barrier(SC->memt, SC->memh, 0, FATMO_END, \
329 BUS_SPACE_BARRIER_READ)
330#define BARRIER_W(SC) \
331 bus_space_barrier(SC->memt, SC->memh, 0, FATMO_END, \
332 BUS_SPACE_BARRIER_WRITE)
333#define BARRIER_RW(SC) \
334 bus_space_barrier(SC->memt, SC->memh, 0, FATMO_END, \
335 BUS_SPACE_BARRIER_WRITE|BUS_SPACE_BARRIER_READ)
336
337#ifdef FATM_DEBUG
338#define DBG(SC, FL, PRINT) do { \
339 if ((SC)->debug & DBG_##FL) { \
340 if_printf(&(SC)->ifatm.ifnet, "%s: ", __func__); \
341 printf PRINT; \
342 printf("\n"); \
343 } \
344 } while (0)
345#define DBGC(SC, FL, PRINT) do { \
346 if ((SC)->debug & DBG_##FL) \
347 printf PRINT; \
348 } while (0)
349
350enum {
351 DBG_RCV = 0x0001,
352 DBG_XMIT = 0x0002,
353 DBG_VCC = 0x0004,
354 DBG_IOCTL = 0x0008,
355 DBG_ATTACH = 0x0010,
356 DBG_INIT = 0x0020,
357 DBG_DMA = 0x0040,
358 DBG_BEAT = 0x0080,
359 DBG_UART = 0x0100,
360 DBG_LOCK = 0x0200,
361
362 DBG_ALL = 0xffff
363};
364
365#else
366#define DBG(SC, FL, PRINT)
367#define DBGC(SC, FL, PRINT)
368#endif
369
370/*
371 * Configuration.
372 *
373 * This section contains tunable parameters and dependend defines.
374 */
375#define FATM_CMD_QLEN 16 /* command queue length */
376#ifndef TEST_DMA_SYNC
377#define FATM_TX_QLEN 128 /* transmit queue length */
378#define FATM_RX_QLEN 64 /* receive queue length */
379#else
380#define FATM_TX_QLEN 8 /* transmit queue length */
381#define FATM_RX_QLEN 8 /* receive queue length */
382#endif
383
384#define SMALL_SUPPLY_QLEN 16
385#define SMALL_POOL_SIZE 256
386#define SMALL_SUPPLY_BLKSIZE 8
387
388#define LARGE_SUPPLY_QLEN 16
389#define LARGE_POOL_SIZE 128
390#define LARGE_SUPPLY_BLKSIZE 8
233
234 /* receiving */
235 struct rbuf *rbufs; /* rbuf array */
236 struct rbuf_list rbuf_free; /* free rbufs list */
237 struct rbuf_list rbuf_used; /* used rbufs list */
238 u_int rbuf_total; /* total number of buffs */
239 bus_dma_tag_t rbuf_tag; /* tag for rbuf mapping */
240
241 /* transmission */
242 bus_dma_tag_t tx_tag; /* transmission tag */
243
244 uint32_t heartbeat; /* last heartbeat */
245 u_int stop_cnt; /* how many times checked */
246
247 struct istats istats; /* internal statistics */
248
249 /* SUNI state */
250 struct utopia utopia;
251
252 /* sysctl support */
253 struct sysctl_ctx_list sysctl_ctx;
254 struct sysctl_oid *sysctl_tree;
255
256#ifdef FATM_DEBUG
257 /* debugging */
258 u_int debug;
259#endif
260};
261
262#ifndef FATM_DEBUG
263#define FATM_LOCK(SC) mtx_lock(&(SC)->mtx)
264#define FATM_UNLOCK(SC) mtx_unlock(&(SC)->mtx)
265#else
266#define FATM_LOCK(SC) do { \
267 DBG(SC, LOCK, ("locking in line %d", __LINE__)); \
268 mtx_lock(&(SC)->mtx); \
269 } while (0)
270#define FATM_UNLOCK(SC) do { \
271 DBG(SC, LOCK, ("unlocking in line %d", __LINE__)); \
272 mtx_unlock(&(SC)->mtx); \
273 } while (0)
274#endif
275#define FATM_CHECKLOCK(SC) mtx_assert(&sc->mtx, MA_OWNED)
276
277/*
278 * Macros to access host memory fields that are also access by the card.
279 * These fields need to little-endian always.
280 */
281#define H_GETSTAT(STATP) (le32toh(*(STATP)))
282#define H_SETSTAT(STATP, S) do { *(STATP) = htole32(S); } while (0)
283#define H_SETDESC(DESC, D) do { (DESC) = htole32(D); } while (0)
284
285#ifdef notyet
286#define H_SYNCSTAT_POSTREAD(SC, P) \
287 bus_dmamap_sync_size((SC)->stat_mem.dmat, \
288 (SC)->stat_mem.map, \
289 (volatile char *)(P) - (volatile char *)(SC)->stat_mem.mem, \
290 sizeof(volatile uint32_t), BUS_DMASYNC_POSTREAD)
291
292#define H_SYNCSTAT_PREWRITE(SC, P) \
293 bus_dmamap_sync_size((SC)->stat_mem.dmat, \
294 (SC)->stat_mem.map, \
295 (volatile char *)(P) - (volatile char *)(SC)->stat_mem.mem, \
296 sizeof(volatile uint32_t), BUS_DMASYNC_PREWRITE)
297
298#define H_SYNCQ_PREWRITE(M, P, SZ) \
299 bus_dmamap_sync_size((M)->dmat, (M)->map, \
300 (volatile char *)(P) - (volatile char *)(M)->mem, (SZ), \
301 BUS_DMASYNC_PREWRITE)
302
303#define H_SYNCQ_POSTREAD(M, P, SZ) \
304 bus_dmamap_sync_size((M)->dmat, (M)->map, \
305 (volatile char *)(P) - (volatile char *)(M)->mem, (SZ), \
306 BUS_DMASYNC_POSTREAD)
307#else
308#define H_SYNCSTAT_POSTREAD(SC, P) do { } while (0)
309#define H_SYNCSTAT_PREWRITE(SC, P) do { } while (0)
310#define H_SYNCQ_PREWRITE(M, P, SZ) do { } while (0)
311#define H_SYNCQ_POSTREAD(M, P, SZ) do { } while (0)
312#endif
313
314/*
315 * Macros to manipulate VPVCs
316 */
317#define MKVPVC(VPI,VCI) (((VPI) << 16) | (VCI))
318#define GETVPI(VPVC) (((VPVC) >> 16) & 0xff)
319#define GETVCI(VPVC) ((VPVC) & 0xffff)
320
321/*
322 * These macros encapsulate the bus_space functions for better readabiliy.
323 */
324#define WRITE4(SC, OFF, VAL) bus_space_write_4(SC->memt, SC->memh, OFF, VAL)
325#define WRITE1(SC, OFF, VAL) bus_space_write_1(SC->memt, SC->memh, OFF, VAL)
326
327#define READ4(SC, OFF) bus_space_read_4(SC->memt, SC->memh, OFF)
328#define READ1(SC, OFF) bus_space_read_1(SC->memt, SC->memh, OFF)
329
330#define BARRIER_R(SC) \
331 bus_space_barrier(SC->memt, SC->memh, 0, FATMO_END, \
332 BUS_SPACE_BARRIER_READ)
333#define BARRIER_W(SC) \
334 bus_space_barrier(SC->memt, SC->memh, 0, FATMO_END, \
335 BUS_SPACE_BARRIER_WRITE)
336#define BARRIER_RW(SC) \
337 bus_space_barrier(SC->memt, SC->memh, 0, FATMO_END, \
338 BUS_SPACE_BARRIER_WRITE|BUS_SPACE_BARRIER_READ)
339
340#ifdef FATM_DEBUG
341#define DBG(SC, FL, PRINT) do { \
342 if ((SC)->debug & DBG_##FL) { \
343 if_printf(&(SC)->ifatm.ifnet, "%s: ", __func__); \
344 printf PRINT; \
345 printf("\n"); \
346 } \
347 } while (0)
348#define DBGC(SC, FL, PRINT) do { \
349 if ((SC)->debug & DBG_##FL) \
350 printf PRINT; \
351 } while (0)
352
353enum {
354 DBG_RCV = 0x0001,
355 DBG_XMIT = 0x0002,
356 DBG_VCC = 0x0004,
357 DBG_IOCTL = 0x0008,
358 DBG_ATTACH = 0x0010,
359 DBG_INIT = 0x0020,
360 DBG_DMA = 0x0040,
361 DBG_BEAT = 0x0080,
362 DBG_UART = 0x0100,
363 DBG_LOCK = 0x0200,
364
365 DBG_ALL = 0xffff
366};
367
368#else
369#define DBG(SC, FL, PRINT)
370#define DBGC(SC, FL, PRINT)
371#endif
372
373/*
374 * Configuration.
375 *
376 * This section contains tunable parameters and dependend defines.
377 */
378#define FATM_CMD_QLEN 16 /* command queue length */
379#ifndef TEST_DMA_SYNC
380#define FATM_TX_QLEN 128 /* transmit queue length */
381#define FATM_RX_QLEN 64 /* receive queue length */
382#else
383#define FATM_TX_QLEN 8 /* transmit queue length */
384#define FATM_RX_QLEN 8 /* receive queue length */
385#endif
386
387#define SMALL_SUPPLY_QLEN 16
388#define SMALL_POOL_SIZE 256
389#define SMALL_SUPPLY_BLKSIZE 8
390
391#define LARGE_SUPPLY_QLEN 16
392#define LARGE_POOL_SIZE 128
393#define LARGE_SUPPLY_BLKSIZE 8