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ncr53c9xvar.h (182876) ncr53c9xvar.h (226381)
1/* $NetBSD: ncr53c9xvar.h,v 1.46 2005/02/04 02:10:36 perry Exp $ */
1/* $NetBSD: ncr53c9xvar.h,v 1.55 2011/07/31 18:39:00 jakllsch Exp $ */
2
3/*-
4 * Copyright (c) 1997 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.

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61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 */
68
2
3/*-
4 * Copyright (c) 1997 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.

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61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 */
68
69/* $FreeBSD: head/sys/dev/esp/ncr53c9xvar.h 182876 2008-09-08 20:20:44Z marius $ */
69/* $FreeBSD: head/sys/dev/esp/ncr53c9xvar.h 226381 2011-10-15 09:29:43Z marius $ */
70
71#ifndef _DEV_IC_NCR53C9XVAR_H_
72#define _DEV_IC_NCR53C9XVAR_H_
73
74#include <sys/lock.h>
75
76/* Set this to 1 for normal debug, or 2 for per-target tracing. */
77/* #define NCR53C9X_DEBUG 2 */

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128#define ECB_SENSE 0x04
129#define ECB_ABORT 0x40
130#define ECB_RESET 0x80
131#define ECB_TENTATIVE_DONE 0x100
132 int timeout;
133 struct callout ch;
134
135 struct {
70
71#ifndef _DEV_IC_NCR53C9XVAR_H_
72#define _DEV_IC_NCR53C9XVAR_H_
73
74#include <sys/lock.h>
75
76/* Set this to 1 for normal debug, or 2 for per-target tracing. */
77/* #define NCR53C9X_DEBUG 2 */

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128#define ECB_SENSE 0x04
129#define ECB_ABORT 0x40
130#define ECB_RESET 0x80
131#define ECB_TENTATIVE_DONE 0x100
132 int timeout;
133 struct callout ch;
134
135 struct {
136 u_char msg[3]; /* Selection Id msg and tags */
136 uint8_t msg[3]; /* Selection Id msg and tags */
137 struct scsi_generic cmd; /* SCSI command block */
138 } cmd;
137 struct scsi_generic cmd; /* SCSI command block */
138 } cmd;
139 char *daddr; /* Saved data pointer */
139 uint8_t *daddr; /* Saved data pointer */
140 int clen; /* Size of command in cmd.cmd */
141 int dleft; /* Residue */
140 int clen; /* Size of command in cmd.cmd */
141 int dleft; /* Residue */
142 u_char stat; /* SCSI status byte */
143 u_char tag[2]; /* TAG bytes */
144 u_char pad[1];
142 uint8_t stat; /* SCSI status byte */
143 uint8_t tag[2]; /* TAG bytes */
144 uint8_t pad[1];
145
146#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
147 char trace[1000];
148#endif
149};
150#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
145
146#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
147 char trace[1000];
148#endif
149};
150#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
151#define ECB_TRACE(ecb, msg, a, b) do { \
152 const char *f = "[" msg "]"; \
153 int n = strlen((ecb)->trace); \
154 if (n < (sizeof((ecb)->trace)-100)) \
155 sprintf((ecb)->trace + n, f, a, b); \
156} while(0)
151#define ECB_TRACE(ecb, msg, a, b) do { \
152 const char *f = "[" msg "]"; \
153 int n = strlen((ecb)->trace); \
154 if (n < (sizeof((ecb)->trace)-100)) \
155 sprintf((ecb)->trace + n, f, a, b); \
156} while (/* CONSTCOND */0)
157#else
158#define ECB_TRACE(ecb, msg, a, b)
159#endif
160
161/*
162 * Some info about each (possible) target and LUN on the SCSI bus.
163 *
164 * SCSI I and II devices can have up to 8 LUNs, each with up to 256

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169 * of 8 pointers to ncr53c9x_linfo structures for fast lookup.
170 * Longer LUNs need to traverse the linked list.
171 */
172
173struct ncr53c9x_linfo {
174 int64_t lun;
175 LIST_ENTRY(ncr53c9x_linfo) link;
176 time_t last_used;
157#else
158#define ECB_TRACE(ecb, msg, a, b)
159#endif
160
161/*
162 * Some info about each (possible) target and LUN on the SCSI bus.
163 *
164 * SCSI I and II devices can have up to 8 LUNs, each with up to 256

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169 * of 8 pointers to ncr53c9x_linfo structures for fast lookup.
170 * Longer LUNs need to traverse the linked list.
171 */
172
173struct ncr53c9x_linfo {
174 int64_t lun;
175 LIST_ENTRY(ncr53c9x_linfo) link;
176 time_t last_used;
177 u_char used; /* # slots in use */
178 u_char avail; /* where to start scanning */
179 u_char busy;
177 uint8_t used; /* # slots in use */
178 uint8_t avail; /* where to start scanning */
179 uint8_t busy;
180 struct ncr53c9x_ecb *untagged;
181 struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH];
182};
183
184struct ncr53c9x_xinfo {
180 struct ncr53c9x_ecb *untagged;
181 struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH];
182};
183
184struct ncr53c9x_xinfo {
185 u_char period;
186 u_char offset;
187 u_char width;
185 uint8_t period;
186 uint8_t offset;
187 uint8_t width;
188};
189
190struct ncr53c9x_tinfo {
191 int cmds; /* # of commands processed */
192 int dconns; /* # of disconnects */
193 int touts; /* # of timeouts */
194 int perrs; /* # of parity errors */
195 int senses; /* # of request sense commands sent */
188};
189
190struct ncr53c9x_tinfo {
191 int cmds; /* # of commands processed */
192 int dconns; /* # of disconnects */
193 int touts; /* # of timeouts */
194 int perrs; /* # of parity errors */
195 int senses; /* # of request sense commands sent */
196 u_char flags;
196 uint8_t flags;
197#define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */
198#define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */
199#define T_TAG 0x04 /* Turn on TAG QUEUEs */
200#define T_SDTRSENT 0x08 /* SDTR message has been sent to */
201#define T_WDTRSENT 0x10 /* WDTR message has been sent to */
202 struct ncr53c9x_xinfo curr;
203 struct ncr53c9x_xinfo goal;
204 LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
205 struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
206};
207
208/* Look up a lun in a tinfo */
197#define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */
198#define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */
199#define T_TAG 0x04 /* Turn on TAG QUEUEs */
200#define T_SDTRSENT 0x08 /* SDTR message has been sent to */
201#define T_WDTRSENT 0x10 /* WDTR message has been sent to */
202 struct ncr53c9x_xinfo curr;
203 struct ncr53c9x_xinfo goal;
204 LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
205 struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
206};
207
208/* Look up a lun in a tinfo */
209#define TINFO_LUN(t, l) ( \
210 (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
211 ? ((t)->lun[(l)]) \
212 : ncr53c9x_lunsearch((t), (int64_t)(l)) \
209#define TINFO_LUN(t, l) ( \
210 (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
211 ? ((t)->lun[(l)]) \
212 : ncr53c9x_lunsearch((t), (int64_t)(l)) \
213)
214
213)
214
215/* Register a linenumber (for debugging) */
215/* Register a linenumber (for debugging). */
216#define LOGLINE(p)
217
218#define NCR_SHOWECBS 0x01
219#define NCR_SHOWINTS 0x02
220#define NCR_SHOWCMDS 0x04
221#define NCR_SHOWMISC 0x08
222#define NCR_SHOWTRAC 0x10
223#define NCR_SHOWSTART 0x20
224#define NCR_SHOWPHASE 0x40
225#define NCR_SHOWDMA 0x80
226#define NCR_SHOWCCMDS 0x100
227#define NCR_SHOWMSGS 0x200
228
229#ifdef NCR53C9X_DEBUG
230extern int ncr53c9x_debug;
216#define LOGLINE(p)
217
218#define NCR_SHOWECBS 0x01
219#define NCR_SHOWINTS 0x02
220#define NCR_SHOWCMDS 0x04
221#define NCR_SHOWMISC 0x08
222#define NCR_SHOWTRAC 0x10
223#define NCR_SHOWSTART 0x20
224#define NCR_SHOWPHASE 0x40
225#define NCR_SHOWDMA 0x80
226#define NCR_SHOWCCMDS 0x100
227#define NCR_SHOWMSGS 0x200
228
229#ifdef NCR53C9X_DEBUG
230extern int ncr53c9x_debug;
231#define NCR_ECBS(str) \
232 do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0)
233#define NCR_MISC(str) \
234 do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0)
235#define NCR_INTS(str) \
236 do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0)
237#define NCR_TRACE(str) \
238 do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0)
239#define NCR_CMDS(str) \
240 do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0)
241#define NCR_START(str) \
242 do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0)
243#define NCR_PHASE(str) \
244 do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0)
245#define NCR_DMA(str) \
246 do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0)
247#define NCR_MSGS(str) \
248 do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0)
231#define NCR_ECBS(str) \
232 do { \
233 if ((ncr53c9x_debug & NCR_SHOWECBS) != 0) \
234 printf str; \
235 } while (/* CONSTCOND */0)
236#define NCR_MISC(str) \
237 do { \
238 if ((ncr53c9x_debug & NCR_SHOWMISC) != 0) \
239 printf str; \
240 } while (/* CONSTCOND */0)
241#define NCR_INTS(str) \
242 do { \
243 if ((ncr53c9x_debug & NCR_SHOWINTS) != 0) \
244 printf str; \
245 } while (/* CONSTCOND */0)
246#define NCR_TRACE(str) \
247 do { \
248 if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) \
249 printf str; \
250 } while (/* CONSTCOND */0)
251#define NCR_CMDS(str) \
252 do { \
253 if ((ncr53c9x_debug & NCR_SHOWCMDS) != 0) \
254 printf str; \
255 } while (/* CONSTCOND */0)
256#define NCR_START(str) \
257 do { \
258 if ((ncr53c9x_debug & NCR_SHOWSTART) != 0) \
259 printf str; \
260 } while (/* CONSTCOND */0)
261#define NCR_PHASE(str) \
262 do { \
263 if ((ncr53c9x_debug & NCR_SHOWPHASE) != 0) \
264 printf str; \
265 } while (/* CONSTCOND */0)
266#define NCR_DMA(str) \
267 do { \
268 if ((ncr53c9x_debug & NCR_SHOWDMA) != 0) \
269 printf str; \
270 } while (/* CONSTCOND */0)
271#define NCR_MSGS(str) \
272 do { \
273 if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) \
274 printf str; \
275 } while (/* CONSTCOND */0)
249#else
250#define NCR_ECBS(str)
251#define NCR_MISC(str)
252#define NCR_INTS(str)
253#define NCR_TRACE(str)
254#define NCR_CMDS(str)
255#define NCR_START(str)
256#define NCR_PHASE(str)

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262
263struct ncr53c9x_softc;
264
265/*
266 * Function switch used as glue to MD code.
267 */
268struct ncr53c9x_glue {
269 /* Mandatory entry points. */
276#else
277#define NCR_ECBS(str)
278#define NCR_MISC(str)
279#define NCR_INTS(str)
280#define NCR_TRACE(str)
281#define NCR_CMDS(str)
282#define NCR_START(str)
283#define NCR_PHASE(str)

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289
290struct ncr53c9x_softc;
291
292/*
293 * Function switch used as glue to MD code.
294 */
295struct ncr53c9x_glue {
296 /* Mandatory entry points. */
270 u_char (*gl_read_reg)(struct ncr53c9x_softc *, int);
271 void (*gl_write_reg)(struct ncr53c9x_softc *, int, u_char);
297 uint8_t (*gl_read_reg)(struct ncr53c9x_softc *, int);
298 void (*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t);
272 int (*gl_dma_isintr)(struct ncr53c9x_softc *);
273 void (*gl_dma_reset)(struct ncr53c9x_softc *);
274 int (*gl_dma_intr)(struct ncr53c9x_softc *);
299 int (*gl_dma_isintr)(struct ncr53c9x_softc *);
300 void (*gl_dma_reset)(struct ncr53c9x_softc *);
301 int (*gl_dma_intr)(struct ncr53c9x_softc *);
275 int (*gl_dma_setup)(struct ncr53c9x_softc *,
276 caddr_t *, size_t *, int, size_t *);
302 int (*gl_dma_setup)(struct ncr53c9x_softc *, void **, size_t *,
303 int, size_t *);
277 void (*gl_dma_go)(struct ncr53c9x_softc *);
278 void (*gl_dma_stop)(struct ncr53c9x_softc *);
279 int (*gl_dma_isactive)(struct ncr53c9x_softc *);
280
281 /* Optional entry points. */
282 void (*gl_clear_latched_intr)(struct ncr53c9x_softc *);
283};
284

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289 struct cam_path *sc_path; /* our scsi channel */
290 struct callout sc_watchdog; /* periodic timer */
291
292 const struct ncr53c9x_glue *sc_glue; /* glue to MD code */
293
294 int sc_cfflags; /* Copy of config flags */
295
296 /* register defaults */
304 void (*gl_dma_go)(struct ncr53c9x_softc *);
305 void (*gl_dma_stop)(struct ncr53c9x_softc *);
306 int (*gl_dma_isactive)(struct ncr53c9x_softc *);
307
308 /* Optional entry points. */
309 void (*gl_clear_latched_intr)(struct ncr53c9x_softc *);
310};
311

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316 struct cam_path *sc_path; /* our scsi channel */
317 struct callout sc_watchdog; /* periodic timer */
318
319 const struct ncr53c9x_glue *sc_glue; /* glue to MD code */
320
321 int sc_cfflags; /* Copy of config flags */
322
323 /* register defaults */
297 u_char sc_cfg1; /* Config 1 */
298 u_char sc_cfg2; /* Config 2, not ESP100 */
299 u_char sc_cfg3; /* Config 3, ESP200,FAS */
300 u_char sc_cfg3_fscsi; /* Chip-specific FSCSI bit */
301 u_char sc_cfg4; /* Config 4, only ESP200 */
302 u_char sc_cfg5; /* Config 5, only ESP200 */
303 u_char sc_ccf; /* Clock Conversion */
304 u_char sc_timeout;
324 uint8_t sc_cfg1; /* Config 1 */
325 uint8_t sc_cfg2; /* Config 2, not ESP100 */
326 uint8_t sc_cfg3; /* Config 3, ESP200,FAS */
327 uint8_t sc_cfg3_fscsi; /* Chip-specific FSCSI bit */
328 uint8_t sc_cfg4; /* Config 4, only ESP200 */
329 uint8_t sc_cfg5; /* Config 5, only ESP200 */
330 uint8_t sc_ccf; /* Clock Conversion */
331 uint8_t sc_timeout;
305
306 /* register copies, see espreadregs() */
332
333 /* register copies, see espreadregs() */
307 u_char sc_espintr;
308 u_char sc_espstat;
309 u_char sc_espstep;
310 u_char sc_espstat2;
311 u_char sc_espfflags;
334 uint8_t sc_espintr;
335 uint8_t sc_espstat;
336 uint8_t sc_espstep;
337 uint8_t sc_espstat2;
338 uint8_t sc_espfflags;
312
313 /* Lists of command blocks */
314 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list;
315
316 struct ncr53c9x_ecb *sc_nexus; /* Current command */
317 int sc_ntarg;
318 struct ncr53c9x_tinfo *sc_tinfo;
319
320 /* Data about the current nexus (updated for every cmd switch) */
339
340 /* Lists of command blocks */
341 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list;
342
343 struct ncr53c9x_ecb *sc_nexus; /* Current command */
344 int sc_ntarg;
345 struct ncr53c9x_tinfo *sc_tinfo;
346
347 /* Data about the current nexus (updated for every cmd switch) */
321 caddr_t sc_dp; /* Current data pointer */
348 void *sc_dp; /* Current data pointer */
322 ssize_t sc_dleft; /* Data left to transfer */
323
324 /* Adapter state */
325 int sc_phase; /* Copy of what bus phase we are in */
326 int sc_prevphase; /* Copy of what bus phase we were in */
349 ssize_t sc_dleft; /* Data left to transfer */
350
351 /* Adapter state */
352 int sc_phase; /* Copy of what bus phase we are in */
353 int sc_prevphase; /* Copy of what bus phase we were in */
327 u_char sc_state; /* State applicable to the adapter */
328 u_char sc_flags; /* See below */
329 u_char sc_selid;
330 u_char sc_lastcmd;
354 uint8_t sc_state; /* State applicable to the adapter */
355 uint8_t sc_flags; /* See below */
356 uint8_t sc_selid;
357 uint8_t sc_lastcmd;
331
332 /* Message stuff */
358
359 /* Message stuff */
333 u_short sc_msgify; /* IDENTIFY message associated with nexus */
334 u_short sc_msgout; /* What message is on its way out? */
335 u_short sc_msgpriq; /* One or more messages to send (encoded) */
336 u_short sc_msgoutq; /* What messages have been sent so far? */
360 uint16_t sc_msgify; /* IDENTIFY message associated with nexus */
361 uint16_t sc_msgout; /* What message is on its way out? */
362 uint16_t sc_msgpriq; /* One or more messages to send (encoded) */
363 uint16_t sc_msgoutq; /* What messages have been sent so far? */
337
364
338 u_char *sc_omess; /* MSGOUT buffer */
365 uint8_t *sc_omess; /* MSGOUT buffer */
339 int sc_omess_self; /* MSGOUT buffer is self-allocated */
366 int sc_omess_self; /* MSGOUT buffer is self-allocated */
340 caddr_t sc_omp; /* Message pointer (for multibyte messages) */
367 void *sc_omp; /* Message pointer (for multibyte messages) */
341 size_t sc_omlen;
368 size_t sc_omlen;
342 u_char *sc_imess; /* MSGIN buffer */
369 uint8_t *sc_imess; /* MSGIN buffer */
343 int sc_imess_self; /* MSGIN buffer is self-allocated */
370 int sc_imess_self; /* MSGIN buffer is self-allocated */
344 caddr_t sc_imp; /* Message pointer (for multibyte messages) */
371 void *sc_imp; /* Message pointer (for multibyte messages) */
345 size_t sc_imlen;
346
372 size_t sc_imlen;
373
347 caddr_t sc_cmdp; /* Command pointer (for DMAed commands) */
374 void *sc_cmdp; /* Command pointer (for DMAed commands) */
348 size_t sc_cmdlen; /* Size of command in transit */
349
350 /* Hardware attributes */
351 int sc_freq; /* SCSI bus frequency in MHz */
352 int sc_id; /* Our SCSI id */
353 int sc_rev; /* Chip revision */
354 int sc_features; /* Chip features */
355 int sc_minsync; /* Minimum sync period / 4 */

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429#define NCR_READ_REG(sc, reg) \
430 (*(sc)->sc_glue->gl_read_reg)((sc), (reg))
431#define NCR_WRITE_REG(sc, reg, val) \
432 (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
433
434#ifdef NCR53C9X_DEBUG
435#define NCRCMD(sc, cmd) do { \
436 if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \
375 size_t sc_cmdlen; /* Size of command in transit */
376
377 /* Hardware attributes */
378 int sc_freq; /* SCSI bus frequency in MHz */
379 int sc_id; /* Our SCSI id */
380 int sc_rev; /* Chip revision */
381 int sc_features; /* Chip features */
382 int sc_minsync; /* Minimum sync period / 4 */

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456#define NCR_READ_REG(sc, reg) \
457 (*(sc)->sc_glue->gl_read_reg)((sc), (reg))
458#define NCR_WRITE_REG(sc, reg, val) \
459 (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
460
461#ifdef NCR53C9X_DEBUG
462#define NCRCMD(sc, cmd) do { \
463 if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \
437 printf("", (unsigned)cmd, __LINE__); \
464 printf("<CMD:0x%x %d>", (unsigned int)cmd, __LINE__); \
438 sc->sc_lastcmd = cmd; \
439 NCR_WRITE_REG(sc, NCR_CMD, cmd); \
465 sc->sc_lastcmd = cmd; \
466 NCR_WRITE_REG(sc, NCR_CMD, cmd); \
440} while (0)
467} while (/* CONSTCOND */ 0)
441#else
442#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd)
443#endif
444
445/*
446 * Macros for locking
447 */
448#define NCR_LOCK_INIT(_sc) \

--- 31 unchanged lines hidden --- 		468#else
469#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd)
470#endif
471
472/*
473 * Macros for locking
474 */
475#define NCR_LOCK_INIT(_sc) \

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