28 */
29
30/*
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
33 *
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
37 *
38 */
39
40#include "ed.h"
41#include "bpfilter.h"
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/conf.h>
46#include <sys/errno.h>
47#include <sys/ioctl.h>
48#include <sys/mbuf.h>
49#include <sys/socket.h>
50#include <sys/syslog.h>
51
52#include <net/if.h>
53#include <net/if_dl.h>
54#include <net/if_mib.h>
55#include <net/if_types.h>
56
57#ifdef INET
58#include <netinet/in.h>
59#include <netinet/in_systm.h>
60#include <netinet/in_var.h>
61#include <netinet/ip.h>
62#include <netinet/if_ether.h>
63#endif
64
65#ifdef IPX
66#include <netipx/ipx.h>
67#include <netipx/ipx_if.h>
68#endif
69
70#ifdef NS
71#include <netns/ns.h>
72#include <netns/ns_if.h>
73#endif
74
75#if NBPFILTER > 0
76#include <net/bpf.h>
77#include <net/bpfdesc.h>
78#endif
79
80#include <machine/clock.h>
81#include <machine/md_var.h>
82
83#include <i386/isa/isa_device.h>
84#include <i386/isa/icu.h>
85#include <i386/isa/if_edreg.h>
86
87/*
88 * ed_softc: per line info and status
89 */
90struct ed_softc {
91 struct arpcom arpcom; /* ethernet common */
92
93 char *type_str; /* pointer to type string */
94 u_char vendor; /* interface vendor */
95 u_char type; /* interface type code */
96 u_char gone; /* HW missing, presumed having a good time */
97
98 u_short asic_addr; /* ASIC I/O bus address */
99 u_short nic_addr; /* NIC (DS8390) I/O bus address */
100
101/*
102 * The following 'proto' variable is part of a work-around for 8013EBT asics
103 * being write-only. It's sort of a prototype/shadow of the real thing.
104 */
105 u_char wd_laar_proto;
106 u_char cr_proto;
107 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
108 int is790; /* set by the probe code if the card is 790
109 * based */
110
111/*
112 * HP PC LAN PLUS card support.
113 */
114
115 u_short hpp_options; /* flags controlling behaviour of the HP card */
116 u_short hpp_id; /* software revision and other fields */
117 caddr_t hpp_mem_start; /* Memory-mapped IO register address */
118
119 caddr_t mem_start; /* NIC memory start address */
120 caddr_t mem_end; /* NIC memory end address */
121 u_long mem_size; /* total NIC memory size */
122 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
123
124 u_char mem_shared; /* NIC memory is shared with host */
125 u_char xmit_busy; /* transmitter is busy */
126 u_char txb_cnt; /* number of transmit buffers */
127 u_char txb_inuse; /* number of TX buffers currently in-use */
128
129 u_char txb_new; /* pointer to where new buffer will be added */
130 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
131 u_short txb_len[8]; /* buffered xmit buffer lengths */
132 u_char tx_page_start; /* first page of TX buffer area */
133 u_char rec_page_start; /* first page of RX ring-buffer */
134 u_char rec_page_stop; /* last page of RX ring-buffer */
135 u_char next_packet; /* pointer to next unread RX packet */
136 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
137};
138
139static struct ed_softc ed_softc[NED];
140
141static int ed_attach __P((struct ed_softc *, int, int));
142static int ed_attach_isa __P((struct isa_device *));
143
144static void ed_init __P((void *));
145static int ed_ioctl __P((struct ifnet *, int, caddr_t));
146static int ed_probe __P((struct isa_device *));
147static void ed_start __P((struct ifnet *));
148static void ed_reset __P((struct ifnet *));
149static void ed_watchdog __P((struct ifnet *));
150
151static void ed_stop __P((struct ed_softc *));
152static int ed_probe_generic8390 __P((struct ed_softc *));
153static int ed_probe_WD80x3 __P((struct isa_device *));
154static int ed_probe_3Com __P((struct isa_device *));
155static int ed_probe_Novell __P((struct isa_device *));
156static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int));
157static int ed_probe_HP_pclanp __P((struct isa_device *));
158
159#include "pci.h"
160#if NPCI > 0
161void *ed_attach_NE2000_pci __P((int, int));
162#endif
163
164#include "crd.h"
165#if NCRD > 0
166static int ed_probe_pccard __P((struct isa_device *, u_char *));
167#endif
168
169static void ds_getmcaf __P((struct ed_softc *, u_long *));
170
171static void ed_get_packet(struct ed_softc *, char *, /* u_short */ int, int);
172
173static void ed_rint __P((struct ed_softc *));
174static void ed_xmit __P((struct ed_softc *));
175static char * ed_ring_copy __P((struct ed_softc *, char *, char *,
176 /* u_short */ int));
177static void ed_hpp_set_physical_link __P((struct ed_softc *));
178static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
179 /* u_short */ int));
180static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
181 int));
182
183static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *,
184 /* u_short */ int));
185static void ed_pio_writemem __P((struct ed_softc *, char *,
186 /* u_short */ int, /* u_short */ int));
187static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
188 int));
189void edintr_sc __P((struct ed_softc *));
190
191static void ed_setrcr(struct ed_softc *);
192
193static u_long ds_crc(u_char *ep);
194
195#if NCRD > 0
196#include <sys/select.h>
197#include <pccard/card.h>
198#include <pccard/driver.h>
199#include <pccard/slot.h>
200
201/*
202 * PC-Card (PCMCIA) specific code.
203 */
204static int card_intr(struct pccard_dev *); /* Interrupt handler */
205static void edunload(struct pccard_dev *); /* Disable driver */
206static void edsuspend(struct pccard_dev *); /* Suspend driver */
207static int edinit(struct pccard_dev *, int); /* init device */
208
209static struct pccard_drv ed_info = {
210 "ed",
211 card_intr,
212 edunload,
213 edsuspend,
214 edinit,
215 0, /* Attributes - presently unused */
216 &net_imask /* Interrupt mask for device */
217 /* XXX - Should this also include net_imask? */
218};
219
220/*
221 * Called when a power down is requested. Shuts down the
222 * device and configures the device as unavailable (but
223 * still loaded...). A resume is done by calling
224 * edinit with first=0. This is called when the user suspends
225 * the system, or the APM code suspends the system.
226 */
227static void
228edsuspend(struct pccard_dev *dp)
229{
230 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit];
231 /*
232 * Some 'ed' cards will generate a interrupt as they go away,
233 * and by the time the interrupt handler gets to the card,
234 * the interrupt can't be cleared.
235 * By setting gone here, we tell the handler to ignore the
236 * interrupt when it happens.
237 */
238 sc->gone = 1; /* avoid spinning endlessly in interrupt handler */
239
240 printf("ed%d: suspending\n", dp->isahd.id_unit);
241}
242
243/*
244 * Initialize the device - called from Slot manager.
245 * If first is set, then check for the device's existence
246 * before initializing it. Once initialized, the device table may
247 * be set up.
248 */
249static int
250edinit(struct pccard_dev *dp, int first)
251{
252 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit];
253
254 /* validate unit number. */
255 if (first) {
256 if (dp->isahd.id_unit >= NED)
257 return(ENODEV);
258 /*
259 * Probe the device. If a value is returned, the
260 * device was found at the location.
261 */
262 sc->gone = 0;
263 if (ed_probe_pccard(&dp->isahd,dp->misc)==0)
264 return(ENXIO);
265 if (ed_attach_isa(&dp->isahd)==0)
266 return(ENXIO);
267 } else {
268 sc->gone = 0; /* reenable after a suspend */
269 }
270 /*
271 * XXX TODO:
272 * If it was initialized before, the device structure
273 * should also be initialized. We should
274 * reset (and possibly restart) the hardware, but
275 * I am not sure of the best way to do this...
276 */
277 return(0);
278}
279
280/*
281 * edunload - unload the driver and clear the table.
282 * XXX TODO:
283 * This is usually called when the card is ejected, but
284 * can be caused by a modunload of a controller driver.
285 * The idea is to reset the driver's view of the device
286 * and ensure that any driver entry points such as
287 * read and write do not hang.
288 */
289static void
290edunload(struct pccard_dev *dp)
291{
292 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit];
293 struct ifnet *ifp = &sc->arpcom.ac_if;
294
295 if (sc->gone) {
296 printf("ed%d: already unloaded\n", dp->isahd.id_unit);
297 return;
298 }
299 ifp->if_flags &= ~IFF_RUNNING;
300 if_down(ifp);
301 sc->gone = 1;
302 printf("ed%d: unload\n", dp->isahd.id_unit);
303}
304
305/*
306 * card_intr - Shared interrupt called from
307 * front end of PC-Card handler.
308 */
309static int
310card_intr(struct pccard_dev *dp)
311{
312 edintr_sc(&ed_softc[dp->isahd.id_unit]);
313 return(1);
314}
315#endif /* NCRD > 0 */
316
317struct isa_driver eddriver = {
318 ed_probe,
319 ed_attach_isa,
320 "ed",
321 1 /* We are ultra sensitive */
322};
323
324/*
325 * Interrupt conversion table for WD/SMC ASIC/83C584
326 * (IRQ* are defined in icu.h)
327 */
328static unsigned short ed_intr_mask[] = {
329 IRQ9,
330 IRQ3,
331 IRQ5,
332 IRQ7,
333 IRQ10,
334 IRQ11,
335 IRQ15,
336 IRQ4
337};
338
339/*
340 * Interrupt conversion table for 83C790
341 */
342static unsigned short ed_790_intr_mask[] = {
343 0,
344 IRQ9,
345 IRQ3,
346 IRQ5,
347 IRQ7,
348 IRQ10,
349 IRQ11,
350 IRQ15
351};
352
353/*
354 * Interrupt conversion table for the HP PC LAN+
355 */
356
357static unsigned short ed_hpp_intr_mask[] = {
358 0, /* 0 */
359 0, /* 1 */
360 0, /* 2 */
361 IRQ3, /* 3 */
362 IRQ4, /* 4 */
363 IRQ5, /* 5 */
364 IRQ6, /* 6 */
365 IRQ7, /* 7 */
366 0, /* 8 */
367 IRQ9, /* 9 */
368 IRQ10, /* 10 */
369 IRQ11, /* 11 */
370 IRQ12, /* 12 */
371 0, /* 13 */
372 0, /* 14 */
373 IRQ15 /* 15 */
374};
375
376/*
377 * Determine if the device is present
378 *
379 * on entry:
380 * a pointer to an isa_device struct
381 * on exit:
382 * NULL if device not found
383 * or # of i/o addresses used (if found)
384 */
385static int
386ed_probe(isa_dev)
387 struct isa_device *isa_dev;
388{
389 int nports;
390
391#if NCRD > 0
392 /*
393 * If PC-Card probe required, then register driver with
394 * slot manager.
395 */
396 pccard_add_driver(&ed_info);
397#endif
398
399 nports = ed_probe_WD80x3(isa_dev);
400 if (nports)
401 return (nports);
402
403 nports = ed_probe_3Com(isa_dev);
404 if (nports)
405 return (nports);
406
407 nports = ed_probe_Novell(isa_dev);
408 if (nports)
409 return (nports);
410
411 nports = ed_probe_HP_pclanp(isa_dev);
412 if (nports)
413 return (nports);
414
415 return (0);
416}
417
418/*
419 * Generic probe routine for testing for the existance of a DS8390.
420 * Must be called after the NIC has just been reset. This routine
421 * works by looking at certain register values that are guaranteed
422 * to be initialized a certain way after power-up or reset. Seems
423 * not to currently work on the 83C690.
424 *
425 * Specifically:
426 *
427 * Register reset bits set bits
428 * Command Register (CR) TXP, STA RD2, STP
429 * Interrupt Status (ISR) RST
430 * Interrupt Mask (IMR) All bits
431 * Data Control (DCR) LAS
432 * Transmit Config. (TCR) LB1, LB0
433 *
434 * We only look at the CR and ISR registers, however, because looking at
435 * the others would require changing register pages (which would be
436 * intrusive if this isn't an 8390).
437 *
438 * Return 1 if 8390 was found, 0 if not.
439 */
440
441static int
442ed_probe_generic8390(sc)
443 struct ed_softc *sc;
444{
445 if ((inb(sc->nic_addr + ED_P0_CR) &
446 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
447 (ED_CR_RD2 | ED_CR_STP))
448 return (0);
449 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
450 return (0);
451
452 return (1);
453}
454
455/*
456 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
457 */
458static int
459ed_probe_WD80x3(isa_dev)
460 struct isa_device *isa_dev;
461{
462 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
463 int i;
464 u_int memsize;
465 u_char iptr, isa16bit, sum;
466
467 sc->asic_addr = isa_dev->id_iobase;
468 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
469 sc->is790 = 0;
470
471#ifdef TOSH_ETHER
472 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
473 DELAY(10000);
474#endif
475
476 /*
477 * Attempt to do a checksum over the station address PROM. If it
478 * fails, it's probably not a SMC/WD board. There is a problem with
479 * this, though: some clone WD boards don't pass the checksum test.
480 * Danpex boards for one.
481 */
482 for (sum = 0, i = 0; i < 8; ++i)
483 sum += inb(sc->asic_addr + ED_WD_PROM + i);
484
485 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
486
487 /*
488 * Checksum is invalid. This often happens with cheap WD8003E
489 * clones. In this case, the checksum byte (the eighth byte)
490 * seems to always be zero.
491 */
492 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
493 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
494 return (0);
495 }
496 /* reset card to force it into a known state. */
497#ifdef TOSH_ETHER
498 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
499#else
500 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
501#endif
502 DELAY(100);
503 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
504 /* wait in the case this card is reading it's EEROM */
505 DELAY(5000);
506
507 sc->vendor = ED_VENDOR_WD_SMC;
508 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
509
510 /*
511 * Set initial values for width/size.
512 */
513 memsize = 8192;
514 isa16bit = 0;
515 switch (sc->type) {
516 case ED_TYPE_WD8003S:
517 sc->type_str = "WD8003S";
518 break;
519 case ED_TYPE_WD8003E:
520 sc->type_str = "WD8003E";
521 break;
522 case ED_TYPE_WD8003EB:
523 sc->type_str = "WD8003EB";
524 break;
525 case ED_TYPE_WD8003W:
526 sc->type_str = "WD8003W";
527 break;
528 case ED_TYPE_WD8013EBT:
529 sc->type_str = "WD8013EBT";
530 memsize = 16384;
531 isa16bit = 1;
532 break;
533 case ED_TYPE_WD8013W:
534 sc->type_str = "WD8013W";
535 memsize = 16384;
536 isa16bit = 1;
537 break;
538 case ED_TYPE_WD8013EP: /* also WD8003EP */
539 if (inb(sc->asic_addr + ED_WD_ICR)
540 & ED_WD_ICR_16BIT) {
541 isa16bit = 1;
542 memsize = 16384;
543 sc->type_str = "WD8013EP";
544 } else {
545 sc->type_str = "WD8003EP";
546 }
547 break;
548 case ED_TYPE_WD8013WC:
549 sc->type_str = "WD8013WC";
550 memsize = 16384;
551 isa16bit = 1;
552 break;
553 case ED_TYPE_WD8013EBP:
554 sc->type_str = "WD8013EBP";
555 memsize = 16384;
556 isa16bit = 1;
557 break;
558 case ED_TYPE_WD8013EPC:
559 sc->type_str = "WD8013EPC";
560 memsize = 16384;
561 isa16bit = 1;
562 break;
563 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
564 case ED_TYPE_SMC8216T:
565 if (sc->type == ED_TYPE_SMC8216C) {
566 sc->type_str = "SMC8216/SMC8216C";
567 } else {
568 sc->type_str = "SMC8216T";
569 }
570
571 outb(sc->asic_addr + ED_WD790_HWR,
572 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
573 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
574 case ED_WD790_RAR_SZ64:
575 memsize = 65536;
576 break;
577 case ED_WD790_RAR_SZ32:
578 memsize = 32768;
579 break;
580 case ED_WD790_RAR_SZ16:
581 memsize = 16384;
582 break;
583 case ED_WD790_RAR_SZ8:
584 /* 8216 has 16K shared mem -- 8416 has 8K */
585 if (sc->type == ED_TYPE_SMC8216C) {
586 sc->type_str = "SMC8416C/SMC8416BT";
587 } else {
588 sc->type_str = "SMC8416T";
589 }
590 memsize = 8192;
591 break;
592 }
593 outb(sc->asic_addr + ED_WD790_HWR,
594 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
595
596 isa16bit = 1;
597 sc->is790 = 1;
598 break;
599#ifdef TOSH_ETHER
600 case ED_TYPE_TOSHIBA1:
601 sc->type_str = "Toshiba1";
602 memsize = 32768;
603 isa16bit = 1;
604 break;
605 case ED_TYPE_TOSHIBA4:
606 sc->type_str = "Toshiba4";
607 memsize = 32768;
608 isa16bit = 1;
609 break;
610#endif
611 default:
612 sc->type_str = "";
613 break;
614 }
615
616 /*
617 * Make some adjustments to initial values depending on what is found
618 * in the ICR.
619 */
620 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
621#ifdef TOSH_ETHER
622 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
623#endif
624 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
625 isa16bit = 0;
626 memsize = 8192;
627 }
628
629#if ED_DEBUG
630 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
631 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize);
632 for (i = 0; i < 8; i++)
633 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
634#endif
635
636 /*
637 * Allow the user to override the autoconfiguration
638 */
639 if (isa_dev->id_msize)
640 memsize = isa_dev->id_msize;
641
642 /*
643 * (note that if the user specifies both of the following flags that
644 * '8bit' mode intentionally has precedence)
645 */
646 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
647 isa16bit = 1;
648 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
649 isa16bit = 0;
650
651 /*
652 * If possible, get the assigned interrupt number from the card and
653 * use it.
654 */
655 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
656
657 /*
658 * Assemble together the encoded interrupt number.
659 */
660 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
661 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
662 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
663
664 /*
665 * If no interrupt specified (or "?"), use what the board tells us.
666 */
667 if (isa_dev->id_irq <= 0)
668 isa_dev->id_irq = ed_intr_mask[iptr];
669
670 /*
671 * Enable the interrupt.
672 */
673 outb(isa_dev->id_iobase + ED_WD_IRR,
674 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
675 }
676 if (sc->is790) {
677 outb(isa_dev->id_iobase + ED_WD790_HWR,
678 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH);
679 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
680 (inb(isa_dev->id_iobase + ED_WD790_GCR) &
681 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
682 outb(isa_dev->id_iobase + ED_WD790_HWR,
683 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
684
685 /*
686 * If no interrupt specified (or "?"), use what the board tells us.
687 */
688 if (isa_dev->id_irq <= 0)
689 isa_dev->id_irq = ed_790_intr_mask[iptr];
690
691 /*
692 * Enable interrupts.
693 */
694 outb(isa_dev->id_iobase + ED_WD790_ICR,
695 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL);
696 }
697 if (isa_dev->id_irq <= 0) {
698 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n",
699 isa_dev->id_unit, sc->type_str);
700 return (0);
701 }
702 sc->isa16bit = isa16bit;
703 sc->mem_shared = 1;
704 isa_dev->id_msize = memsize;
705 sc->mem_start = (caddr_t) isa_dev->id_maddr;
706
707 /*
708 * allocate one xmit buffer if < 16k, two buffers otherwise
709 */
710 if ((memsize < 16384) ||
711 (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
712 sc->txb_cnt = 1;
713 } else {
714 sc->txb_cnt = 2;
715 }
716 sc->tx_page_start = ED_WD_PAGE_OFFSET;
717 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
718 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
719 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
720 sc->mem_size = memsize;
721 sc->mem_end = sc->mem_start + memsize;
722
723 /*
724 * Get station address from on-board ROM
725 */
726 for (i = 0; i < ETHER_ADDR_LEN; ++i)
727 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
728
729 /*
730 * Set upper address bits and 8/16 bit access to shared memory
731 */
732 if (isa16bit) {
733 if (sc->is790) {
734 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
735 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
736 } else {
737 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
738 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
739 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
740 }
741 } else {
742 if (((sc->type & ED_WD_SOFTCONFIG) ||
743#ifdef TOSH_ETHER
744 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
745#endif
746 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
747 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
748 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
749 }
750 }
751
752 /*
753 * Set address and enable interface shared memory.
754 */
755 if (!sc->is790) {
756#ifdef TOSH_ETHER
757 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
758 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f));
759 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW);
760
761#else
762 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
763 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
764#endif
765 sc->cr_proto = ED_CR_RD2;
766 } else {
767 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
768 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH));
769 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
770 ((kvtop(sc->mem_start) >> 11) & 0x40) |
771 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0));
772 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
773 sc->cr_proto = 0;
774 }
775
776#if 0
777 printf("starting memory performance test at 0x%x, size %d...\n",
778 sc->mem_start, memsize*16384);
779 for (i = 0; i < 16384; i++)
780 bzero(sc->mem_start, memsize);
781 printf("***DONE***\n");
782#endif
783
784 /*
785 * Now zero memory and verify that it is clear
786 */
787 bzero(sc->mem_start, memsize);
788
789 for (i = 0; i < memsize; ++i) {
790 if (sc->mem_start[i]) {
791 printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
792 isa_dev->id_unit, kvtop(sc->mem_start + i));
793
794 /*
795 * Disable 16 bit access to shared memory
796 */
797 if (isa16bit) {
798 if (sc->is790) {
799 outb(sc->asic_addr + ED_WD_MSR, 0x00);
800 }
801 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
802 ~ED_WD_LAAR_M16EN));
803 }
804 return (0);
805 }
806 }
807
808 /*
809 * Disable 16bit access to shared memory - we leave it
810 * disabled so that 1) machines reboot properly when the board
811 * is set 16 bit mode and there are conflicting 8bit
812 * devices/ROMS in the same 128k address space as this boards
813 * shared memory. and 2) so that other 8 bit devices with
814 * shared memory can be used in this 128k region, too.
815 */
816 if (isa16bit) {
817 if (sc->is790) {
818 outb(sc->asic_addr + ED_WD_MSR, 0x00);
819 }
820 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
821 ~ED_WD_LAAR_M16EN));
822 }
823 return (ED_WD_IO_PORTS);
824}
825
826/*
827 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
828 */
829static int
830ed_probe_3Com(isa_dev)
831 struct isa_device *isa_dev;
832{
833 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
834 int i;
835 u_int memsize;
836 u_char isa16bit;
837
838 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
839 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
840
841 /*
842 * Verify that the kernel configured I/O address matches the board
843 * configured address
844 */
845 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
846 case ED_3COM_BCFR_300:
847 if (isa_dev->id_iobase != 0x300)
848 return (0);
849 break;
850 case ED_3COM_BCFR_310:
851 if (isa_dev->id_iobase != 0x310)
852 return (0);
853 break;
854 case ED_3COM_BCFR_330:
855 if (isa_dev->id_iobase != 0x330)
856 return (0);
857 break;
858 case ED_3COM_BCFR_350:
859 if (isa_dev->id_iobase != 0x350)
860 return (0);
861 break;
862 case ED_3COM_BCFR_250:
863 if (isa_dev->id_iobase != 0x250)
864 return (0);
865 break;
866 case ED_3COM_BCFR_280:
867 if (isa_dev->id_iobase != 0x280)
868 return (0);
869 break;
870 case ED_3COM_BCFR_2A0:
871 if (isa_dev->id_iobase != 0x2a0)
872 return (0);
873 break;
874 case ED_3COM_BCFR_2E0:
875 if (isa_dev->id_iobase != 0x2e0)
876 return (0);
877 break;
878 default:
879 return (0);
880 }
881
882 /*
883 * Verify that the kernel shared memory address matches the board
884 * configured address.
885 */
886 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
887 case ED_3COM_PCFR_DC000:
888 if (kvtop(isa_dev->id_maddr) != 0xdc000)
889 return (0);
890 break;
891 case ED_3COM_PCFR_D8000:
892 if (kvtop(isa_dev->id_maddr) != 0xd8000)
893 return (0);
894 break;
895 case ED_3COM_PCFR_CC000:
896 if (kvtop(isa_dev->id_maddr) != 0xcc000)
897 return (0);
898 break;
899 case ED_3COM_PCFR_C8000:
900 if (kvtop(isa_dev->id_maddr) != 0xc8000)
901 return (0);
902 break;
903 default:
904 return (0);
905 }
906
907
908 /*
909 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
910 * sequence because it'll lock up if the cable isn't connected if we
911 * don't.
912 */
913 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
914
915 /*
916 * Wait for a while, then un-reset it
917 */
918 DELAY(50);
919
920 /*
921 * The 3Com ASIC defaults to rather strange settings for the CR after
922 * a reset - it's important to set it again after the following outb
923 * (this is done when we map the PROM below).
924 */
925 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
926
927 /*
928 * Wait a bit for the NIC to recover from the reset
929 */
930 DELAY(5000);
931
932 sc->vendor = ED_VENDOR_3COM;
933 sc->type_str = "3c503";
934 sc->mem_shared = 1;
935 sc->cr_proto = ED_CR_RD2;
936
937 /*
938 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
939 * to it.
940 */
941 memsize = 8192;
942
943 /*
944 * Get station address from on-board ROM
945 */
946
947 /*
948 * First, map ethernet address PROM over the top of where the NIC
949 * registers normally appear.
950 */
951 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
952
953 for (i = 0; i < ETHER_ADDR_LEN; ++i)
954 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
955
956 /*
957 * Unmap PROM - select NIC registers. The proper setting of the
958 * tranceiver is set in ed_init so that the attach code is given a
959 * chance to set the default based on a compile-time config option
960 */
961 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
962
963 /*
964 * Determine if this is an 8bit or 16bit board
965 */
966
967 /*
968 * select page 0 registers
969 */
970 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
971
972 /*
973 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
974 * board.
975 */
976 outb(sc->nic_addr + ED_P0_DCR, 0);
977
978 /*
979 * select page 2 registers
980 */
981 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
982
983 /*
984 * The 3c503 forces the WTS bit to a one if this is a 16bit board
985 */
986 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
987 isa16bit = 1;
988 else
989 isa16bit = 0;
990
991 /*
992 * select page 0 registers
993 */
994 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
995
996 sc->mem_start = (caddr_t) isa_dev->id_maddr;
997 sc->mem_size = memsize;
998 sc->mem_end = sc->mem_start + memsize;
999
1000 /*
1001 * We have an entire 8k window to put the transmit buffers on the
1002 * 16bit boards. But since the 16bit 3c503's shared memory is only
1003 * fast enough to overlap the loading of one full-size packet, trying
1004 * to load more than 2 buffers can actually leave the transmitter idle
1005 * during the load. So 2 seems the best value. (Although a mix of
1006 * variable-sized packets might change this assumption. Nonetheless,
1007 * we optimize for linear transfers of same-size packets.)
1008 */
1009 if (isa16bit) {
1010 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
1011 sc->txb_cnt = 1;
1012 else
1013 sc->txb_cnt = 2;
1014
1015 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
1016 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
1017 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
1018 ED_3COM_RX_PAGE_OFFSET_16BIT;
1019 sc->mem_ring = sc->mem_start;
1020 } else {
1021 sc->txb_cnt = 1;
1022 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
1023 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
1024 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
1025 ED_3COM_TX_PAGE_OFFSET_8BIT;
1026 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
1027 }
1028
1029 sc->isa16bit = isa16bit;
1030
1031 /*
1032 * Initialize GA page start/stop registers. Probably only needed if
1033 * doing DMA, but what the hell.
1034 */
1035 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
1036 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
1037
1038 /*
1039 * Set IRQ. 3c503 only allows a choice of irq 2-5.
1040 */
1041 switch (isa_dev->id_irq) {
1042 case IRQ2:
1043 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
1044 break;
1045 case IRQ3:
1046 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
1047 break;
1048 case IRQ4:
1049 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
1050 break;
1051 case IRQ5:
1052 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
1053 break;
1054 default:
1055 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n",
1056 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
1057 return (0);
1058 }
1059
1060 /*
1061 * Initialize GA configuration register. Set bank and enable shared
1062 * mem.
1063 */
1064 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
1065 ED_3COM_GACFR_MBS0);
1066
1067 /*
1068 * Initialize "Vector Pointer" registers. These gawd-awful things are
1069 * compared to 20 bits of the address on ISA, and if they match, the
1070 * shared memory is disabled. We set them to 0xffff0...allegedly the
1071 * reset vector.
1072 */
1073 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
1074 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
1075 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
1076
1077 /*
1078 * Zero memory and verify that it is clear
1079 */
1080 bzero(sc->mem_start, memsize);
1081
1082 for (i = 0; i < memsize; ++i)
1083 if (sc->mem_start[i]) {
1084 printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
1085 isa_dev->id_unit, kvtop(sc->mem_start + i));
1086 return (0);
1087 }
1088 isa_dev->id_msize = memsize;
1089 return (ED_3COM_IO_PORTS);
1090}
1091
1092/*
1093 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1094 */
1095static int
1096ed_probe_Novell_generic(sc, port, unit, flags)
1097 struct ed_softc *sc;
1098 int port;
1099 int unit;
1100 int flags;
1101{
1102 u_int memsize, n;
1103 u_char romdata[16], tmp;
1104 static char test_pattern[32] = "THIS is A memory TEST pattern";
1105 char test_buffer[32];
1106
1107 sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET;
1108 sc->nic_addr = port + ED_NOVELL_NIC_OFFSET;
1109
1110 /* XXX - do Novell-specific probe here */
1111
1112 /* Reset the board */
1113#ifdef GWETHER
1114 outb(sc->asic_addr + ED_NOVELL_RESET, 0);
1115 DELAY(200);
1116#endif /* GWETHER */
1117 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
1118
1119 /*
1120 * I don't know if this is necessary; probably cruft leftover from
1121 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1122 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
1123 * non-invasive...but some boards don't seem to reset and I don't have
1124 * complete documentation on what the 'right' thing to do is...so we
1125 * do the invasive thing for now. Yuck.]
1126 */
1127 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
1128 DELAY(5000);
1129
1130 /*
1131 * This is needed because some NE clones apparently don't reset the
1132 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1133 * - this makes the probe invasive! ...Done against my better
1134 * judgement. -DLG
1135 */
1136 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1137
1138 DELAY(5000);
1139
1140 /* Make sure that we really have an 8390 based board */
1141 if (!ed_probe_generic8390(sc))
1142 return (0);
1143
1144 sc->vendor = ED_VENDOR_NOVELL;
1145 sc->mem_shared = 0;
1146 sc->cr_proto = ED_CR_RD2;
1147
1148 /*
1149 * Test the ability to read and write to the NIC memory. This has the
1150 * side affect of determining if this is an NE1000 or an NE2000.
1151 */
1152
1153 /*
1154 * This prevents packets from being stored in the NIC memory when the
1155 * readmem routine turns on the start bit in the CR.
1156 */
1157 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1158
1159 /* Temporarily initialize DCR for byte operations */
1160 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1161
1162 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1163 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1164
1165 sc->isa16bit = 0;
1166
1167 /*
1168 * Write a test pattern in byte mode. If this fails, then there
1169 * probably isn't any memory at 8k - which likely means that the board
1170 * is an NE2000.
1171 */
1172 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1173 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1174
1175 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
1176 /* not an NE1000 - try NE2000 */
1177
1178 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1179 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1180 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1181
1182 sc->isa16bit = 1;
1183
1184 /*
1185 * Write a test pattern in word mode. If this also fails, then
1186 * we don't know what this board is.
1187 */
1188 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1189 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1190
1191 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
1192 return (0); /* not an NE2000 either */
1193
1194 sc->type = ED_TYPE_NE2000;
1195 sc->type_str = "NE2000";
1196 } else {
1197 sc->type = ED_TYPE_NE1000;
1198 sc->type_str = "NE1000";
1199 }
1200
1201 /* 8k of memory plus an additional 8k if 16bit */
1202 memsize = 8192 + sc->isa16bit * 8192;
1203
1204#if 0 /* probably not useful - NE boards only come two ways */
1205 /* allow kernel config file overrides */
1206 if (isa_dev->id_msize)
1207 memsize = isa_dev->id_msize;
1208#endif
1209
1210 sc->mem_size = memsize;
1211
1212 /* NIC memory doesn't start at zero on an NE board */
1213 /* The start address is tied to the bus width */
1214 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1215 sc->mem_end = sc->mem_start + memsize;
1216 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1217
1218#ifdef GWETHER
1219 {
1220 int x, i, mstart = 0, msize = 0;
1221 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1222
1223 for (i = 0; i < ED_PAGE_SIZE; i++)
1224 pbuf0[i] = 0;
1225
1226 /* Clear all the memory. */
1227 for (x = 1; x < 256; x++)
1228 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1229
1230 /* Search for the start of RAM. */
1231 for (x = 1; x < 256; x++) {
1232 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1233 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1234 for (i = 0; i < ED_PAGE_SIZE; i++)
1235 pbuf[i] = 255 - x;
1236 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1237 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1238 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1239 mstart = x * ED_PAGE_SIZE;
1240 msize = ED_PAGE_SIZE;
1241 break;
1242 }
1243 }
1244 }
1245
1246 if (mstart == 0) {
1247 printf("ed%d: Cannot find start of RAM.\n", unit);
1248 return 0;
1249 }
1250 /* Search for the start of RAM. */
1251 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1252 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1253 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1254 for (i = 0; i < ED_PAGE_SIZE; i++)
1255 pbuf[i] = 255 - x;
1256 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1257 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1258 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1259 msize += ED_PAGE_SIZE;
1260 else {
1261 break;
1262 }
1263 } else {
1264 break;
1265 }
1266 }
1267
1268 if (msize == 0) {
1269 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x);
1270 return 0;
1271 }
1272 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize);
1273
1274 sc->mem_size = msize;
1275 sc->mem_start = (char *) mstart;
1276 sc->mem_end = (char *) (msize + mstart);
1277 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1278 }
1279#endif /* GWETHER */
1280
1281 /*
1282 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1283 * otherwise).
1284 */
1285 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1286 sc->txb_cnt = 1;
1287 else
1288 sc->txb_cnt = 2;
1289
1290 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1291 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1292
1293 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1294
1295 ed_pio_readmem(sc, 0, romdata, 16);
1296 for (n = 0; n < ETHER_ADDR_LEN; n++)
1297 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1298
1299#ifdef GWETHER
1300 if (sc->arpcom.ac_enaddr[2] == 0x86) {
1301 sc->type_str = "Gateway AT";
1302 }
1303#endif /* GWETHER */
1304
1305 /* clear any pending interrupts that might have occurred above */
1306 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1307
1308 return (ED_NOVELL_IO_PORTS);
1309}
1310
1311static int
1312ed_probe_Novell(isa_dev)
1313 struct isa_device *isa_dev;
1314{
1315 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1316
1317 isa_dev->id_maddr = 0;
1318 return ed_probe_Novell_generic(sc, isa_dev->id_iobase,
1319 isa_dev->id_unit, isa_dev->id_flags);
1320}
1321
1322#if NCRD > 0
1323
1324/*
1325 * Probe framework for pccards. Replicates the standard framework,
1326 * minus the pccard driver registration and ignores the ether address
1327 * supplied (from the CIS), relying on the probe to find it instead.
1328 */
1329static int
1330ed_probe_pccard(isa_dev, ether)
1331 struct isa_device *isa_dev;
1332 u_char *ether;
1333{
1334 int nports;
1335
1336 nports = ed_probe_WD80x3(isa_dev);
1337 if (nports)
1338 return (nports);
1339
1340 nports = ed_probe_Novell(isa_dev);
1341 if (nports)
1342 return (nports);
1343
1344 return (0);
1345}
1346
1347#endif /* NCRD > 0 */
1348
1349#define ED_HPP_TEST_SIZE 16
1350
1351/*
1352 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1353 * (HP Part nos: 27247B and 27252A).
1354 *
1355 * The card has an asic wrapper around a DS8390 core. The asic handles
1356 * host accesses and offers both standard register IO and memory mapped
1357 * IO. Memory mapped I/O allows better performance at the expense of greater
1358 * chance of an incompatibility with existing ISA cards.
1359 *
1360 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1361 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1362 * don't allow 32 bit accesses; these are indicated by a bit in the software
1363 * ID register (see if_edreg.h).
1364 *
1365 * Other caveats are: we should read the MAC address only when the card
1366 * is inactive.
1367 *
1368 * For more information; please consult the CRYNWR packet driver.
1369 *
1370 * The AUI port is turned on using the "link2" option on the ifconfig
1371 * command line.
1372 */
1373static int
1374ed_probe_HP_pclanp(isa_dev)
1375 struct isa_device *isa_dev;
1376{
1377 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1378 int n; /* temp var */
1379 int memsize; /* mem on board */
1380 u_char checksum; /* checksum of board address */
1381 u_char irq; /* board configured IRQ */
1382 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1383 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1384
1385
1386 /* Fill in basic information */
1387 sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET;
1388 sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET;
1389 sc->is790 = 0;
1390 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1391
1392 /*
1393 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1394 */
1395
1396 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) ||
1397 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) ||
1398 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) ||
1399 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53))
1400 return 0;
1401
1402 /*
1403 * Read the MAC address and verify checksum on the address.
1404 */
1405
1406 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1407 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1408 checksum += (sc->arpcom.ac_enaddr[n] =
1409 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n));
1410
1411 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1412
1413 if (checksum != 0xFF)
1414 return 0;
1415
1416 /*
1417 * Verify that the software model number is 0.
1418 */
1419
1420 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID);
1421 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) &
1422 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1423 return 0;
1424
1425 /*
1426 * Read in and save the current options configured on card.
1427 */
1428
1429 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION);
1430
1431 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1432 ED_HPP_OPTION_CHIP_RESET |
1433 ED_HPP_OPTION_ENABLE_IRQ);
1434
1435 /*
1436 * Reset the chip. This requires writing to the option register
1437 * so take care to preserve the other bits.
1438 */
1439
1440 outw(sc->asic_addr + ED_HPP_OPTION,
1441 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1442 ED_HPP_OPTION_CHIP_RESET)));
1443
1444 DELAY(5000); /* wait for chip reset to complete */
1445
1446 outw(sc->asic_addr + ED_HPP_OPTION,
1447 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1448 ED_HPP_OPTION_CHIP_RESET |
1449 ED_HPP_OPTION_ENABLE_IRQ)));
1450
1451 DELAY(5000);
1452
1453 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST))
1454 return 0; /* reset did not complete */
1455
1456 /*
1457 * Read out configuration information.
1458 */
1459
1460 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1461
1462 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ);
1463
1464 /*
1465 * Check for impossible IRQ.
1466 */
1467
1468 if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0])))
1469 return 0;
1470
1471 /*
1472 * If the kernel IRQ was specified with a '?' use the cards idea
1473 * of the IRQ. If the kernel IRQ was explicitly specified, it
1474 * should match that of the hardware.
1475 */
1476
1477 if (isa_dev->id_irq <= 0)
1478 isa_dev->id_irq = ed_hpp_intr_mask[irq];
1479 else if (isa_dev->id_irq != ed_hpp_intr_mask[irq])
1480 return 0;
1481
1482 /*
1483 * Fill in softconfig info.
1484 */
1485
1486 sc->vendor = ED_VENDOR_HP;
1487 sc->type = ED_TYPE_HP_PCLANPLUS;
1488 sc->type_str = "HP-PCLAN+";
1489
1490 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1491 sc->mem_start = 0; /* we use offsets inside the card RAM */
1492
1493 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1494
1495 /*
1496 * Check if memory mapping of the I/O registers possible.
1497 */
1498
1499 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1500 {
1501 u_long mem_addr;
1502
1503 /*
1504 * determine the memory address from the board.
1505 */
1506
1507 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1508 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8);
1509
1510 /*
1511 * Check that the kernel specified start of memory and
1512 * hardware's idea of it match.
1513 */
1514
1515 if (mem_addr != kvtop(isa_dev->id_maddr))
1516 return 0;
1517
1518 sc->hpp_mem_start = isa_dev->id_maddr;
1519 }
1520
1521 /*
1522 * The board has 32KB of memory. Is there a way to determine
1523 * this programmatically?
1524 */
1525
1526 memsize = 32768;
1527
1528 /*
1529 * Fill in the rest of the soft config structure.
1530 */
1531
1532 /*
1533 * The transmit page index.
1534 */
1535
1536 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1537
1538 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
1539 sc->txb_cnt = 1;
1540 else
1541 sc->txb_cnt = 2;
1542
1543 /*
1544 * Memory description
1545 */
1546
1547 sc->mem_size = memsize;
1548 sc->mem_ring = sc->mem_start +
1549 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1550 sc->mem_end = sc->mem_start + sc->mem_size;
1551
1552 /*
1553 * Receive area starts after the transmit area and
1554 * continues till the end of memory.
1555 */
1556
1557 sc->rec_page_start = sc->tx_page_start +
1558 (sc->txb_cnt * ED_TXBUF_SIZE);
1559 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1560
1561
1562 sc->cr_proto = 0; /* value works */
1563
1564 /*
1565 * Set the wrap registers for string I/O reads.
1566 */
1567
1568 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1569 outw(sc->asic_addr + ED_HPP_HW_WRAP,
1570 ((sc->rec_page_start / ED_PAGE_SIZE) |
1571 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1572
1573 /*
1574 * Reset the register page to normal operation.
1575 */
1576
1577 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1578
1579 /*
1580 * Verify that we can read/write from adapter memory.
1581 * Create test pattern.
1582 */
1583
1584 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1585 {
1586 test_pattern[n] = (n*n) ^ ~n;
1587 }
1588
1589#undef ED_HPP_TEST_SIZE
1590
1591 /*
1592 * Check that the memory is accessible thru the I/O ports.
1593 * Write out the contents of "test_pattern", read back
1594 * into "test_buffer" and compare the two for any
1595 * mismatch.
1596 */
1597
1598 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1599
1600 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1601 sizeof(test_pattern));
1602 ed_pio_readmem(sc, (n * ED_PAGE_SIZE),
1603 test_buffer, sizeof(test_pattern));
1604
1605 if (bcmp(test_pattern, test_buffer,
1606 sizeof(test_pattern)))
1607 return 0;
1608 }
1609
1610 return (ED_HPP_IO_PORTS);
1611
1612}
1613
1614/*
1615 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1616 */
1617
1618void
1619ed_hpp_set_physical_link(struct ed_softc *sc)
1620{
1621 struct ifnet *ifp = &sc->arpcom.ac_if;
1622 int lan_page;
1623
1624 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1625 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0);
1626
1627 if (ifp->if_flags & IFF_ALTPHYS) {
1628
1629 /*
1630 * Use the AUI port.
1631 */
1632
1633 lan_page |= ED_HPP_LAN_AUI;
1634
1635 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1636 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1637
1638
1639 } else {
1640
1641 /*
1642 * Use the ThinLan interface
1643 */
1644
1645 lan_page &= ~ED_HPP_LAN_AUI;
1646
1647 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1648 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1649
1650 }
1651
1652 /*
1653 * Wait for the lan card to re-initialize itself
1654 */
1655
1656 DELAY(150000); /* wait 150 ms */
1657
1658 /*
1659 * Restore normal pages.
1660 */
1661
1662 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1663
1664}
1665
1666
1667/*
1668 * Install interface into kernel networking data structures
1669 */
1670static int
1671ed_attach(sc, unit, flags)
1672 struct ed_softc *sc;
1673 int unit;
1674 int flags;
1675{
1676 struct ifnet *ifp = &sc->arpcom.ac_if;
1677
1678 /*
1679 * Set interface to stopped condition (reset)
1680 */
1681 ed_stop(sc);
1682
1683 if (!ifp->if_name) {
1684 /*
1685 * Initialize ifnet structure
1686 */
1687 ifp->if_softc = sc;
1688 ifp->if_unit = unit;
1689 ifp->if_name = "ed";
1690 ifp->if_output = ether_output;
1691 ifp->if_start = ed_start;
1692 ifp->if_ioctl = ed_ioctl;
1693 ifp->if_watchdog = ed_watchdog;
1694 ifp->if_init = ed_init;
1695 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1696 ifp->if_linkmib = &sc->mibdata;
1697 ifp->if_linkmiblen = sizeof sc->mibdata;
1698 /*
1699 * XXX - should do a better job.
1700 */
1701 if (sc->is790)
1702 sc->mibdata.dot3StatsEtherChipSet =
1703 DOT3CHIPSET(dot3VendorWesternDigital,
1704 dot3ChipSetWesternDigital83C790);
1705 else
1706 sc->mibdata.dot3StatsEtherChipSet =
1707 DOT3CHIPSET(dot3VendorNational,
1708 dot3ChipSetNational8390);
1709 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1710
1711 /*
1712 * Set default state for ALTPHYS flag (used to disable the
1713 * tranceiver for AUI operation), based on compile-time
1714 * config option.
1715 */
1716 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1717 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1718 IFF_MULTICAST | IFF_ALTPHYS);
1719 else
1720 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1721 IFF_MULTICAST);
1722
1723 /*
1724 * Attach the interface
1725 */
1726 if_attach(ifp);
1727 ether_ifattach(ifp);
1728 }
1729 /* device attach does transition from UNCONFIGURED to IDLE state */
1730
1731 /*
1732 * Print additional info when attached
1733 */
1734 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit,
1735 sc->arpcom.ac_enaddr, ":");
1736
1737 if (sc->type_str && (*sc->type_str != 0))
1738 printf("type %s ", sc->type_str);
1739 else
1740 printf("type unknown (0x%x) ", sc->type);
1741
1742 if (sc->vendor == ED_VENDOR_HP)
1743 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1744 "16-bit" : "32-bit",
1745 sc->hpp_mem_start ? "memory mapped" : "regular");
1746 else
1747 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1748
1749 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1750 (sc->vendor == ED_VENDOR_HP)) &&
1751 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1752
1753 /*
1754 * If BPF is in the kernel, call the attach for it
1755 */
1756#if NBPFILTER > 0
1757 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1758#endif
1759 return 1;
1760}
1761
1762static int
1763ed_attach_isa(isa_dev)
1764 struct isa_device *isa_dev;
1765{
1766 int unit = isa_dev->id_unit;
1767 struct ed_softc *sc = &ed_softc[unit];
1768 int flags = isa_dev->id_flags;
1769
1770 return ed_attach(sc, unit, flags);
1771}
1772
1773#if NPCI > 0
1774void *
1775ed_attach_NE2000_pci(unit, port)
1776 int unit;
1777 int port;
1778{
1779 struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT);
1780 int isa_flags = 0;
1781
1782 if (!sc)
1783 return sc;
1784
1785 bzero(sc, sizeof *sc);
1786 if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0
1787 || ed_attach(sc, unit, isa_flags) == 0) {
1788 free(sc, M_DEVBUF);
1789 return NULL;
1790 }
1791 return sc;
1792}
1793#endif
1794
1795/*
1796 * Reset interface.
1797 */
1798static void
1799ed_reset(ifp)
1800 struct ifnet *ifp;
1801{
1802 struct ed_softc *sc = ifp->if_softc;
1803 int s;
1804
1805 if (sc->gone)
1806 return;
1807 s = splimp();
1808
1809 /*
1810 * Stop interface and re-initialize.
1811 */
1812 ed_stop(sc);
1813 ed_init(sc);
1814
1815 (void) splx(s);
1816}
1817
1818/*
1819 * Take interface offline.
1820 */
1821static void
1822ed_stop(sc)
1823 struct ed_softc *sc;
1824{
1825 int n = 5000;
1826
1827 if (sc->gone)
1828 return;
1829 /*
1830 * Stop everything on the interface, and select page 0 registers.
1831 */
1832 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1833
1834 /*
1835 * Wait for interface to enter stopped state, but limit # of checks to
1836 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1837 * just in case it's an old one.
1838 */
1839 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1840}
1841
1842/*
1843 * Device timeout/watchdog routine. Entered if the device neglects to
1844 * generate an interrupt after a transmit has been started on it.
1845 */
1846static void
1847ed_watchdog(ifp)
1848 struct ifnet *ifp;
1849{
1850 struct ed_softc *sc = ifp->if_softc;
1851
1852 if (sc->gone)
1853 return;
1854 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1855 ifp->if_oerrors++;
1856
1857 ed_reset(ifp);
1858}
1859
1860/*
1861 * Initialize device.
1862 */
1863static void
1864ed_init(xsc)
1865 void *xsc;
1866{
1867 struct ed_softc *sc = xsc;
1868 struct ifnet *ifp = &sc->arpcom.ac_if;
1869 int i, s;
1870
1871 if (sc->gone)
1872 return;
1873
1874 /* address not known */
1875 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1876 return;
1877
1878 /*
1879 * Initialize the NIC in the exact order outlined in the NS manual.
1880 * This init procedure is "mandatory"...don't change what or when
1881 * things happen.
1882 */
1883 s = splimp();
1884
1885 /* reset transmitter flags */
1886 sc->xmit_busy = 0;
1887 ifp->if_timer = 0;
1888
1889 sc->txb_inuse = 0;
1890 sc->txb_new = 0;
1891 sc->txb_next_tx = 0;
1892
1893 /* This variable is used below - don't move this assignment */
1894 sc->next_packet = sc->rec_page_start + 1;
1895
1896 /*
1897 * Set interface for page 0, Remote DMA complete, Stopped
1898 */
1899 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1900
1901 if (sc->isa16bit) {
1902
1903 /*
1904 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1905 * order=80x86, word-wide DMA xfers,
1906 */
1907 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1908 } else {
1909
1910 /*
1911 * Same as above, but byte-wide DMA xfers
1912 */
1913 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1914 }
1915
1916 /*
1917 * Clear Remote Byte Count Registers
1918 */
1919 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1920 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1921
1922 /*
1923 * For the moment, don't store incoming packets in memory.
1924 */
1925 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1926
1927 /*
1928 * Place NIC in internal loopback mode
1929 */
1930 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1931
1932 /*
1933 * Initialize transmit/receive (ring-buffer) Page Start
1934 */
1935 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1936 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1937 /* Set lower bits of byte addressable framing to 0 */
1938 if (sc->is790)
1939 outb(sc->nic_addr + 0x09, 0);
1940
1941 /*
1942 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1943 */
1944 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1945 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1946
1947 /*
1948 * Clear all interrupts. A '1' in each bit position clears the
1949 * corresponding flag.
1950 */
1951 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1952
1953 /*
1954 * Enable the following interrupts: receive/transmit complete,
1955 * receive/transmit error, and Receiver OverWrite.
1956 *
1957 * Counter overflow and Remote DMA complete are *not* enabled.
1958 */
1959 outb(sc->nic_addr + ED_P0_IMR,
1960 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1961
1962 /*
1963 * Program Command Register for page 1
1964 */
1965 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1966
1967 /*
1968 * Copy out our station address
1969 */
1970 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1971 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1972
1973 /*
1974 * Set Current Page pointer to next_packet (initialized above)
1975 */
1976 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1977
1978 /*
1979 * Program Receiver Configuration Register and multicast filter. CR is
1980 * set to page 0 on return.
1981 */
1982 ed_setrcr(sc);
1983
1984 /*
1985 * Take interface out of loopback
1986 */
1987 outb(sc->nic_addr + ED_P0_TCR, 0);
1988
1989 /*
1990 * If this is a 3Com board, the tranceiver must be software enabled
1991 * (there is no settable hardware default).
1992 */
1993 if (sc->vendor == ED_VENDOR_3COM) {
1994 if (ifp->if_flags & IFF_ALTPHYS) {
1995 outb(sc->asic_addr + ED_3COM_CR, 0);
1996 } else {
1997 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1998 }
1999 }
2000
2001 /*
2002 * Set 'running' flag, and clear output active flag.
2003 */
2004 ifp->if_flags |= IFF_RUNNING;
2005 ifp->if_flags &= ~IFF_OACTIVE;
2006
2007 /*
2008 * ...and attempt to start output
2009 */
2010 ed_start(ifp);
2011
2012 (void) splx(s);
2013}
2014
2015/*
2016 * This routine actually starts the transmission on the interface
2017 */
2018static inline void
2019ed_xmit(sc)
2020 struct ed_softc *sc;
2021{
2022 struct ifnet *ifp = (struct ifnet *)sc;
2023 unsigned short len;
2024
2025 if (sc->gone)
2026 return;
2027 len = sc->txb_len[sc->txb_next_tx];
2028
2029 /*
2030 * Set NIC for page 0 register access
2031 */
2032 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2033
2034 /*
2035 * Set TX buffer start page
2036 */
2037 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
2038 sc->txb_next_tx * ED_TXBUF_SIZE);
2039
2040 /*
2041 * Set TX length
2042 */
2043 outb(sc->nic_addr + ED_P0_TBCR0, len);
2044 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
2045
2046 /*
2047 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2048 */
2049 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2050 sc->xmit_busy = 1;
2051
2052 /*
2053 * Point to next transmit buffer slot and wrap if necessary.
2054 */
2055 sc->txb_next_tx++;
2056 if (sc->txb_next_tx == sc->txb_cnt)
2057 sc->txb_next_tx = 0;
2058
2059 /*
2060 * Set a timer just in case we never hear from the board again
2061 */
2062 ifp->if_timer = 2;
2063}
2064
2065/*
2066 * Start output on interface.
2067 * We make two assumptions here:
2068 * 1) that the current priority is set to splimp _before_ this code
2069 * is called *and* is returned to the appropriate priority after
2070 * return
2071 * 2) that the IFF_OACTIVE flag is checked before this code is called
2072 * (i.e. that the output part of the interface is idle)
2073 */
2074static void
2075ed_start(ifp)
2076 struct ifnet *ifp;
2077{
2078 struct ed_softc *sc = ifp->if_softc;
2079 struct mbuf *m0, *m;
2080 caddr_t buffer;
2081 int len;
2082
2083 if (sc->gone) {
2084 printf("ed_start(%p) GONE\n",ifp);
2085 return;
2086 }
2087outloop:
2088
2089 /*
2090 * First, see if there are buffered packets and an idle transmitter -
2091 * should never happen at this point.
2092 */
2093 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2094 printf("ed: packets buffered, but transmitter idle\n");
2095 ed_xmit(sc);
2096 }
2097
2098 /*
2099 * See if there is room to put another packet in the buffer.
2100 */
2101 if (sc->txb_inuse == sc->txb_cnt) {
2102
2103 /*
2104 * No room. Indicate this to the outside world and exit.
2105 */
2106 ifp->if_flags |= IFF_OACTIVE;
2107 return;
2108 }
2109 IF_DEQUEUE(&ifp->if_snd, m);
2110 if (m == 0) {
2111
2112 /*
2113 * We are using the !OACTIVE flag to indicate to the outside
2114 * world that we can accept an additional packet rather than
2115 * that the transmitter is _actually_ active. Indeed, the
2116 * transmitter may be active, but if we haven't filled all the
2117 * buffers with data then we still want to accept more.
2118 */
2119 ifp->if_flags &= ~IFF_OACTIVE;
2120 return;
2121 }
2122
2123 /*
2124 * Copy the mbuf chain into the transmit buffer
2125 */
2126
2127 m0 = m;
2128
2129 /* txb_new points to next open buffer slot */
2130 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2131
2132 if (sc->mem_shared) {
2133
2134 /*
2135 * Special case setup for 16 bit boards...
2136 */
2137 if (sc->isa16bit) {
2138 switch (sc->vendor) {
2139
2140 /*
2141 * For 16bit 3Com boards (which have 16k of
2142 * memory), we have the xmit buffers in a
2143 * different page of memory ('page 0') - so
2144 * change pages.
2145 */
2146 case ED_VENDOR_3COM:
2147 outb(sc->asic_addr + ED_3COM_GACFR,
2148 ED_3COM_GACFR_RSEL);
2149 break;
2150
2151 /*
2152 * Enable 16bit access to shared memory on
2153 * WD/SMC boards.
2154 */
2155 case ED_VENDOR_WD_SMC:{
2156 outb(sc->asic_addr + ED_WD_LAAR,
2157 (sc->wd_laar_proto | ED_WD_LAAR_M16EN));
2158 if (sc->is790) {
2159 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
2160 }
2161 break;
2162 }
2163 }
2164 }
2165 for (len = 0; m != 0; m = m->m_next) {
2166 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2167 buffer += m->m_len;
2168 len += m->m_len;
2169 }
2170
2171 /*
2172 * Restore previous shared memory access
2173 */
2174 if (sc->isa16bit) {
2175 switch (sc->vendor) {
2176 case ED_VENDOR_3COM:
2177 outb(sc->asic_addr + ED_3COM_GACFR,
2178 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2179 break;
2180 case ED_VENDOR_WD_SMC:{
2181 if (sc->is790) {
2182 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2183 }
2184 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
2185 break;
2186 }
2187 }
2188 }
2189 } else {
2190 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2191 if (len == 0)
2192 goto outloop;
2193 }
2194
2195 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2196
2197 sc->txb_inuse++;
2198
2199 /*
2200 * Point to next buffer slot and wrap if necessary.
2201 */
2202 sc->txb_new++;
2203 if (sc->txb_new == sc->txb_cnt)
2204 sc->txb_new = 0;
2205
2206 if (sc->xmit_busy == 0)
2207 ed_xmit(sc);
2208
2209 /*
2210 * Tap off here if there is a bpf listener.
2211 */
2212#if NBPFILTER > 0
2213 if (ifp->if_bpf) {
2214 bpf_mtap(ifp, m0);
2215 }
2216#endif
2217
2218 m_freem(m0);
2219
2220 /*
2221 * Loop back to the top to possibly buffer more packets
2222 */
2223 goto outloop;
2224}
2225
2226/*
2227 * Ethernet interface receiver interrupt.
2228 */
2229static inline void
2230ed_rint(sc)
2231 struct ed_softc *sc;
2232{
2233 struct ifnet *ifp = &sc->arpcom.ac_if;
2234 u_char boundry;
2235 u_short len;
2236 struct ed_ring packet_hdr;
2237 char *packet_ptr;
2238
2239 if (sc->gone)
2240 return;
2241
2242 /*
2243 * Set NIC to page 1 registers to get 'current' pointer
2244 */
2245 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2246
2247 /*
2248 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2249 * i.e. it points to where new data has been buffered. The 'CURR'
2250 * (current) register points to the logical end of the ring-buffer -
2251 * i.e. it points to where additional new data will be added. We loop
2252 * here until the logical beginning equals the logical end (or in
2253 * other words, until the ring-buffer is empty).
2254 */
2255 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
2256
2257 /* get pointer to this buffer's header structure */
2258 packet_ptr = sc->mem_ring +
2259 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2260
2261 /*
2262 * The byte count includes a 4 byte header that was added by
2263 * the NIC.
2264 */
2265 if (sc->mem_shared)
2266 packet_hdr = *(struct ed_ring *) packet_ptr;
2267 else
2268 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2269 sizeof(packet_hdr));
2270 len = packet_hdr.count;
2271 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2272 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2273 /*
2274 * Length is a wild value. There's a good chance that
2275 * this was caused by the NIC being old and buggy.
2276 * The bug is that the length low byte is duplicated in
2277 * the high byte. Try to recalculate the length based on
2278 * the pointer to the next packet.
2279 */
2280 /*
2281 * NOTE: sc->next_packet is pointing at the current packet.
2282 */
2283 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2284 if (packet_hdr.next_packet >= sc->next_packet) {
2285 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2286 } else {
2287 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2288 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2289 }
2290 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2291 + sizeof(struct ed_ring)))
2292 sc->mibdata.dot3StatsFrameTooLongs++;
2293 }
2294 /*
2295 * Be fairly liberal about what we allow as a "reasonable" length
2296 * so that a [crufty] packet will make it to BPF (and can thus
2297 * be analyzed). Note that all that is really important is that
2298 * we have a length that will fit into one mbuf cluster or less;
2299 * the upper layer protocols can then figure out the length from
2300 * their own length field(s).
2301 */
2302 if ((len > sizeof(struct ed_ring)) &&
2303 (len <= MCLBYTES) &&
2304 (packet_hdr.next_packet >= sc->rec_page_start) &&
2305 (packet_hdr.next_packet < sc->rec_page_stop)) {
2306 /*
2307 * Go get packet.
2308 */
2309 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2310 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY);
2311 ifp->if_ipackets++;
2312 } else {
2313 /*
2314 * Really BAD. The ring pointers are corrupted.
2315 */
2316 log(LOG_ERR,
2317 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2318 ifp->if_unit, len);
2319 ifp->if_ierrors++;
2320 ed_reset(ifp);
2321 return;
2322 }
2323
2324 /*
2325 * Update next packet pointer
2326 */
2327 sc->next_packet = packet_hdr.next_packet;
2328
2329 /*
2330 * Update NIC boundry pointer - being careful to keep it one
2331 * buffer behind. (as recommended by NS databook)
2332 */
2333 boundry = sc->next_packet - 1;
2334 if (boundry < sc->rec_page_start)
2335 boundry = sc->rec_page_stop - 1;
2336
2337 /*
2338 * Set NIC to page 0 registers to update boundry register
2339 */
2340 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2341
2342 outb(sc->nic_addr + ED_P0_BNRY, boundry);
2343
2344 /*
2345 * Set NIC to page 1 registers before looping to top (prepare
2346 * to get 'CURR' current pointer)
2347 */
2348 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2349 }
2350}
2351
2352/*
2353 * Ethernet interface interrupt processor
2354 */
2355void
2356edintr_sc(sc)
2357 struct ed_softc *sc;
2358{
2359 struct ifnet *ifp = (struct ifnet *)sc;
2360 u_char isr;
2361
2362 if (sc->gone)
2363 return;
2364 /*
2365 * Set NIC to page 0 registers
2366 */
2367 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2368
2369 /*
2370 * loop until there are no more new interrupts
2371 */
2372 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) {
2373
2374 /*
2375 * reset all the bits that we are 'acknowledging' by writing a
2376 * '1' to each bit position that was set (writing a '1'
2377 * *clears* the bit)
2378 */
2379 outb(sc->nic_addr + ED_P0_ISR, isr);
2380
2381 /*
2382 * Handle transmitter interrupts. Handle these first because
2383 * the receiver will reset the board under some conditions.
2384 */
2385 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2386 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
2387
2388 /*
2389 * Check for transmit error. If a TX completed with an
2390 * error, we end up throwing the packet away. Really
2391 * the only error that is possible is excessive
2392 * collisions, and in this case it is best to allow
2393 * the automatic mechanisms of TCP to backoff the
2394 * flow. Of course, with UDP we're screwed, but this
2395 * is expected when a network is heavily loaded.
2396 */
2397 (void) inb(sc->nic_addr + ED_P0_TSR);
2398 if (isr & ED_ISR_TXE) {
2399 u_char tsr;
2400
2401 /*
2402 * Excessive collisions (16)
2403 */
2404 tsr = inb(sc->nic_addr + ED_P0_TSR);
2405 if ((tsr & ED_TSR_ABT)
2406 && (collisions == 0)) {
2407
2408 /*
2409 * When collisions total 16, the
2410 * P0_NCR will indicate 0, and the
2411 * TSR_ABT is set.
2412 */
2413 collisions = 16;
2414 sc->mibdata.dot3StatsExcessiveCollisions++;
2415 sc->mibdata.dot3StatsCollFrequencies[15]++;
2416 }
2417 if (tsr & ED_TSR_OWC)
2418 sc->mibdata.dot3StatsLateCollisions++;
2419 if (tsr & ED_TSR_CDH)
2420 sc->mibdata.dot3StatsSQETestErrors++;
2421 if (tsr & ED_TSR_CRS)
2422 sc->mibdata.dot3StatsCarrierSenseErrors++;
2423 if (tsr & ED_TSR_FU)
2424 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2425
2426 /*
2427 * update output errors counter
2428 */
2429 ifp->if_oerrors++;
2430 } else {
2431
2432 /*
2433 * Update total number of successfully
2434 * transmitted packets.
2435 */
2436 ifp->if_opackets++;
2437 }
2438
2439 /*
2440 * reset tx busy and output active flags
2441 */
2442 sc->xmit_busy = 0;
2443 ifp->if_flags &= ~IFF_OACTIVE;
2444
2445 /*
2446 * clear watchdog timer
2447 */
2448 ifp->if_timer = 0;
2449
2450 /*
2451 * Add in total number of collisions on last
2452 * transmission.
2453 */
2454 ifp->if_collisions += collisions;
2455 switch(collisions) {
2456 case 0:
2457 case 16:
2458 break;
2459 case 1:
2460 sc->mibdata.dot3StatsSingleCollisionFrames++;
2461 sc->mibdata.dot3StatsCollFrequencies[0]++;
2462 break;
2463 default:
2464 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2465 sc->mibdata.
2466 dot3StatsCollFrequencies[collisions-1]
2467 ++;
2468 break;
2469 }
2470
2471 /*
2472 * Decrement buffer in-use count if not zero (can only
2473 * be zero if a transmitter interrupt occured while
2474 * not actually transmitting). If data is ready to
2475 * transmit, start it transmitting, otherwise defer
2476 * until after handling receiver
2477 */
2478 if (sc->txb_inuse && --sc->txb_inuse)
2479 ed_xmit(sc);
2480 }
2481
2482 /*
2483 * Handle receiver interrupts
2484 */
2485 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2486
2487 /*
2488 * Overwrite warning. In order to make sure that a
2489 * lockup of the local DMA hasn't occurred, we reset
2490 * and re-init the NIC. The NSC manual suggests only a
2491 * partial reset/re-init is necessary - but some chips
2492 * seem to want more. The DMA lockup has been seen
2493 * only with early rev chips - Methinks this bug was
2494 * fixed in later revs. -DG
2495 */
2496 if (isr & ED_ISR_OVW) {
2497 ifp->if_ierrors++;
2498#ifdef DIAGNOSTIC
2499 log(LOG_WARNING,
2500 "ed%d: warning - receiver ring buffer overrun\n",
2501 ifp->if_unit);
2502#endif
2503
2504 /*
2505 * Stop/reset/re-init NIC
2506 */
2507 ed_reset(ifp);
2508 } else {
2509
2510 /*
2511 * Receiver Error. One or more of: CRC error,
2512 * frame alignment error FIFO overrun, or
2513 * missed packet.
2514 */
2515 if (isr & ED_ISR_RXE) {
2516 u_char rsr;
2517 rsr = inb(sc->nic_addr + ED_P0_RSR);
2518 if (rsr & ED_RSR_CRC)
2519 sc->mibdata.dot3StatsFCSErrors++;
2520 if (rsr & ED_RSR_FAE)
2521 sc->mibdata.dot3StatsAlignmentErrors++;
2522 if (rsr & ED_RSR_FO)
2523 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2524 ifp->if_ierrors++;
2525#ifdef ED_DEBUG
2526 printf("ed%d: receive error %x\n", ifp->if_unit,
2527 inb(sc->nic_addr + ED_P0_RSR));
2528#endif
2529 }
2530
2531 /*
2532 * Go get the packet(s) XXX - Doing this on an
2533 * error is dubious because there shouldn't be
2534 * any data to get (we've configured the
2535 * interface to not accept packets with
2536 * errors).
2537 */
2538
2539 /*
2540 * Enable 16bit access to shared memory first
2541 * on WD/SMC boards.
2542 */
2543 if (sc->isa16bit &&
2544 (sc->vendor == ED_VENDOR_WD_SMC)) {
2545
2546 outb(sc->asic_addr + ED_WD_LAAR,
2547 (sc->wd_laar_proto |=
2548 ED_WD_LAAR_M16EN));
2549 if (sc->is790) {
2550 outb(sc->asic_addr + ED_WD_MSR,
2551 ED_WD_MSR_MENB);
2552 }
2553 }
2554 ed_rint(sc);
2555
2556 /* disable 16bit access */
2557 if (sc->isa16bit &&
2558 (sc->vendor == ED_VENDOR_WD_SMC)) {
2559
2560 if (sc->is790) {
2561 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2562 }
2563 outb(sc->asic_addr + ED_WD_LAAR,
2564 (sc->wd_laar_proto &=
2565 ~ED_WD_LAAR_M16EN));
2566 }
2567 }
2568 }
2569
2570 /*
2571 * If it looks like the transmitter can take more data,
2572 * attempt to start output on the interface. This is done
2573 * after handling the receiver to give the receiver priority.
2574 */
2575 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2576 ed_start(ifp);
2577
2578 /*
2579 * return NIC CR to standard state: page 0, remote DMA
2580 * complete, start (toggling the TXP bit off, even if was just
2581 * set in the transmit routine, is *okay* - it is 'edge'
2582 * triggered from low to high)
2583 */
2584 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2585
2586 /*
2587 * If the Network Talley Counters overflow, read them to reset
2588 * them. It appears that old 8390's won't clear the ISR flag
2589 * otherwise - resulting in an infinite loop.
2590 */
2591 if (isr & ED_ISR_CNT) {
2592 (void) inb(sc->nic_addr + ED_P0_CNTR0);
2593 (void) inb(sc->nic_addr + ED_P0_CNTR1);
2594 (void) inb(sc->nic_addr + ED_P0_CNTR2);
2595 }
2596 }
2597}
2598
2599void
2600edintr(unit)
2601 int unit;
2602{
2603 edintr_sc (&ed_softc[unit]);
2604}
2605
2606/*
2607 * Process an ioctl request. This code needs some work - it looks
2608 * pretty ugly.
2609 */
2610static int
2611ed_ioctl(ifp, command, data)
2612 register struct ifnet *ifp;
2613 int command;
2614 caddr_t data;
2615{
2616 struct ed_softc *sc = ifp->if_softc;
2617 struct ifreq *ifr = (struct ifreq *) data;
2618 int s, error = 0;
2619
2620 if (sc->gone) {
2621 ifp->if_flags &= ~IFF_RUNNING;
2622 return ENXIO;
2623 }
2624 s = splimp();
2625
2626 switch (command) {
2627
2628 case SIOCSIFADDR:
2629 case SIOCGIFADDR:
2630 case SIOCSIFMTU:
2631 error = ether_ioctl(ifp, command, data);
2632 break;
2633
2634 case SIOCSIFFLAGS:
2635
2636 /*
2637 * If the interface is marked up and stopped, then start it.
2638 * If it is marked down and running, then stop it.
2639 */
2640 if (ifp->if_flags & IFF_UP) {
2641 if ((ifp->if_flags & IFF_RUNNING) == 0)
2642 ed_init(ifp->if_softc);
2643 } else {
2644 if (ifp->if_flags & IFF_RUNNING) {
2645 ed_stop(sc);
2646 ifp->if_flags &= ~IFF_RUNNING;
2647 }
2648 }
2649
2650#if NBPFILTER > 0
2651
2652 /*
2653 * Promiscuous flag may have changed, so reprogram the RCR.
2654 */
2655 ed_setrcr(sc);
2656#endif
2657
2658 /*
2659 * An unfortunate hack to provide the (required) software
2660 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2661 * disables the tranceiver if set.
2662 */
2663 if (sc->vendor == ED_VENDOR_3COM) {
2664 if (ifp->if_flags & IFF_ALTPHYS) {
2665 outb(sc->asic_addr + ED_3COM_CR, 0);
2666 } else {
2667 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2668 }
2669 } else if (sc->vendor == ED_VENDOR_HP)
2670 ed_hpp_set_physical_link(sc);
2671 break;
2672
2673 case SIOCADDMULTI:
2674 case SIOCDELMULTI:
2675 /*
| 28 */
29
30/*
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
33 *
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
37 *
38 */
39
40#include "ed.h"
41#include "bpfilter.h"
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/conf.h>
46#include <sys/errno.h>
47#include <sys/ioctl.h>
48#include <sys/mbuf.h>
49#include <sys/socket.h>
50#include <sys/syslog.h>
51
52#include <net/if.h>
53#include <net/if_dl.h>
54#include <net/if_mib.h>
55#include <net/if_types.h>
56
57#ifdef INET
58#include <netinet/in.h>
59#include <netinet/in_systm.h>
60#include <netinet/in_var.h>
61#include <netinet/ip.h>
62#include <netinet/if_ether.h>
63#endif
64
65#ifdef IPX
66#include <netipx/ipx.h>
67#include <netipx/ipx_if.h>
68#endif
69
70#ifdef NS
71#include <netns/ns.h>
72#include <netns/ns_if.h>
73#endif
74
75#if NBPFILTER > 0
76#include <net/bpf.h>
77#include <net/bpfdesc.h>
78#endif
79
80#include <machine/clock.h>
81#include <machine/md_var.h>
82
83#include <i386/isa/isa_device.h>
84#include <i386/isa/icu.h>
85#include <i386/isa/if_edreg.h>
86
87/*
88 * ed_softc: per line info and status
89 */
90struct ed_softc {
91 struct arpcom arpcom; /* ethernet common */
92
93 char *type_str; /* pointer to type string */
94 u_char vendor; /* interface vendor */
95 u_char type; /* interface type code */
96 u_char gone; /* HW missing, presumed having a good time */
97
98 u_short asic_addr; /* ASIC I/O bus address */
99 u_short nic_addr; /* NIC (DS8390) I/O bus address */
100
101/*
102 * The following 'proto' variable is part of a work-around for 8013EBT asics
103 * being write-only. It's sort of a prototype/shadow of the real thing.
104 */
105 u_char wd_laar_proto;
106 u_char cr_proto;
107 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
108 int is790; /* set by the probe code if the card is 790
109 * based */
110
111/*
112 * HP PC LAN PLUS card support.
113 */
114
115 u_short hpp_options; /* flags controlling behaviour of the HP card */
116 u_short hpp_id; /* software revision and other fields */
117 caddr_t hpp_mem_start; /* Memory-mapped IO register address */
118
119 caddr_t mem_start; /* NIC memory start address */
120 caddr_t mem_end; /* NIC memory end address */
121 u_long mem_size; /* total NIC memory size */
122 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
123
124 u_char mem_shared; /* NIC memory is shared with host */
125 u_char xmit_busy; /* transmitter is busy */
126 u_char txb_cnt; /* number of transmit buffers */
127 u_char txb_inuse; /* number of TX buffers currently in-use */
128
129 u_char txb_new; /* pointer to where new buffer will be added */
130 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
131 u_short txb_len[8]; /* buffered xmit buffer lengths */
132 u_char tx_page_start; /* first page of TX buffer area */
133 u_char rec_page_start; /* first page of RX ring-buffer */
134 u_char rec_page_stop; /* last page of RX ring-buffer */
135 u_char next_packet; /* pointer to next unread RX packet */
136 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
137};
138
139static struct ed_softc ed_softc[NED];
140
141static int ed_attach __P((struct ed_softc *, int, int));
142static int ed_attach_isa __P((struct isa_device *));
143
144static void ed_init __P((void *));
145static int ed_ioctl __P((struct ifnet *, int, caddr_t));
146static int ed_probe __P((struct isa_device *));
147static void ed_start __P((struct ifnet *));
148static void ed_reset __P((struct ifnet *));
149static void ed_watchdog __P((struct ifnet *));
150
151static void ed_stop __P((struct ed_softc *));
152static int ed_probe_generic8390 __P((struct ed_softc *));
153static int ed_probe_WD80x3 __P((struct isa_device *));
154static int ed_probe_3Com __P((struct isa_device *));
155static int ed_probe_Novell __P((struct isa_device *));
156static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int));
157static int ed_probe_HP_pclanp __P((struct isa_device *));
158
159#include "pci.h"
160#if NPCI > 0
161void *ed_attach_NE2000_pci __P((int, int));
162#endif
163
164#include "crd.h"
165#if NCRD > 0
166static int ed_probe_pccard __P((struct isa_device *, u_char *));
167#endif
168
169static void ds_getmcaf __P((struct ed_softc *, u_long *));
170
171static void ed_get_packet(struct ed_softc *, char *, /* u_short */ int, int);
172
173static void ed_rint __P((struct ed_softc *));
174static void ed_xmit __P((struct ed_softc *));
175static char * ed_ring_copy __P((struct ed_softc *, char *, char *,
176 /* u_short */ int));
177static void ed_hpp_set_physical_link __P((struct ed_softc *));
178static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
179 /* u_short */ int));
180static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
181 int));
182
183static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *,
184 /* u_short */ int));
185static void ed_pio_writemem __P((struct ed_softc *, char *,
186 /* u_short */ int, /* u_short */ int));
187static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
188 int));
189void edintr_sc __P((struct ed_softc *));
190
191static void ed_setrcr(struct ed_softc *);
192
193static u_long ds_crc(u_char *ep);
194
195#if NCRD > 0
196#include <sys/select.h>
197#include <pccard/card.h>
198#include <pccard/driver.h>
199#include <pccard/slot.h>
200
201/*
202 * PC-Card (PCMCIA) specific code.
203 */
204static int card_intr(struct pccard_dev *); /* Interrupt handler */
205static void edunload(struct pccard_dev *); /* Disable driver */
206static void edsuspend(struct pccard_dev *); /* Suspend driver */
207static int edinit(struct pccard_dev *, int); /* init device */
208
209static struct pccard_drv ed_info = {
210 "ed",
211 card_intr,
212 edunload,
213 edsuspend,
214 edinit,
215 0, /* Attributes - presently unused */
216 &net_imask /* Interrupt mask for device */
217 /* XXX - Should this also include net_imask? */
218};
219
220/*
221 * Called when a power down is requested. Shuts down the
222 * device and configures the device as unavailable (but
223 * still loaded...). A resume is done by calling
224 * edinit with first=0. This is called when the user suspends
225 * the system, or the APM code suspends the system.
226 */
227static void
228edsuspend(struct pccard_dev *dp)
229{
230 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit];
231 /*
232 * Some 'ed' cards will generate a interrupt as they go away,
233 * and by the time the interrupt handler gets to the card,
234 * the interrupt can't be cleared.
235 * By setting gone here, we tell the handler to ignore the
236 * interrupt when it happens.
237 */
238 sc->gone = 1; /* avoid spinning endlessly in interrupt handler */
239
240 printf("ed%d: suspending\n", dp->isahd.id_unit);
241}
242
243/*
244 * Initialize the device - called from Slot manager.
245 * If first is set, then check for the device's existence
246 * before initializing it. Once initialized, the device table may
247 * be set up.
248 */
249static int
250edinit(struct pccard_dev *dp, int first)
251{
252 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit];
253
254 /* validate unit number. */
255 if (first) {
256 if (dp->isahd.id_unit >= NED)
257 return(ENODEV);
258 /*
259 * Probe the device. If a value is returned, the
260 * device was found at the location.
261 */
262 sc->gone = 0;
263 if (ed_probe_pccard(&dp->isahd,dp->misc)==0)
264 return(ENXIO);
265 if (ed_attach_isa(&dp->isahd)==0)
266 return(ENXIO);
267 } else {
268 sc->gone = 0; /* reenable after a suspend */
269 }
270 /*
271 * XXX TODO:
272 * If it was initialized before, the device structure
273 * should also be initialized. We should
274 * reset (and possibly restart) the hardware, but
275 * I am not sure of the best way to do this...
276 */
277 return(0);
278}
279
280/*
281 * edunload - unload the driver and clear the table.
282 * XXX TODO:
283 * This is usually called when the card is ejected, but
284 * can be caused by a modunload of a controller driver.
285 * The idea is to reset the driver's view of the device
286 * and ensure that any driver entry points such as
287 * read and write do not hang.
288 */
289static void
290edunload(struct pccard_dev *dp)
291{
292 struct ed_softc *sc = &ed_softc[dp->isahd.id_unit];
293 struct ifnet *ifp = &sc->arpcom.ac_if;
294
295 if (sc->gone) {
296 printf("ed%d: already unloaded\n", dp->isahd.id_unit);
297 return;
298 }
299 ifp->if_flags &= ~IFF_RUNNING;
300 if_down(ifp);
301 sc->gone = 1;
302 printf("ed%d: unload\n", dp->isahd.id_unit);
303}
304
305/*
306 * card_intr - Shared interrupt called from
307 * front end of PC-Card handler.
308 */
309static int
310card_intr(struct pccard_dev *dp)
311{
312 edintr_sc(&ed_softc[dp->isahd.id_unit]);
313 return(1);
314}
315#endif /* NCRD > 0 */
316
317struct isa_driver eddriver = {
318 ed_probe,
319 ed_attach_isa,
320 "ed",
321 1 /* We are ultra sensitive */
322};
323
324/*
325 * Interrupt conversion table for WD/SMC ASIC/83C584
326 * (IRQ* are defined in icu.h)
327 */
328static unsigned short ed_intr_mask[] = {
329 IRQ9,
330 IRQ3,
331 IRQ5,
332 IRQ7,
333 IRQ10,
334 IRQ11,
335 IRQ15,
336 IRQ4
337};
338
339/*
340 * Interrupt conversion table for 83C790
341 */
342static unsigned short ed_790_intr_mask[] = {
343 0,
344 IRQ9,
345 IRQ3,
346 IRQ5,
347 IRQ7,
348 IRQ10,
349 IRQ11,
350 IRQ15
351};
352
353/*
354 * Interrupt conversion table for the HP PC LAN+
355 */
356
357static unsigned short ed_hpp_intr_mask[] = {
358 0, /* 0 */
359 0, /* 1 */
360 0, /* 2 */
361 IRQ3, /* 3 */
362 IRQ4, /* 4 */
363 IRQ5, /* 5 */
364 IRQ6, /* 6 */
365 IRQ7, /* 7 */
366 0, /* 8 */
367 IRQ9, /* 9 */
368 IRQ10, /* 10 */
369 IRQ11, /* 11 */
370 IRQ12, /* 12 */
371 0, /* 13 */
372 0, /* 14 */
373 IRQ15 /* 15 */
374};
375
376/*
377 * Determine if the device is present
378 *
379 * on entry:
380 * a pointer to an isa_device struct
381 * on exit:
382 * NULL if device not found
383 * or # of i/o addresses used (if found)
384 */
385static int
386ed_probe(isa_dev)
387 struct isa_device *isa_dev;
388{
389 int nports;
390
391#if NCRD > 0
392 /*
393 * If PC-Card probe required, then register driver with
394 * slot manager.
395 */
396 pccard_add_driver(&ed_info);
397#endif
398
399 nports = ed_probe_WD80x3(isa_dev);
400 if (nports)
401 return (nports);
402
403 nports = ed_probe_3Com(isa_dev);
404 if (nports)
405 return (nports);
406
407 nports = ed_probe_Novell(isa_dev);
408 if (nports)
409 return (nports);
410
411 nports = ed_probe_HP_pclanp(isa_dev);
412 if (nports)
413 return (nports);
414
415 return (0);
416}
417
418/*
419 * Generic probe routine for testing for the existance of a DS8390.
420 * Must be called after the NIC has just been reset. This routine
421 * works by looking at certain register values that are guaranteed
422 * to be initialized a certain way after power-up or reset. Seems
423 * not to currently work on the 83C690.
424 *
425 * Specifically:
426 *
427 * Register reset bits set bits
428 * Command Register (CR) TXP, STA RD2, STP
429 * Interrupt Status (ISR) RST
430 * Interrupt Mask (IMR) All bits
431 * Data Control (DCR) LAS
432 * Transmit Config. (TCR) LB1, LB0
433 *
434 * We only look at the CR and ISR registers, however, because looking at
435 * the others would require changing register pages (which would be
436 * intrusive if this isn't an 8390).
437 *
438 * Return 1 if 8390 was found, 0 if not.
439 */
440
441static int
442ed_probe_generic8390(sc)
443 struct ed_softc *sc;
444{
445 if ((inb(sc->nic_addr + ED_P0_CR) &
446 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
447 (ED_CR_RD2 | ED_CR_STP))
448 return (0);
449 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
450 return (0);
451
452 return (1);
453}
454
455/*
456 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
457 */
458static int
459ed_probe_WD80x3(isa_dev)
460 struct isa_device *isa_dev;
461{
462 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
463 int i;
464 u_int memsize;
465 u_char iptr, isa16bit, sum;
466
467 sc->asic_addr = isa_dev->id_iobase;
468 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
469 sc->is790 = 0;
470
471#ifdef TOSH_ETHER
472 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
473 DELAY(10000);
474#endif
475
476 /*
477 * Attempt to do a checksum over the station address PROM. If it
478 * fails, it's probably not a SMC/WD board. There is a problem with
479 * this, though: some clone WD boards don't pass the checksum test.
480 * Danpex boards for one.
481 */
482 for (sum = 0, i = 0; i < 8; ++i)
483 sum += inb(sc->asic_addr + ED_WD_PROM + i);
484
485 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
486
487 /*
488 * Checksum is invalid. This often happens with cheap WD8003E
489 * clones. In this case, the checksum byte (the eighth byte)
490 * seems to always be zero.
491 */
492 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
493 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
494 return (0);
495 }
496 /* reset card to force it into a known state. */
497#ifdef TOSH_ETHER
498 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
499#else
500 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
501#endif
502 DELAY(100);
503 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
504 /* wait in the case this card is reading it's EEROM */
505 DELAY(5000);
506
507 sc->vendor = ED_VENDOR_WD_SMC;
508 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
509
510 /*
511 * Set initial values for width/size.
512 */
513 memsize = 8192;
514 isa16bit = 0;
515 switch (sc->type) {
516 case ED_TYPE_WD8003S:
517 sc->type_str = "WD8003S";
518 break;
519 case ED_TYPE_WD8003E:
520 sc->type_str = "WD8003E";
521 break;
522 case ED_TYPE_WD8003EB:
523 sc->type_str = "WD8003EB";
524 break;
525 case ED_TYPE_WD8003W:
526 sc->type_str = "WD8003W";
527 break;
528 case ED_TYPE_WD8013EBT:
529 sc->type_str = "WD8013EBT";
530 memsize = 16384;
531 isa16bit = 1;
532 break;
533 case ED_TYPE_WD8013W:
534 sc->type_str = "WD8013W";
535 memsize = 16384;
536 isa16bit = 1;
537 break;
538 case ED_TYPE_WD8013EP: /* also WD8003EP */
539 if (inb(sc->asic_addr + ED_WD_ICR)
540 & ED_WD_ICR_16BIT) {
541 isa16bit = 1;
542 memsize = 16384;
543 sc->type_str = "WD8013EP";
544 } else {
545 sc->type_str = "WD8003EP";
546 }
547 break;
548 case ED_TYPE_WD8013WC:
549 sc->type_str = "WD8013WC";
550 memsize = 16384;
551 isa16bit = 1;
552 break;
553 case ED_TYPE_WD8013EBP:
554 sc->type_str = "WD8013EBP";
555 memsize = 16384;
556 isa16bit = 1;
557 break;
558 case ED_TYPE_WD8013EPC:
559 sc->type_str = "WD8013EPC";
560 memsize = 16384;
561 isa16bit = 1;
562 break;
563 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
564 case ED_TYPE_SMC8216T:
565 if (sc->type == ED_TYPE_SMC8216C) {
566 sc->type_str = "SMC8216/SMC8216C";
567 } else {
568 sc->type_str = "SMC8216T";
569 }
570
571 outb(sc->asic_addr + ED_WD790_HWR,
572 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
573 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
574 case ED_WD790_RAR_SZ64:
575 memsize = 65536;
576 break;
577 case ED_WD790_RAR_SZ32:
578 memsize = 32768;
579 break;
580 case ED_WD790_RAR_SZ16:
581 memsize = 16384;
582 break;
583 case ED_WD790_RAR_SZ8:
584 /* 8216 has 16K shared mem -- 8416 has 8K */
585 if (sc->type == ED_TYPE_SMC8216C) {
586 sc->type_str = "SMC8416C/SMC8416BT";
587 } else {
588 sc->type_str = "SMC8416T";
589 }
590 memsize = 8192;
591 break;
592 }
593 outb(sc->asic_addr + ED_WD790_HWR,
594 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
595
596 isa16bit = 1;
597 sc->is790 = 1;
598 break;
599#ifdef TOSH_ETHER
600 case ED_TYPE_TOSHIBA1:
601 sc->type_str = "Toshiba1";
602 memsize = 32768;
603 isa16bit = 1;
604 break;
605 case ED_TYPE_TOSHIBA4:
606 sc->type_str = "Toshiba4";
607 memsize = 32768;
608 isa16bit = 1;
609 break;
610#endif
611 default:
612 sc->type_str = "";
613 break;
614 }
615
616 /*
617 * Make some adjustments to initial values depending on what is found
618 * in the ICR.
619 */
620 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
621#ifdef TOSH_ETHER
622 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
623#endif
624 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
625 isa16bit = 0;
626 memsize = 8192;
627 }
628
629#if ED_DEBUG
630 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
631 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize);
632 for (i = 0; i < 8; i++)
633 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
634#endif
635
636 /*
637 * Allow the user to override the autoconfiguration
638 */
639 if (isa_dev->id_msize)
640 memsize = isa_dev->id_msize;
641
642 /*
643 * (note that if the user specifies both of the following flags that
644 * '8bit' mode intentionally has precedence)
645 */
646 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
647 isa16bit = 1;
648 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
649 isa16bit = 0;
650
651 /*
652 * If possible, get the assigned interrupt number from the card and
653 * use it.
654 */
655 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
656
657 /*
658 * Assemble together the encoded interrupt number.
659 */
660 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
661 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
662 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
663
664 /*
665 * If no interrupt specified (or "?"), use what the board tells us.
666 */
667 if (isa_dev->id_irq <= 0)
668 isa_dev->id_irq = ed_intr_mask[iptr];
669
670 /*
671 * Enable the interrupt.
672 */
673 outb(isa_dev->id_iobase + ED_WD_IRR,
674 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
675 }
676 if (sc->is790) {
677 outb(isa_dev->id_iobase + ED_WD790_HWR,
678 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH);
679 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
680 (inb(isa_dev->id_iobase + ED_WD790_GCR) &
681 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
682 outb(isa_dev->id_iobase + ED_WD790_HWR,
683 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
684
685 /*
686 * If no interrupt specified (or "?"), use what the board tells us.
687 */
688 if (isa_dev->id_irq <= 0)
689 isa_dev->id_irq = ed_790_intr_mask[iptr];
690
691 /*
692 * Enable interrupts.
693 */
694 outb(isa_dev->id_iobase + ED_WD790_ICR,
695 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL);
696 }
697 if (isa_dev->id_irq <= 0) {
698 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n",
699 isa_dev->id_unit, sc->type_str);
700 return (0);
701 }
702 sc->isa16bit = isa16bit;
703 sc->mem_shared = 1;
704 isa_dev->id_msize = memsize;
705 sc->mem_start = (caddr_t) isa_dev->id_maddr;
706
707 /*
708 * allocate one xmit buffer if < 16k, two buffers otherwise
709 */
710 if ((memsize < 16384) ||
711 (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
712 sc->txb_cnt = 1;
713 } else {
714 sc->txb_cnt = 2;
715 }
716 sc->tx_page_start = ED_WD_PAGE_OFFSET;
717 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
718 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
719 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
720 sc->mem_size = memsize;
721 sc->mem_end = sc->mem_start + memsize;
722
723 /*
724 * Get station address from on-board ROM
725 */
726 for (i = 0; i < ETHER_ADDR_LEN; ++i)
727 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
728
729 /*
730 * Set upper address bits and 8/16 bit access to shared memory
731 */
732 if (isa16bit) {
733 if (sc->is790) {
734 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
735 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
736 } else {
737 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
738 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
739 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
740 }
741 } else {
742 if (((sc->type & ED_WD_SOFTCONFIG) ||
743#ifdef TOSH_ETHER
744 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
745#endif
746 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
747 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
748 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
749 }
750 }
751
752 /*
753 * Set address and enable interface shared memory.
754 */
755 if (!sc->is790) {
756#ifdef TOSH_ETHER
757 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
758 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f));
759 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW);
760
761#else
762 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
763 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
764#endif
765 sc->cr_proto = ED_CR_RD2;
766 } else {
767 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
768 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH));
769 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
770 ((kvtop(sc->mem_start) >> 11) & 0x40) |
771 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0));
772 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
773 sc->cr_proto = 0;
774 }
775
776#if 0
777 printf("starting memory performance test at 0x%x, size %d...\n",
778 sc->mem_start, memsize*16384);
779 for (i = 0; i < 16384; i++)
780 bzero(sc->mem_start, memsize);
781 printf("***DONE***\n");
782#endif
783
784 /*
785 * Now zero memory and verify that it is clear
786 */
787 bzero(sc->mem_start, memsize);
788
789 for (i = 0; i < memsize; ++i) {
790 if (sc->mem_start[i]) {
791 printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
792 isa_dev->id_unit, kvtop(sc->mem_start + i));
793
794 /*
795 * Disable 16 bit access to shared memory
796 */
797 if (isa16bit) {
798 if (sc->is790) {
799 outb(sc->asic_addr + ED_WD_MSR, 0x00);
800 }
801 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
802 ~ED_WD_LAAR_M16EN));
803 }
804 return (0);
805 }
806 }
807
808 /*
809 * Disable 16bit access to shared memory - we leave it
810 * disabled so that 1) machines reboot properly when the board
811 * is set 16 bit mode and there are conflicting 8bit
812 * devices/ROMS in the same 128k address space as this boards
813 * shared memory. and 2) so that other 8 bit devices with
814 * shared memory can be used in this 128k region, too.
815 */
816 if (isa16bit) {
817 if (sc->is790) {
818 outb(sc->asic_addr + ED_WD_MSR, 0x00);
819 }
820 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
821 ~ED_WD_LAAR_M16EN));
822 }
823 return (ED_WD_IO_PORTS);
824}
825
826/*
827 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
828 */
829static int
830ed_probe_3Com(isa_dev)
831 struct isa_device *isa_dev;
832{
833 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
834 int i;
835 u_int memsize;
836 u_char isa16bit;
837
838 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
839 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
840
841 /*
842 * Verify that the kernel configured I/O address matches the board
843 * configured address
844 */
845 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
846 case ED_3COM_BCFR_300:
847 if (isa_dev->id_iobase != 0x300)
848 return (0);
849 break;
850 case ED_3COM_BCFR_310:
851 if (isa_dev->id_iobase != 0x310)
852 return (0);
853 break;
854 case ED_3COM_BCFR_330:
855 if (isa_dev->id_iobase != 0x330)
856 return (0);
857 break;
858 case ED_3COM_BCFR_350:
859 if (isa_dev->id_iobase != 0x350)
860 return (0);
861 break;
862 case ED_3COM_BCFR_250:
863 if (isa_dev->id_iobase != 0x250)
864 return (0);
865 break;
866 case ED_3COM_BCFR_280:
867 if (isa_dev->id_iobase != 0x280)
868 return (0);
869 break;
870 case ED_3COM_BCFR_2A0:
871 if (isa_dev->id_iobase != 0x2a0)
872 return (0);
873 break;
874 case ED_3COM_BCFR_2E0:
875 if (isa_dev->id_iobase != 0x2e0)
876 return (0);
877 break;
878 default:
879 return (0);
880 }
881
882 /*
883 * Verify that the kernel shared memory address matches the board
884 * configured address.
885 */
886 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
887 case ED_3COM_PCFR_DC000:
888 if (kvtop(isa_dev->id_maddr) != 0xdc000)
889 return (0);
890 break;
891 case ED_3COM_PCFR_D8000:
892 if (kvtop(isa_dev->id_maddr) != 0xd8000)
893 return (0);
894 break;
895 case ED_3COM_PCFR_CC000:
896 if (kvtop(isa_dev->id_maddr) != 0xcc000)
897 return (0);
898 break;
899 case ED_3COM_PCFR_C8000:
900 if (kvtop(isa_dev->id_maddr) != 0xc8000)
901 return (0);
902 break;
903 default:
904 return (0);
905 }
906
907
908 /*
909 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
910 * sequence because it'll lock up if the cable isn't connected if we
911 * don't.
912 */
913 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
914
915 /*
916 * Wait for a while, then un-reset it
917 */
918 DELAY(50);
919
920 /*
921 * The 3Com ASIC defaults to rather strange settings for the CR after
922 * a reset - it's important to set it again after the following outb
923 * (this is done when we map the PROM below).
924 */
925 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
926
927 /*
928 * Wait a bit for the NIC to recover from the reset
929 */
930 DELAY(5000);
931
932 sc->vendor = ED_VENDOR_3COM;
933 sc->type_str = "3c503";
934 sc->mem_shared = 1;
935 sc->cr_proto = ED_CR_RD2;
936
937 /*
938 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
939 * to it.
940 */
941 memsize = 8192;
942
943 /*
944 * Get station address from on-board ROM
945 */
946
947 /*
948 * First, map ethernet address PROM over the top of where the NIC
949 * registers normally appear.
950 */
951 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
952
953 for (i = 0; i < ETHER_ADDR_LEN; ++i)
954 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
955
956 /*
957 * Unmap PROM - select NIC registers. The proper setting of the
958 * tranceiver is set in ed_init so that the attach code is given a
959 * chance to set the default based on a compile-time config option
960 */
961 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
962
963 /*
964 * Determine if this is an 8bit or 16bit board
965 */
966
967 /*
968 * select page 0 registers
969 */
970 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
971
972 /*
973 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
974 * board.
975 */
976 outb(sc->nic_addr + ED_P0_DCR, 0);
977
978 /*
979 * select page 2 registers
980 */
981 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
982
983 /*
984 * The 3c503 forces the WTS bit to a one if this is a 16bit board
985 */
986 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
987 isa16bit = 1;
988 else
989 isa16bit = 0;
990
991 /*
992 * select page 0 registers
993 */
994 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
995
996 sc->mem_start = (caddr_t) isa_dev->id_maddr;
997 sc->mem_size = memsize;
998 sc->mem_end = sc->mem_start + memsize;
999
1000 /*
1001 * We have an entire 8k window to put the transmit buffers on the
1002 * 16bit boards. But since the 16bit 3c503's shared memory is only
1003 * fast enough to overlap the loading of one full-size packet, trying
1004 * to load more than 2 buffers can actually leave the transmitter idle
1005 * during the load. So 2 seems the best value. (Although a mix of
1006 * variable-sized packets might change this assumption. Nonetheless,
1007 * we optimize for linear transfers of same-size packets.)
1008 */
1009 if (isa16bit) {
1010 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
1011 sc->txb_cnt = 1;
1012 else
1013 sc->txb_cnt = 2;
1014
1015 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
1016 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
1017 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
1018 ED_3COM_RX_PAGE_OFFSET_16BIT;
1019 sc->mem_ring = sc->mem_start;
1020 } else {
1021 sc->txb_cnt = 1;
1022 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
1023 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
1024 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
1025 ED_3COM_TX_PAGE_OFFSET_8BIT;
1026 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
1027 }
1028
1029 sc->isa16bit = isa16bit;
1030
1031 /*
1032 * Initialize GA page start/stop registers. Probably only needed if
1033 * doing DMA, but what the hell.
1034 */
1035 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
1036 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
1037
1038 /*
1039 * Set IRQ. 3c503 only allows a choice of irq 2-5.
1040 */
1041 switch (isa_dev->id_irq) {
1042 case IRQ2:
1043 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
1044 break;
1045 case IRQ3:
1046 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
1047 break;
1048 case IRQ4:
1049 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
1050 break;
1051 case IRQ5:
1052 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
1053 break;
1054 default:
1055 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n",
1056 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
1057 return (0);
1058 }
1059
1060 /*
1061 * Initialize GA configuration register. Set bank and enable shared
1062 * mem.
1063 */
1064 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
1065 ED_3COM_GACFR_MBS0);
1066
1067 /*
1068 * Initialize "Vector Pointer" registers. These gawd-awful things are
1069 * compared to 20 bits of the address on ISA, and if they match, the
1070 * shared memory is disabled. We set them to 0xffff0...allegedly the
1071 * reset vector.
1072 */
1073 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
1074 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
1075 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
1076
1077 /*
1078 * Zero memory and verify that it is clear
1079 */
1080 bzero(sc->mem_start, memsize);
1081
1082 for (i = 0; i < memsize; ++i)
1083 if (sc->mem_start[i]) {
1084 printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
1085 isa_dev->id_unit, kvtop(sc->mem_start + i));
1086 return (0);
1087 }
1088 isa_dev->id_msize = memsize;
1089 return (ED_3COM_IO_PORTS);
1090}
1091
1092/*
1093 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1094 */
1095static int
1096ed_probe_Novell_generic(sc, port, unit, flags)
1097 struct ed_softc *sc;
1098 int port;
1099 int unit;
1100 int flags;
1101{
1102 u_int memsize, n;
1103 u_char romdata[16], tmp;
1104 static char test_pattern[32] = "THIS is A memory TEST pattern";
1105 char test_buffer[32];
1106
1107 sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET;
1108 sc->nic_addr = port + ED_NOVELL_NIC_OFFSET;
1109
1110 /* XXX - do Novell-specific probe here */
1111
1112 /* Reset the board */
1113#ifdef GWETHER
1114 outb(sc->asic_addr + ED_NOVELL_RESET, 0);
1115 DELAY(200);
1116#endif /* GWETHER */
1117 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
1118
1119 /*
1120 * I don't know if this is necessary; probably cruft leftover from
1121 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1122 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
1123 * non-invasive...but some boards don't seem to reset and I don't have
1124 * complete documentation on what the 'right' thing to do is...so we
1125 * do the invasive thing for now. Yuck.]
1126 */
1127 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
1128 DELAY(5000);
1129
1130 /*
1131 * This is needed because some NE clones apparently don't reset the
1132 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1133 * - this makes the probe invasive! ...Done against my better
1134 * judgement. -DLG
1135 */
1136 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1137
1138 DELAY(5000);
1139
1140 /* Make sure that we really have an 8390 based board */
1141 if (!ed_probe_generic8390(sc))
1142 return (0);
1143
1144 sc->vendor = ED_VENDOR_NOVELL;
1145 sc->mem_shared = 0;
1146 sc->cr_proto = ED_CR_RD2;
1147
1148 /*
1149 * Test the ability to read and write to the NIC memory. This has the
1150 * side affect of determining if this is an NE1000 or an NE2000.
1151 */
1152
1153 /*
1154 * This prevents packets from being stored in the NIC memory when the
1155 * readmem routine turns on the start bit in the CR.
1156 */
1157 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1158
1159 /* Temporarily initialize DCR for byte operations */
1160 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1161
1162 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1163 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1164
1165 sc->isa16bit = 0;
1166
1167 /*
1168 * Write a test pattern in byte mode. If this fails, then there
1169 * probably isn't any memory at 8k - which likely means that the board
1170 * is an NE2000.
1171 */
1172 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1173 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1174
1175 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
1176 /* not an NE1000 - try NE2000 */
1177
1178 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1179 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1180 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1181
1182 sc->isa16bit = 1;
1183
1184 /*
1185 * Write a test pattern in word mode. If this also fails, then
1186 * we don't know what this board is.
1187 */
1188 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1189 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1190
1191 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
1192 return (0); /* not an NE2000 either */
1193
1194 sc->type = ED_TYPE_NE2000;
1195 sc->type_str = "NE2000";
1196 } else {
1197 sc->type = ED_TYPE_NE1000;
1198 sc->type_str = "NE1000";
1199 }
1200
1201 /* 8k of memory plus an additional 8k if 16bit */
1202 memsize = 8192 + sc->isa16bit * 8192;
1203
1204#if 0 /* probably not useful - NE boards only come two ways */
1205 /* allow kernel config file overrides */
1206 if (isa_dev->id_msize)
1207 memsize = isa_dev->id_msize;
1208#endif
1209
1210 sc->mem_size = memsize;
1211
1212 /* NIC memory doesn't start at zero on an NE board */
1213 /* The start address is tied to the bus width */
1214 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1215 sc->mem_end = sc->mem_start + memsize;
1216 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1217
1218#ifdef GWETHER
1219 {
1220 int x, i, mstart = 0, msize = 0;
1221 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1222
1223 for (i = 0; i < ED_PAGE_SIZE; i++)
1224 pbuf0[i] = 0;
1225
1226 /* Clear all the memory. */
1227 for (x = 1; x < 256; x++)
1228 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1229
1230 /* Search for the start of RAM. */
1231 for (x = 1; x < 256; x++) {
1232 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1233 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1234 for (i = 0; i < ED_PAGE_SIZE; i++)
1235 pbuf[i] = 255 - x;
1236 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1237 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1238 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1239 mstart = x * ED_PAGE_SIZE;
1240 msize = ED_PAGE_SIZE;
1241 break;
1242 }
1243 }
1244 }
1245
1246 if (mstart == 0) {
1247 printf("ed%d: Cannot find start of RAM.\n", unit);
1248 return 0;
1249 }
1250 /* Search for the start of RAM. */
1251 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1252 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1253 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1254 for (i = 0; i < ED_PAGE_SIZE; i++)
1255 pbuf[i] = 255 - x;
1256 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1257 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1258 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1259 msize += ED_PAGE_SIZE;
1260 else {
1261 break;
1262 }
1263 } else {
1264 break;
1265 }
1266 }
1267
1268 if (msize == 0) {
1269 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x);
1270 return 0;
1271 }
1272 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize);
1273
1274 sc->mem_size = msize;
1275 sc->mem_start = (char *) mstart;
1276 sc->mem_end = (char *) (msize + mstart);
1277 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1278 }
1279#endif /* GWETHER */
1280
1281 /*
1282 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1283 * otherwise).
1284 */
1285 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1286 sc->txb_cnt = 1;
1287 else
1288 sc->txb_cnt = 2;
1289
1290 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1291 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1292
1293 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1294
1295 ed_pio_readmem(sc, 0, romdata, 16);
1296 for (n = 0; n < ETHER_ADDR_LEN; n++)
1297 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1298
1299#ifdef GWETHER
1300 if (sc->arpcom.ac_enaddr[2] == 0x86) {
1301 sc->type_str = "Gateway AT";
1302 }
1303#endif /* GWETHER */
1304
1305 /* clear any pending interrupts that might have occurred above */
1306 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1307
1308 return (ED_NOVELL_IO_PORTS);
1309}
1310
1311static int
1312ed_probe_Novell(isa_dev)
1313 struct isa_device *isa_dev;
1314{
1315 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1316
1317 isa_dev->id_maddr = 0;
1318 return ed_probe_Novell_generic(sc, isa_dev->id_iobase,
1319 isa_dev->id_unit, isa_dev->id_flags);
1320}
1321
1322#if NCRD > 0
1323
1324/*
1325 * Probe framework for pccards. Replicates the standard framework,
1326 * minus the pccard driver registration and ignores the ether address
1327 * supplied (from the CIS), relying on the probe to find it instead.
1328 */
1329static int
1330ed_probe_pccard(isa_dev, ether)
1331 struct isa_device *isa_dev;
1332 u_char *ether;
1333{
1334 int nports;
1335
1336 nports = ed_probe_WD80x3(isa_dev);
1337 if (nports)
1338 return (nports);
1339
1340 nports = ed_probe_Novell(isa_dev);
1341 if (nports)
1342 return (nports);
1343
1344 return (0);
1345}
1346
1347#endif /* NCRD > 0 */
1348
1349#define ED_HPP_TEST_SIZE 16
1350
1351/*
1352 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1353 * (HP Part nos: 27247B and 27252A).
1354 *
1355 * The card has an asic wrapper around a DS8390 core. The asic handles
1356 * host accesses and offers both standard register IO and memory mapped
1357 * IO. Memory mapped I/O allows better performance at the expense of greater
1358 * chance of an incompatibility with existing ISA cards.
1359 *
1360 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1361 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1362 * don't allow 32 bit accesses; these are indicated by a bit in the software
1363 * ID register (see if_edreg.h).
1364 *
1365 * Other caveats are: we should read the MAC address only when the card
1366 * is inactive.
1367 *
1368 * For more information; please consult the CRYNWR packet driver.
1369 *
1370 * The AUI port is turned on using the "link2" option on the ifconfig
1371 * command line.
1372 */
1373static int
1374ed_probe_HP_pclanp(isa_dev)
1375 struct isa_device *isa_dev;
1376{
1377 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1378 int n; /* temp var */
1379 int memsize; /* mem on board */
1380 u_char checksum; /* checksum of board address */
1381 u_char irq; /* board configured IRQ */
1382 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1383 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1384
1385
1386 /* Fill in basic information */
1387 sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET;
1388 sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET;
1389 sc->is790 = 0;
1390 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1391
1392 /*
1393 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1394 */
1395
1396 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) ||
1397 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) ||
1398 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) ||
1399 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53))
1400 return 0;
1401
1402 /*
1403 * Read the MAC address and verify checksum on the address.
1404 */
1405
1406 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1407 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1408 checksum += (sc->arpcom.ac_enaddr[n] =
1409 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n));
1410
1411 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1412
1413 if (checksum != 0xFF)
1414 return 0;
1415
1416 /*
1417 * Verify that the software model number is 0.
1418 */
1419
1420 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID);
1421 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) &
1422 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1423 return 0;
1424
1425 /*
1426 * Read in and save the current options configured on card.
1427 */
1428
1429 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION);
1430
1431 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1432 ED_HPP_OPTION_CHIP_RESET |
1433 ED_HPP_OPTION_ENABLE_IRQ);
1434
1435 /*
1436 * Reset the chip. This requires writing to the option register
1437 * so take care to preserve the other bits.
1438 */
1439
1440 outw(sc->asic_addr + ED_HPP_OPTION,
1441 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1442 ED_HPP_OPTION_CHIP_RESET)));
1443
1444 DELAY(5000); /* wait for chip reset to complete */
1445
1446 outw(sc->asic_addr + ED_HPP_OPTION,
1447 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1448 ED_HPP_OPTION_CHIP_RESET |
1449 ED_HPP_OPTION_ENABLE_IRQ)));
1450
1451 DELAY(5000);
1452
1453 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST))
1454 return 0; /* reset did not complete */
1455
1456 /*
1457 * Read out configuration information.
1458 */
1459
1460 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1461
1462 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ);
1463
1464 /*
1465 * Check for impossible IRQ.
1466 */
1467
1468 if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0])))
1469 return 0;
1470
1471 /*
1472 * If the kernel IRQ was specified with a '?' use the cards idea
1473 * of the IRQ. If the kernel IRQ was explicitly specified, it
1474 * should match that of the hardware.
1475 */
1476
1477 if (isa_dev->id_irq <= 0)
1478 isa_dev->id_irq = ed_hpp_intr_mask[irq];
1479 else if (isa_dev->id_irq != ed_hpp_intr_mask[irq])
1480 return 0;
1481
1482 /*
1483 * Fill in softconfig info.
1484 */
1485
1486 sc->vendor = ED_VENDOR_HP;
1487 sc->type = ED_TYPE_HP_PCLANPLUS;
1488 sc->type_str = "HP-PCLAN+";
1489
1490 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1491 sc->mem_start = 0; /* we use offsets inside the card RAM */
1492
1493 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1494
1495 /*
1496 * Check if memory mapping of the I/O registers possible.
1497 */
1498
1499 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1500 {
1501 u_long mem_addr;
1502
1503 /*
1504 * determine the memory address from the board.
1505 */
1506
1507 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1508 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8);
1509
1510 /*
1511 * Check that the kernel specified start of memory and
1512 * hardware's idea of it match.
1513 */
1514
1515 if (mem_addr != kvtop(isa_dev->id_maddr))
1516 return 0;
1517
1518 sc->hpp_mem_start = isa_dev->id_maddr;
1519 }
1520
1521 /*
1522 * The board has 32KB of memory. Is there a way to determine
1523 * this programmatically?
1524 */
1525
1526 memsize = 32768;
1527
1528 /*
1529 * Fill in the rest of the soft config structure.
1530 */
1531
1532 /*
1533 * The transmit page index.
1534 */
1535
1536 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1537
1538 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
1539 sc->txb_cnt = 1;
1540 else
1541 sc->txb_cnt = 2;
1542
1543 /*
1544 * Memory description
1545 */
1546
1547 sc->mem_size = memsize;
1548 sc->mem_ring = sc->mem_start +
1549 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1550 sc->mem_end = sc->mem_start + sc->mem_size;
1551
1552 /*
1553 * Receive area starts after the transmit area and
1554 * continues till the end of memory.
1555 */
1556
1557 sc->rec_page_start = sc->tx_page_start +
1558 (sc->txb_cnt * ED_TXBUF_SIZE);
1559 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1560
1561
1562 sc->cr_proto = 0; /* value works */
1563
1564 /*
1565 * Set the wrap registers for string I/O reads.
1566 */
1567
1568 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1569 outw(sc->asic_addr + ED_HPP_HW_WRAP,
1570 ((sc->rec_page_start / ED_PAGE_SIZE) |
1571 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1572
1573 /*
1574 * Reset the register page to normal operation.
1575 */
1576
1577 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1578
1579 /*
1580 * Verify that we can read/write from adapter memory.
1581 * Create test pattern.
1582 */
1583
1584 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1585 {
1586 test_pattern[n] = (n*n) ^ ~n;
1587 }
1588
1589#undef ED_HPP_TEST_SIZE
1590
1591 /*
1592 * Check that the memory is accessible thru the I/O ports.
1593 * Write out the contents of "test_pattern", read back
1594 * into "test_buffer" and compare the two for any
1595 * mismatch.
1596 */
1597
1598 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1599
1600 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1601 sizeof(test_pattern));
1602 ed_pio_readmem(sc, (n * ED_PAGE_SIZE),
1603 test_buffer, sizeof(test_pattern));
1604
1605 if (bcmp(test_pattern, test_buffer,
1606 sizeof(test_pattern)))
1607 return 0;
1608 }
1609
1610 return (ED_HPP_IO_PORTS);
1611
1612}
1613
1614/*
1615 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1616 */
1617
1618void
1619ed_hpp_set_physical_link(struct ed_softc *sc)
1620{
1621 struct ifnet *ifp = &sc->arpcom.ac_if;
1622 int lan_page;
1623
1624 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1625 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0);
1626
1627 if (ifp->if_flags & IFF_ALTPHYS) {
1628
1629 /*
1630 * Use the AUI port.
1631 */
1632
1633 lan_page |= ED_HPP_LAN_AUI;
1634
1635 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1636 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1637
1638
1639 } else {
1640
1641 /*
1642 * Use the ThinLan interface
1643 */
1644
1645 lan_page &= ~ED_HPP_LAN_AUI;
1646
1647 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1648 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1649
1650 }
1651
1652 /*
1653 * Wait for the lan card to re-initialize itself
1654 */
1655
1656 DELAY(150000); /* wait 150 ms */
1657
1658 /*
1659 * Restore normal pages.
1660 */
1661
1662 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1663
1664}
1665
1666
1667/*
1668 * Install interface into kernel networking data structures
1669 */
1670static int
1671ed_attach(sc, unit, flags)
1672 struct ed_softc *sc;
1673 int unit;
1674 int flags;
1675{
1676 struct ifnet *ifp = &sc->arpcom.ac_if;
1677
1678 /*
1679 * Set interface to stopped condition (reset)
1680 */
1681 ed_stop(sc);
1682
1683 if (!ifp->if_name) {
1684 /*
1685 * Initialize ifnet structure
1686 */
1687 ifp->if_softc = sc;
1688 ifp->if_unit = unit;
1689 ifp->if_name = "ed";
1690 ifp->if_output = ether_output;
1691 ifp->if_start = ed_start;
1692 ifp->if_ioctl = ed_ioctl;
1693 ifp->if_watchdog = ed_watchdog;
1694 ifp->if_init = ed_init;
1695 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1696 ifp->if_linkmib = &sc->mibdata;
1697 ifp->if_linkmiblen = sizeof sc->mibdata;
1698 /*
1699 * XXX - should do a better job.
1700 */
1701 if (sc->is790)
1702 sc->mibdata.dot3StatsEtherChipSet =
1703 DOT3CHIPSET(dot3VendorWesternDigital,
1704 dot3ChipSetWesternDigital83C790);
1705 else
1706 sc->mibdata.dot3StatsEtherChipSet =
1707 DOT3CHIPSET(dot3VendorNational,
1708 dot3ChipSetNational8390);
1709 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1710
1711 /*
1712 * Set default state for ALTPHYS flag (used to disable the
1713 * tranceiver for AUI operation), based on compile-time
1714 * config option.
1715 */
1716 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1717 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1718 IFF_MULTICAST | IFF_ALTPHYS);
1719 else
1720 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1721 IFF_MULTICAST);
1722
1723 /*
1724 * Attach the interface
1725 */
1726 if_attach(ifp);
1727 ether_ifattach(ifp);
1728 }
1729 /* device attach does transition from UNCONFIGURED to IDLE state */
1730
1731 /*
1732 * Print additional info when attached
1733 */
1734 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit,
1735 sc->arpcom.ac_enaddr, ":");
1736
1737 if (sc->type_str && (*sc->type_str != 0))
1738 printf("type %s ", sc->type_str);
1739 else
1740 printf("type unknown (0x%x) ", sc->type);
1741
1742 if (sc->vendor == ED_VENDOR_HP)
1743 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1744 "16-bit" : "32-bit",
1745 sc->hpp_mem_start ? "memory mapped" : "regular");
1746 else
1747 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1748
1749 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1750 (sc->vendor == ED_VENDOR_HP)) &&
1751 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1752
1753 /*
1754 * If BPF is in the kernel, call the attach for it
1755 */
1756#if NBPFILTER > 0
1757 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1758#endif
1759 return 1;
1760}
1761
1762static int
1763ed_attach_isa(isa_dev)
1764 struct isa_device *isa_dev;
1765{
1766 int unit = isa_dev->id_unit;
1767 struct ed_softc *sc = &ed_softc[unit];
1768 int flags = isa_dev->id_flags;
1769
1770 return ed_attach(sc, unit, flags);
1771}
1772
1773#if NPCI > 0
1774void *
1775ed_attach_NE2000_pci(unit, port)
1776 int unit;
1777 int port;
1778{
1779 struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT);
1780 int isa_flags = 0;
1781
1782 if (!sc)
1783 return sc;
1784
1785 bzero(sc, sizeof *sc);
1786 if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0
1787 || ed_attach(sc, unit, isa_flags) == 0) {
1788 free(sc, M_DEVBUF);
1789 return NULL;
1790 }
1791 return sc;
1792}
1793#endif
1794
1795/*
1796 * Reset interface.
1797 */
1798static void
1799ed_reset(ifp)
1800 struct ifnet *ifp;
1801{
1802 struct ed_softc *sc = ifp->if_softc;
1803 int s;
1804
1805 if (sc->gone)
1806 return;
1807 s = splimp();
1808
1809 /*
1810 * Stop interface and re-initialize.
1811 */
1812 ed_stop(sc);
1813 ed_init(sc);
1814
1815 (void) splx(s);
1816}
1817
1818/*
1819 * Take interface offline.
1820 */
1821static void
1822ed_stop(sc)
1823 struct ed_softc *sc;
1824{
1825 int n = 5000;
1826
1827 if (sc->gone)
1828 return;
1829 /*
1830 * Stop everything on the interface, and select page 0 registers.
1831 */
1832 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1833
1834 /*
1835 * Wait for interface to enter stopped state, but limit # of checks to
1836 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1837 * just in case it's an old one.
1838 */
1839 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1840}
1841
1842/*
1843 * Device timeout/watchdog routine. Entered if the device neglects to
1844 * generate an interrupt after a transmit has been started on it.
1845 */
1846static void
1847ed_watchdog(ifp)
1848 struct ifnet *ifp;
1849{
1850 struct ed_softc *sc = ifp->if_softc;
1851
1852 if (sc->gone)
1853 return;
1854 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1855 ifp->if_oerrors++;
1856
1857 ed_reset(ifp);
1858}
1859
1860/*
1861 * Initialize device.
1862 */
1863static void
1864ed_init(xsc)
1865 void *xsc;
1866{
1867 struct ed_softc *sc = xsc;
1868 struct ifnet *ifp = &sc->arpcom.ac_if;
1869 int i, s;
1870
1871 if (sc->gone)
1872 return;
1873
1874 /* address not known */
1875 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1876 return;
1877
1878 /*
1879 * Initialize the NIC in the exact order outlined in the NS manual.
1880 * This init procedure is "mandatory"...don't change what or when
1881 * things happen.
1882 */
1883 s = splimp();
1884
1885 /* reset transmitter flags */
1886 sc->xmit_busy = 0;
1887 ifp->if_timer = 0;
1888
1889 sc->txb_inuse = 0;
1890 sc->txb_new = 0;
1891 sc->txb_next_tx = 0;
1892
1893 /* This variable is used below - don't move this assignment */
1894 sc->next_packet = sc->rec_page_start + 1;
1895
1896 /*
1897 * Set interface for page 0, Remote DMA complete, Stopped
1898 */
1899 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1900
1901 if (sc->isa16bit) {
1902
1903 /*
1904 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1905 * order=80x86, word-wide DMA xfers,
1906 */
1907 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1908 } else {
1909
1910 /*
1911 * Same as above, but byte-wide DMA xfers
1912 */
1913 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1914 }
1915
1916 /*
1917 * Clear Remote Byte Count Registers
1918 */
1919 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1920 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1921
1922 /*
1923 * For the moment, don't store incoming packets in memory.
1924 */
1925 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1926
1927 /*
1928 * Place NIC in internal loopback mode
1929 */
1930 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1931
1932 /*
1933 * Initialize transmit/receive (ring-buffer) Page Start
1934 */
1935 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1936 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1937 /* Set lower bits of byte addressable framing to 0 */
1938 if (sc->is790)
1939 outb(sc->nic_addr + 0x09, 0);
1940
1941 /*
1942 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1943 */
1944 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1945 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1946
1947 /*
1948 * Clear all interrupts. A '1' in each bit position clears the
1949 * corresponding flag.
1950 */
1951 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1952
1953 /*
1954 * Enable the following interrupts: receive/transmit complete,
1955 * receive/transmit error, and Receiver OverWrite.
1956 *
1957 * Counter overflow and Remote DMA complete are *not* enabled.
1958 */
1959 outb(sc->nic_addr + ED_P0_IMR,
1960 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1961
1962 /*
1963 * Program Command Register for page 1
1964 */
1965 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1966
1967 /*
1968 * Copy out our station address
1969 */
1970 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1971 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1972
1973 /*
1974 * Set Current Page pointer to next_packet (initialized above)
1975 */
1976 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1977
1978 /*
1979 * Program Receiver Configuration Register and multicast filter. CR is
1980 * set to page 0 on return.
1981 */
1982 ed_setrcr(sc);
1983
1984 /*
1985 * Take interface out of loopback
1986 */
1987 outb(sc->nic_addr + ED_P0_TCR, 0);
1988
1989 /*
1990 * If this is a 3Com board, the tranceiver must be software enabled
1991 * (there is no settable hardware default).
1992 */
1993 if (sc->vendor == ED_VENDOR_3COM) {
1994 if (ifp->if_flags & IFF_ALTPHYS) {
1995 outb(sc->asic_addr + ED_3COM_CR, 0);
1996 } else {
1997 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1998 }
1999 }
2000
2001 /*
2002 * Set 'running' flag, and clear output active flag.
2003 */
2004 ifp->if_flags |= IFF_RUNNING;
2005 ifp->if_flags &= ~IFF_OACTIVE;
2006
2007 /*
2008 * ...and attempt to start output
2009 */
2010 ed_start(ifp);
2011
2012 (void) splx(s);
2013}
2014
2015/*
2016 * This routine actually starts the transmission on the interface
2017 */
2018static inline void
2019ed_xmit(sc)
2020 struct ed_softc *sc;
2021{
2022 struct ifnet *ifp = (struct ifnet *)sc;
2023 unsigned short len;
2024
2025 if (sc->gone)
2026 return;
2027 len = sc->txb_len[sc->txb_next_tx];
2028
2029 /*
2030 * Set NIC for page 0 register access
2031 */
2032 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2033
2034 /*
2035 * Set TX buffer start page
2036 */
2037 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
2038 sc->txb_next_tx * ED_TXBUF_SIZE);
2039
2040 /*
2041 * Set TX length
2042 */
2043 outb(sc->nic_addr + ED_P0_TBCR0, len);
2044 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
2045
2046 /*
2047 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2048 */
2049 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2050 sc->xmit_busy = 1;
2051
2052 /*
2053 * Point to next transmit buffer slot and wrap if necessary.
2054 */
2055 sc->txb_next_tx++;
2056 if (sc->txb_next_tx == sc->txb_cnt)
2057 sc->txb_next_tx = 0;
2058
2059 /*
2060 * Set a timer just in case we never hear from the board again
2061 */
2062 ifp->if_timer = 2;
2063}
2064
2065/*
2066 * Start output on interface.
2067 * We make two assumptions here:
2068 * 1) that the current priority is set to splimp _before_ this code
2069 * is called *and* is returned to the appropriate priority after
2070 * return
2071 * 2) that the IFF_OACTIVE flag is checked before this code is called
2072 * (i.e. that the output part of the interface is idle)
2073 */
2074static void
2075ed_start(ifp)
2076 struct ifnet *ifp;
2077{
2078 struct ed_softc *sc = ifp->if_softc;
2079 struct mbuf *m0, *m;
2080 caddr_t buffer;
2081 int len;
2082
2083 if (sc->gone) {
2084 printf("ed_start(%p) GONE\n",ifp);
2085 return;
2086 }
2087outloop:
2088
2089 /*
2090 * First, see if there are buffered packets and an idle transmitter -
2091 * should never happen at this point.
2092 */
2093 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2094 printf("ed: packets buffered, but transmitter idle\n");
2095 ed_xmit(sc);
2096 }
2097
2098 /*
2099 * See if there is room to put another packet in the buffer.
2100 */
2101 if (sc->txb_inuse == sc->txb_cnt) {
2102
2103 /*
2104 * No room. Indicate this to the outside world and exit.
2105 */
2106 ifp->if_flags |= IFF_OACTIVE;
2107 return;
2108 }
2109 IF_DEQUEUE(&ifp->if_snd, m);
2110 if (m == 0) {
2111
2112 /*
2113 * We are using the !OACTIVE flag to indicate to the outside
2114 * world that we can accept an additional packet rather than
2115 * that the transmitter is _actually_ active. Indeed, the
2116 * transmitter may be active, but if we haven't filled all the
2117 * buffers with data then we still want to accept more.
2118 */
2119 ifp->if_flags &= ~IFF_OACTIVE;
2120 return;
2121 }
2122
2123 /*
2124 * Copy the mbuf chain into the transmit buffer
2125 */
2126
2127 m0 = m;
2128
2129 /* txb_new points to next open buffer slot */
2130 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2131
2132 if (sc->mem_shared) {
2133
2134 /*
2135 * Special case setup for 16 bit boards...
2136 */
2137 if (sc->isa16bit) {
2138 switch (sc->vendor) {
2139
2140 /*
2141 * For 16bit 3Com boards (which have 16k of
2142 * memory), we have the xmit buffers in a
2143 * different page of memory ('page 0') - so
2144 * change pages.
2145 */
2146 case ED_VENDOR_3COM:
2147 outb(sc->asic_addr + ED_3COM_GACFR,
2148 ED_3COM_GACFR_RSEL);
2149 break;
2150
2151 /*
2152 * Enable 16bit access to shared memory on
2153 * WD/SMC boards.
2154 */
2155 case ED_VENDOR_WD_SMC:{
2156 outb(sc->asic_addr + ED_WD_LAAR,
2157 (sc->wd_laar_proto | ED_WD_LAAR_M16EN));
2158 if (sc->is790) {
2159 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
2160 }
2161 break;
2162 }
2163 }
2164 }
2165 for (len = 0; m != 0; m = m->m_next) {
2166 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2167 buffer += m->m_len;
2168 len += m->m_len;
2169 }
2170
2171 /*
2172 * Restore previous shared memory access
2173 */
2174 if (sc->isa16bit) {
2175 switch (sc->vendor) {
2176 case ED_VENDOR_3COM:
2177 outb(sc->asic_addr + ED_3COM_GACFR,
2178 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2179 break;
2180 case ED_VENDOR_WD_SMC:{
2181 if (sc->is790) {
2182 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2183 }
2184 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
2185 break;
2186 }
2187 }
2188 }
2189 } else {
2190 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2191 if (len == 0)
2192 goto outloop;
2193 }
2194
2195 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2196
2197 sc->txb_inuse++;
2198
2199 /*
2200 * Point to next buffer slot and wrap if necessary.
2201 */
2202 sc->txb_new++;
2203 if (sc->txb_new == sc->txb_cnt)
2204 sc->txb_new = 0;
2205
2206 if (sc->xmit_busy == 0)
2207 ed_xmit(sc);
2208
2209 /*
2210 * Tap off here if there is a bpf listener.
2211 */
2212#if NBPFILTER > 0
2213 if (ifp->if_bpf) {
2214 bpf_mtap(ifp, m0);
2215 }
2216#endif
2217
2218 m_freem(m0);
2219
2220 /*
2221 * Loop back to the top to possibly buffer more packets
2222 */
2223 goto outloop;
2224}
2225
2226/*
2227 * Ethernet interface receiver interrupt.
2228 */
2229static inline void
2230ed_rint(sc)
2231 struct ed_softc *sc;
2232{
2233 struct ifnet *ifp = &sc->arpcom.ac_if;
2234 u_char boundry;
2235 u_short len;
2236 struct ed_ring packet_hdr;
2237 char *packet_ptr;
2238
2239 if (sc->gone)
2240 return;
2241
2242 /*
2243 * Set NIC to page 1 registers to get 'current' pointer
2244 */
2245 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2246
2247 /*
2248 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2249 * i.e. it points to where new data has been buffered. The 'CURR'
2250 * (current) register points to the logical end of the ring-buffer -
2251 * i.e. it points to where additional new data will be added. We loop
2252 * here until the logical beginning equals the logical end (or in
2253 * other words, until the ring-buffer is empty).
2254 */
2255 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
2256
2257 /* get pointer to this buffer's header structure */
2258 packet_ptr = sc->mem_ring +
2259 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2260
2261 /*
2262 * The byte count includes a 4 byte header that was added by
2263 * the NIC.
2264 */
2265 if (sc->mem_shared)
2266 packet_hdr = *(struct ed_ring *) packet_ptr;
2267 else
2268 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2269 sizeof(packet_hdr));
2270 len = packet_hdr.count;
2271 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2272 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2273 /*
2274 * Length is a wild value. There's a good chance that
2275 * this was caused by the NIC being old and buggy.
2276 * The bug is that the length low byte is duplicated in
2277 * the high byte. Try to recalculate the length based on
2278 * the pointer to the next packet.
2279 */
2280 /*
2281 * NOTE: sc->next_packet is pointing at the current packet.
2282 */
2283 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2284 if (packet_hdr.next_packet >= sc->next_packet) {
2285 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2286 } else {
2287 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2288 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2289 }
2290 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2291 + sizeof(struct ed_ring)))
2292 sc->mibdata.dot3StatsFrameTooLongs++;
2293 }
2294 /*
2295 * Be fairly liberal about what we allow as a "reasonable" length
2296 * so that a [crufty] packet will make it to BPF (and can thus
2297 * be analyzed). Note that all that is really important is that
2298 * we have a length that will fit into one mbuf cluster or less;
2299 * the upper layer protocols can then figure out the length from
2300 * their own length field(s).
2301 */
2302 if ((len > sizeof(struct ed_ring)) &&
2303 (len <= MCLBYTES) &&
2304 (packet_hdr.next_packet >= sc->rec_page_start) &&
2305 (packet_hdr.next_packet < sc->rec_page_stop)) {
2306 /*
2307 * Go get packet.
2308 */
2309 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2310 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY);
2311 ifp->if_ipackets++;
2312 } else {
2313 /*
2314 * Really BAD. The ring pointers are corrupted.
2315 */
2316 log(LOG_ERR,
2317 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2318 ifp->if_unit, len);
2319 ifp->if_ierrors++;
2320 ed_reset(ifp);
2321 return;
2322 }
2323
2324 /*
2325 * Update next packet pointer
2326 */
2327 sc->next_packet = packet_hdr.next_packet;
2328
2329 /*
2330 * Update NIC boundry pointer - being careful to keep it one
2331 * buffer behind. (as recommended by NS databook)
2332 */
2333 boundry = sc->next_packet - 1;
2334 if (boundry < sc->rec_page_start)
2335 boundry = sc->rec_page_stop - 1;
2336
2337 /*
2338 * Set NIC to page 0 registers to update boundry register
2339 */
2340 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2341
2342 outb(sc->nic_addr + ED_P0_BNRY, boundry);
2343
2344 /*
2345 * Set NIC to page 1 registers before looping to top (prepare
2346 * to get 'CURR' current pointer)
2347 */
2348 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2349 }
2350}
2351
2352/*
2353 * Ethernet interface interrupt processor
2354 */
2355void
2356edintr_sc(sc)
2357 struct ed_softc *sc;
2358{
2359 struct ifnet *ifp = (struct ifnet *)sc;
2360 u_char isr;
2361
2362 if (sc->gone)
2363 return;
2364 /*
2365 * Set NIC to page 0 registers
2366 */
2367 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2368
2369 /*
2370 * loop until there are no more new interrupts
2371 */
2372 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) {
2373
2374 /*
2375 * reset all the bits that we are 'acknowledging' by writing a
2376 * '1' to each bit position that was set (writing a '1'
2377 * *clears* the bit)
2378 */
2379 outb(sc->nic_addr + ED_P0_ISR, isr);
2380
2381 /*
2382 * Handle transmitter interrupts. Handle these first because
2383 * the receiver will reset the board under some conditions.
2384 */
2385 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2386 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
2387
2388 /*
2389 * Check for transmit error. If a TX completed with an
2390 * error, we end up throwing the packet away. Really
2391 * the only error that is possible is excessive
2392 * collisions, and in this case it is best to allow
2393 * the automatic mechanisms of TCP to backoff the
2394 * flow. Of course, with UDP we're screwed, but this
2395 * is expected when a network is heavily loaded.
2396 */
2397 (void) inb(sc->nic_addr + ED_P0_TSR);
2398 if (isr & ED_ISR_TXE) {
2399 u_char tsr;
2400
2401 /*
2402 * Excessive collisions (16)
2403 */
2404 tsr = inb(sc->nic_addr + ED_P0_TSR);
2405 if ((tsr & ED_TSR_ABT)
2406 && (collisions == 0)) {
2407
2408 /*
2409 * When collisions total 16, the
2410 * P0_NCR will indicate 0, and the
2411 * TSR_ABT is set.
2412 */
2413 collisions = 16;
2414 sc->mibdata.dot3StatsExcessiveCollisions++;
2415 sc->mibdata.dot3StatsCollFrequencies[15]++;
2416 }
2417 if (tsr & ED_TSR_OWC)
2418 sc->mibdata.dot3StatsLateCollisions++;
2419 if (tsr & ED_TSR_CDH)
2420 sc->mibdata.dot3StatsSQETestErrors++;
2421 if (tsr & ED_TSR_CRS)
2422 sc->mibdata.dot3StatsCarrierSenseErrors++;
2423 if (tsr & ED_TSR_FU)
2424 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2425
2426 /*
2427 * update output errors counter
2428 */
2429 ifp->if_oerrors++;
2430 } else {
2431
2432 /*
2433 * Update total number of successfully
2434 * transmitted packets.
2435 */
2436 ifp->if_opackets++;
2437 }
2438
2439 /*
2440 * reset tx busy and output active flags
2441 */
2442 sc->xmit_busy = 0;
2443 ifp->if_flags &= ~IFF_OACTIVE;
2444
2445 /*
2446 * clear watchdog timer
2447 */
2448 ifp->if_timer = 0;
2449
2450 /*
2451 * Add in total number of collisions on last
2452 * transmission.
2453 */
2454 ifp->if_collisions += collisions;
2455 switch(collisions) {
2456 case 0:
2457 case 16:
2458 break;
2459 case 1:
2460 sc->mibdata.dot3StatsSingleCollisionFrames++;
2461 sc->mibdata.dot3StatsCollFrequencies[0]++;
2462 break;
2463 default:
2464 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2465 sc->mibdata.
2466 dot3StatsCollFrequencies[collisions-1]
2467 ++;
2468 break;
2469 }
2470
2471 /*
2472 * Decrement buffer in-use count if not zero (can only
2473 * be zero if a transmitter interrupt occured while
2474 * not actually transmitting). If data is ready to
2475 * transmit, start it transmitting, otherwise defer
2476 * until after handling receiver
2477 */
2478 if (sc->txb_inuse && --sc->txb_inuse)
2479 ed_xmit(sc);
2480 }
2481
2482 /*
2483 * Handle receiver interrupts
2484 */
2485 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2486
2487 /*
2488 * Overwrite warning. In order to make sure that a
2489 * lockup of the local DMA hasn't occurred, we reset
2490 * and re-init the NIC. The NSC manual suggests only a
2491 * partial reset/re-init is necessary - but some chips
2492 * seem to want more. The DMA lockup has been seen
2493 * only with early rev chips - Methinks this bug was
2494 * fixed in later revs. -DG
2495 */
2496 if (isr & ED_ISR_OVW) {
2497 ifp->if_ierrors++;
2498#ifdef DIAGNOSTIC
2499 log(LOG_WARNING,
2500 "ed%d: warning - receiver ring buffer overrun\n",
2501 ifp->if_unit);
2502#endif
2503
2504 /*
2505 * Stop/reset/re-init NIC
2506 */
2507 ed_reset(ifp);
2508 } else {
2509
2510 /*
2511 * Receiver Error. One or more of: CRC error,
2512 * frame alignment error FIFO overrun, or
2513 * missed packet.
2514 */
2515 if (isr & ED_ISR_RXE) {
2516 u_char rsr;
2517 rsr = inb(sc->nic_addr + ED_P0_RSR);
2518 if (rsr & ED_RSR_CRC)
2519 sc->mibdata.dot3StatsFCSErrors++;
2520 if (rsr & ED_RSR_FAE)
2521 sc->mibdata.dot3StatsAlignmentErrors++;
2522 if (rsr & ED_RSR_FO)
2523 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2524 ifp->if_ierrors++;
2525#ifdef ED_DEBUG
2526 printf("ed%d: receive error %x\n", ifp->if_unit,
2527 inb(sc->nic_addr + ED_P0_RSR));
2528#endif
2529 }
2530
2531 /*
2532 * Go get the packet(s) XXX - Doing this on an
2533 * error is dubious because there shouldn't be
2534 * any data to get (we've configured the
2535 * interface to not accept packets with
2536 * errors).
2537 */
2538
2539 /*
2540 * Enable 16bit access to shared memory first
2541 * on WD/SMC boards.
2542 */
2543 if (sc->isa16bit &&
2544 (sc->vendor == ED_VENDOR_WD_SMC)) {
2545
2546 outb(sc->asic_addr + ED_WD_LAAR,
2547 (sc->wd_laar_proto |=
2548 ED_WD_LAAR_M16EN));
2549 if (sc->is790) {
2550 outb(sc->asic_addr + ED_WD_MSR,
2551 ED_WD_MSR_MENB);
2552 }
2553 }
2554 ed_rint(sc);
2555
2556 /* disable 16bit access */
2557 if (sc->isa16bit &&
2558 (sc->vendor == ED_VENDOR_WD_SMC)) {
2559
2560 if (sc->is790) {
2561 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2562 }
2563 outb(sc->asic_addr + ED_WD_LAAR,
2564 (sc->wd_laar_proto &=
2565 ~ED_WD_LAAR_M16EN));
2566 }
2567 }
2568 }
2569
2570 /*
2571 * If it looks like the transmitter can take more data,
2572 * attempt to start output on the interface. This is done
2573 * after handling the receiver to give the receiver priority.
2574 */
2575 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2576 ed_start(ifp);
2577
2578 /*
2579 * return NIC CR to standard state: page 0, remote DMA
2580 * complete, start (toggling the TXP bit off, even if was just
2581 * set in the transmit routine, is *okay* - it is 'edge'
2582 * triggered from low to high)
2583 */
2584 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2585
2586 /*
2587 * If the Network Talley Counters overflow, read them to reset
2588 * them. It appears that old 8390's won't clear the ISR flag
2589 * otherwise - resulting in an infinite loop.
2590 */
2591 if (isr & ED_ISR_CNT) {
2592 (void) inb(sc->nic_addr + ED_P0_CNTR0);
2593 (void) inb(sc->nic_addr + ED_P0_CNTR1);
2594 (void) inb(sc->nic_addr + ED_P0_CNTR2);
2595 }
2596 }
2597}
2598
2599void
2600edintr(unit)
2601 int unit;
2602{
2603 edintr_sc (&ed_softc[unit]);
2604}
2605
2606/*
2607 * Process an ioctl request. This code needs some work - it looks
2608 * pretty ugly.
2609 */
2610static int
2611ed_ioctl(ifp, command, data)
2612 register struct ifnet *ifp;
2613 int command;
2614 caddr_t data;
2615{
2616 struct ed_softc *sc = ifp->if_softc;
2617 struct ifreq *ifr = (struct ifreq *) data;
2618 int s, error = 0;
2619
2620 if (sc->gone) {
2621 ifp->if_flags &= ~IFF_RUNNING;
2622 return ENXIO;
2623 }
2624 s = splimp();
2625
2626 switch (command) {
2627
2628 case SIOCSIFADDR:
2629 case SIOCGIFADDR:
2630 case SIOCSIFMTU:
2631 error = ether_ioctl(ifp, command, data);
2632 break;
2633
2634 case SIOCSIFFLAGS:
2635
2636 /*
2637 * If the interface is marked up and stopped, then start it.
2638 * If it is marked down and running, then stop it.
2639 */
2640 if (ifp->if_flags & IFF_UP) {
2641 if ((ifp->if_flags & IFF_RUNNING) == 0)
2642 ed_init(ifp->if_softc);
2643 } else {
2644 if (ifp->if_flags & IFF_RUNNING) {
2645 ed_stop(sc);
2646 ifp->if_flags &= ~IFF_RUNNING;
2647 }
2648 }
2649
2650#if NBPFILTER > 0
2651
2652 /*
2653 * Promiscuous flag may have changed, so reprogram the RCR.
2654 */
2655 ed_setrcr(sc);
2656#endif
2657
2658 /*
2659 * An unfortunate hack to provide the (required) software
2660 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2661 * disables the tranceiver if set.
2662 */
2663 if (sc->vendor == ED_VENDOR_3COM) {
2664 if (ifp->if_flags & IFF_ALTPHYS) {
2665 outb(sc->asic_addr + ED_3COM_CR, 0);
2666 } else {
2667 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2668 }
2669 } else if (sc->vendor == ED_VENDOR_HP)
2670 ed_hpp_set_physical_link(sc);
2671 break;
2672
2673 case SIOCADDMULTI:
2674 case SIOCDELMULTI:
2675 /*
|
2691 break;
2692
2693 default:
2694 error = EINVAL;
2695 }
2696 (void) splx(s);
2697 return (error);
2698}
2699
2700/*
2701 * Given a source and destination address, copy 'amount' of a packet from
2702 * the ring buffer into a linear destination buffer. Takes into account
2703 * ring-wrap.
2704 */
2705static inline char *
2706ed_ring_copy(sc, src, dst, amount)
2707 struct ed_softc *sc;
2708 char *src;
2709 char *dst;
2710 u_short amount;
2711{
2712 u_short tmp_amount;
2713
2714 /* does copy wrap to lower addr in ring buffer? */
2715 if (src + amount > sc->mem_end) {
2716 tmp_amount = sc->mem_end - src;
2717
2718 /* copy amount up to end of NIC memory */
2719 if (sc->mem_shared)
2720 bcopy(src, dst, tmp_amount);
2721 else
2722 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2723
2724 amount -= tmp_amount;
2725 src = sc->mem_ring;
2726 dst += tmp_amount;
2727 }
2728 if (sc->mem_shared)
2729 bcopy(src, dst, amount);
2730 else
2731 ed_pio_readmem(sc, (int)src, dst, amount);
2732
2733 return (src + amount);
2734}
2735
2736/*
2737 * Retreive packet from shared memory and send to the next level up via
2738 * ether_input(). If there is a BPF listener, give a copy to BPF, too.
2739 */
2740static void
2741ed_get_packet(sc, buf, len, multicast)
2742 struct ed_softc *sc;
2743 char *buf;
2744 u_short len;
2745 int multicast;
2746{
2747 struct ether_header *eh;
2748 struct mbuf *m;
2749
2750 /* Allocate a header mbuf */
2751 MGETHDR(m, M_DONTWAIT, MT_DATA);
2752 if (m == NULL)
2753 return;
2754 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2755 m->m_pkthdr.len = m->m_len = len;
2756
2757 /*
2758 * We always put the received packet in a single buffer -
2759 * either with just an mbuf header or in a cluster attached
2760 * to the header. The +2 is to compensate for the alignment
2761 * fixup below.
2762 */
2763 if ((len + 2) > MHLEN) {
2764 /* Attach an mbuf cluster */
2765 MCLGET(m, M_DONTWAIT);
2766
2767 /* Insist on getting a cluster */
2768 if ((m->m_flags & M_EXT) == 0) {
2769 m_freem(m);
2770 return;
2771 }
2772 }
2773
2774 /*
2775 * The +2 is to longword align the start of the real packet.
2776 * This is important for NFS.
2777 */
2778 m->m_data += 2;
2779 eh = mtod(m, struct ether_header *);
2780
2781 /*
2782 * Get packet, including link layer address, from interface.
2783 */
2784 ed_ring_copy(sc, buf, (char *)eh, len);
2785
2786#if NBPFILTER > 0
2787
2788 /*
2789 * Check if there's a BPF listener on this interface. If so, hand off
2790 * the raw packet to bpf.
2791 */
2792 if (sc->arpcom.ac_if.if_bpf) {
2793 bpf_mtap(&sc->arpcom.ac_if, m);
2794
2795 /*
2796 * Note that the interface cannot be in promiscuous mode if
2797 * there are no BPF listeners. And if we are in promiscuous
2798 * mode, we have to check if this packet is really ours.
2799 */
2800 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
2801 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
2802 sizeof(eh->ether_dhost)) != 0 && multicast == 0) {
2803 m_freem(m);
2804 return;
2805 }
2806 }
2807#endif
2808
2809 /*
2810 * Remove link layer address.
2811 */
2812 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
2813 m->m_data += sizeof(struct ether_header);
2814
2815 ether_input(&sc->arpcom.ac_if, eh, m);
2816 return;
2817}
2818
2819/*
2820 * Supporting routines
2821 */
2822
2823/*
2824 * Given a NIC memory source address and a host memory destination
2825 * address, copy 'amount' from NIC to host using Programmed I/O.
2826 * The 'amount' is rounded up to a word - okay as long as mbufs
2827 * are word sized.
2828 * This routine is currently Novell-specific.
2829 */
2830static void
2831ed_pio_readmem(sc, src, dst, amount)
2832 struct ed_softc *sc;
2833 int src;
2834 unsigned char *dst;
2835 unsigned short amount;
2836{
2837 /* HP cards need special handling */
2838 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2839 ed_hpp_readmem(sc, src, dst, amount);
2840 return;
2841 }
2842
2843 /* Regular Novell cards */
2844 /* select page 0 registers */
2845 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2846
2847 /* round up to a word */
2848 if (amount & 1)
2849 ++amount;
2850
2851 /* set up DMA byte count */
2852 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2853 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8);
2854
2855 /* set up source address in NIC mem */
2856 outb(sc->nic_addr + ED_P0_RSAR0, src);
2857 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8);
2858
2859 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2860
2861 if (sc->isa16bit) {
2862 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2);
2863 } else
2864 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2865
2866}
2867
2868/*
2869 * Stripped down routine for writing a linear buffer to NIC memory.
2870 * Only used in the probe routine to test the memory. 'len' must
2871 * be even.
2872 */
2873static void
2874ed_pio_writemem(sc, src, dst, len)
2875 struct ed_softc *sc;
2876 char *src;
2877 unsigned short dst;
2878 unsigned short len;
2879{
2880 int maxwait = 200; /* about 240us */
2881
2882 if (sc->vendor == ED_VENDOR_NOVELL) {
2883
2884 /* select page 0 registers */
2885 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2886
2887 /* reset remote DMA complete flag */
2888 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2889
2890 /* set up DMA byte count */
2891 outb(sc->nic_addr + ED_P0_RBCR0, len);
2892 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8);
2893
2894 /* set up destination address in NIC mem */
2895 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2896 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2897
2898 /* set remote DMA write */
2899 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2900
2901 if (sc->isa16bit)
2902 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2);
2903 else
2904 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2905
2906 /*
2907 * Wait for remote DMA complete. This is necessary because on the
2908 * transmit side, data is handled internally by the NIC in bursts and
2909 * we can't start another remote DMA until this one completes. Not
2910 * waiting causes really bad things to happen - like the NIC
2911 * irrecoverably jamming the ISA bus.
2912 */
2913 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2914
2915 } else if ((sc->vendor == ED_VENDOR_HP) &&
2916 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2917
2918 /* HP PCLAN+ */
2919
2920 /* reset remote DMA complete flag */
2921 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2922
2923 /* program the write address in RAM */
2924 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
2925
2926 if (sc->hpp_mem_start) {
2927 u_short *s = (u_short *) src;
2928 volatile u_short *d = (u_short *) sc->hpp_mem_start;
2929 u_short *const fence = s + (len >> 1);
2930
2931 /*
2932 * Enable memory mapped access.
2933 */
2934
2935 outw(sc->asic_addr + ED_HPP_OPTION,
2936 sc->hpp_options &
2937 ~(ED_HPP_OPTION_MEM_DISABLE |
2938 ED_HPP_OPTION_BOOT_ROM_ENB));
2939
2940 /*
2941 * Copy to NIC memory.
2942 */
2943
2944 while (s < fence)
2945 *d = *s++;
2946
2947 /*
2948 * Restore Boot ROM access.
2949 */
2950
2951 outw(sc->asic_addr + ED_HPP_OPTION,
2952 sc->hpp_options);
2953
2954 } else {
2955 /* write data using I/O writes */
2956 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2);
2957 }
2958
2959 }
2960}
2961
2962/*
2963 * Write an mbuf chain to the destination NIC memory address using
2964 * programmed I/O.
2965 */
2966static u_short
2967ed_pio_write_mbufs(sc, m, dst)
2968 struct ed_softc *sc;
2969 struct mbuf *m;
2970 int dst;
2971{
2972 struct ifnet *ifp = (struct ifnet *)sc;
2973 unsigned short total_len, dma_len;
2974 struct mbuf *mp;
2975 int maxwait = 200; /* about 240us */
2976
2977 /* HP PC Lan+ cards need special handling */
2978 if ((sc->vendor == ED_VENDOR_HP) &&
2979 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2980 return ed_hpp_write_mbufs(sc, m, dst);
2981 }
2982
2983 /* First, count up the total number of bytes to copy */
2984 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2985 total_len += mp->m_len;
2986
2987 dma_len = total_len;
2988 if (sc->isa16bit && (dma_len & 1))
2989 dma_len++;
2990
2991 /* select page 0 registers */
2992 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2993
2994 /* reset remote DMA complete flag */
2995 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2996
2997 /* set up DMA byte count */
2998 outb(sc->nic_addr + ED_P0_RBCR0, dma_len);
2999 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8);
3000
3001 /* set up destination address in NIC mem */
3002 outb(sc->nic_addr + ED_P0_RSAR0, dst);
3003 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
3004
3005 /* set remote DMA write */
3006 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
3007
3008 /*
3009 * Transfer the mbuf chain to the NIC memory.
3010 * 16-bit cards require that data be transferred as words, and only words.
3011 * So that case requires some extra code to patch over odd-length mbufs.
3012 */
3013
3014 if (!sc->isa16bit) {
3015 /* NE1000s are easy */
3016 while (m) {
3017 if (m->m_len) {
3018 outsb(sc->asic_addr + ED_NOVELL_DATA,
3019 m->m_data, m->m_len);
3020 }
3021 m = m->m_next;
3022 }
3023 } else {
3024 /* NE2000s are a pain */
3025 unsigned char *data;
3026 int len, wantbyte;
3027 unsigned char savebyte[2];
3028
3029 wantbyte = 0;
3030
3031 while (m) {
3032 len = m->m_len;
3033 if (len) {
3034 data = mtod(m, caddr_t);
3035 /* finish the last word */
3036 if (wantbyte) {
3037 savebyte[1] = *data;
3038 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
3039 data++;
3040 len--;
3041 wantbyte = 0;
3042 }
3043 /* output contiguous words */
3044 if (len > 1) {
3045 outsw(sc->asic_addr + ED_NOVELL_DATA,
3046 data, len >> 1);
3047 data += len & ~1;
3048 len &= 1;
3049 }
3050 /* save last byte, if necessary */
3051 if (len == 1) {
3052 savebyte[0] = *data;
3053 wantbyte = 1;
3054 }
3055 }
3056 m = m->m_next;
3057 }
3058 /* spit last byte */
3059 if (wantbyte) {
3060 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
3061 }
3062 }
3063
3064 /*
3065 * Wait for remote DMA complete. This is necessary because on the
3066 * transmit side, data is handled internally by the NIC in bursts and
3067 * we can't start another remote DMA until this one completes. Not
3068 * waiting causes really bad things to happen - like the NIC
3069 * irrecoverably jamming the ISA bus.
3070 */
3071 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
3072
3073 if (!maxwait) {
3074 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
3075 ifp->if_unit);
3076 ed_reset(ifp);
3077 return(0);
3078 }
3079 return (total_len);
3080}
3081
3082/*
3083 * Support routines to handle the HP PC Lan+ card.
3084 */
3085
3086/*
3087 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
3088 * IO.
3089 */
3090
3091static void
3092ed_hpp_readmem(sc, src, dst, amount)
3093 struct ed_softc *sc;
3094 unsigned short src;
3095 unsigned char *dst;
3096 unsigned short amount;
3097{
3098
3099 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3100
3101
3102 /* Program the source address in RAM */
3103 outw(sc->asic_addr + ED_HPP_PAGE_2, src);
3104
3105 /*
3106 * The HP PC Lan+ card supports word reads as well as
3107 * a memory mapped i/o port that is aliased to every
3108 * even address on the board.
3109 */
3110
3111 if (sc->hpp_mem_start) {
3112
3113 /* Enable memory mapped access. */
3114 outw(sc->asic_addr + ED_HPP_OPTION,
3115 sc->hpp_options &
3116 ~(ED_HPP_OPTION_MEM_DISABLE |
3117 ED_HPP_OPTION_BOOT_ROM_ENB));
3118
3119 if (use_32bit_access && (amount > 3)) {
3120 u_long *dl = (u_long *) dst;
3121 volatile u_long *const sl =
3122 (u_long *) sc->hpp_mem_start;
3123 u_long *const fence = dl + (amount >> 2);
3124
3125 /* Copy out NIC data. We could probably write this
3126 as a `movsl'. The currently generated code is lousy.
3127 */
3128
3129 while (dl < fence)
3130 *dl++ = *sl;
3131
3132 dst += (amount & ~3);
3133 amount &= 3;
3134
3135 }
3136
3137 /* Finish off any words left, as a series of short reads */
3138 if (amount > 1) {
3139 u_short *d = (u_short *) dst;
3140 volatile u_short *const s =
3141 (u_short *) sc->hpp_mem_start;
3142 u_short *const fence = d + (amount >> 1);
3143
3144 /* Copy out NIC data. */
3145
3146 while (d < fence)
3147 *d++ = *s;
3148
3149 dst += (amount & ~1);
3150 amount &= 1;
3151 }
3152
3153 /*
3154 * read in a byte; however we need to always read 16 bits
3155 * at a time or the hardware gets into a funny state
3156 */
3157
3158 if (amount == 1) {
3159 /* need to read in a short and copy LSB */
3160 volatile u_short *const s =
3161 (volatile u_short *) sc->hpp_mem_start;
3162
3163 *dst = (*s) & 0xFF;
3164 }
3165
3166 /* Restore Boot ROM access. */
3167
3168 outw(sc->asic_addr + ED_HPP_OPTION,
3169 sc->hpp_options);
3170
3171
3172 } else {
3173 /* Read in data using the I/O port */
3174 if (use_32bit_access && (amount > 3)) {
3175 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2);
3176 dst += (amount & ~3);
3177 amount &= 3;
3178 }
3179 if (amount > 1) {
3180 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1);
3181 dst += (amount & ~1);
3182 amount &= 1;
3183 }
3184 if (amount == 1) { /* read in a short and keep the LSB */
3185 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF;
3186 }
3187 }
3188}
3189
3190/*
3191 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3192 * outsw() or via the memory mapped interface to the same register.
3193 * Writes have to be in word units; byte accesses won't work and may cause
3194 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC
3195 * allows it.
3196 */
3197
3198static u_short
3199ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3200{
3201 int len, wantbyte;
3202 unsigned short total_len;
3203 unsigned char savebyte[2];
3204 volatile u_short * const d =
3205 (volatile u_short *) sc->hpp_mem_start;
3206 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3207
3208 /* select page 0 registers */
3209 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3210
3211 /* reset remote DMA complete flag */
3212 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
3213
3214 /* program the write address in RAM */
3215 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
3216
3217 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3218 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options &
3219 ~(ED_HPP_OPTION_MEM_DISABLE |
3220 ED_HPP_OPTION_BOOT_ROM_ENB));
3221
3222 wantbyte = 0;
3223 total_len = 0;
3224
3225 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3226 while (m) {
3227 total_len += (len = m->m_len);
3228 if (len) {
3229 caddr_t data = mtod(m, caddr_t);
3230 /* finish the last word of the previous mbuf */
3231 if (wantbyte) {
3232 savebyte[1] = *data;
3233 *d = *((ushort *) savebyte);
3234 data++; len--; wantbyte = 0;
3235 }
3236 /* output contiguous words */
3237 if ((len > 3) && (use_32bit_accesses)) {
3238 volatile u_long *const dl =
3239 (volatile u_long *) d;
3240 u_long *sl = (u_long *) data;
3241 u_long *fence = sl + (len >> 2);
3242
3243 while (sl < fence)
3244 *dl = *sl++;
3245
3246 data += (len & ~3);
3247 len &= 3;
3248 }
3249 /* finish off remain 16 bit writes */
3250 if (len > 1) {
3251 u_short *s = (u_short *) data;
3252 u_short *fence = s + (len >> 1);
3253
3254 while (s < fence)
3255 *d = *s++;
3256
3257 data += (len & ~1);
3258 len &= 1;
3259 }
3260 /* save last byte if needed */
3261 if (wantbyte = (len == 1))
3262 savebyte[0] = *data;
3263 }
3264 m = m->m_next; /* to next mbuf */
3265 }
3266 if (wantbyte) /* write last byte */
3267 *d = *((u_short *) savebyte);
3268 } else {
3269 /* use programmed I/O */
3270 while (m) {
3271 total_len += (len = m->m_len);
3272 if (len) {
3273 caddr_t data = mtod(m, caddr_t);
3274 /* finish the last word of the previous mbuf */
3275 if (wantbyte) {
3276 savebyte[1] = *data;
3277 outw(sc->asic_addr + ED_HPP_PAGE_4,
3278 *((u_short *)savebyte));
3279 data++;
3280 len--;
3281 wantbyte = 0;
3282 }
3283 /* output contiguous words */
3284 if ((len > 3) && use_32bit_accesses) {
3285 outsl(sc->asic_addr + ED_HPP_PAGE_4,
3286 data, len >> 2);
3287 data += (len & ~3);
3288 len &= 3;
3289 }
3290 /* finish off remaining 16 bit accesses */
3291 if (len > 1) {
3292 outsw(sc->asic_addr + ED_HPP_PAGE_4,
3293 data, len >> 1);
3294 data += (len & ~1);
3295 len &= 1;
3296 }
3297 if (wantbyte = (len == 1))
3298 savebyte[0] = *data;
3299
3300 } /* if len != 0 */
3301 m = m->m_next;
3302 }
3303 if (wantbyte) /* spit last byte */
3304 outw(sc->asic_addr + ED_HPP_PAGE_4,
3305 *(u_short *)savebyte);
3306
3307 }
3308
3309 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3310 outw(sc->asic_addr + ED_HPP_OPTION,
3311 sc->hpp_options);
3312
3313 return (total_len);
3314}
3315
3316static void
3317ed_setrcr(sc)
3318 struct ed_softc *sc;
3319{
3320 struct ifnet *ifp = (struct ifnet *)sc;
3321 int i;
3322
3323 /* set page 1 registers */
3324 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3325
3326 if (ifp->if_flags & IFF_PROMISC) {
3327
3328 /*
3329 * Reconfigure the multicast filter.
3330 */
3331 for (i = 0; i < 8; i++)
3332 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
3333
3334 /*
3335 * And turn on promiscuous mode. Also enable reception of
3336 * runts and packets with CRC & alignment errors.
3337 */
3338 /* Set page 0 registers */
3339 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3340
3341 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3342 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP);
3343 } else {
3344 /* set up multicast addresses and filter modes */
3345 if (ifp->if_flags & IFF_MULTICAST) {
3346 u_long mcaf[2];
3347
3348 if (ifp->if_flags & IFF_ALLMULTI) {
3349 mcaf[0] = 0xffffffff;
3350 mcaf[1] = 0xffffffff;
3351 } else
3352 ds_getmcaf(sc, mcaf);
3353
3354 /*
3355 * Set multicast filter on chip.
3356 */
3357 for (i = 0; i < 8; i++)
3358 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]);
3359
3360 /* Set page 0 registers */
3361 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3362
3363 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB);
3364 } else {
3365
3366 /*
3367 * Initialize multicast address hashing registers to
3368 * not accept multicasts.
3369 */
3370 for (i = 0; i < 8; ++i)
3371 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00);
3372
3373 /* Set page 0 registers */
3374 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3375
3376 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
3377 }
3378 }
3379
3380 /*
3381 * Start interface.
3382 */
3383 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3384}
3385
3386/*
3387 * Compute crc for ethernet address
3388 */
3389static u_long
3390ds_crc(ep)
3391 u_char *ep;
3392{
3393#define POLYNOMIAL 0x04c11db6
3394 register u_long crc = 0xffffffffL;
3395 register int carry, i, j;
3396 register u_char b;
3397
3398 for (i = 6; --i >= 0;) {
3399 b = *ep++;
3400 for (j = 8; --j >= 0;) {
3401 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
3402 crc <<= 1;
3403 b >>= 1;
3404 if (carry)
3405 crc = ((crc ^ POLYNOMIAL) | carry);
3406 }
3407 }
3408 return crc;
3409#undef POLYNOMIAL
3410}
3411
3412/*
3413 * Compute the multicast address filter from the
3414 * list of multicast addresses we need to listen to.
3415 */
3416static void
3417ds_getmcaf(sc, mcaf)
3418 struct ed_softc *sc;
3419 u_long *mcaf;
3420{
3421 register u_int index;
3422 register u_char *af = (u_char *) mcaf;
| 2681 break;
2682
2683 default:
2684 error = EINVAL;
2685 }
2686 (void) splx(s);
2687 return (error);
2688}
2689
2690/*
2691 * Given a source and destination address, copy 'amount' of a packet from
2692 * the ring buffer into a linear destination buffer. Takes into account
2693 * ring-wrap.
2694 */
2695static inline char *
2696ed_ring_copy(sc, src, dst, amount)
2697 struct ed_softc *sc;
2698 char *src;
2699 char *dst;
2700 u_short amount;
2701{
2702 u_short tmp_amount;
2703
2704 /* does copy wrap to lower addr in ring buffer? */
2705 if (src + amount > sc->mem_end) {
2706 tmp_amount = sc->mem_end - src;
2707
2708 /* copy amount up to end of NIC memory */
2709 if (sc->mem_shared)
2710 bcopy(src, dst, tmp_amount);
2711 else
2712 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2713
2714 amount -= tmp_amount;
2715 src = sc->mem_ring;
2716 dst += tmp_amount;
2717 }
2718 if (sc->mem_shared)
2719 bcopy(src, dst, amount);
2720 else
2721 ed_pio_readmem(sc, (int)src, dst, amount);
2722
2723 return (src + amount);
2724}
2725
2726/*
2727 * Retreive packet from shared memory and send to the next level up via
2728 * ether_input(). If there is a BPF listener, give a copy to BPF, too.
2729 */
2730static void
2731ed_get_packet(sc, buf, len, multicast)
2732 struct ed_softc *sc;
2733 char *buf;
2734 u_short len;
2735 int multicast;
2736{
2737 struct ether_header *eh;
2738 struct mbuf *m;
2739
2740 /* Allocate a header mbuf */
2741 MGETHDR(m, M_DONTWAIT, MT_DATA);
2742 if (m == NULL)
2743 return;
2744 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2745 m->m_pkthdr.len = m->m_len = len;
2746
2747 /*
2748 * We always put the received packet in a single buffer -
2749 * either with just an mbuf header or in a cluster attached
2750 * to the header. The +2 is to compensate for the alignment
2751 * fixup below.
2752 */
2753 if ((len + 2) > MHLEN) {
2754 /* Attach an mbuf cluster */
2755 MCLGET(m, M_DONTWAIT);
2756
2757 /* Insist on getting a cluster */
2758 if ((m->m_flags & M_EXT) == 0) {
2759 m_freem(m);
2760 return;
2761 }
2762 }
2763
2764 /*
2765 * The +2 is to longword align the start of the real packet.
2766 * This is important for NFS.
2767 */
2768 m->m_data += 2;
2769 eh = mtod(m, struct ether_header *);
2770
2771 /*
2772 * Get packet, including link layer address, from interface.
2773 */
2774 ed_ring_copy(sc, buf, (char *)eh, len);
2775
2776#if NBPFILTER > 0
2777
2778 /*
2779 * Check if there's a BPF listener on this interface. If so, hand off
2780 * the raw packet to bpf.
2781 */
2782 if (sc->arpcom.ac_if.if_bpf) {
2783 bpf_mtap(&sc->arpcom.ac_if, m);
2784
2785 /*
2786 * Note that the interface cannot be in promiscuous mode if
2787 * there are no BPF listeners. And if we are in promiscuous
2788 * mode, we have to check if this packet is really ours.
2789 */
2790 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
2791 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
2792 sizeof(eh->ether_dhost)) != 0 && multicast == 0) {
2793 m_freem(m);
2794 return;
2795 }
2796 }
2797#endif
2798
2799 /*
2800 * Remove link layer address.
2801 */
2802 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
2803 m->m_data += sizeof(struct ether_header);
2804
2805 ether_input(&sc->arpcom.ac_if, eh, m);
2806 return;
2807}
2808
2809/*
2810 * Supporting routines
2811 */
2812
2813/*
2814 * Given a NIC memory source address and a host memory destination
2815 * address, copy 'amount' from NIC to host using Programmed I/O.
2816 * The 'amount' is rounded up to a word - okay as long as mbufs
2817 * are word sized.
2818 * This routine is currently Novell-specific.
2819 */
2820static void
2821ed_pio_readmem(sc, src, dst, amount)
2822 struct ed_softc *sc;
2823 int src;
2824 unsigned char *dst;
2825 unsigned short amount;
2826{
2827 /* HP cards need special handling */
2828 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2829 ed_hpp_readmem(sc, src, dst, amount);
2830 return;
2831 }
2832
2833 /* Regular Novell cards */
2834 /* select page 0 registers */
2835 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2836
2837 /* round up to a word */
2838 if (amount & 1)
2839 ++amount;
2840
2841 /* set up DMA byte count */
2842 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2843 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8);
2844
2845 /* set up source address in NIC mem */
2846 outb(sc->nic_addr + ED_P0_RSAR0, src);
2847 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8);
2848
2849 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2850
2851 if (sc->isa16bit) {
2852 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2);
2853 } else
2854 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2855
2856}
2857
2858/*
2859 * Stripped down routine for writing a linear buffer to NIC memory.
2860 * Only used in the probe routine to test the memory. 'len' must
2861 * be even.
2862 */
2863static void
2864ed_pio_writemem(sc, src, dst, len)
2865 struct ed_softc *sc;
2866 char *src;
2867 unsigned short dst;
2868 unsigned short len;
2869{
2870 int maxwait = 200; /* about 240us */
2871
2872 if (sc->vendor == ED_VENDOR_NOVELL) {
2873
2874 /* select page 0 registers */
2875 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2876
2877 /* reset remote DMA complete flag */
2878 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2879
2880 /* set up DMA byte count */
2881 outb(sc->nic_addr + ED_P0_RBCR0, len);
2882 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8);
2883
2884 /* set up destination address in NIC mem */
2885 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2886 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2887
2888 /* set remote DMA write */
2889 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2890
2891 if (sc->isa16bit)
2892 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2);
2893 else
2894 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2895
2896 /*
2897 * Wait for remote DMA complete. This is necessary because on the
2898 * transmit side, data is handled internally by the NIC in bursts and
2899 * we can't start another remote DMA until this one completes. Not
2900 * waiting causes really bad things to happen - like the NIC
2901 * irrecoverably jamming the ISA bus.
2902 */
2903 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2904
2905 } else if ((sc->vendor == ED_VENDOR_HP) &&
2906 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2907
2908 /* HP PCLAN+ */
2909
2910 /* reset remote DMA complete flag */
2911 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2912
2913 /* program the write address in RAM */
2914 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
2915
2916 if (sc->hpp_mem_start) {
2917 u_short *s = (u_short *) src;
2918 volatile u_short *d = (u_short *) sc->hpp_mem_start;
2919 u_short *const fence = s + (len >> 1);
2920
2921 /*
2922 * Enable memory mapped access.
2923 */
2924
2925 outw(sc->asic_addr + ED_HPP_OPTION,
2926 sc->hpp_options &
2927 ~(ED_HPP_OPTION_MEM_DISABLE |
2928 ED_HPP_OPTION_BOOT_ROM_ENB));
2929
2930 /*
2931 * Copy to NIC memory.
2932 */
2933
2934 while (s < fence)
2935 *d = *s++;
2936
2937 /*
2938 * Restore Boot ROM access.
2939 */
2940
2941 outw(sc->asic_addr + ED_HPP_OPTION,
2942 sc->hpp_options);
2943
2944 } else {
2945 /* write data using I/O writes */
2946 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2);
2947 }
2948
2949 }
2950}
2951
2952/*
2953 * Write an mbuf chain to the destination NIC memory address using
2954 * programmed I/O.
2955 */
2956static u_short
2957ed_pio_write_mbufs(sc, m, dst)
2958 struct ed_softc *sc;
2959 struct mbuf *m;
2960 int dst;
2961{
2962 struct ifnet *ifp = (struct ifnet *)sc;
2963 unsigned short total_len, dma_len;
2964 struct mbuf *mp;
2965 int maxwait = 200; /* about 240us */
2966
2967 /* HP PC Lan+ cards need special handling */
2968 if ((sc->vendor == ED_VENDOR_HP) &&
2969 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2970 return ed_hpp_write_mbufs(sc, m, dst);
2971 }
2972
2973 /* First, count up the total number of bytes to copy */
2974 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2975 total_len += mp->m_len;
2976
2977 dma_len = total_len;
2978 if (sc->isa16bit && (dma_len & 1))
2979 dma_len++;
2980
2981 /* select page 0 registers */
2982 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2983
2984 /* reset remote DMA complete flag */
2985 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2986
2987 /* set up DMA byte count */
2988 outb(sc->nic_addr + ED_P0_RBCR0, dma_len);
2989 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8);
2990
2991 /* set up destination address in NIC mem */
2992 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2993 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2994
2995 /* set remote DMA write */
2996 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2997
2998 /*
2999 * Transfer the mbuf chain to the NIC memory.
3000 * 16-bit cards require that data be transferred as words, and only words.
3001 * So that case requires some extra code to patch over odd-length mbufs.
3002 */
3003
3004 if (!sc->isa16bit) {
3005 /* NE1000s are easy */
3006 while (m) {
3007 if (m->m_len) {
3008 outsb(sc->asic_addr + ED_NOVELL_DATA,
3009 m->m_data, m->m_len);
3010 }
3011 m = m->m_next;
3012 }
3013 } else {
3014 /* NE2000s are a pain */
3015 unsigned char *data;
3016 int len, wantbyte;
3017 unsigned char savebyte[2];
3018
3019 wantbyte = 0;
3020
3021 while (m) {
3022 len = m->m_len;
3023 if (len) {
3024 data = mtod(m, caddr_t);
3025 /* finish the last word */
3026 if (wantbyte) {
3027 savebyte[1] = *data;
3028 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
3029 data++;
3030 len--;
3031 wantbyte = 0;
3032 }
3033 /* output contiguous words */
3034 if (len > 1) {
3035 outsw(sc->asic_addr + ED_NOVELL_DATA,
3036 data, len >> 1);
3037 data += len & ~1;
3038 len &= 1;
3039 }
3040 /* save last byte, if necessary */
3041 if (len == 1) {
3042 savebyte[0] = *data;
3043 wantbyte = 1;
3044 }
3045 }
3046 m = m->m_next;
3047 }
3048 /* spit last byte */
3049 if (wantbyte) {
3050 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
3051 }
3052 }
3053
3054 /*
3055 * Wait for remote DMA complete. This is necessary because on the
3056 * transmit side, data is handled internally by the NIC in bursts and
3057 * we can't start another remote DMA until this one completes. Not
3058 * waiting causes really bad things to happen - like the NIC
3059 * irrecoverably jamming the ISA bus.
3060 */
3061 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
3062
3063 if (!maxwait) {
3064 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
3065 ifp->if_unit);
3066 ed_reset(ifp);
3067 return(0);
3068 }
3069 return (total_len);
3070}
3071
3072/*
3073 * Support routines to handle the HP PC Lan+ card.
3074 */
3075
3076/*
3077 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
3078 * IO.
3079 */
3080
3081static void
3082ed_hpp_readmem(sc, src, dst, amount)
3083 struct ed_softc *sc;
3084 unsigned short src;
3085 unsigned char *dst;
3086 unsigned short amount;
3087{
3088
3089 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3090
3091
3092 /* Program the source address in RAM */
3093 outw(sc->asic_addr + ED_HPP_PAGE_2, src);
3094
3095 /*
3096 * The HP PC Lan+ card supports word reads as well as
3097 * a memory mapped i/o port that is aliased to every
3098 * even address on the board.
3099 */
3100
3101 if (sc->hpp_mem_start) {
3102
3103 /* Enable memory mapped access. */
3104 outw(sc->asic_addr + ED_HPP_OPTION,
3105 sc->hpp_options &
3106 ~(ED_HPP_OPTION_MEM_DISABLE |
3107 ED_HPP_OPTION_BOOT_ROM_ENB));
3108
3109 if (use_32bit_access && (amount > 3)) {
3110 u_long *dl = (u_long *) dst;
3111 volatile u_long *const sl =
3112 (u_long *) sc->hpp_mem_start;
3113 u_long *const fence = dl + (amount >> 2);
3114
3115 /* Copy out NIC data. We could probably write this
3116 as a `movsl'. The currently generated code is lousy.
3117 */
3118
3119 while (dl < fence)
3120 *dl++ = *sl;
3121
3122 dst += (amount & ~3);
3123 amount &= 3;
3124
3125 }
3126
3127 /* Finish off any words left, as a series of short reads */
3128 if (amount > 1) {
3129 u_short *d = (u_short *) dst;
3130 volatile u_short *const s =
3131 (u_short *) sc->hpp_mem_start;
3132 u_short *const fence = d + (amount >> 1);
3133
3134 /* Copy out NIC data. */
3135
3136 while (d < fence)
3137 *d++ = *s;
3138
3139 dst += (amount & ~1);
3140 amount &= 1;
3141 }
3142
3143 /*
3144 * read in a byte; however we need to always read 16 bits
3145 * at a time or the hardware gets into a funny state
3146 */
3147
3148 if (amount == 1) {
3149 /* need to read in a short and copy LSB */
3150 volatile u_short *const s =
3151 (volatile u_short *) sc->hpp_mem_start;
3152
3153 *dst = (*s) & 0xFF;
3154 }
3155
3156 /* Restore Boot ROM access. */
3157
3158 outw(sc->asic_addr + ED_HPP_OPTION,
3159 sc->hpp_options);
3160
3161
3162 } else {
3163 /* Read in data using the I/O port */
3164 if (use_32bit_access && (amount > 3)) {
3165 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2);
3166 dst += (amount & ~3);
3167 amount &= 3;
3168 }
3169 if (amount > 1) {
3170 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1);
3171 dst += (amount & ~1);
3172 amount &= 1;
3173 }
3174 if (amount == 1) { /* read in a short and keep the LSB */
3175 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF;
3176 }
3177 }
3178}
3179
3180/*
3181 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3182 * outsw() or via the memory mapped interface to the same register.
3183 * Writes have to be in word units; byte accesses won't work and may cause
3184 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC
3185 * allows it.
3186 */
3187
3188static u_short
3189ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3190{
3191 int len, wantbyte;
3192 unsigned short total_len;
3193 unsigned char savebyte[2];
3194 volatile u_short * const d =
3195 (volatile u_short *) sc->hpp_mem_start;
3196 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3197
3198 /* select page 0 registers */
3199 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3200
3201 /* reset remote DMA complete flag */
3202 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
3203
3204 /* program the write address in RAM */
3205 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
3206
3207 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3208 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options &
3209 ~(ED_HPP_OPTION_MEM_DISABLE |
3210 ED_HPP_OPTION_BOOT_ROM_ENB));
3211
3212 wantbyte = 0;
3213 total_len = 0;
3214
3215 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3216 while (m) {
3217 total_len += (len = m->m_len);
3218 if (len) {
3219 caddr_t data = mtod(m, caddr_t);
3220 /* finish the last word of the previous mbuf */
3221 if (wantbyte) {
3222 savebyte[1] = *data;
3223 *d = *((ushort *) savebyte);
3224 data++; len--; wantbyte = 0;
3225 }
3226 /* output contiguous words */
3227 if ((len > 3) && (use_32bit_accesses)) {
3228 volatile u_long *const dl =
3229 (volatile u_long *) d;
3230 u_long *sl = (u_long *) data;
3231 u_long *fence = sl + (len >> 2);
3232
3233 while (sl < fence)
3234 *dl = *sl++;
3235
3236 data += (len & ~3);
3237 len &= 3;
3238 }
3239 /* finish off remain 16 bit writes */
3240 if (len > 1) {
3241 u_short *s = (u_short *) data;
3242 u_short *fence = s + (len >> 1);
3243
3244 while (s < fence)
3245 *d = *s++;
3246
3247 data += (len & ~1);
3248 len &= 1;
3249 }
3250 /* save last byte if needed */
3251 if (wantbyte = (len == 1))
3252 savebyte[0] = *data;
3253 }
3254 m = m->m_next; /* to next mbuf */
3255 }
3256 if (wantbyte) /* write last byte */
3257 *d = *((u_short *) savebyte);
3258 } else {
3259 /* use programmed I/O */
3260 while (m) {
3261 total_len += (len = m->m_len);
3262 if (len) {
3263 caddr_t data = mtod(m, caddr_t);
3264 /* finish the last word of the previous mbuf */
3265 if (wantbyte) {
3266 savebyte[1] = *data;
3267 outw(sc->asic_addr + ED_HPP_PAGE_4,
3268 *((u_short *)savebyte));
3269 data++;
3270 len--;
3271 wantbyte = 0;
3272 }
3273 /* output contiguous words */
3274 if ((len > 3) && use_32bit_accesses) {
3275 outsl(sc->asic_addr + ED_HPP_PAGE_4,
3276 data, len >> 2);
3277 data += (len & ~3);
3278 len &= 3;
3279 }
3280 /* finish off remaining 16 bit accesses */
3281 if (len > 1) {
3282 outsw(sc->asic_addr + ED_HPP_PAGE_4,
3283 data, len >> 1);
3284 data += (len & ~1);
3285 len &= 1;
3286 }
3287 if (wantbyte = (len == 1))
3288 savebyte[0] = *data;
3289
3290 } /* if len != 0 */
3291 m = m->m_next;
3292 }
3293 if (wantbyte) /* spit last byte */
3294 outw(sc->asic_addr + ED_HPP_PAGE_4,
3295 *(u_short *)savebyte);
3296
3297 }
3298
3299 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3300 outw(sc->asic_addr + ED_HPP_OPTION,
3301 sc->hpp_options);
3302
3303 return (total_len);
3304}
3305
3306static void
3307ed_setrcr(sc)
3308 struct ed_softc *sc;
3309{
3310 struct ifnet *ifp = (struct ifnet *)sc;
3311 int i;
3312
3313 /* set page 1 registers */
3314 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3315
3316 if (ifp->if_flags & IFF_PROMISC) {
3317
3318 /*
3319 * Reconfigure the multicast filter.
3320 */
3321 for (i = 0; i < 8; i++)
3322 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
3323
3324 /*
3325 * And turn on promiscuous mode. Also enable reception of
3326 * runts and packets with CRC & alignment errors.
3327 */
3328 /* Set page 0 registers */
3329 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3330
3331 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3332 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP);
3333 } else {
3334 /* set up multicast addresses and filter modes */
3335 if (ifp->if_flags & IFF_MULTICAST) {
3336 u_long mcaf[2];
3337
3338 if (ifp->if_flags & IFF_ALLMULTI) {
3339 mcaf[0] = 0xffffffff;
3340 mcaf[1] = 0xffffffff;
3341 } else
3342 ds_getmcaf(sc, mcaf);
3343
3344 /*
3345 * Set multicast filter on chip.
3346 */
3347 for (i = 0; i < 8; i++)
3348 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]);
3349
3350 /* Set page 0 registers */
3351 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3352
3353 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB);
3354 } else {
3355
3356 /*
3357 * Initialize multicast address hashing registers to
3358 * not accept multicasts.
3359 */
3360 for (i = 0; i < 8; ++i)
3361 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00);
3362
3363 /* Set page 0 registers */
3364 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3365
3366 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
3367 }
3368 }
3369
3370 /*
3371 * Start interface.
3372 */
3373 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3374}
3375
3376/*
3377 * Compute crc for ethernet address
3378 */
3379static u_long
3380ds_crc(ep)
3381 u_char *ep;
3382{
3383#define POLYNOMIAL 0x04c11db6
3384 register u_long crc = 0xffffffffL;
3385 register int carry, i, j;
3386 register u_char b;
3387
3388 for (i = 6; --i >= 0;) {
3389 b = *ep++;
3390 for (j = 8; --j >= 0;) {
3391 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
3392 crc <<= 1;
3393 b >>= 1;
3394 if (carry)
3395 crc = ((crc ^ POLYNOMIAL) | carry);
3396 }
3397 }
3398 return crc;
3399#undef POLYNOMIAL
3400}
3401
3402/*
3403 * Compute the multicast address filter from the
3404 * list of multicast addresses we need to listen to.
3405 */
3406static void
3407ds_getmcaf(sc, mcaf)
3408 struct ed_softc *sc;
3409 u_long *mcaf;
3410{
3411 register u_int index;
3412 register u_char *af = (u_char *) mcaf;
|