28 */
29
30/*
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
33 *
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
37 *
38 */
39
40#include "opt_ed.h"
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/sockio.h>
45#include <sys/mbuf.h>
46#include <sys/kernel.h>
47#include <sys/socket.h>
48#include <sys/syslog.h>
49
50#include <sys/bus.h>
51
52#include <machine/bus.h>
53#include <sys/rman.h>
54#include <machine/resource.h>
55
56#include <net/ethernet.h>
57#include <net/if.h>
58#include <net/if_arp.h>
59#include <net/if_dl.h>
60#include <net/if_mib.h>
61#include <net/if_media.h>
62
63#ifndef ED_NO_MIIBUS
64#include <dev/mii/mii.h>
65#include <dev/mii/miivar.h>
66#endif
67
68#include <net/bpf.h>
69#include <net/bridge.h>
70
71#include <machine/md_var.h>
72
73#include <dev/ed/if_edreg.h>
74#include <dev/ed/if_edvar.h>
75
76devclass_t ed_devclass;
77
78static void ed_init (void *);
79static int ed_ioctl (struct ifnet *, u_long, caddr_t);
80static void ed_start (struct ifnet *);
81static void ed_reset (struct ifnet *);
82static void ed_watchdog (struct ifnet *);
83#ifndef ED_NO_MIIBUS
84static void ed_tick (void *);
85#endif
86
87static void ds_getmcaf (struct ed_softc *, u_int32_t *);
88
89static void ed_get_packet (struct ed_softc *, char *, /* u_short */ int);
90
91static __inline void ed_rint (struct ed_softc *);
92static __inline void ed_xmit (struct ed_softc *);
93static __inline char * ed_ring_copy(struct ed_softc *, char *, char *,
94 /* u_short */ int);
95static void ed_hpp_set_physical_link(struct ed_softc *);
96static void ed_hpp_readmem (struct ed_softc *, int, unsigned char *,
97 /* u_short */ int);
98static void ed_hpp_writemem (struct ed_softc *, unsigned char *,
99 /* u_short */ int, /* u_short */ int);
100static u_short ed_hpp_write_mbufs(struct ed_softc *, struct mbuf *, int);
101
102static u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, int);
103
104static void ed_setrcr (struct ed_softc *);
105
106static u_int32_t ds_crc (u_char *ep);
107
108/*
109 * Interrupt conversion table for WD/SMC ASIC/83C584
110 */
111static unsigned short ed_intr_val[] = {
112 9,
113 3,
114 5,
115 7,
116 10,
117 11,
118 15,
119 4
120};
121
122/*
123 * Interrupt conversion table for 83C790
124 */
125static unsigned short ed_790_intr_val[] = {
126 0,
127 9,
128 3,
129 5,
130 7,
131 10,
132 11,
133 15
134};
135
136/*
137 * Interrupt conversion table for the HP PC LAN+
138 */
139
140static unsigned short ed_hpp_intr_val[] = {
141 0, /* 0 */
142 0, /* 1 */
143 0, /* 2 */
144 3, /* 3 */
145 4, /* 4 */
146 5, /* 5 */
147 6, /* 6 */
148 7, /* 7 */
149 0, /* 8 */
150 9, /* 9 */
151 10, /* 10 */
152 11, /* 11 */
153 12, /* 12 */
154 0, /* 13 */
155 0, /* 14 */
156 15 /* 15 */
157};
158
159/*
160 * Generic probe routine for testing for the existance of a DS8390.
161 * Must be called after the NIC has just been reset. This routine
162 * works by looking at certain register values that are guaranteed
163 * to be initialized a certain way after power-up or reset. Seems
164 * not to currently work on the 83C690.
165 *
166 * Specifically:
167 *
168 * Register reset bits set bits
169 * Command Register (CR) TXP, STA RD2, STP
170 * Interrupt Status (ISR) RST
171 * Interrupt Mask (IMR) All bits
172 * Data Control (DCR) LAS
173 * Transmit Config. (TCR) LB1, LB0
174 *
175 * We only look at the CR and ISR registers, however, because looking at
176 * the others would require changing register pages (which would be
177 * intrusive if this isn't an 8390).
178 *
179 * Return 1 if 8390 was found, 0 if not.
180 */
181
182int
183ed_probe_generic8390(sc)
184 struct ed_softc *sc;
185{
186 if ((ed_nic_inb(sc, ED_P0_CR) &
187 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
188 (ED_CR_RD2 | ED_CR_STP))
189 return (0);
190 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
191 return (0);
192
193 return (1);
194}
195
196/*
197 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
198 */
199int
200ed_probe_WD80x3_generic(dev, flags, intr_vals)
201 device_t dev;
202 int flags;
203 unsigned short *intr_vals[];
204{
205 struct ed_softc *sc = device_get_softc(dev);
206 int error;
207 int i;
208 u_int memsize, maddr;
209 u_char iptr, isa16bit, sum, totalsum;
210 u_long conf_maddr, conf_msize, irq, junk;
211
212 sc->chip_type = ED_CHIP_TYPE_DP8390;
213
214 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
215 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
216 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
217 DELAY(10000);
218 }
219 else
220 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
221
222 /*
223 * Attempt to do a checksum over the station address PROM. If it
224 * fails, it's probably not a SMC/WD board. There is a problem with
225 * this, though: some clone WD boards don't pass the checksum test.
226 * Danpex boards for one.
227 */
228 for (sum = 0, i = 0; i < 8; ++i)
229 sum += ed_asic_inb(sc, ED_WD_PROM + i);
230
231 if (sum != totalsum) {
232
233 /*
234 * Checksum is invalid. This often happens with cheap WD8003E
235 * clones. In this case, the checksum byte (the eighth byte)
236 * seems to always be zero.
237 */
238 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
239 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
240 return (ENXIO);
241 }
242 /* reset card to force it into a known state. */
243 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
244 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
245 else
246 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
247
248 DELAY(100);
249 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
250 /* wait in the case this card is reading its EEROM */
251 DELAY(5000);
252
253 sc->vendor = ED_VENDOR_WD_SMC;
254 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
255
256 /*
257 * Set initial values for width/size.
258 */
259 memsize = 8192;
260 isa16bit = 0;
261 switch (sc->type) {
262 case ED_TYPE_WD8003S:
263 sc->type_str = "WD8003S";
264 break;
265 case ED_TYPE_WD8003E:
266 sc->type_str = "WD8003E";
267 break;
268 case ED_TYPE_WD8003EB:
269 sc->type_str = "WD8003EB";
270 break;
271 case ED_TYPE_WD8003W:
272 sc->type_str = "WD8003W";
273 break;
274 case ED_TYPE_WD8013EBT:
275 sc->type_str = "WD8013EBT";
276 memsize = 16384;
277 isa16bit = 1;
278 break;
279 case ED_TYPE_WD8013W:
280 sc->type_str = "WD8013W";
281 memsize = 16384;
282 isa16bit = 1;
283 break;
284 case ED_TYPE_WD8013EP: /* also WD8003EP */
285 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
286 isa16bit = 1;
287 memsize = 16384;
288 sc->type_str = "WD8013EP";
289 } else {
290 sc->type_str = "WD8003EP";
291 }
292 break;
293 case ED_TYPE_WD8013WC:
294 sc->type_str = "WD8013WC";
295 memsize = 16384;
296 isa16bit = 1;
297 break;
298 case ED_TYPE_WD8013EBP:
299 sc->type_str = "WD8013EBP";
300 memsize = 16384;
301 isa16bit = 1;
302 break;
303 case ED_TYPE_WD8013EPC:
304 sc->type_str = "WD8013EPC";
305 memsize = 16384;
306 isa16bit = 1;
307 break;
308 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
309 case ED_TYPE_SMC8216T:
310 if (sc->type == ED_TYPE_SMC8216C) {
311 sc->type_str = "SMC8216/SMC8216C";
312 } else {
313 sc->type_str = "SMC8216T";
314 }
315
316 ed_asic_outb(sc, ED_WD790_HWR,
317 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
318 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
319 case ED_WD790_RAR_SZ64:
320 memsize = 65536;
321 break;
322 case ED_WD790_RAR_SZ32:
323 memsize = 32768;
324 break;
325 case ED_WD790_RAR_SZ16:
326 memsize = 16384;
327 break;
328 case ED_WD790_RAR_SZ8:
329 /* 8216 has 16K shared mem -- 8416 has 8K */
330 if (sc->type == ED_TYPE_SMC8216C) {
331 sc->type_str = "SMC8416C/SMC8416BT";
332 } else {
333 sc->type_str = "SMC8416T";
334 }
335 memsize = 8192;
336 break;
337 }
338 ed_asic_outb(sc, ED_WD790_HWR,
339 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
340
341 isa16bit = 1;
342 sc->chip_type = ED_CHIP_TYPE_WD790;
343 break;
344 case ED_TYPE_TOSHIBA1:
345 sc->type_str = "Toshiba1";
346 memsize = 32768;
347 isa16bit = 1;
348 break;
349 case ED_TYPE_TOSHIBA4:
350 sc->type_str = "Toshiba4";
351 memsize = 32768;
352 isa16bit = 1;
353 break;
354 default:
355 sc->type_str = "";
356 break;
357 }
358
359 /*
360 * Make some adjustments to initial values depending on what is found
361 * in the ICR.
362 */
363 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
364 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
365 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
366 isa16bit = 0;
367 memsize = 8192;
368 }
369
370 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
371 &conf_maddr, &conf_msize);
372 if (error)
373 return (error);
374
375#if ED_DEBUG
376 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
377 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
378 for (i = 0; i < 8; i++)
379 printf("%x -> %x\n", i, ed_asic_inb(sc, i));
380#endif
381
382 /*
383 * Allow the user to override the autoconfiguration
384 */
385 if (conf_msize > 1)
386 memsize = conf_msize;
387
388 maddr = conf_maddr;
389 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
390 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
391 maddr, maddr + memsize);
392 return (ENXIO);
393 }
394
395 /*
396 * (note that if the user specifies both of the following flags that
397 * '8bit' mode intentionally has precedence)
398 */
399 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
400 isa16bit = 1;
401 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
402 isa16bit = 0;
403
404 /*
405 * If possible, get the assigned interrupt number from the card and
406 * use it.
407 */
408 if ((sc->type & ED_WD_SOFTCONFIG) &&
409 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
410
411 /*
412 * Assemble together the encoded interrupt number.
413 */
414 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
415 ((ed_asic_inb(sc, ED_WD_IRR) &
416 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
417
418 /*
419 * If no interrupt specified (or "?"), use what the board tells us.
420 */
421 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
422 &irq, &junk);
423 if (error && intr_vals[0] != NULL) {
424 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
425 intr_vals[0][iptr], 1);
426 }
427 if (error)
428 return (error);
429
430 /*
431 * Enable the interrupt.
432 */
433 ed_asic_outb(sc, ED_WD_IRR,
434 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
435 }
436 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
437 ed_asic_outb(sc, ED_WD790_HWR,
438 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
439 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
440 (ed_asic_inb(sc, ED_WD790_GCR) &
441 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
442 ed_asic_outb(sc, ED_WD790_HWR,
443 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
444
445 /*
446 * If no interrupt specified (or "?"), use what the board tells us.
447 */
448 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
449 &irq, &junk);
450 if (error && intr_vals[1] != NULL) {
451 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
452 intr_vals[1][iptr], 1);
453 }
454 if (error)
455 return (error);
456
457 /*
458 * Enable interrupts.
459 */
460 ed_asic_outb(sc, ED_WD790_ICR,
461 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
462 }
463 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
464 &irq, &junk);
465 if (error) {
466 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
467 sc->type_str);
468 return (ENXIO);
469 }
470 sc->isa16bit = isa16bit;
471 sc->mem_shared = 1;
472
473 error = ed_alloc_memory(dev, 0, memsize);
474 if (error) {
475 printf("*** ed_alloc_memory() failed! (%d)\n", error);
476 return (error);
477 }
478 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
479
480 /*
481 * allocate one xmit buffer if < 16k, two buffers otherwise
482 */
483 if ((memsize < 16384) ||
484 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
485 sc->txb_cnt = 1;
486 } else {
487 sc->txb_cnt = 2;
488 }
489 sc->tx_page_start = ED_WD_PAGE_OFFSET;
490 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
491 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
492 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
493 sc->mem_size = memsize;
494 sc->mem_end = sc->mem_start + memsize;
495
496 /*
497 * Get station address from on-board ROM
498 */
499 for (i = 0; i < ETHER_ADDR_LEN; ++i)
500 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
501
502 /*
503 * Set upper address bits and 8/16 bit access to shared memory.
504 */
505 if (isa16bit) {
506 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
507 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
508 } else {
509 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
510 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
511 }
512 /*
513 * Enable 16bit access
514 */
515 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
516 ED_WD_LAAR_M16EN);
517 } else {
518 if (((sc->type & ED_WD_SOFTCONFIG) ||
519 (sc->type == ED_TYPE_TOSHIBA1) ||
520 (sc->type == ED_TYPE_TOSHIBA4) ||
521 (sc->type == ED_TYPE_WD8013EBT)) &&
522 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
523 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
524 ED_WD_LAAR_ADDRHI;
525 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
526 }
527 }
528
529 /*
530 * Set address and enable interface shared memory.
531 */
532 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
533 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
534 ed_asic_outb(sc, ED_WD_MSR + 1,
535 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
536 ed_asic_outb(sc, ED_WD_MSR + 2,
537 ((kvtop(sc->mem_start) >> 16) & 0x0f));
538 ed_asic_outb(sc, ED_WD_MSR,
539 ED_WD_MSR_MENB | ED_WD_MSR_POW);
540 } else {
541 ed_asic_outb(sc, ED_WD_MSR,
542 ((kvtop(sc->mem_start) >> 13) &
543 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
544 }
545 sc->cr_proto = ED_CR_RD2;
546 } else {
547 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
548 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
549 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
550 ((kvtop(sc->mem_start) >> 11) & 0x40) |
551 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
552 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
553 sc->cr_proto = 0;
554 }
555
556#if 0
557 printf("starting memory performance test at 0x%x, size %d...\n",
558 sc->mem_start, memsize*16384);
559 for (i = 0; i < 16384; i++)
560 bzero(sc->mem_start, memsize);
561 printf("***DONE***\n");
562#endif
563
564 /*
565 * Now zero memory and verify that it is clear
566 */
567 bzero(sc->mem_start, memsize);
568
569 for (i = 0; i < memsize; ++i) {
570 if (sc->mem_start[i]) {
571 device_printf(dev, "failed to clear shared memory at %jx - check configuration\n",
572 (uintmax_t)kvtop(sc->mem_start + i));
573
574 /*
575 * Disable 16 bit access to shared memory
576 */
577 if (isa16bit) {
578 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
579 ed_asic_outb(sc, ED_WD_MSR, 0x00);
580 }
581 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
582 ~ED_WD_LAAR_M16EN);
583 }
584 return (ENXIO);
585 }
586 }
587
588 /*
589 * Disable 16bit access to shared memory - we leave it
590 * disabled so that 1) machines reboot properly when the board
591 * is set 16 bit mode and there are conflicting 8bit
592 * devices/ROMS in the same 128k address space as this boards
593 * shared memory. and 2) so that other 8 bit devices with
594 * shared memory can be used in this 128k region, too.
595 */
596 if (isa16bit) {
597 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
598 ed_asic_outb(sc, ED_WD_MSR, 0x00);
599 }
600 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
601 ~ED_WD_LAAR_M16EN);
602 }
603 return (0);
604}
605
606int
607ed_probe_WD80x3(dev, port_rid, flags)
608 device_t dev;
609 int port_rid;
610 int flags;
611{
612 struct ed_softc *sc = device_get_softc(dev);
613 int error;
614 static unsigned short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
615
616 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
617 if (error)
618 return (error);
619
620 sc->asic_offset = ED_WD_ASIC_OFFSET;
621 sc->nic_offset = ED_WD_NIC_OFFSET;
622
623 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
624}
625
626/*
627 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
628 */
629int
630ed_probe_3Com(dev, port_rid, flags)
631 device_t dev;
632 int port_rid;
633 int flags;
634{
635 struct ed_softc *sc = device_get_softc(dev);
636 int error;
637 int i;
638 u_int memsize;
639 u_char isa16bit;
640 u_long conf_maddr, conf_msize, irq, junk;
641
642 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
643 if (error)
644 return (error);
645
646 sc->asic_offset = ED_3COM_ASIC_OFFSET;
647 sc->nic_offset = ED_3COM_NIC_OFFSET;
648
649 /*
650 * Verify that the kernel configured I/O address matches the board
651 * configured address
652 */
653 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
654 case ED_3COM_BCFR_300:
655 if (rman_get_start(sc->port_res) != 0x300)
656 return (ENXIO);
657 break;
658 case ED_3COM_BCFR_310:
659 if (rman_get_start(sc->port_res) != 0x310)
660 return (ENXIO);
661 break;
662 case ED_3COM_BCFR_330:
663 if (rman_get_start(sc->port_res) != 0x330)
664 return (ENXIO);
665 break;
666 case ED_3COM_BCFR_350:
667 if (rman_get_start(sc->port_res) != 0x350)
668 return (ENXIO);
669 break;
670 case ED_3COM_BCFR_250:
671 if (rman_get_start(sc->port_res) != 0x250)
672 return (ENXIO);
673 break;
674 case ED_3COM_BCFR_280:
675 if (rman_get_start(sc->port_res) != 0x280)
676 return (ENXIO);
677 break;
678 case ED_3COM_BCFR_2A0:
679 if (rman_get_start(sc->port_res) != 0x2a0)
680 return (ENXIO);
681 break;
682 case ED_3COM_BCFR_2E0:
683 if (rman_get_start(sc->port_res) != 0x2e0)
684 return (ENXIO);
685 break;
686 default:
687 return (ENXIO);
688 }
689
690 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
691 &conf_maddr, &conf_msize);
692 if (error)
693 return (error);
694
695 /*
696 * Verify that the kernel shared memory address matches the board
697 * configured address.
698 */
699 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
700 case ED_3COM_PCFR_DC000:
701 if (conf_maddr != 0xdc000)
702 return (ENXIO);
703 break;
704 case ED_3COM_PCFR_D8000:
705 if (conf_maddr != 0xd8000)
706 return (ENXIO);
707 break;
708 case ED_3COM_PCFR_CC000:
709 if (conf_maddr != 0xcc000)
710 return (ENXIO);
711 break;
712 case ED_3COM_PCFR_C8000:
713 if (conf_maddr != 0xc8000)
714 return (ENXIO);
715 break;
716 default:
717 return (ENXIO);
718 }
719
720
721 /*
722 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
723 * sequence because it'll lock up if the cable isn't connected if we
724 * don't.
725 */
726 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
727
728 /*
729 * Wait for a while, then un-reset it
730 */
731 DELAY(50);
732
733 /*
734 * The 3Com ASIC defaults to rather strange settings for the CR after
735 * a reset - it's important to set it again after the following outb
736 * (this is done when we map the PROM below).
737 */
738 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
739
740 /*
741 * Wait a bit for the NIC to recover from the reset
742 */
743 DELAY(5000);
744
745 sc->vendor = ED_VENDOR_3COM;
746 sc->type_str = "3c503";
747 sc->mem_shared = 1;
748 sc->cr_proto = ED_CR_RD2;
749
750 /*
751 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
752 * to it.
753 */
754 memsize = 8192;
755
756 /*
757 * Get station address from on-board ROM
758 */
759
760 /*
761 * First, map ethernet address PROM over the top of where the NIC
762 * registers normally appear.
763 */
764 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
765
766 for (i = 0; i < ETHER_ADDR_LEN; ++i)
767 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
768
769 /*
770 * Unmap PROM - select NIC registers. The proper setting of the
771 * tranceiver is set in ed_init so that the attach code is given a
772 * chance to set the default based on a compile-time config option
773 */
774 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
775
776 /*
777 * Determine if this is an 8bit or 16bit board
778 */
779
780 /*
781 * select page 0 registers
782 */
783 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
784
785 /*
786 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
787 * board.
788 */
789 ed_nic_outb(sc, ED_P0_DCR, 0);
790
791 /*
792 * select page 2 registers
793 */
794 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
795
796 /*
797 * The 3c503 forces the WTS bit to a one if this is a 16bit board
798 */
799 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
800 isa16bit = 1;
801 else
802 isa16bit = 0;
803
804 /*
805 * select page 0 registers
806 */
807 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
808
809 error = ed_alloc_memory(dev, 0, memsize);
810 if (error)
811 return (error);
812
813 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
814 sc->mem_size = memsize;
815 sc->mem_end = sc->mem_start + memsize;
816
817 /*
818 * We have an entire 8k window to put the transmit buffers on the
819 * 16bit boards. But since the 16bit 3c503's shared memory is only
820 * fast enough to overlap the loading of one full-size packet, trying
821 * to load more than 2 buffers can actually leave the transmitter idle
822 * during the load. So 2 seems the best value. (Although a mix of
823 * variable-sized packets might change this assumption. Nonetheless,
824 * we optimize for linear transfers of same-size packets.)
825 */
826 if (isa16bit) {
827 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
828 sc->txb_cnt = 1;
829 else
830 sc->txb_cnt = 2;
831
832 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
833 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
834 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
835 ED_3COM_RX_PAGE_OFFSET_16BIT;
836 sc->mem_ring = sc->mem_start;
837 } else {
838 sc->txb_cnt = 1;
839 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
840 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
841 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
842 ED_3COM_TX_PAGE_OFFSET_8BIT;
843 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
844 }
845
846 sc->isa16bit = isa16bit;
847
848 /*
849 * Initialize GA page start/stop registers. Probably only needed if
850 * doing DMA, but what the hell.
851 */
852 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
853 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
854
855 /*
856 * Set IRQ. 3c503 only allows a choice of irq 2-5.
857 */
858 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
859 if (error)
860 return (error);
861
862 switch (irq) {
863 case 2:
864 case 9:
865 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
866 break;
867 case 3:
868 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
869 break;
870 case 4:
871 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
872 break;
873 case 5:
874 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
875 break;
876 default:
877 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
878 irq);
879 return (ENXIO);
880 }
881
882 /*
883 * Initialize GA configuration register. Set bank and enable shared
884 * mem.
885 */
886 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
887 ED_3COM_GACFR_MBS0);
888
889 /*
890 * Initialize "Vector Pointer" registers. These gawd-awful things are
891 * compared to 20 bits of the address on ISA, and if they match, the
892 * shared memory is disabled. We set them to 0xffff0...allegedly the
893 * reset vector.
894 */
895 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
896 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
897 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
898
899 /*
900 * Zero memory and verify that it is clear
901 */
902 bzero(sc->mem_start, memsize);
903
904 for (i = 0; i < memsize; ++i)
905 if (sc->mem_start[i]) {
906 device_printf(dev, "failed to clear shared memory at %jx - check configuration\n",
907 (uintmax_t)kvtop(sc->mem_start + i));
908 return (ENXIO);
909 }
910 return (0);
911}
912
913/*
914 * Probe and vendor-specific initialization routine for NE1000/2000 boards
915 */
916int
917ed_probe_Novell_generic(dev, flags)
918 device_t dev;
919 int flags;
920{
921 struct ed_softc *sc = device_get_softc(dev);
922 u_int memsize, n;
923 u_char romdata[16], tmp;
924 static char test_pattern[32] = "THIS is A memory TEST pattern";
925 char test_buffer[32];
926
927 /* XXX - do Novell-specific probe here */
928
929 /* Reset the board */
930 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
931 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
932 DELAY(200);
933 }
934 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
935
936 /*
937 * I don't know if this is necessary; probably cruft leftover from
938 * Clarkson packet driver code. Doesn't do a thing on the boards I've
939 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is
940 * non-invasive...but some boards don't seem to reset and I don't have
941 * complete documentation on what the 'right' thing to do is...so we
942 * do the invasive thing for now. Yuck.]
943 */
944 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
945 DELAY(5000);
946
947 /*
948 * This is needed because some NE clones apparently don't reset the
949 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
950 * - this makes the probe invasive! ...Done against my better
951 * judgement. -DLG
952 */
953 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
954
955 DELAY(5000);
956
957 /* Make sure that we really have an 8390 based board */
958 if (!ed_probe_generic8390(sc))
959 return (ENXIO);
960
961 sc->vendor = ED_VENDOR_NOVELL;
962 sc->mem_shared = 0;
963 sc->cr_proto = ED_CR_RD2;
964
965 /*
966 * Test the ability to read and write to the NIC memory. This has the
967 * side affect of determining if this is an NE1000 or an NE2000.
968 */
969
970 /*
971 * This prevents packets from being stored in the NIC memory when the
972 * readmem routine turns on the start bit in the CR.
973 */
974 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
975
976 /* Temporarily initialize DCR for byte operations */
977 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
978
979 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
980 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
981
982 sc->isa16bit = 0;
983
984 /*
985 * Write a test pattern in byte mode. If this fails, then there
986 * probably isn't any memory at 8k - which likely means that the board
987 * is an NE2000.
988 */
989 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
990 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
991
992 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
993 sc->type = ED_TYPE_NE1000;
994 sc->type_str = "NE1000";
995 } else {
996
997 /* neither an NE1000 nor a Linksys - try NE2000 */
998 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
999 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1000 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1001
1002 sc->isa16bit = 1;
1003
1004 /*
1005 * Write a test pattern in word mode. If this also fails, then
1006 * we don't know what this board is.
1007 */
1008 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1009 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1010 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1011 sc->type = ED_TYPE_NE2000;
1012 sc->type_str = "NE2000";
1013 } else {
1014 return (ENXIO);
1015 }
1016 }
1017
1018
1019 /* 8k of memory plus an additional 8k if 16bit */
1020 memsize = 8192 + sc->isa16bit * 8192;
1021
1022#if 0 /* probably not useful - NE boards only come two ways */
1023 /* allow kernel config file overrides */
1024 if (isa_dev->id_msize)
1025 memsize = isa_dev->id_msize;
1026#endif
1027
1028 sc->mem_size = memsize;
1029
1030 /* NIC memory doesn't start at zero on an NE board */
1031 /* The start address is tied to the bus width */
1032 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1033 sc->mem_end = sc->mem_start + memsize;
1034 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1035
1036 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1037 int x, i, mstart = 0, msize = 0;
1038 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1039
1040 for (i = 0; i < ED_PAGE_SIZE; i++)
1041 pbuf0[i] = 0;
1042
1043 /* Clear all the memory. */
1044 for (x = 1; x < 256; x++)
1045 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1046
1047 /* Search for the start of RAM. */
1048 for (x = 1; x < 256; x++) {
1049 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1050 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1051 for (i = 0; i < ED_PAGE_SIZE; i++)
1052 pbuf[i] = 255 - x;
1053 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1054 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1055 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1056 mstart = x * ED_PAGE_SIZE;
1057 msize = ED_PAGE_SIZE;
1058 break;
1059 }
1060 }
1061 }
1062
1063 if (mstart == 0) {
1064 device_printf(dev, "Cannot find start of RAM.\n");
1065 return (ENXIO);
1066 }
1067 /* Search for the start of RAM. */
1068 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1069 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1070 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1071 for (i = 0; i < ED_PAGE_SIZE; i++)
1072 pbuf[i] = 255 - x;
1073 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1074 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1075 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1076 msize += ED_PAGE_SIZE;
1077 else {
1078 break;
1079 }
1080 } else {
1081 break;
1082 }
1083 }
1084
1085 if (msize == 0) {
1086 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1087 return (ENXIO);
1088 }
1089 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1090
1091 sc->mem_size = msize;
1092 sc->mem_start = (caddr_t) mstart;
1093 sc->mem_end = (caddr_t) (msize + mstart);
1094 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1095 }
1096
1097 /*
1098 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1099 * otherwise).
1100 */
1101 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1102 sc->txb_cnt = 1;
1103 else
1104 sc->txb_cnt = 2;
1105
1106 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1107 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1108
1109 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1110
1111 ed_pio_readmem(sc, 0, romdata, 16);
1112 for (n = 0; n < ETHER_ADDR_LEN; n++)
1113 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1114
1115 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1116 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1117 sc->type_str = "Gateway AT";
1118 }
1119
1120 /* clear any pending interrupts that might have occurred above */
1121 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1122
1123 return (0);
1124}
1125
1126int
1127ed_probe_Novell(dev, port_rid, flags)
1128 device_t dev;
1129 int port_rid;
1130 int flags;
1131{
1132 struct ed_softc *sc = device_get_softc(dev);
1133 int error;
1134
1135 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1136 if (error)
1137 return (error);
1138
1139 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1140 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1141
1142 return ed_probe_Novell_generic(dev, flags);
1143}
1144
1145#define ED_HPP_TEST_SIZE 16
1146
1147/*
1148 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1149 * (HP Part nos: 27247B and 27252A).
1150 *
1151 * The card has an asic wrapper around a DS8390 core. The asic handles
1152 * host accesses and offers both standard register IO and memory mapped
1153 * IO. Memory mapped I/O allows better performance at the expense of greater
1154 * chance of an incompatibility with existing ISA cards.
1155 *
1156 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1157 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1158 * don't allow 32 bit accesses; these are indicated by a bit in the software
1159 * ID register (see if_edreg.h).
1160 *
1161 * Other caveats are: we should read the MAC address only when the card
1162 * is inactive.
1163 *
1164 * For more information; please consult the CRYNWR packet driver.
1165 *
1166 * The AUI port is turned on using the "link2" option on the ifconfig
1167 * command line.
1168 */
1169int
1170ed_probe_HP_pclanp(dev, port_rid, flags)
1171 device_t dev;
1172 int port_rid;
1173 int flags;
1174{
1175 struct ed_softc *sc = device_get_softc(dev);
1176 int error;
1177 int n; /* temp var */
1178 int memsize; /* mem on board */
1179 u_char checksum; /* checksum of board address */
1180 u_char irq; /* board configured IRQ */
1181 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1182 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1183 u_long conf_maddr, conf_msize, conf_irq, junk;
1184
1185 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1186 if (error)
1187 return (error);
1188
1189 /* Fill in basic information */
1190 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1191 sc->nic_offset = ED_HPP_NIC_OFFSET;
1192
1193 sc->chip_type = ED_CHIP_TYPE_DP8390;
1194 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1195
1196 /*
1197 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1198 */
1199
1200 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1201 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1202 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1203 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1204 return ENXIO;
1205
1206 /*
1207 * Read the MAC address and verify checksum on the address.
1208 */
1209
1210 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1211 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1212 checksum += (sc->arpcom.ac_enaddr[n] =
1213 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1214
1215 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1216
1217 if (checksum != 0xFF)
1218 return ENXIO;
1219
1220 /*
1221 * Verify that the software model number is 0.
1222 */
1223
1224 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1225 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1226 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1227 return ENXIO;
1228
1229 /*
1230 * Read in and save the current options configured on card.
1231 */
1232
1233 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1234
1235 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1236 ED_HPP_OPTION_CHIP_RESET |
1237 ED_HPP_OPTION_ENABLE_IRQ);
1238
1239 /*
1240 * Reset the chip. This requires writing to the option register
1241 * so take care to preserve the other bits.
1242 */
1243
1244 ed_asic_outw(sc, ED_HPP_OPTION,
1245 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1246 ED_HPP_OPTION_CHIP_RESET)));
1247
1248 DELAY(5000); /* wait for chip reset to complete */
1249
1250 ed_asic_outw(sc, ED_HPP_OPTION,
1251 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1252 ED_HPP_OPTION_CHIP_RESET |
1253 ED_HPP_OPTION_ENABLE_IRQ)));
1254
1255 DELAY(5000);
1256
1257 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1258 return ENXIO; /* reset did not complete */
1259
1260 /*
1261 * Read out configuration information.
1262 */
1263
1264 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1265
1266 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1267
1268 /*
1269 * Check for impossible IRQ.
1270 */
1271
1272 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1273 return ENXIO;
1274
1275 /*
1276 * If the kernel IRQ was specified with a '?' use the cards idea
1277 * of the IRQ. If the kernel IRQ was explicitly specified, it
1278 * should match that of the hardware.
1279 */
1280 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1281 &conf_irq, &junk);
1282 if (error) {
1283 bus_set_resource(dev, SYS_RES_IRQ, 0,
1284 ed_hpp_intr_val[irq], 1);
1285 } else {
1286 if (conf_irq != ed_hpp_intr_val[irq])
1287 return (ENXIO);
1288 }
1289
1290 /*
1291 * Fill in softconfig info.
1292 */
1293
1294 sc->vendor = ED_VENDOR_HP;
1295 sc->type = ED_TYPE_HP_PCLANPLUS;
1296 sc->type_str = "HP-PCLAN+";
1297
1298 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1299 sc->mem_start = 0; /* we use offsets inside the card RAM */
1300
1301 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1302
1303 /*
1304 * The board has 32KB of memory. Is there a way to determine
1305 * this programmatically?
1306 */
1307
1308 memsize = 32768;
1309
1310 /*
1311 * Check if memory mapping of the I/O registers possible.
1312 */
1313
1314 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1315 {
1316 u_long mem_addr;
1317
1318 /*
1319 * determine the memory address from the board.
1320 */
1321
1322 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1323 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1324
1325 /*
1326 * Check that the kernel specified start of memory and
1327 * hardware's idea of it match.
1328 */
1329 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1330 &conf_maddr, &conf_msize);
1331 if (error)
1332 return (error);
1333
1334 if (mem_addr != conf_maddr)
1335 return ENXIO;
1336
1337 error = ed_alloc_memory(dev, 0, memsize);
1338 if (error)
1339 return (error);
1340
1341 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1342 }
1343
1344 /*
1345 * Fill in the rest of the soft config structure.
1346 */
1347
1348 /*
1349 * The transmit page index.
1350 */
1351
1352 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1353
1354 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1355 sc->txb_cnt = 1;
1356 else
1357 sc->txb_cnt = 2;
1358
1359 /*
1360 * Memory description
1361 */
1362
1363 sc->mem_size = memsize;
1364 sc->mem_ring = sc->mem_start +
1365 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1366 sc->mem_end = sc->mem_start + sc->mem_size;
1367
1368 /*
1369 * Receive area starts after the transmit area and
1370 * continues till the end of memory.
1371 */
1372
1373 sc->rec_page_start = sc->tx_page_start +
1374 (sc->txb_cnt * ED_TXBUF_SIZE);
1375 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1376
1377
1378 sc->cr_proto = 0; /* value works */
1379
1380 /*
1381 * Set the wrap registers for string I/O reads.
1382 */
1383
1384 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1385 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1386 ((sc->rec_page_start / ED_PAGE_SIZE) |
1387 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1388
1389 /*
1390 * Reset the register page to normal operation.
1391 */
1392
1393 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1394
1395 /*
1396 * Verify that we can read/write from adapter memory.
1397 * Create test pattern.
1398 */
1399
1400 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1401 {
1402 test_pattern[n] = (n*n) ^ ~n;
1403 }
1404
1405#undef ED_HPP_TEST_SIZE
1406
1407 /*
1408 * Check that the memory is accessible thru the I/O ports.
1409 * Write out the contents of "test_pattern", read back
1410 * into "test_buffer" and compare the two for any
1411 * mismatch.
1412 */
1413
1414 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1415
1416 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1417 sizeof(test_pattern));
1418 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1419 test_buffer, sizeof(test_pattern));
1420
1421 if (bcmp(test_pattern, test_buffer,
1422 sizeof(test_pattern)))
1423 return ENXIO;
1424 }
1425
1426 return (0);
1427
1428}
1429
1430/*
1431 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1432 */
1433
1434static void
1435ed_hpp_set_physical_link(struct ed_softc *sc)
1436{
1437 struct ifnet *ifp = &sc->arpcom.ac_if;
1438 int lan_page;
1439
1440 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1441 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1442
1443 if (ifp->if_flags & IFF_ALTPHYS) {
1444
1445 /*
1446 * Use the AUI port.
1447 */
1448
1449 lan_page |= ED_HPP_LAN_AUI;
1450
1451 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1452 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1453
1454
1455 } else {
1456
1457 /*
1458 * Use the ThinLan interface
1459 */
1460
1461 lan_page &= ~ED_HPP_LAN_AUI;
1462
1463 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1464 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1465
1466 }
1467
1468 /*
1469 * Wait for the lan card to re-initialize itself
1470 */
1471
1472 DELAY(150000); /* wait 150 ms */
1473
1474 /*
1475 * Restore normal pages.
1476 */
1477
1478 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1479
1480}
1481
1482/*
1483 * Allocate a port resource with the given resource id.
1484 */
1485int
1486ed_alloc_port(dev, rid, size)
1487 device_t dev;
1488 int rid;
1489 int size;
1490{
1491 struct ed_softc *sc = device_get_softc(dev);
1492 struct resource *res;
1493
1494 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1495 0ul, ~0ul, size, RF_ACTIVE);
1496 if (res) {
1497 sc->port_rid = rid;
1498 sc->port_res = res;
1499 sc->port_used = size;
1500 return (0);
1501 } else {
1502 return (ENOENT);
1503 }
1504}
1505
1506/*
1507 * Allocate a memory resource with the given resource id.
1508 */
1509int
1510ed_alloc_memory(dev, rid, size)
1511 device_t dev;
1512 int rid;
1513 int size;
1514{
1515 struct ed_softc *sc = device_get_softc(dev);
1516 struct resource *res;
1517
1518 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1519 0ul, ~0ul, size, RF_ACTIVE);
1520 if (res) {
1521 sc->mem_rid = rid;
1522 sc->mem_res = res;
1523 sc->mem_used = size;
1524 return (0);
1525 } else {
1526 return (ENOENT);
1527 }
1528}
1529
1530/*
1531 * Allocate an irq resource with the given resource id.
1532 */
1533int
1534ed_alloc_irq(dev, rid, flags)
1535 device_t dev;
1536 int rid;
1537 int flags;
1538{
1539 struct ed_softc *sc = device_get_softc(dev);
1540 struct resource *res;
1541
1542 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
1543 0ul, ~0ul, 1, (RF_ACTIVE | flags));
1544 if (res) {
1545 sc->irq_rid = rid;
1546 sc->irq_res = res;
1547 return (0);
1548 } else {
1549 return (ENOENT);
1550 }
1551}
1552
1553/*
1554 * Release all resources
1555 */
1556void
1557ed_release_resources(dev)
1558 device_t dev;
1559{
1560 struct ed_softc *sc = device_get_softc(dev);
1561
1562 if (sc->port_res) {
1563 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1564 sc->port_rid, sc->port_res);
1565 bus_release_resource(dev, SYS_RES_IOPORT,
1566 sc->port_rid, sc->port_res);
1567 sc->port_res = 0;
1568 }
1569 if (sc->mem_res) {
1570 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1571 sc->mem_rid, sc->mem_res);
1572 bus_release_resource(dev, SYS_RES_MEMORY,
1573 sc->mem_rid, sc->mem_res);
1574 sc->mem_res = 0;
1575 }
1576 if (sc->irq_res) {
1577 bus_deactivate_resource(dev, SYS_RES_IRQ,
1578 sc->irq_rid, sc->irq_res);
1579 bus_release_resource(dev, SYS_RES_IRQ,
1580 sc->irq_rid, sc->irq_res);
1581 sc->irq_res = 0;
1582 }
1583}
1584
1585/*
1586 * Install interface into kernel networking data structures
1587 */
1588int
1589ed_attach(sc, unit, flags)
1590 struct ed_softc *sc;
1591 int unit;
1592 int flags;
1593{
1594 struct ifnet *ifp = &sc->arpcom.ac_if;
1595
1596 callout_handle_init(&sc->tick_ch);
1597 /*
1598 * Set interface to stopped condition (reset)
1599 */
1600 ed_stop(sc);
1601
1602 if (!ifp->if_name) {
1603 /*
1604 * Initialize ifnet structure
1605 */
1606 ifp->if_softc = sc;
1607 ifp->if_unit = unit;
1608 ifp->if_name = "ed";
1609 ifp->if_output = ether_output;
1610 ifp->if_start = ed_start;
1611 ifp->if_ioctl = ed_ioctl;
1612 ifp->if_watchdog = ed_watchdog;
1613 ifp->if_init = ed_init;
1614 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1615 ifp->if_linkmib = &sc->mibdata;
1616 ifp->if_linkmiblen = sizeof sc->mibdata;
1617 /*
1618 * XXX - should do a better job.
1619 */
1620 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1621 sc->mibdata.dot3StatsEtherChipSet =
1622 DOT3CHIPSET(dot3VendorWesternDigital,
1623 dot3ChipSetWesternDigital83C790);
1624 else
1625 sc->mibdata.dot3StatsEtherChipSet =
1626 DOT3CHIPSET(dot3VendorNational,
1627 dot3ChipSetNational8390);
1628 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1629
1630 /*
1631 * Set default state for ALTPHYS flag (used to disable the
1632 * tranceiver for AUI operation), based on compile-time
1633 * config option.
1634 */
1635 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1636 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1637 IFF_MULTICAST | IFF_ALTPHYS);
1638 else
1639 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1640 IFF_MULTICAST);
1641
1642 /*
1643 * Attach the interface
1644 */
1645 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1646 }
1647 /* device attach does transition from UNCONFIGURED to IDLE state */
1648
1649 /*
1650 * Print additional info when attached
1651 */
1652 if_printf(ifp, "address %6D, ", sc->arpcom.ac_enaddr, ":");
1653
1654 if (sc->type_str && (*sc->type_str != 0))
1655 printf("type %s ", sc->type_str);
1656 else
1657 printf("type unknown (0x%x) ", sc->type);
1658
1659 if (sc->vendor == ED_VENDOR_HP)
1660 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1661 "16-bit" : "32-bit",
1662 sc->hpp_mem_start ? "memory mapped" : "regular");
1663 else
1664 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1665
1666 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1667 (sc->vendor == ED_VENDOR_HP)) &&
1668 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1669
1670 return (0);
1671}
1672
1673/*
1674 * Reset interface.
1675 */
1676static void
1677ed_reset(ifp)
1678 struct ifnet *ifp;
1679{
1680 struct ed_softc *sc = ifp->if_softc;
1681 int s;
1682
1683 if (sc->gone)
1684 return;
1685 s = splimp();
1686
1687 /*
1688 * Stop interface and re-initialize.
1689 */
1690 ed_stop(sc);
1691 ed_init(sc);
1692
1693 (void) splx(s);
1694}
1695
1696/*
1697 * Take interface offline.
1698 */
1699void
1700ed_stop(sc)
1701 struct ed_softc *sc;
1702{
1703 int n = 5000;
1704
1705#ifndef ED_NO_MIIBUS
1706 untimeout(ed_tick, sc, sc->tick_ch);
1707 callout_handle_init(&sc->tick_ch);
1708#endif
1709 if (sc->gone)
1710 return;
1711 /*
1712 * Stop everything on the interface, and select page 0 registers.
1713 */
1714 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1715
1716 /*
1717 * Wait for interface to enter stopped state, but limit # of checks to
1718 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1719 * just in case it's an old one.
1720 */
1721 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1722 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1723}
1724
1725/*
1726 * Device timeout/watchdog routine. Entered if the device neglects to
1727 * generate an interrupt after a transmit has been started on it.
1728 */
1729static void
1730ed_watchdog(ifp)
1731 struct ifnet *ifp;
1732{
1733 struct ed_softc *sc = ifp->if_softc;
1734
1735 if (sc->gone)
1736 return;
1737 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1738 ifp->if_oerrors++;
1739
1740 ed_reset(ifp);
1741}
1742
1743#ifndef ED_NO_MIIBUS
1744static void
1745ed_tick(arg)
1746 void *arg;
1747{
1748 struct ed_softc *sc = arg;
1749 struct mii_data *mii;
1750 int s;
1751
1752 if (sc->gone) {
1753 callout_handle_init(&sc->tick_ch);
1754 return;
1755 }
1756 s = splimp();
1757 if (sc->miibus != NULL) {
1758 mii = device_get_softc(sc->miibus);
1759 mii_tick(mii);
1760 }
1761 sc->tick_ch = timeout(ed_tick, sc, hz);
1762 splx(s);
1763}
1764#endif
1765
1766/*
1767 * Initialize device.
1768 */
1769static void
1770ed_init(xsc)
1771 void *xsc;
1772{
1773 struct ed_softc *sc = xsc;
1774 struct ifnet *ifp = &sc->arpcom.ac_if;
1775 int i, s;
1776
1777 if (sc->gone)
1778 return;
1779
1780 /* address not known */
1781 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1782 return;
1783
1784 /*
1785 * Initialize the NIC in the exact order outlined in the NS manual.
1786 * This init procedure is "mandatory"...don't change what or when
1787 * things happen.
1788 */
1789 s = splimp();
1790
1791 /* reset transmitter flags */
1792 sc->xmit_busy = 0;
1793 ifp->if_timer = 0;
1794
1795 sc->txb_inuse = 0;
1796 sc->txb_new = 0;
1797 sc->txb_next_tx = 0;
1798
1799 /* This variable is used below - don't move this assignment */
1800 sc->next_packet = sc->rec_page_start + 1;
1801
1802 /*
1803 * Set interface for page 0, Remote DMA complete, Stopped
1804 */
1805 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1806
1807 if (sc->isa16bit) {
1808
1809 /*
1810 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1811 * order=80x86, word-wide DMA xfers,
1812 */
1813 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1814 } else {
1815
1816 /*
1817 * Same as above, but byte-wide DMA xfers
1818 */
1819 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1820 }
1821
1822 /*
1823 * Clear Remote Byte Count Registers
1824 */
1825 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1826 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1827
1828 /*
1829 * For the moment, don't store incoming packets in memory.
1830 */
1831 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1832
1833 /*
1834 * Place NIC in internal loopback mode
1835 */
1836 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1837
1838 /*
1839 * Initialize transmit/receive (ring-buffer) Page Start
1840 */
1841 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1842 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1843 /* Set lower bits of byte addressable framing to 0 */
1844 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1845 ed_nic_outb(sc, 0x09, 0);
1846
1847 /*
1848 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1849 */
1850 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1851 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1852
1853 /*
1854 * Clear all interrupts. A '1' in each bit position clears the
1855 * corresponding flag.
1856 */
1857 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1858
1859 /*
1860 * Enable the following interrupts: receive/transmit complete,
1861 * receive/transmit error, and Receiver OverWrite.
1862 *
1863 * Counter overflow and Remote DMA complete are *not* enabled.
1864 */
1865 ed_nic_outb(sc, ED_P0_IMR,
1866 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1867
1868 /*
1869 * Program Command Register for page 1
1870 */
1871 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1872
1873 /*
1874 * Copy out our station address
1875 */
1876 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1877 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1878
1879 /*
1880 * Set Current Page pointer to next_packet (initialized above)
1881 */
1882 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1883
1884 /*
1885 * Program Receiver Configuration Register and multicast filter. CR is
1886 * set to page 0 on return.
1887 */
1888 ed_setrcr(sc);
1889
1890 /*
1891 * Take interface out of loopback
1892 */
1893 ed_nic_outb(sc, ED_P0_TCR, 0);
1894
1895 /*
1896 * If this is a 3Com board, the tranceiver must be software enabled
1897 * (there is no settable hardware default).
1898 */
1899 if (sc->vendor == ED_VENDOR_3COM) {
1900 if (ifp->if_flags & IFF_ALTPHYS) {
1901 ed_asic_outb(sc, ED_3COM_CR, 0);
1902 } else {
1903 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1904 }
1905 }
1906
1907#ifndef ED_NO_MIIBUS
1908 if (sc->miibus != NULL) {
1909 struct mii_data *mii;
1910 mii = device_get_softc(sc->miibus);
1911 mii_mediachg(mii);
1912 }
1913#endif
1914 /*
1915 * Set 'running' flag, and clear output active flag.
1916 */
1917 ifp->if_flags |= IFF_RUNNING;
1918 ifp->if_flags &= ~IFF_OACTIVE;
1919
1920 /*
1921 * ...and attempt to start output
1922 */
1923 ed_start(ifp);
1924
1925#ifndef ED_NO_MIIBUS
1926 untimeout(ed_tick, sc, sc->tick_ch);
1927 sc->tick_ch = timeout(ed_tick, sc, hz);
1928#endif
1929 (void) splx(s);
1930}
1931
1932/*
1933 * This routine actually starts the transmission on the interface
1934 */
1935static __inline void
1936ed_xmit(sc)
1937 struct ed_softc *sc;
1938{
1939 struct ifnet *ifp = (struct ifnet *)sc;
1940 unsigned short len;
1941
1942 if (sc->gone)
1943 return;
1944 len = sc->txb_len[sc->txb_next_tx];
1945
1946 /*
1947 * Set NIC for page 0 register access
1948 */
1949 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1950
1951 /*
1952 * Set TX buffer start page
1953 */
1954 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
1955 sc->txb_next_tx * ED_TXBUF_SIZE);
1956
1957 /*
1958 * Set TX length
1959 */
1960 ed_nic_outb(sc, ED_P0_TBCR0, len);
1961 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
1962
1963 /*
1964 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1965 */
1966 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
1967 sc->xmit_busy = 1;
1968
1969 /*
1970 * Point to next transmit buffer slot and wrap if necessary.
1971 */
1972 sc->txb_next_tx++;
1973 if (sc->txb_next_tx == sc->txb_cnt)
1974 sc->txb_next_tx = 0;
1975
1976 /*
1977 * Set a timer just in case we never hear from the board again
1978 */
1979 ifp->if_timer = 2;
1980}
1981
1982/*
1983 * Start output on interface.
1984 * We make two assumptions here:
1985 * 1) that the current priority is set to splimp _before_ this code
1986 * is called *and* is returned to the appropriate priority after
1987 * return
1988 * 2) that the IFF_OACTIVE flag is checked before this code is called
1989 * (i.e. that the output part of the interface is idle)
1990 */
1991static void
1992ed_start(ifp)
1993 struct ifnet *ifp;
1994{
1995 struct ed_softc *sc = ifp->if_softc;
1996 struct mbuf *m0, *m;
1997 caddr_t buffer;
1998 int len;
1999
2000 if (sc->gone) {
2001 printf("ed_start(%p) GONE\n",ifp);
2002 return;
2003 }
2004outloop:
2005
2006 /*
2007 * First, see if there are buffered packets and an idle transmitter -
2008 * should never happen at this point.
2009 */
2010 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2011 printf("ed: packets buffered, but transmitter idle\n");
2012 ed_xmit(sc);
2013 }
2014
2015 /*
2016 * See if there is room to put another packet in the buffer.
2017 */
2018 if (sc->txb_inuse == sc->txb_cnt) {
2019
2020 /*
2021 * No room. Indicate this to the outside world and exit.
2022 */
2023 ifp->if_flags |= IFF_OACTIVE;
2024 return;
2025 }
2026 IF_DEQUEUE(&ifp->if_snd, m);
2027 if (m == 0) {
2028
2029 /*
2030 * We are using the !OACTIVE flag to indicate to the outside
2031 * world that we can accept an additional packet rather than
2032 * that the transmitter is _actually_ active. Indeed, the
2033 * transmitter may be active, but if we haven't filled all the
2034 * buffers with data then we still want to accept more.
2035 */
2036 ifp->if_flags &= ~IFF_OACTIVE;
2037 return;
2038 }
2039
2040 /*
2041 * Copy the mbuf chain into the transmit buffer
2042 */
2043
2044 m0 = m;
2045
2046 /* txb_new points to next open buffer slot */
2047 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2048
2049 if (sc->mem_shared) {
2050
2051 /*
2052 * Special case setup for 16 bit boards...
2053 */
2054 if (sc->isa16bit) {
2055 switch (sc->vendor) {
2056
2057 /*
2058 * For 16bit 3Com boards (which have 16k of
2059 * memory), we have the xmit buffers in a
2060 * different page of memory ('page 0') - so
2061 * change pages.
2062 */
2063 case ED_VENDOR_3COM:
2064 ed_asic_outb(sc, ED_3COM_GACFR,
2065 ED_3COM_GACFR_RSEL);
2066 break;
2067
2068 /*
2069 * Enable 16bit access to shared memory on
2070 * WD/SMC boards.
2071 */
2072 case ED_VENDOR_WD_SMC:
2073 ed_asic_outb(sc, ED_WD_LAAR,
2074 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2075 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2076 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2077 }
2078 break;
2079 }
2080 }
2081 for (len = 0; m != 0; m = m->m_next) {
2082 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2083 buffer += m->m_len;
2084 len += m->m_len;
2085 }
2086
2087 /*
2088 * Restore previous shared memory access
2089 */
2090 if (sc->isa16bit) {
2091 switch (sc->vendor) {
2092 case ED_VENDOR_3COM:
2093 ed_asic_outb(sc, ED_3COM_GACFR,
2094 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2095 break;
2096 case ED_VENDOR_WD_SMC:
2097 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2098 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2099 }
2100 ed_asic_outb(sc, ED_WD_LAAR,
2101 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2102 break;
2103 }
2104 }
2105 } else {
2106 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2107 if (len == 0) {
2108 m_freem(m0);
2109 goto outloop;
2110 }
2111 }
2112
2113 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2114
2115 sc->txb_inuse++;
2116
2117 /*
2118 * Point to next buffer slot and wrap if necessary.
2119 */
2120 sc->txb_new++;
2121 if (sc->txb_new == sc->txb_cnt)
2122 sc->txb_new = 0;
2123
2124 if (sc->xmit_busy == 0)
2125 ed_xmit(sc);
2126
2127 /*
2128 * Tap off here if there is a bpf listener.
2129 */
2130 BPF_MTAP(ifp, m0);
2131
2132 m_freem(m0);
2133
2134 /*
2135 * Loop back to the top to possibly buffer more packets
2136 */
2137 goto outloop;
2138}
2139
2140/*
2141 * Ethernet interface receiver interrupt.
2142 */
2143static __inline void
2144ed_rint(sc)
2145 struct ed_softc *sc;
2146{
2147 struct ifnet *ifp = &sc->arpcom.ac_if;
2148 u_char boundry;
2149 u_short len;
2150 struct ed_ring packet_hdr;
2151 char *packet_ptr;
2152
2153 if (sc->gone)
2154 return;
2155
2156 /*
2157 * Set NIC to page 1 registers to get 'current' pointer
2158 */
2159 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2160
2161 /*
2162 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2163 * i.e. it points to where new data has been buffered. The 'CURR'
2164 * (current) register points to the logical end of the ring-buffer -
2165 * i.e. it points to where additional new data will be added. We loop
2166 * here until the logical beginning equals the logical end (or in
2167 * other words, until the ring-buffer is empty).
2168 */
2169 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2170
2171 /* get pointer to this buffer's header structure */
2172 packet_ptr = sc->mem_ring +
2173 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2174
2175 /*
2176 * The byte count includes a 4 byte header that was added by
2177 * the NIC.
2178 */
2179 if (sc->mem_shared)
2180 packet_hdr = *(struct ed_ring *) packet_ptr;
2181 else
2182 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2183 sizeof(packet_hdr));
2184 len = packet_hdr.count;
2185 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2186 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2187 /*
2188 * Length is a wild value. There's a good chance that
2189 * this was caused by the NIC being old and buggy.
2190 * The bug is that the length low byte is duplicated in
2191 * the high byte. Try to recalculate the length based on
2192 * the pointer to the next packet.
2193 */
2194 /*
2195 * NOTE: sc->next_packet is pointing at the current packet.
2196 */
2197 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2198 if (packet_hdr.next_packet >= sc->next_packet) {
2199 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2200 } else {
2201 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2202 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2203 }
2204 /*
2205 * because buffers are aligned on 256-byte boundary,
2206 * the length computed above is off by 256 in almost
2207 * all cases. Fix it...
2208 */
2209 if (len & 0xff)
2210 len -= 256 ;
2211 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2212 + sizeof(struct ed_ring)))
2213 sc->mibdata.dot3StatsFrameTooLongs++;
2214 }
2215 /*
2216 * Be fairly liberal about what we allow as a "reasonable" length
2217 * so that a [crufty] packet will make it to BPF (and can thus
2218 * be analyzed). Note that all that is really important is that
2219 * we have a length that will fit into one mbuf cluster or less;
2220 * the upper layer protocols can then figure out the length from
2221 * their own length field(s).
2222 * But make sure that we have at least a full ethernet header
2223 * or we would be unable to call ether_input() later.
2224 */
2225 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2226 (len <= MCLBYTES) &&
2227 (packet_hdr.next_packet >= sc->rec_page_start) &&
2228 (packet_hdr.next_packet < sc->rec_page_stop)) {
2229 /*
2230 * Go get packet.
2231 */
2232 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2233 len - sizeof(struct ed_ring));
2234 ifp->if_ipackets++;
2235 } else {
2236 /*
2237 * Really BAD. The ring pointers are corrupted.
2238 */
2239 log(LOG_ERR,
2240 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2241 ifp->if_unit, len);
2242 ifp->if_ierrors++;
2243 ed_reset(ifp);
2244 return;
2245 }
2246
2247 /*
2248 * Update next packet pointer
2249 */
2250 sc->next_packet = packet_hdr.next_packet;
2251
2252 /*
2253 * Update NIC boundry pointer - being careful to keep it one
2254 * buffer behind. (as recommended by NS databook)
2255 */
2256 boundry = sc->next_packet - 1;
2257 if (boundry < sc->rec_page_start)
2258 boundry = sc->rec_page_stop - 1;
2259
2260 /*
2261 * Set NIC to page 0 registers to update boundry register
2262 */
2263 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2264
2265 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2266
2267 /*
2268 * Set NIC to page 1 registers before looping to top (prepare
2269 * to get 'CURR' current pointer)
2270 */
2271 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2272 }
2273}
2274
2275/*
2276 * Ethernet interface interrupt processor
2277 */
2278void
2279edintr(arg)
2280 void *arg;
2281{
2282 struct ed_softc *sc = (struct ed_softc*) arg;
2283 struct ifnet *ifp = (struct ifnet *)sc;
2284 u_char isr;
2285 int count;
2286
2287 if (sc->gone)
2288 return;
2289 /*
2290 * Set NIC to page 0 registers
2291 */
2292 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2293
2294 /*
2295 * loop until there are no more new interrupts. When the card
2296 * goes away, the hardware will read back 0xff. Looking at
2297 * the interrupts, it would appear that 0xff is impossible,
2298 * or at least extremely unlikely.
2299 */
2300 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
2301
2302 /*
2303 * reset all the bits that we are 'acknowledging' by writing a
2304 * '1' to each bit position that was set (writing a '1'
2305 * *clears* the bit)
2306 */
2307 ed_nic_outb(sc, ED_P0_ISR, isr);
2308
2309 /*
2310 * XXX workaround for AX88190
2311 * We limit this to 5000 iterations. At 1us per inb/outb,
2312 * this translates to about 15ms, which should be plenty
2313 * of time, and also gives protection in the card eject
2314 * case.
2315 */
2316 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2317 count = 5000; /* 15ms */
2318 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
2319 ed_nic_outb(sc, ED_P0_ISR,0);
2320 ed_nic_outb(sc, ED_P0_ISR,isr);
2321 }
2322 if (count == 0)
2323 break;
2324 }
2325
2326 /*
2327 * Handle transmitter interrupts. Handle these first because
2328 * the receiver will reset the board under some conditions.
2329 */
2330 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2331 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2332
2333 /*
2334 * Check for transmit error. If a TX completed with an
2335 * error, we end up throwing the packet away. Really
2336 * the only error that is possible is excessive
2337 * collisions, and in this case it is best to allow
2338 * the automatic mechanisms of TCP to backoff the
2339 * flow. Of course, with UDP we're screwed, but this
2340 * is expected when a network is heavily loaded.
2341 */
2342 (void) ed_nic_inb(sc, ED_P0_TSR);
2343 if (isr & ED_ISR_TXE) {
2344 u_char tsr;
2345
2346 /*
2347 * Excessive collisions (16)
2348 */
2349 tsr = ed_nic_inb(sc, ED_P0_TSR);
2350 if ((tsr & ED_TSR_ABT)
2351 && (collisions == 0)) {
2352
2353 /*
2354 * When collisions total 16, the
2355 * P0_NCR will indicate 0, and the
2356 * TSR_ABT is set.
2357 */
2358 collisions = 16;
2359 sc->mibdata.dot3StatsExcessiveCollisions++;
2360 sc->mibdata.dot3StatsCollFrequencies[15]++;
2361 }
2362 if (tsr & ED_TSR_OWC)
2363 sc->mibdata.dot3StatsLateCollisions++;
2364 if (tsr & ED_TSR_CDH)
2365 sc->mibdata.dot3StatsSQETestErrors++;
2366 if (tsr & ED_TSR_CRS)
2367 sc->mibdata.dot3StatsCarrierSenseErrors++;
2368 if (tsr & ED_TSR_FU)
2369 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2370
2371 /*
2372 * update output errors counter
2373 */
2374 ifp->if_oerrors++;
2375 } else {
2376
2377 /*
2378 * Update total number of successfully
2379 * transmitted packets.
2380 */
2381 ifp->if_opackets++;
2382 }
2383
2384 /*
2385 * reset tx busy and output active flags
2386 */
2387 sc->xmit_busy = 0;
2388 ifp->if_flags &= ~IFF_OACTIVE;
2389
2390 /*
2391 * clear watchdog timer
2392 */
2393 ifp->if_timer = 0;
2394
2395 /*
2396 * Add in total number of collisions on last
2397 * transmission.
2398 */
2399 ifp->if_collisions += collisions;
2400 switch(collisions) {
2401 case 0:
2402 case 16:
2403 break;
2404 case 1:
2405 sc->mibdata.dot3StatsSingleCollisionFrames++;
2406 sc->mibdata.dot3StatsCollFrequencies[0]++;
2407 break;
2408 default:
2409 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2410 sc->mibdata.
2411 dot3StatsCollFrequencies[collisions-1]
2412 ++;
2413 break;
2414 }
2415
2416 /*
2417 * Decrement buffer in-use count if not zero (can only
2418 * be zero if a transmitter interrupt occured while
2419 * not actually transmitting). If data is ready to
2420 * transmit, start it transmitting, otherwise defer
2421 * until after handling receiver
2422 */
2423 if (sc->txb_inuse && --sc->txb_inuse)
2424 ed_xmit(sc);
2425 }
2426
2427 /*
2428 * Handle receiver interrupts
2429 */
2430 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2431
2432 /*
2433 * Overwrite warning. In order to make sure that a
2434 * lockup of the local DMA hasn't occurred, we reset
2435 * and re-init the NIC. The NSC manual suggests only a
2436 * partial reset/re-init is necessary - but some chips
2437 * seem to want more. The DMA lockup has been seen
2438 * only with early rev chips - Methinks this bug was
2439 * fixed in later revs. -DG
2440 */
2441 if (isr & ED_ISR_OVW) {
2442 ifp->if_ierrors++;
2443#ifdef DIAGNOSTIC
2444 log(LOG_WARNING,
2445 "ed%d: warning - receiver ring buffer overrun\n",
2446 ifp->if_unit);
2447#endif
2448
2449 /*
2450 * Stop/reset/re-init NIC
2451 */
2452 ed_reset(ifp);
2453 } else {
2454
2455 /*
2456 * Receiver Error. One or more of: CRC error,
2457 * frame alignment error FIFO overrun, or
2458 * missed packet.
2459 */
2460 if (isr & ED_ISR_RXE) {
2461 u_char rsr;
2462 rsr = ed_nic_inb(sc, ED_P0_RSR);
2463 if (rsr & ED_RSR_CRC)
2464 sc->mibdata.dot3StatsFCSErrors++;
2465 if (rsr & ED_RSR_FAE)
2466 sc->mibdata.dot3StatsAlignmentErrors++;
2467 if (rsr & ED_RSR_FO)
2468 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2469 ifp->if_ierrors++;
2470#ifdef ED_DEBUG
2471 if_printf(ifp, "receive error %x\n",
2472 ed_nic_inb(sc, ED_P0_RSR));
2473#endif
2474 }
2475
2476 /*
2477 * Go get the packet(s) XXX - Doing this on an
2478 * error is dubious because there shouldn't be
2479 * any data to get (we've configured the
2480 * interface to not accept packets with
2481 * errors).
2482 */
2483
2484 /*
2485 * Enable 16bit access to shared memory first
2486 * on WD/SMC boards.
2487 */
2488 if (sc->isa16bit &&
2489 (sc->vendor == ED_VENDOR_WD_SMC)) {
2490
2491 ed_asic_outb(sc, ED_WD_LAAR,
2492 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2493 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2494 ed_asic_outb(sc, ED_WD_MSR,
2495 ED_WD_MSR_MENB);
2496 }
2497 }
2498 ed_rint(sc);
2499
2500 /* disable 16bit access */
2501 if (sc->isa16bit &&
2502 (sc->vendor == ED_VENDOR_WD_SMC)) {
2503
2504 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2505 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2506 }
2507 ed_asic_outb(sc, ED_WD_LAAR,
2508 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2509 }
2510 }
2511 }
2512
2513 /*
2514 * If it looks like the transmitter can take more data,
2515 * attempt to start output on the interface. This is done
2516 * after handling the receiver to give the receiver priority.
2517 */
2518 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2519 ed_start(ifp);
2520
2521 /*
2522 * return NIC CR to standard state: page 0, remote DMA
2523 * complete, start (toggling the TXP bit off, even if was just
2524 * set in the transmit routine, is *okay* - it is 'edge'
2525 * triggered from low to high)
2526 */
2527 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2528
2529 /*
2530 * If the Network Talley Counters overflow, read them to reset
2531 * them. It appears that old 8390's won't clear the ISR flag
2532 * otherwise - resulting in an infinite loop.
2533 */
2534 if (isr & ED_ISR_CNT) {
2535 (void) ed_nic_inb(sc, ED_P0_CNTR0);
2536 (void) ed_nic_inb(sc, ED_P0_CNTR1);
2537 (void) ed_nic_inb(sc, ED_P0_CNTR2);
2538 }
2539 }
2540}
2541
2542/*
2543 * Process an ioctl request. This code needs some work - it looks
2544 * pretty ugly.
2545 */
2546static int
2547ed_ioctl(ifp, command, data)
2548 register struct ifnet *ifp;
2549 u_long command;
2550 caddr_t data;
2551{
2552 struct ed_softc *sc = ifp->if_softc;
2553#ifndef ED_NO_MIIBUS
2554 struct ifreq *ifr = (struct ifreq *)data;
2555 struct mii_data *mii;
2556#endif
2557 int s, error = 0;
2558
2559 if (sc == NULL || sc->gone) {
2560 ifp->if_flags &= ~IFF_RUNNING;
2561 return ENXIO;
2562 }
2563 s = splimp();
2564
2565 switch (command) {
2566 case SIOCSIFFLAGS:
2567
2568 /*
2569 * If the interface is marked up and stopped, then start it.
2570 * If it is marked down and running, then stop it.
2571 */
2572 if (ifp->if_flags & IFF_UP) {
2573 if ((ifp->if_flags & IFF_RUNNING) == 0)
2574 ed_init(sc);
2575 } else {
2576 if (ifp->if_flags & IFF_RUNNING) {
2577 ed_stop(sc);
2578 ifp->if_flags &= ~IFF_RUNNING;
2579 }
2580 }
2581
2582 /*
2583 * Promiscuous flag may have changed, so reprogram the RCR.
2584 */
2585 ed_setrcr(sc);
2586
2587 /*
2588 * An unfortunate hack to provide the (required) software
2589 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2590 * disables the tranceiver if set.
2591 */
2592 if (sc->vendor == ED_VENDOR_3COM) {
2593 if (ifp->if_flags & IFF_ALTPHYS) {
2594 ed_asic_outb(sc, ED_3COM_CR, 0);
2595 } else {
2596 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2597 }
2598 } else if (sc->vendor == ED_VENDOR_HP)
2599 ed_hpp_set_physical_link(sc);
2600 break;
2601
2602 case SIOCADDMULTI:
2603 case SIOCDELMULTI:
2604 /*
2605 * Multicast list has changed; set the hardware filter
2606 * accordingly.
2607 */
2608 ed_setrcr(sc);
2609 error = 0;
2610 break;
2611
2612#ifndef ED_NO_MIIBUS
2613 case SIOCGIFMEDIA:
2614 case SIOCSIFMEDIA:
2615 if (sc->miibus == NULL) {
2616 error = EINVAL;
2617 break;
2618 }
2619 mii = device_get_softc(sc->miibus);
2620 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2621 break;
2622#endif
2623
2624 default:
2625 error = ether_ioctl(ifp, command, data);
2626 }
2627 (void) splx(s);
2628 return (error);
2629}
2630
2631/*
2632 * Given a source and destination address, copy 'amount' of a packet from
2633 * the ring buffer into a linear destination buffer. Takes into account
2634 * ring-wrap.
2635 */
2636static __inline char *
2637ed_ring_copy(sc, src, dst, amount)
2638 struct ed_softc *sc;
2639 char *src;
2640 char *dst;
2641 u_short amount;
2642{
2643 u_short tmp_amount;
2644
2645 /* does copy wrap to lower addr in ring buffer? */
2646 if (src + amount > sc->mem_end) {
2647 tmp_amount = sc->mem_end - src;
2648
2649 /* copy amount up to end of NIC memory */
2650 if (sc->mem_shared)
2651 bcopy(src, dst, tmp_amount);
2652 else
2653 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2654
2655 amount -= tmp_amount;
2656 src = sc->mem_ring;
2657 dst += tmp_amount;
2658 }
2659 if (sc->mem_shared)
2660 bcopy(src, dst, amount);
2661 else
2662 ed_pio_readmem(sc, (int)src, dst, amount);
2663
2664 return (src + amount);
2665}
2666
2667/*
2668 * Retreive packet from shared memory and send to the next level up via
2669 * ether_input().
2670 */
2671static void
2672ed_get_packet(sc, buf, len)
2673 struct ed_softc *sc;
2674 char *buf;
2675 u_short len;
2676{
2677 struct ifnet *ifp = &sc->arpcom.ac_if;
2678 struct ether_header *eh;
2679 struct mbuf *m;
2680
2681 /* Allocate a header mbuf */
2682 MGETHDR(m, M_DONTWAIT, MT_DATA);
2683 if (m == NULL)
2684 return;
2685 m->m_pkthdr.rcvif = ifp;
2686 m->m_pkthdr.len = m->m_len = len;
2687
2688 /*
2689 * We always put the received packet in a single buffer -
2690 * either with just an mbuf header or in a cluster attached
2691 * to the header. The +2 is to compensate for the alignment
2692 * fixup below.
2693 */
2694 if ((len + 2) > MHLEN) {
2695 /* Attach an mbuf cluster */
2696 MCLGET(m, M_DONTWAIT);
2697
2698 /* Insist on getting a cluster */
2699 if ((m->m_flags & M_EXT) == 0) {
2700 m_freem(m);
2701 return;
2702 }
2703 }
2704
2705 /*
2706 * The +2 is to longword align the start of the real packet.
2707 * This is important for NFS.
2708 */
2709 m->m_data += 2;
2710 eh = mtod(m, struct ether_header *);
2711
2712 /*
2713 * Don't read in the entire packet if we know we're going to drop it
2714 * and no bpf is active.
2715 */
2716 if (!ifp->if_bpf && BDG_ACTIVE( (ifp) ) ) {
2717 struct ifnet *bif;
2718
2719 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
2720 bif = bridge_in_ptr(ifp, eh) ;
2721 if (bif == BDG_DROP) {
2722 m_freem(m);
2723 return;
2724 }
2725 if (len > ETHER_HDR_LEN)
2726 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2727 (char *)(eh + 1), len - ETHER_HDR_LEN);
2728 } else
2729 /*
2730 * Get packet, including link layer address, from interface.
2731 */
2732 ed_ring_copy(sc, buf, (char *)eh, len);
2733
2734 m->m_pkthdr.len = m->m_len = len;
2735
2736 (*ifp->if_input)(ifp, m);
2737}
2738
2739/*
2740 * Supporting routines
2741 */
2742
2743/*
2744 * Given a NIC memory source address and a host memory destination
2745 * address, copy 'amount' from NIC to host using Programmed I/O.
2746 * The 'amount' is rounded up to a word - okay as long as mbufs
2747 * are word sized.
2748 * This routine is currently Novell-specific.
2749 */
2750void
2751ed_pio_readmem(sc, src, dst, amount)
2752 struct ed_softc *sc;
2753 int src;
2754 unsigned char *dst;
2755 unsigned short amount;
2756{
2757 /* HP PC Lan+ cards need special handling */
2758 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2759 ed_hpp_readmem(sc, src, dst, amount);
2760 return;
2761 }
2762
2763 /* Regular Novell cards */
2764 /* select page 0 registers */
2765 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2766
2767 /* round up to a word */
2768 if (amount & 1)
2769 ++amount;
2770
2771 /* set up DMA byte count */
2772 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2773 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2774
2775 /* set up source address in NIC mem */
2776 ed_nic_outb(sc, ED_P0_RSAR0, src);
2777 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2778
2779 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2780
2781 if (sc->isa16bit) {
2782 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2783 } else {
2784 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2785 }
2786}
2787
2788/*
2789 * Stripped down routine for writing a linear buffer to NIC memory.
2790 * Only used in the probe routine to test the memory. 'len' must
2791 * be even.
2792 */
2793void
2794ed_pio_writemem(sc, src, dst, len)
2795 struct ed_softc *sc;
2796 char *src;
2797 unsigned short dst;
2798 unsigned short len;
2799{
2800 int maxwait = 200; /* about 240us */
2801
2802 /* select page 0 registers */
2803 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2804
2805 /* reset remote DMA complete flag */
2806 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2807
2808 /* set up DMA byte count */
2809 ed_nic_outb(sc, ED_P0_RBCR0, len);
2810 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2811
2812 /* set up destination address in NIC mem */
2813 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2814 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2815
2816 /* set remote DMA write */
2817 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2818
2819 if (sc->isa16bit) {
2820 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2821 } else {
2822 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2823 }
2824
2825 /*
2826 * Wait for remote DMA complete. This is necessary because on the
2827 * transmit side, data is handled internally by the NIC in bursts and
2828 * we can't start another remote DMA until this one completes. Not
2829 * waiting causes really bad things to happen - like the NIC
2830 * irrecoverably jamming the ISA bus.
2831 */
2832 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2833}
2834
2835/*
2836 * Write an mbuf chain to the destination NIC memory address using
2837 * programmed I/O.
2838 */
2839static u_short
2840ed_pio_write_mbufs(sc, m, dst)
2841 struct ed_softc *sc;
2842 struct mbuf *m;
2843 int dst;
2844{
2845 struct ifnet *ifp = (struct ifnet *)sc;
2846 unsigned short total_len, dma_len;
2847 struct mbuf *mp;
2848 int maxwait = 200; /* about 240us */
2849
2850 /* HP PC Lan+ cards need special handling */
2851 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2852 return ed_hpp_write_mbufs(sc, m, dst);
2853 }
2854
2855 /* Regular Novell cards */
2856 /* First, count up the total number of bytes to copy */
2857 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2858 total_len += mp->m_len;
2859
2860 dma_len = total_len;
2861 if (sc->isa16bit && (dma_len & 1))
2862 dma_len++;
2863
2864 /* select page 0 registers */
2865 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2866
2867 /* reset remote DMA complete flag */
2868 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2869
2870 /* set up DMA byte count */
2871 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2872 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2873
2874 /* set up destination address in NIC mem */
2875 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2876 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2877
2878 /* set remote DMA write */
2879 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2880
2881 /*
2882 * Transfer the mbuf chain to the NIC memory.
2883 * 16-bit cards require that data be transferred as words, and only words.
2884 * So that case requires some extra code to patch over odd-length mbufs.
2885 */
2886
2887 if (!sc->isa16bit) {
2888 /* NE1000s are easy */
2889 while (m) {
2890 if (m->m_len) {
2891 ed_asic_outsb(sc, ED_NOVELL_DATA,
2892 m->m_data, m->m_len);
2893 }
2894 m = m->m_next;
2895 }
2896 } else {
2897 /* NE2000s are a pain */
2898 unsigned char *data;
2899 int len, wantbyte;
2900 unsigned char savebyte[2];
2901
2902 wantbyte = 0;
2903
2904 while (m) {
2905 len = m->m_len;
2906 if (len) {
2907 data = mtod(m, caddr_t);
2908 /* finish the last word */
2909 if (wantbyte) {
2910 savebyte[1] = *data;
2911 ed_asic_outw(sc, ED_NOVELL_DATA,
2912 *(u_short *)savebyte);
2913 data++;
2914 len--;
2915 wantbyte = 0;
2916 }
2917 /* output contiguous words */
2918 if (len > 1) {
2919 ed_asic_outsw(sc, ED_NOVELL_DATA,
2920 data, len >> 1);
2921 data += len & ~1;
2922 len &= 1;
2923 }
2924 /* save last byte, if necessary */
2925 if (len == 1) {
2926 savebyte[0] = *data;
2927 wantbyte = 1;
2928 }
2929 }
2930 m = m->m_next;
2931 }
2932 /* spit last byte */
2933 if (wantbyte) {
2934 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
2935 }
2936 }
2937
2938 /*
2939 * Wait for remote DMA complete. This is necessary because on the
2940 * transmit side, data is handled internally by the NIC in bursts and
2941 * we can't start another remote DMA until this one completes. Not
2942 * waiting causes really bad things to happen - like the NIC
2943 * irrecoverably jamming the ISA bus.
2944 */
2945 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2946
2947 if (!maxwait) {
2948 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2949 ifp->if_unit);
2950 ed_reset(ifp);
2951 return(0);
2952 }
2953 return (total_len);
2954}
2955
2956/*
2957 * Support routines to handle the HP PC Lan+ card.
2958 */
2959
2960/*
2961 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2962 * IO.
2963 */
2964
2965static void
2966ed_hpp_readmem(sc, src, dst, amount)
2967 struct ed_softc *sc;
2968 unsigned short src;
2969 unsigned char *dst;
2970 unsigned short amount;
2971{
2972
2973 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
2974
2975
2976 /* Program the source address in RAM */
2977 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
2978
2979 /*
2980 * The HP PC Lan+ card supports word reads as well as
2981 * a memory mapped i/o port that is aliased to every
2982 * even address on the board.
2983 */
2984
2985 if (sc->hpp_mem_start) {
2986
2987 /* Enable memory mapped access. */
2988 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
2989 ~(ED_HPP_OPTION_MEM_DISABLE |
2990 ED_HPP_OPTION_BOOT_ROM_ENB));
2991
2992 if (use_32bit_access && (amount > 3)) {
2993 u_int32_t *dl = (u_int32_t *) dst;
2994 volatile u_int32_t *const sl =
2995 (u_int32_t *) sc->hpp_mem_start;
2996 u_int32_t *const fence = dl + (amount >> 2);
2997
2998 /* Copy out NIC data. We could probably write this
2999 as a `movsl'. The currently generated code is lousy.
3000 */
3001
3002 while (dl < fence)
3003 *dl++ = *sl;
3004
3005 dst += (amount & ~3);
3006 amount &= 3;
3007
3008 }
3009
3010 /* Finish off any words left, as a series of short reads */
3011 if (amount > 1) {
3012 u_short *d = (u_short *) dst;
3013 volatile u_short *const s =
3014 (u_short *) sc->hpp_mem_start;
3015 u_short *const fence = d + (amount >> 1);
3016
3017 /* Copy out NIC data. */
3018
3019 while (d < fence)
3020 *d++ = *s;
3021
3022 dst += (amount & ~1);
3023 amount &= 1;
3024 }
3025
3026 /*
3027 * read in a byte; however we need to always read 16 bits
3028 * at a time or the hardware gets into a funny state
3029 */
3030
3031 if (amount == 1) {
3032 /* need to read in a short and copy LSB */
3033 volatile u_short *const s =
3034 (volatile u_short *) sc->hpp_mem_start;
3035
3036 *dst = (*s) & 0xFF;
3037 }
3038
3039 /* Restore Boot ROM access. */
3040
3041 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3042
3043
3044 } else {
3045 /* Read in data using the I/O port */
3046 if (use_32bit_access && (amount > 3)) {
3047 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3048 dst += (amount & ~3);
3049 amount &= 3;
3050 }
3051 if (amount > 1) {
3052 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3053 dst += (amount & ~1);
3054 amount &= 1;
3055 }
3056 if (amount == 1) { /* read in a short and keep the LSB */
3057 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3058 }
3059 }
3060}
3061
3062/*
3063 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3064 * IO.
3065 * Only used in the probe routine to test the memory. 'len' must
3066 * be even.
3067 */
3068static void
3069ed_hpp_writemem(sc, src, dst, len)
3070 struct ed_softc *sc;
3071 unsigned char *src;
3072 unsigned short dst;
3073 unsigned short len;
3074{
3075 /* reset remote DMA complete flag */
3076 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3077
3078 /* program the write address in RAM */
3079 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3080
3081 if (sc->hpp_mem_start) {
3082 u_short *s = (u_short *) src;
3083 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3084 u_short *const fence = s + (len >> 1);
3085
3086 /*
3087 * Enable memory mapped access.
3088 */
3089
3090 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3091 ~(ED_HPP_OPTION_MEM_DISABLE |
3092 ED_HPP_OPTION_BOOT_ROM_ENB));
3093
3094 /*
3095 * Copy to NIC memory.
3096 */
3097
3098 while (s < fence)
3099 *d = *s++;
3100
3101 /*
3102 * Restore Boot ROM access.
3103 */
3104
3105 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3106
3107 } else {
3108 /* write data using I/O writes */
3109 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3110 }
3111}
3112
3113/*
3114 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3115 * outsw() or via the memory mapped interface to the same register.
3116 * Writes have to be in word units; byte accesses won't work and may cause
3117 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
3118 * allows it.
3119 */
3120
3121static u_short
3122ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3123{
3124 int len, wantbyte;
3125 unsigned short total_len;
3126 unsigned char savebyte[2];
3127 volatile u_short * const d =
3128 (volatile u_short *) sc->hpp_mem_start;
3129 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3130
3131 /* select page 0 registers */
3132 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3133
3134 /* reset remote DMA complete flag */
3135 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3136
3137 /* program the write address in RAM */
3138 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3139
3140 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3141 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3142 ~(ED_HPP_OPTION_MEM_DISABLE |
3143 ED_HPP_OPTION_BOOT_ROM_ENB));
3144
3145 wantbyte = 0;
3146 total_len = 0;
3147
3148 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3149 while (m) {
3150 total_len += (len = m->m_len);
3151 if (len) {
3152 caddr_t data = mtod(m, caddr_t);
3153 /* finish the last word of the previous mbuf */
3154 if (wantbyte) {
3155 savebyte[1] = *data;
| 28 */
29
30/*
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
33 *
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
37 *
38 */
39
40#include "opt_ed.h"
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/sockio.h>
45#include <sys/mbuf.h>
46#include <sys/kernel.h>
47#include <sys/socket.h>
48#include <sys/syslog.h>
49
50#include <sys/bus.h>
51
52#include <machine/bus.h>
53#include <sys/rman.h>
54#include <machine/resource.h>
55
56#include <net/ethernet.h>
57#include <net/if.h>
58#include <net/if_arp.h>
59#include <net/if_dl.h>
60#include <net/if_mib.h>
61#include <net/if_media.h>
62
63#ifndef ED_NO_MIIBUS
64#include <dev/mii/mii.h>
65#include <dev/mii/miivar.h>
66#endif
67
68#include <net/bpf.h>
69#include <net/bridge.h>
70
71#include <machine/md_var.h>
72
73#include <dev/ed/if_edreg.h>
74#include <dev/ed/if_edvar.h>
75
76devclass_t ed_devclass;
77
78static void ed_init (void *);
79static int ed_ioctl (struct ifnet *, u_long, caddr_t);
80static void ed_start (struct ifnet *);
81static void ed_reset (struct ifnet *);
82static void ed_watchdog (struct ifnet *);
83#ifndef ED_NO_MIIBUS
84static void ed_tick (void *);
85#endif
86
87static void ds_getmcaf (struct ed_softc *, u_int32_t *);
88
89static void ed_get_packet (struct ed_softc *, char *, /* u_short */ int);
90
91static __inline void ed_rint (struct ed_softc *);
92static __inline void ed_xmit (struct ed_softc *);
93static __inline char * ed_ring_copy(struct ed_softc *, char *, char *,
94 /* u_short */ int);
95static void ed_hpp_set_physical_link(struct ed_softc *);
96static void ed_hpp_readmem (struct ed_softc *, int, unsigned char *,
97 /* u_short */ int);
98static void ed_hpp_writemem (struct ed_softc *, unsigned char *,
99 /* u_short */ int, /* u_short */ int);
100static u_short ed_hpp_write_mbufs(struct ed_softc *, struct mbuf *, int);
101
102static u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, int);
103
104static void ed_setrcr (struct ed_softc *);
105
106static u_int32_t ds_crc (u_char *ep);
107
108/*
109 * Interrupt conversion table for WD/SMC ASIC/83C584
110 */
111static unsigned short ed_intr_val[] = {
112 9,
113 3,
114 5,
115 7,
116 10,
117 11,
118 15,
119 4
120};
121
122/*
123 * Interrupt conversion table for 83C790
124 */
125static unsigned short ed_790_intr_val[] = {
126 0,
127 9,
128 3,
129 5,
130 7,
131 10,
132 11,
133 15
134};
135
136/*
137 * Interrupt conversion table for the HP PC LAN+
138 */
139
140static unsigned short ed_hpp_intr_val[] = {
141 0, /* 0 */
142 0, /* 1 */
143 0, /* 2 */
144 3, /* 3 */
145 4, /* 4 */
146 5, /* 5 */
147 6, /* 6 */
148 7, /* 7 */
149 0, /* 8 */
150 9, /* 9 */
151 10, /* 10 */
152 11, /* 11 */
153 12, /* 12 */
154 0, /* 13 */
155 0, /* 14 */
156 15 /* 15 */
157};
158
159/*
160 * Generic probe routine for testing for the existance of a DS8390.
161 * Must be called after the NIC has just been reset. This routine
162 * works by looking at certain register values that are guaranteed
163 * to be initialized a certain way after power-up or reset. Seems
164 * not to currently work on the 83C690.
165 *
166 * Specifically:
167 *
168 * Register reset bits set bits
169 * Command Register (CR) TXP, STA RD2, STP
170 * Interrupt Status (ISR) RST
171 * Interrupt Mask (IMR) All bits
172 * Data Control (DCR) LAS
173 * Transmit Config. (TCR) LB1, LB0
174 *
175 * We only look at the CR and ISR registers, however, because looking at
176 * the others would require changing register pages (which would be
177 * intrusive if this isn't an 8390).
178 *
179 * Return 1 if 8390 was found, 0 if not.
180 */
181
182int
183ed_probe_generic8390(sc)
184 struct ed_softc *sc;
185{
186 if ((ed_nic_inb(sc, ED_P0_CR) &
187 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
188 (ED_CR_RD2 | ED_CR_STP))
189 return (0);
190 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
191 return (0);
192
193 return (1);
194}
195
196/*
197 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
198 */
199int
200ed_probe_WD80x3_generic(dev, flags, intr_vals)
201 device_t dev;
202 int flags;
203 unsigned short *intr_vals[];
204{
205 struct ed_softc *sc = device_get_softc(dev);
206 int error;
207 int i;
208 u_int memsize, maddr;
209 u_char iptr, isa16bit, sum, totalsum;
210 u_long conf_maddr, conf_msize, irq, junk;
211
212 sc->chip_type = ED_CHIP_TYPE_DP8390;
213
214 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
215 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
216 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
217 DELAY(10000);
218 }
219 else
220 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
221
222 /*
223 * Attempt to do a checksum over the station address PROM. If it
224 * fails, it's probably not a SMC/WD board. There is a problem with
225 * this, though: some clone WD boards don't pass the checksum test.
226 * Danpex boards for one.
227 */
228 for (sum = 0, i = 0; i < 8; ++i)
229 sum += ed_asic_inb(sc, ED_WD_PROM + i);
230
231 if (sum != totalsum) {
232
233 /*
234 * Checksum is invalid. This often happens with cheap WD8003E
235 * clones. In this case, the checksum byte (the eighth byte)
236 * seems to always be zero.
237 */
238 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
239 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
240 return (ENXIO);
241 }
242 /* reset card to force it into a known state. */
243 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
244 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
245 else
246 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
247
248 DELAY(100);
249 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
250 /* wait in the case this card is reading its EEROM */
251 DELAY(5000);
252
253 sc->vendor = ED_VENDOR_WD_SMC;
254 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
255
256 /*
257 * Set initial values for width/size.
258 */
259 memsize = 8192;
260 isa16bit = 0;
261 switch (sc->type) {
262 case ED_TYPE_WD8003S:
263 sc->type_str = "WD8003S";
264 break;
265 case ED_TYPE_WD8003E:
266 sc->type_str = "WD8003E";
267 break;
268 case ED_TYPE_WD8003EB:
269 sc->type_str = "WD8003EB";
270 break;
271 case ED_TYPE_WD8003W:
272 sc->type_str = "WD8003W";
273 break;
274 case ED_TYPE_WD8013EBT:
275 sc->type_str = "WD8013EBT";
276 memsize = 16384;
277 isa16bit = 1;
278 break;
279 case ED_TYPE_WD8013W:
280 sc->type_str = "WD8013W";
281 memsize = 16384;
282 isa16bit = 1;
283 break;
284 case ED_TYPE_WD8013EP: /* also WD8003EP */
285 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
286 isa16bit = 1;
287 memsize = 16384;
288 sc->type_str = "WD8013EP";
289 } else {
290 sc->type_str = "WD8003EP";
291 }
292 break;
293 case ED_TYPE_WD8013WC:
294 sc->type_str = "WD8013WC";
295 memsize = 16384;
296 isa16bit = 1;
297 break;
298 case ED_TYPE_WD8013EBP:
299 sc->type_str = "WD8013EBP";
300 memsize = 16384;
301 isa16bit = 1;
302 break;
303 case ED_TYPE_WD8013EPC:
304 sc->type_str = "WD8013EPC";
305 memsize = 16384;
306 isa16bit = 1;
307 break;
308 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
309 case ED_TYPE_SMC8216T:
310 if (sc->type == ED_TYPE_SMC8216C) {
311 sc->type_str = "SMC8216/SMC8216C";
312 } else {
313 sc->type_str = "SMC8216T";
314 }
315
316 ed_asic_outb(sc, ED_WD790_HWR,
317 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
318 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
319 case ED_WD790_RAR_SZ64:
320 memsize = 65536;
321 break;
322 case ED_WD790_RAR_SZ32:
323 memsize = 32768;
324 break;
325 case ED_WD790_RAR_SZ16:
326 memsize = 16384;
327 break;
328 case ED_WD790_RAR_SZ8:
329 /* 8216 has 16K shared mem -- 8416 has 8K */
330 if (sc->type == ED_TYPE_SMC8216C) {
331 sc->type_str = "SMC8416C/SMC8416BT";
332 } else {
333 sc->type_str = "SMC8416T";
334 }
335 memsize = 8192;
336 break;
337 }
338 ed_asic_outb(sc, ED_WD790_HWR,
339 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
340
341 isa16bit = 1;
342 sc->chip_type = ED_CHIP_TYPE_WD790;
343 break;
344 case ED_TYPE_TOSHIBA1:
345 sc->type_str = "Toshiba1";
346 memsize = 32768;
347 isa16bit = 1;
348 break;
349 case ED_TYPE_TOSHIBA4:
350 sc->type_str = "Toshiba4";
351 memsize = 32768;
352 isa16bit = 1;
353 break;
354 default:
355 sc->type_str = "";
356 break;
357 }
358
359 /*
360 * Make some adjustments to initial values depending on what is found
361 * in the ICR.
362 */
363 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
364 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
365 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
366 isa16bit = 0;
367 memsize = 8192;
368 }
369
370 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
371 &conf_maddr, &conf_msize);
372 if (error)
373 return (error);
374
375#if ED_DEBUG
376 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
377 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
378 for (i = 0; i < 8; i++)
379 printf("%x -> %x\n", i, ed_asic_inb(sc, i));
380#endif
381
382 /*
383 * Allow the user to override the autoconfiguration
384 */
385 if (conf_msize > 1)
386 memsize = conf_msize;
387
388 maddr = conf_maddr;
389 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
390 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
391 maddr, maddr + memsize);
392 return (ENXIO);
393 }
394
395 /*
396 * (note that if the user specifies both of the following flags that
397 * '8bit' mode intentionally has precedence)
398 */
399 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
400 isa16bit = 1;
401 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
402 isa16bit = 0;
403
404 /*
405 * If possible, get the assigned interrupt number from the card and
406 * use it.
407 */
408 if ((sc->type & ED_WD_SOFTCONFIG) &&
409 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
410
411 /*
412 * Assemble together the encoded interrupt number.
413 */
414 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
415 ((ed_asic_inb(sc, ED_WD_IRR) &
416 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
417
418 /*
419 * If no interrupt specified (or "?"), use what the board tells us.
420 */
421 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
422 &irq, &junk);
423 if (error && intr_vals[0] != NULL) {
424 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
425 intr_vals[0][iptr], 1);
426 }
427 if (error)
428 return (error);
429
430 /*
431 * Enable the interrupt.
432 */
433 ed_asic_outb(sc, ED_WD_IRR,
434 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
435 }
436 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
437 ed_asic_outb(sc, ED_WD790_HWR,
438 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
439 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
440 (ed_asic_inb(sc, ED_WD790_GCR) &
441 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
442 ed_asic_outb(sc, ED_WD790_HWR,
443 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
444
445 /*
446 * If no interrupt specified (or "?"), use what the board tells us.
447 */
448 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
449 &irq, &junk);
450 if (error && intr_vals[1] != NULL) {
451 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
452 intr_vals[1][iptr], 1);
453 }
454 if (error)
455 return (error);
456
457 /*
458 * Enable interrupts.
459 */
460 ed_asic_outb(sc, ED_WD790_ICR,
461 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
462 }
463 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
464 &irq, &junk);
465 if (error) {
466 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
467 sc->type_str);
468 return (ENXIO);
469 }
470 sc->isa16bit = isa16bit;
471 sc->mem_shared = 1;
472
473 error = ed_alloc_memory(dev, 0, memsize);
474 if (error) {
475 printf("*** ed_alloc_memory() failed! (%d)\n", error);
476 return (error);
477 }
478 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
479
480 /*
481 * allocate one xmit buffer if < 16k, two buffers otherwise
482 */
483 if ((memsize < 16384) ||
484 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
485 sc->txb_cnt = 1;
486 } else {
487 sc->txb_cnt = 2;
488 }
489 sc->tx_page_start = ED_WD_PAGE_OFFSET;
490 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
491 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
492 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
493 sc->mem_size = memsize;
494 sc->mem_end = sc->mem_start + memsize;
495
496 /*
497 * Get station address from on-board ROM
498 */
499 for (i = 0; i < ETHER_ADDR_LEN; ++i)
500 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
501
502 /*
503 * Set upper address bits and 8/16 bit access to shared memory.
504 */
505 if (isa16bit) {
506 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
507 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
508 } else {
509 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
510 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
511 }
512 /*
513 * Enable 16bit access
514 */
515 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
516 ED_WD_LAAR_M16EN);
517 } else {
518 if (((sc->type & ED_WD_SOFTCONFIG) ||
519 (sc->type == ED_TYPE_TOSHIBA1) ||
520 (sc->type == ED_TYPE_TOSHIBA4) ||
521 (sc->type == ED_TYPE_WD8013EBT)) &&
522 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
523 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
524 ED_WD_LAAR_ADDRHI;
525 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
526 }
527 }
528
529 /*
530 * Set address and enable interface shared memory.
531 */
532 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
533 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
534 ed_asic_outb(sc, ED_WD_MSR + 1,
535 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
536 ed_asic_outb(sc, ED_WD_MSR + 2,
537 ((kvtop(sc->mem_start) >> 16) & 0x0f));
538 ed_asic_outb(sc, ED_WD_MSR,
539 ED_WD_MSR_MENB | ED_WD_MSR_POW);
540 } else {
541 ed_asic_outb(sc, ED_WD_MSR,
542 ((kvtop(sc->mem_start) >> 13) &
543 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
544 }
545 sc->cr_proto = ED_CR_RD2;
546 } else {
547 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
548 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
549 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
550 ((kvtop(sc->mem_start) >> 11) & 0x40) |
551 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
552 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
553 sc->cr_proto = 0;
554 }
555
556#if 0
557 printf("starting memory performance test at 0x%x, size %d...\n",
558 sc->mem_start, memsize*16384);
559 for (i = 0; i < 16384; i++)
560 bzero(sc->mem_start, memsize);
561 printf("***DONE***\n");
562#endif
563
564 /*
565 * Now zero memory and verify that it is clear
566 */
567 bzero(sc->mem_start, memsize);
568
569 for (i = 0; i < memsize; ++i) {
570 if (sc->mem_start[i]) {
571 device_printf(dev, "failed to clear shared memory at %jx - check configuration\n",
572 (uintmax_t)kvtop(sc->mem_start + i));
573
574 /*
575 * Disable 16 bit access to shared memory
576 */
577 if (isa16bit) {
578 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
579 ed_asic_outb(sc, ED_WD_MSR, 0x00);
580 }
581 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
582 ~ED_WD_LAAR_M16EN);
583 }
584 return (ENXIO);
585 }
586 }
587
588 /*
589 * Disable 16bit access to shared memory - we leave it
590 * disabled so that 1) machines reboot properly when the board
591 * is set 16 bit mode and there are conflicting 8bit
592 * devices/ROMS in the same 128k address space as this boards
593 * shared memory. and 2) so that other 8 bit devices with
594 * shared memory can be used in this 128k region, too.
595 */
596 if (isa16bit) {
597 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
598 ed_asic_outb(sc, ED_WD_MSR, 0x00);
599 }
600 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
601 ~ED_WD_LAAR_M16EN);
602 }
603 return (0);
604}
605
606int
607ed_probe_WD80x3(dev, port_rid, flags)
608 device_t dev;
609 int port_rid;
610 int flags;
611{
612 struct ed_softc *sc = device_get_softc(dev);
613 int error;
614 static unsigned short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
615
616 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
617 if (error)
618 return (error);
619
620 sc->asic_offset = ED_WD_ASIC_OFFSET;
621 sc->nic_offset = ED_WD_NIC_OFFSET;
622
623 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
624}
625
626/*
627 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
628 */
629int
630ed_probe_3Com(dev, port_rid, flags)
631 device_t dev;
632 int port_rid;
633 int flags;
634{
635 struct ed_softc *sc = device_get_softc(dev);
636 int error;
637 int i;
638 u_int memsize;
639 u_char isa16bit;
640 u_long conf_maddr, conf_msize, irq, junk;
641
642 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
643 if (error)
644 return (error);
645
646 sc->asic_offset = ED_3COM_ASIC_OFFSET;
647 sc->nic_offset = ED_3COM_NIC_OFFSET;
648
649 /*
650 * Verify that the kernel configured I/O address matches the board
651 * configured address
652 */
653 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
654 case ED_3COM_BCFR_300:
655 if (rman_get_start(sc->port_res) != 0x300)
656 return (ENXIO);
657 break;
658 case ED_3COM_BCFR_310:
659 if (rman_get_start(sc->port_res) != 0x310)
660 return (ENXIO);
661 break;
662 case ED_3COM_BCFR_330:
663 if (rman_get_start(sc->port_res) != 0x330)
664 return (ENXIO);
665 break;
666 case ED_3COM_BCFR_350:
667 if (rman_get_start(sc->port_res) != 0x350)
668 return (ENXIO);
669 break;
670 case ED_3COM_BCFR_250:
671 if (rman_get_start(sc->port_res) != 0x250)
672 return (ENXIO);
673 break;
674 case ED_3COM_BCFR_280:
675 if (rman_get_start(sc->port_res) != 0x280)
676 return (ENXIO);
677 break;
678 case ED_3COM_BCFR_2A0:
679 if (rman_get_start(sc->port_res) != 0x2a0)
680 return (ENXIO);
681 break;
682 case ED_3COM_BCFR_2E0:
683 if (rman_get_start(sc->port_res) != 0x2e0)
684 return (ENXIO);
685 break;
686 default:
687 return (ENXIO);
688 }
689
690 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
691 &conf_maddr, &conf_msize);
692 if (error)
693 return (error);
694
695 /*
696 * Verify that the kernel shared memory address matches the board
697 * configured address.
698 */
699 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
700 case ED_3COM_PCFR_DC000:
701 if (conf_maddr != 0xdc000)
702 return (ENXIO);
703 break;
704 case ED_3COM_PCFR_D8000:
705 if (conf_maddr != 0xd8000)
706 return (ENXIO);
707 break;
708 case ED_3COM_PCFR_CC000:
709 if (conf_maddr != 0xcc000)
710 return (ENXIO);
711 break;
712 case ED_3COM_PCFR_C8000:
713 if (conf_maddr != 0xc8000)
714 return (ENXIO);
715 break;
716 default:
717 return (ENXIO);
718 }
719
720
721 /*
722 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
723 * sequence because it'll lock up if the cable isn't connected if we
724 * don't.
725 */
726 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
727
728 /*
729 * Wait for a while, then un-reset it
730 */
731 DELAY(50);
732
733 /*
734 * The 3Com ASIC defaults to rather strange settings for the CR after
735 * a reset - it's important to set it again after the following outb
736 * (this is done when we map the PROM below).
737 */
738 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
739
740 /*
741 * Wait a bit for the NIC to recover from the reset
742 */
743 DELAY(5000);
744
745 sc->vendor = ED_VENDOR_3COM;
746 sc->type_str = "3c503";
747 sc->mem_shared = 1;
748 sc->cr_proto = ED_CR_RD2;
749
750 /*
751 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
752 * to it.
753 */
754 memsize = 8192;
755
756 /*
757 * Get station address from on-board ROM
758 */
759
760 /*
761 * First, map ethernet address PROM over the top of where the NIC
762 * registers normally appear.
763 */
764 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
765
766 for (i = 0; i < ETHER_ADDR_LEN; ++i)
767 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
768
769 /*
770 * Unmap PROM - select NIC registers. The proper setting of the
771 * tranceiver is set in ed_init so that the attach code is given a
772 * chance to set the default based on a compile-time config option
773 */
774 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
775
776 /*
777 * Determine if this is an 8bit or 16bit board
778 */
779
780 /*
781 * select page 0 registers
782 */
783 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
784
785 /*
786 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
787 * board.
788 */
789 ed_nic_outb(sc, ED_P0_DCR, 0);
790
791 /*
792 * select page 2 registers
793 */
794 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
795
796 /*
797 * The 3c503 forces the WTS bit to a one if this is a 16bit board
798 */
799 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
800 isa16bit = 1;
801 else
802 isa16bit = 0;
803
804 /*
805 * select page 0 registers
806 */
807 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
808
809 error = ed_alloc_memory(dev, 0, memsize);
810 if (error)
811 return (error);
812
813 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
814 sc->mem_size = memsize;
815 sc->mem_end = sc->mem_start + memsize;
816
817 /*
818 * We have an entire 8k window to put the transmit buffers on the
819 * 16bit boards. But since the 16bit 3c503's shared memory is only
820 * fast enough to overlap the loading of one full-size packet, trying
821 * to load more than 2 buffers can actually leave the transmitter idle
822 * during the load. So 2 seems the best value. (Although a mix of
823 * variable-sized packets might change this assumption. Nonetheless,
824 * we optimize for linear transfers of same-size packets.)
825 */
826 if (isa16bit) {
827 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
828 sc->txb_cnt = 1;
829 else
830 sc->txb_cnt = 2;
831
832 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
833 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
834 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
835 ED_3COM_RX_PAGE_OFFSET_16BIT;
836 sc->mem_ring = sc->mem_start;
837 } else {
838 sc->txb_cnt = 1;
839 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
840 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
841 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
842 ED_3COM_TX_PAGE_OFFSET_8BIT;
843 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
844 }
845
846 sc->isa16bit = isa16bit;
847
848 /*
849 * Initialize GA page start/stop registers. Probably only needed if
850 * doing DMA, but what the hell.
851 */
852 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
853 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
854
855 /*
856 * Set IRQ. 3c503 only allows a choice of irq 2-5.
857 */
858 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
859 if (error)
860 return (error);
861
862 switch (irq) {
863 case 2:
864 case 9:
865 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
866 break;
867 case 3:
868 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
869 break;
870 case 4:
871 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
872 break;
873 case 5:
874 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
875 break;
876 default:
877 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
878 irq);
879 return (ENXIO);
880 }
881
882 /*
883 * Initialize GA configuration register. Set bank and enable shared
884 * mem.
885 */
886 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
887 ED_3COM_GACFR_MBS0);
888
889 /*
890 * Initialize "Vector Pointer" registers. These gawd-awful things are
891 * compared to 20 bits of the address on ISA, and if they match, the
892 * shared memory is disabled. We set them to 0xffff0...allegedly the
893 * reset vector.
894 */
895 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
896 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
897 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
898
899 /*
900 * Zero memory and verify that it is clear
901 */
902 bzero(sc->mem_start, memsize);
903
904 for (i = 0; i < memsize; ++i)
905 if (sc->mem_start[i]) {
906 device_printf(dev, "failed to clear shared memory at %jx - check configuration\n",
907 (uintmax_t)kvtop(sc->mem_start + i));
908 return (ENXIO);
909 }
910 return (0);
911}
912
913/*
914 * Probe and vendor-specific initialization routine for NE1000/2000 boards
915 */
916int
917ed_probe_Novell_generic(dev, flags)
918 device_t dev;
919 int flags;
920{
921 struct ed_softc *sc = device_get_softc(dev);
922 u_int memsize, n;
923 u_char romdata[16], tmp;
924 static char test_pattern[32] = "THIS is A memory TEST pattern";
925 char test_buffer[32];
926
927 /* XXX - do Novell-specific probe here */
928
929 /* Reset the board */
930 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
931 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
932 DELAY(200);
933 }
934 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
935
936 /*
937 * I don't know if this is necessary; probably cruft leftover from
938 * Clarkson packet driver code. Doesn't do a thing on the boards I've
939 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is
940 * non-invasive...but some boards don't seem to reset and I don't have
941 * complete documentation on what the 'right' thing to do is...so we
942 * do the invasive thing for now. Yuck.]
943 */
944 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
945 DELAY(5000);
946
947 /*
948 * This is needed because some NE clones apparently don't reset the
949 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
950 * - this makes the probe invasive! ...Done against my better
951 * judgement. -DLG
952 */
953 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
954
955 DELAY(5000);
956
957 /* Make sure that we really have an 8390 based board */
958 if (!ed_probe_generic8390(sc))
959 return (ENXIO);
960
961 sc->vendor = ED_VENDOR_NOVELL;
962 sc->mem_shared = 0;
963 sc->cr_proto = ED_CR_RD2;
964
965 /*
966 * Test the ability to read and write to the NIC memory. This has the
967 * side affect of determining if this is an NE1000 or an NE2000.
968 */
969
970 /*
971 * This prevents packets from being stored in the NIC memory when the
972 * readmem routine turns on the start bit in the CR.
973 */
974 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
975
976 /* Temporarily initialize DCR for byte operations */
977 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
978
979 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
980 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
981
982 sc->isa16bit = 0;
983
984 /*
985 * Write a test pattern in byte mode. If this fails, then there
986 * probably isn't any memory at 8k - which likely means that the board
987 * is an NE2000.
988 */
989 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
990 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
991
992 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
993 sc->type = ED_TYPE_NE1000;
994 sc->type_str = "NE1000";
995 } else {
996
997 /* neither an NE1000 nor a Linksys - try NE2000 */
998 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
999 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1000 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1001
1002 sc->isa16bit = 1;
1003
1004 /*
1005 * Write a test pattern in word mode. If this also fails, then
1006 * we don't know what this board is.
1007 */
1008 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1009 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1010 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1011 sc->type = ED_TYPE_NE2000;
1012 sc->type_str = "NE2000";
1013 } else {
1014 return (ENXIO);
1015 }
1016 }
1017
1018
1019 /* 8k of memory plus an additional 8k if 16bit */
1020 memsize = 8192 + sc->isa16bit * 8192;
1021
1022#if 0 /* probably not useful - NE boards only come two ways */
1023 /* allow kernel config file overrides */
1024 if (isa_dev->id_msize)
1025 memsize = isa_dev->id_msize;
1026#endif
1027
1028 sc->mem_size = memsize;
1029
1030 /* NIC memory doesn't start at zero on an NE board */
1031 /* The start address is tied to the bus width */
1032 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1033 sc->mem_end = sc->mem_start + memsize;
1034 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1035
1036 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1037 int x, i, mstart = 0, msize = 0;
1038 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1039
1040 for (i = 0; i < ED_PAGE_SIZE; i++)
1041 pbuf0[i] = 0;
1042
1043 /* Clear all the memory. */
1044 for (x = 1; x < 256; x++)
1045 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1046
1047 /* Search for the start of RAM. */
1048 for (x = 1; x < 256; x++) {
1049 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1050 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1051 for (i = 0; i < ED_PAGE_SIZE; i++)
1052 pbuf[i] = 255 - x;
1053 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1054 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1055 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1056 mstart = x * ED_PAGE_SIZE;
1057 msize = ED_PAGE_SIZE;
1058 break;
1059 }
1060 }
1061 }
1062
1063 if (mstart == 0) {
1064 device_printf(dev, "Cannot find start of RAM.\n");
1065 return (ENXIO);
1066 }
1067 /* Search for the start of RAM. */
1068 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1069 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1070 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1071 for (i = 0; i < ED_PAGE_SIZE; i++)
1072 pbuf[i] = 255 - x;
1073 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1074 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1075 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1076 msize += ED_PAGE_SIZE;
1077 else {
1078 break;
1079 }
1080 } else {
1081 break;
1082 }
1083 }
1084
1085 if (msize == 0) {
1086 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1087 return (ENXIO);
1088 }
1089 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1090
1091 sc->mem_size = msize;
1092 sc->mem_start = (caddr_t) mstart;
1093 sc->mem_end = (caddr_t) (msize + mstart);
1094 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1095 }
1096
1097 /*
1098 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1099 * otherwise).
1100 */
1101 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1102 sc->txb_cnt = 1;
1103 else
1104 sc->txb_cnt = 2;
1105
1106 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1107 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1108
1109 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1110
1111 ed_pio_readmem(sc, 0, romdata, 16);
1112 for (n = 0; n < ETHER_ADDR_LEN; n++)
1113 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1114
1115 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1116 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1117 sc->type_str = "Gateway AT";
1118 }
1119
1120 /* clear any pending interrupts that might have occurred above */
1121 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1122
1123 return (0);
1124}
1125
1126int
1127ed_probe_Novell(dev, port_rid, flags)
1128 device_t dev;
1129 int port_rid;
1130 int flags;
1131{
1132 struct ed_softc *sc = device_get_softc(dev);
1133 int error;
1134
1135 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1136 if (error)
1137 return (error);
1138
1139 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1140 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1141
1142 return ed_probe_Novell_generic(dev, flags);
1143}
1144
1145#define ED_HPP_TEST_SIZE 16
1146
1147/*
1148 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1149 * (HP Part nos: 27247B and 27252A).
1150 *
1151 * The card has an asic wrapper around a DS8390 core. The asic handles
1152 * host accesses and offers both standard register IO and memory mapped
1153 * IO. Memory mapped I/O allows better performance at the expense of greater
1154 * chance of an incompatibility with existing ISA cards.
1155 *
1156 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1157 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1158 * don't allow 32 bit accesses; these are indicated by a bit in the software
1159 * ID register (see if_edreg.h).
1160 *
1161 * Other caveats are: we should read the MAC address only when the card
1162 * is inactive.
1163 *
1164 * For more information; please consult the CRYNWR packet driver.
1165 *
1166 * The AUI port is turned on using the "link2" option on the ifconfig
1167 * command line.
1168 */
1169int
1170ed_probe_HP_pclanp(dev, port_rid, flags)
1171 device_t dev;
1172 int port_rid;
1173 int flags;
1174{
1175 struct ed_softc *sc = device_get_softc(dev);
1176 int error;
1177 int n; /* temp var */
1178 int memsize; /* mem on board */
1179 u_char checksum; /* checksum of board address */
1180 u_char irq; /* board configured IRQ */
1181 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1182 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1183 u_long conf_maddr, conf_msize, conf_irq, junk;
1184
1185 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1186 if (error)
1187 return (error);
1188
1189 /* Fill in basic information */
1190 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1191 sc->nic_offset = ED_HPP_NIC_OFFSET;
1192
1193 sc->chip_type = ED_CHIP_TYPE_DP8390;
1194 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1195
1196 /*
1197 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1198 */
1199
1200 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1201 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1202 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1203 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1204 return ENXIO;
1205
1206 /*
1207 * Read the MAC address and verify checksum on the address.
1208 */
1209
1210 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1211 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1212 checksum += (sc->arpcom.ac_enaddr[n] =
1213 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1214
1215 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1216
1217 if (checksum != 0xFF)
1218 return ENXIO;
1219
1220 /*
1221 * Verify that the software model number is 0.
1222 */
1223
1224 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1225 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1226 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1227 return ENXIO;
1228
1229 /*
1230 * Read in and save the current options configured on card.
1231 */
1232
1233 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1234
1235 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1236 ED_HPP_OPTION_CHIP_RESET |
1237 ED_HPP_OPTION_ENABLE_IRQ);
1238
1239 /*
1240 * Reset the chip. This requires writing to the option register
1241 * so take care to preserve the other bits.
1242 */
1243
1244 ed_asic_outw(sc, ED_HPP_OPTION,
1245 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1246 ED_HPP_OPTION_CHIP_RESET)));
1247
1248 DELAY(5000); /* wait for chip reset to complete */
1249
1250 ed_asic_outw(sc, ED_HPP_OPTION,
1251 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1252 ED_HPP_OPTION_CHIP_RESET |
1253 ED_HPP_OPTION_ENABLE_IRQ)));
1254
1255 DELAY(5000);
1256
1257 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1258 return ENXIO; /* reset did not complete */
1259
1260 /*
1261 * Read out configuration information.
1262 */
1263
1264 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1265
1266 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1267
1268 /*
1269 * Check for impossible IRQ.
1270 */
1271
1272 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1273 return ENXIO;
1274
1275 /*
1276 * If the kernel IRQ was specified with a '?' use the cards idea
1277 * of the IRQ. If the kernel IRQ was explicitly specified, it
1278 * should match that of the hardware.
1279 */
1280 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1281 &conf_irq, &junk);
1282 if (error) {
1283 bus_set_resource(dev, SYS_RES_IRQ, 0,
1284 ed_hpp_intr_val[irq], 1);
1285 } else {
1286 if (conf_irq != ed_hpp_intr_val[irq])
1287 return (ENXIO);
1288 }
1289
1290 /*
1291 * Fill in softconfig info.
1292 */
1293
1294 sc->vendor = ED_VENDOR_HP;
1295 sc->type = ED_TYPE_HP_PCLANPLUS;
1296 sc->type_str = "HP-PCLAN+";
1297
1298 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1299 sc->mem_start = 0; /* we use offsets inside the card RAM */
1300
1301 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1302
1303 /*
1304 * The board has 32KB of memory. Is there a way to determine
1305 * this programmatically?
1306 */
1307
1308 memsize = 32768;
1309
1310 /*
1311 * Check if memory mapping of the I/O registers possible.
1312 */
1313
1314 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1315 {
1316 u_long mem_addr;
1317
1318 /*
1319 * determine the memory address from the board.
1320 */
1321
1322 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1323 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1324
1325 /*
1326 * Check that the kernel specified start of memory and
1327 * hardware's idea of it match.
1328 */
1329 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1330 &conf_maddr, &conf_msize);
1331 if (error)
1332 return (error);
1333
1334 if (mem_addr != conf_maddr)
1335 return ENXIO;
1336
1337 error = ed_alloc_memory(dev, 0, memsize);
1338 if (error)
1339 return (error);
1340
1341 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1342 }
1343
1344 /*
1345 * Fill in the rest of the soft config structure.
1346 */
1347
1348 /*
1349 * The transmit page index.
1350 */
1351
1352 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1353
1354 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1355 sc->txb_cnt = 1;
1356 else
1357 sc->txb_cnt = 2;
1358
1359 /*
1360 * Memory description
1361 */
1362
1363 sc->mem_size = memsize;
1364 sc->mem_ring = sc->mem_start +
1365 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1366 sc->mem_end = sc->mem_start + sc->mem_size;
1367
1368 /*
1369 * Receive area starts after the transmit area and
1370 * continues till the end of memory.
1371 */
1372
1373 sc->rec_page_start = sc->tx_page_start +
1374 (sc->txb_cnt * ED_TXBUF_SIZE);
1375 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1376
1377
1378 sc->cr_proto = 0; /* value works */
1379
1380 /*
1381 * Set the wrap registers for string I/O reads.
1382 */
1383
1384 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1385 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1386 ((sc->rec_page_start / ED_PAGE_SIZE) |
1387 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1388
1389 /*
1390 * Reset the register page to normal operation.
1391 */
1392
1393 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1394
1395 /*
1396 * Verify that we can read/write from adapter memory.
1397 * Create test pattern.
1398 */
1399
1400 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1401 {
1402 test_pattern[n] = (n*n) ^ ~n;
1403 }
1404
1405#undef ED_HPP_TEST_SIZE
1406
1407 /*
1408 * Check that the memory is accessible thru the I/O ports.
1409 * Write out the contents of "test_pattern", read back
1410 * into "test_buffer" and compare the two for any
1411 * mismatch.
1412 */
1413
1414 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1415
1416 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1417 sizeof(test_pattern));
1418 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1419 test_buffer, sizeof(test_pattern));
1420
1421 if (bcmp(test_pattern, test_buffer,
1422 sizeof(test_pattern)))
1423 return ENXIO;
1424 }
1425
1426 return (0);
1427
1428}
1429
1430/*
1431 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1432 */
1433
1434static void
1435ed_hpp_set_physical_link(struct ed_softc *sc)
1436{
1437 struct ifnet *ifp = &sc->arpcom.ac_if;
1438 int lan_page;
1439
1440 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1441 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1442
1443 if (ifp->if_flags & IFF_ALTPHYS) {
1444
1445 /*
1446 * Use the AUI port.
1447 */
1448
1449 lan_page |= ED_HPP_LAN_AUI;
1450
1451 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1452 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1453
1454
1455 } else {
1456
1457 /*
1458 * Use the ThinLan interface
1459 */
1460
1461 lan_page &= ~ED_HPP_LAN_AUI;
1462
1463 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1464 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1465
1466 }
1467
1468 /*
1469 * Wait for the lan card to re-initialize itself
1470 */
1471
1472 DELAY(150000); /* wait 150 ms */
1473
1474 /*
1475 * Restore normal pages.
1476 */
1477
1478 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1479
1480}
1481
1482/*
1483 * Allocate a port resource with the given resource id.
1484 */
1485int
1486ed_alloc_port(dev, rid, size)
1487 device_t dev;
1488 int rid;
1489 int size;
1490{
1491 struct ed_softc *sc = device_get_softc(dev);
1492 struct resource *res;
1493
1494 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1495 0ul, ~0ul, size, RF_ACTIVE);
1496 if (res) {
1497 sc->port_rid = rid;
1498 sc->port_res = res;
1499 sc->port_used = size;
1500 return (0);
1501 } else {
1502 return (ENOENT);
1503 }
1504}
1505
1506/*
1507 * Allocate a memory resource with the given resource id.
1508 */
1509int
1510ed_alloc_memory(dev, rid, size)
1511 device_t dev;
1512 int rid;
1513 int size;
1514{
1515 struct ed_softc *sc = device_get_softc(dev);
1516 struct resource *res;
1517
1518 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1519 0ul, ~0ul, size, RF_ACTIVE);
1520 if (res) {
1521 sc->mem_rid = rid;
1522 sc->mem_res = res;
1523 sc->mem_used = size;
1524 return (0);
1525 } else {
1526 return (ENOENT);
1527 }
1528}
1529
1530/*
1531 * Allocate an irq resource with the given resource id.
1532 */
1533int
1534ed_alloc_irq(dev, rid, flags)
1535 device_t dev;
1536 int rid;
1537 int flags;
1538{
1539 struct ed_softc *sc = device_get_softc(dev);
1540 struct resource *res;
1541
1542 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
1543 0ul, ~0ul, 1, (RF_ACTIVE | flags));
1544 if (res) {
1545 sc->irq_rid = rid;
1546 sc->irq_res = res;
1547 return (0);
1548 } else {
1549 return (ENOENT);
1550 }
1551}
1552
1553/*
1554 * Release all resources
1555 */
1556void
1557ed_release_resources(dev)
1558 device_t dev;
1559{
1560 struct ed_softc *sc = device_get_softc(dev);
1561
1562 if (sc->port_res) {
1563 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1564 sc->port_rid, sc->port_res);
1565 bus_release_resource(dev, SYS_RES_IOPORT,
1566 sc->port_rid, sc->port_res);
1567 sc->port_res = 0;
1568 }
1569 if (sc->mem_res) {
1570 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1571 sc->mem_rid, sc->mem_res);
1572 bus_release_resource(dev, SYS_RES_MEMORY,
1573 sc->mem_rid, sc->mem_res);
1574 sc->mem_res = 0;
1575 }
1576 if (sc->irq_res) {
1577 bus_deactivate_resource(dev, SYS_RES_IRQ,
1578 sc->irq_rid, sc->irq_res);
1579 bus_release_resource(dev, SYS_RES_IRQ,
1580 sc->irq_rid, sc->irq_res);
1581 sc->irq_res = 0;
1582 }
1583}
1584
1585/*
1586 * Install interface into kernel networking data structures
1587 */
1588int
1589ed_attach(sc, unit, flags)
1590 struct ed_softc *sc;
1591 int unit;
1592 int flags;
1593{
1594 struct ifnet *ifp = &sc->arpcom.ac_if;
1595
1596 callout_handle_init(&sc->tick_ch);
1597 /*
1598 * Set interface to stopped condition (reset)
1599 */
1600 ed_stop(sc);
1601
1602 if (!ifp->if_name) {
1603 /*
1604 * Initialize ifnet structure
1605 */
1606 ifp->if_softc = sc;
1607 ifp->if_unit = unit;
1608 ifp->if_name = "ed";
1609 ifp->if_output = ether_output;
1610 ifp->if_start = ed_start;
1611 ifp->if_ioctl = ed_ioctl;
1612 ifp->if_watchdog = ed_watchdog;
1613 ifp->if_init = ed_init;
1614 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1615 ifp->if_linkmib = &sc->mibdata;
1616 ifp->if_linkmiblen = sizeof sc->mibdata;
1617 /*
1618 * XXX - should do a better job.
1619 */
1620 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1621 sc->mibdata.dot3StatsEtherChipSet =
1622 DOT3CHIPSET(dot3VendorWesternDigital,
1623 dot3ChipSetWesternDigital83C790);
1624 else
1625 sc->mibdata.dot3StatsEtherChipSet =
1626 DOT3CHIPSET(dot3VendorNational,
1627 dot3ChipSetNational8390);
1628 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1629
1630 /*
1631 * Set default state for ALTPHYS flag (used to disable the
1632 * tranceiver for AUI operation), based on compile-time
1633 * config option.
1634 */
1635 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1636 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1637 IFF_MULTICAST | IFF_ALTPHYS);
1638 else
1639 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1640 IFF_MULTICAST);
1641
1642 /*
1643 * Attach the interface
1644 */
1645 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1646 }
1647 /* device attach does transition from UNCONFIGURED to IDLE state */
1648
1649 /*
1650 * Print additional info when attached
1651 */
1652 if_printf(ifp, "address %6D, ", sc->arpcom.ac_enaddr, ":");
1653
1654 if (sc->type_str && (*sc->type_str != 0))
1655 printf("type %s ", sc->type_str);
1656 else
1657 printf("type unknown (0x%x) ", sc->type);
1658
1659 if (sc->vendor == ED_VENDOR_HP)
1660 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1661 "16-bit" : "32-bit",
1662 sc->hpp_mem_start ? "memory mapped" : "regular");
1663 else
1664 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1665
1666 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1667 (sc->vendor == ED_VENDOR_HP)) &&
1668 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1669
1670 return (0);
1671}
1672
1673/*
1674 * Reset interface.
1675 */
1676static void
1677ed_reset(ifp)
1678 struct ifnet *ifp;
1679{
1680 struct ed_softc *sc = ifp->if_softc;
1681 int s;
1682
1683 if (sc->gone)
1684 return;
1685 s = splimp();
1686
1687 /*
1688 * Stop interface and re-initialize.
1689 */
1690 ed_stop(sc);
1691 ed_init(sc);
1692
1693 (void) splx(s);
1694}
1695
1696/*
1697 * Take interface offline.
1698 */
1699void
1700ed_stop(sc)
1701 struct ed_softc *sc;
1702{
1703 int n = 5000;
1704
1705#ifndef ED_NO_MIIBUS
1706 untimeout(ed_tick, sc, sc->tick_ch);
1707 callout_handle_init(&sc->tick_ch);
1708#endif
1709 if (sc->gone)
1710 return;
1711 /*
1712 * Stop everything on the interface, and select page 0 registers.
1713 */
1714 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1715
1716 /*
1717 * Wait for interface to enter stopped state, but limit # of checks to
1718 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1719 * just in case it's an old one.
1720 */
1721 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1722 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1723}
1724
1725/*
1726 * Device timeout/watchdog routine. Entered if the device neglects to
1727 * generate an interrupt after a transmit has been started on it.
1728 */
1729static void
1730ed_watchdog(ifp)
1731 struct ifnet *ifp;
1732{
1733 struct ed_softc *sc = ifp->if_softc;
1734
1735 if (sc->gone)
1736 return;
1737 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1738 ifp->if_oerrors++;
1739
1740 ed_reset(ifp);
1741}
1742
1743#ifndef ED_NO_MIIBUS
1744static void
1745ed_tick(arg)
1746 void *arg;
1747{
1748 struct ed_softc *sc = arg;
1749 struct mii_data *mii;
1750 int s;
1751
1752 if (sc->gone) {
1753 callout_handle_init(&sc->tick_ch);
1754 return;
1755 }
1756 s = splimp();
1757 if (sc->miibus != NULL) {
1758 mii = device_get_softc(sc->miibus);
1759 mii_tick(mii);
1760 }
1761 sc->tick_ch = timeout(ed_tick, sc, hz);
1762 splx(s);
1763}
1764#endif
1765
1766/*
1767 * Initialize device.
1768 */
1769static void
1770ed_init(xsc)
1771 void *xsc;
1772{
1773 struct ed_softc *sc = xsc;
1774 struct ifnet *ifp = &sc->arpcom.ac_if;
1775 int i, s;
1776
1777 if (sc->gone)
1778 return;
1779
1780 /* address not known */
1781 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1782 return;
1783
1784 /*
1785 * Initialize the NIC in the exact order outlined in the NS manual.
1786 * This init procedure is "mandatory"...don't change what or when
1787 * things happen.
1788 */
1789 s = splimp();
1790
1791 /* reset transmitter flags */
1792 sc->xmit_busy = 0;
1793 ifp->if_timer = 0;
1794
1795 sc->txb_inuse = 0;
1796 sc->txb_new = 0;
1797 sc->txb_next_tx = 0;
1798
1799 /* This variable is used below - don't move this assignment */
1800 sc->next_packet = sc->rec_page_start + 1;
1801
1802 /*
1803 * Set interface for page 0, Remote DMA complete, Stopped
1804 */
1805 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1806
1807 if (sc->isa16bit) {
1808
1809 /*
1810 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1811 * order=80x86, word-wide DMA xfers,
1812 */
1813 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1814 } else {
1815
1816 /*
1817 * Same as above, but byte-wide DMA xfers
1818 */
1819 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1820 }
1821
1822 /*
1823 * Clear Remote Byte Count Registers
1824 */
1825 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1826 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1827
1828 /*
1829 * For the moment, don't store incoming packets in memory.
1830 */
1831 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1832
1833 /*
1834 * Place NIC in internal loopback mode
1835 */
1836 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1837
1838 /*
1839 * Initialize transmit/receive (ring-buffer) Page Start
1840 */
1841 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1842 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1843 /* Set lower bits of byte addressable framing to 0 */
1844 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1845 ed_nic_outb(sc, 0x09, 0);
1846
1847 /*
1848 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1849 */
1850 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1851 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1852
1853 /*
1854 * Clear all interrupts. A '1' in each bit position clears the
1855 * corresponding flag.
1856 */
1857 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1858
1859 /*
1860 * Enable the following interrupts: receive/transmit complete,
1861 * receive/transmit error, and Receiver OverWrite.
1862 *
1863 * Counter overflow and Remote DMA complete are *not* enabled.
1864 */
1865 ed_nic_outb(sc, ED_P0_IMR,
1866 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1867
1868 /*
1869 * Program Command Register for page 1
1870 */
1871 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1872
1873 /*
1874 * Copy out our station address
1875 */
1876 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1877 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1878
1879 /*
1880 * Set Current Page pointer to next_packet (initialized above)
1881 */
1882 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1883
1884 /*
1885 * Program Receiver Configuration Register and multicast filter. CR is
1886 * set to page 0 on return.
1887 */
1888 ed_setrcr(sc);
1889
1890 /*
1891 * Take interface out of loopback
1892 */
1893 ed_nic_outb(sc, ED_P0_TCR, 0);
1894
1895 /*
1896 * If this is a 3Com board, the tranceiver must be software enabled
1897 * (there is no settable hardware default).
1898 */
1899 if (sc->vendor == ED_VENDOR_3COM) {
1900 if (ifp->if_flags & IFF_ALTPHYS) {
1901 ed_asic_outb(sc, ED_3COM_CR, 0);
1902 } else {
1903 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1904 }
1905 }
1906
1907#ifndef ED_NO_MIIBUS
1908 if (sc->miibus != NULL) {
1909 struct mii_data *mii;
1910 mii = device_get_softc(sc->miibus);
1911 mii_mediachg(mii);
1912 }
1913#endif
1914 /*
1915 * Set 'running' flag, and clear output active flag.
1916 */
1917 ifp->if_flags |= IFF_RUNNING;
1918 ifp->if_flags &= ~IFF_OACTIVE;
1919
1920 /*
1921 * ...and attempt to start output
1922 */
1923 ed_start(ifp);
1924
1925#ifndef ED_NO_MIIBUS
1926 untimeout(ed_tick, sc, sc->tick_ch);
1927 sc->tick_ch = timeout(ed_tick, sc, hz);
1928#endif
1929 (void) splx(s);
1930}
1931
1932/*
1933 * This routine actually starts the transmission on the interface
1934 */
1935static __inline void
1936ed_xmit(sc)
1937 struct ed_softc *sc;
1938{
1939 struct ifnet *ifp = (struct ifnet *)sc;
1940 unsigned short len;
1941
1942 if (sc->gone)
1943 return;
1944 len = sc->txb_len[sc->txb_next_tx];
1945
1946 /*
1947 * Set NIC for page 0 register access
1948 */
1949 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1950
1951 /*
1952 * Set TX buffer start page
1953 */
1954 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
1955 sc->txb_next_tx * ED_TXBUF_SIZE);
1956
1957 /*
1958 * Set TX length
1959 */
1960 ed_nic_outb(sc, ED_P0_TBCR0, len);
1961 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
1962
1963 /*
1964 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1965 */
1966 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
1967 sc->xmit_busy = 1;
1968
1969 /*
1970 * Point to next transmit buffer slot and wrap if necessary.
1971 */
1972 sc->txb_next_tx++;
1973 if (sc->txb_next_tx == sc->txb_cnt)
1974 sc->txb_next_tx = 0;
1975
1976 /*
1977 * Set a timer just in case we never hear from the board again
1978 */
1979 ifp->if_timer = 2;
1980}
1981
1982/*
1983 * Start output on interface.
1984 * We make two assumptions here:
1985 * 1) that the current priority is set to splimp _before_ this code
1986 * is called *and* is returned to the appropriate priority after
1987 * return
1988 * 2) that the IFF_OACTIVE flag is checked before this code is called
1989 * (i.e. that the output part of the interface is idle)
1990 */
1991static void
1992ed_start(ifp)
1993 struct ifnet *ifp;
1994{
1995 struct ed_softc *sc = ifp->if_softc;
1996 struct mbuf *m0, *m;
1997 caddr_t buffer;
1998 int len;
1999
2000 if (sc->gone) {
2001 printf("ed_start(%p) GONE\n",ifp);
2002 return;
2003 }
2004outloop:
2005
2006 /*
2007 * First, see if there are buffered packets and an idle transmitter -
2008 * should never happen at this point.
2009 */
2010 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2011 printf("ed: packets buffered, but transmitter idle\n");
2012 ed_xmit(sc);
2013 }
2014
2015 /*
2016 * See if there is room to put another packet in the buffer.
2017 */
2018 if (sc->txb_inuse == sc->txb_cnt) {
2019
2020 /*
2021 * No room. Indicate this to the outside world and exit.
2022 */
2023 ifp->if_flags |= IFF_OACTIVE;
2024 return;
2025 }
2026 IF_DEQUEUE(&ifp->if_snd, m);
2027 if (m == 0) {
2028
2029 /*
2030 * We are using the !OACTIVE flag to indicate to the outside
2031 * world that we can accept an additional packet rather than
2032 * that the transmitter is _actually_ active. Indeed, the
2033 * transmitter may be active, but if we haven't filled all the
2034 * buffers with data then we still want to accept more.
2035 */
2036 ifp->if_flags &= ~IFF_OACTIVE;
2037 return;
2038 }
2039
2040 /*
2041 * Copy the mbuf chain into the transmit buffer
2042 */
2043
2044 m0 = m;
2045
2046 /* txb_new points to next open buffer slot */
2047 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2048
2049 if (sc->mem_shared) {
2050
2051 /*
2052 * Special case setup for 16 bit boards...
2053 */
2054 if (sc->isa16bit) {
2055 switch (sc->vendor) {
2056
2057 /*
2058 * For 16bit 3Com boards (which have 16k of
2059 * memory), we have the xmit buffers in a
2060 * different page of memory ('page 0') - so
2061 * change pages.
2062 */
2063 case ED_VENDOR_3COM:
2064 ed_asic_outb(sc, ED_3COM_GACFR,
2065 ED_3COM_GACFR_RSEL);
2066 break;
2067
2068 /*
2069 * Enable 16bit access to shared memory on
2070 * WD/SMC boards.
2071 */
2072 case ED_VENDOR_WD_SMC:
2073 ed_asic_outb(sc, ED_WD_LAAR,
2074 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2075 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2076 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2077 }
2078 break;
2079 }
2080 }
2081 for (len = 0; m != 0; m = m->m_next) {
2082 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2083 buffer += m->m_len;
2084 len += m->m_len;
2085 }
2086
2087 /*
2088 * Restore previous shared memory access
2089 */
2090 if (sc->isa16bit) {
2091 switch (sc->vendor) {
2092 case ED_VENDOR_3COM:
2093 ed_asic_outb(sc, ED_3COM_GACFR,
2094 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2095 break;
2096 case ED_VENDOR_WD_SMC:
2097 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2098 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2099 }
2100 ed_asic_outb(sc, ED_WD_LAAR,
2101 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2102 break;
2103 }
2104 }
2105 } else {
2106 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2107 if (len == 0) {
2108 m_freem(m0);
2109 goto outloop;
2110 }
2111 }
2112
2113 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2114
2115 sc->txb_inuse++;
2116
2117 /*
2118 * Point to next buffer slot and wrap if necessary.
2119 */
2120 sc->txb_new++;
2121 if (sc->txb_new == sc->txb_cnt)
2122 sc->txb_new = 0;
2123
2124 if (sc->xmit_busy == 0)
2125 ed_xmit(sc);
2126
2127 /*
2128 * Tap off here if there is a bpf listener.
2129 */
2130 BPF_MTAP(ifp, m0);
2131
2132 m_freem(m0);
2133
2134 /*
2135 * Loop back to the top to possibly buffer more packets
2136 */
2137 goto outloop;
2138}
2139
2140/*
2141 * Ethernet interface receiver interrupt.
2142 */
2143static __inline void
2144ed_rint(sc)
2145 struct ed_softc *sc;
2146{
2147 struct ifnet *ifp = &sc->arpcom.ac_if;
2148 u_char boundry;
2149 u_short len;
2150 struct ed_ring packet_hdr;
2151 char *packet_ptr;
2152
2153 if (sc->gone)
2154 return;
2155
2156 /*
2157 * Set NIC to page 1 registers to get 'current' pointer
2158 */
2159 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2160
2161 /*
2162 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2163 * i.e. it points to where new data has been buffered. The 'CURR'
2164 * (current) register points to the logical end of the ring-buffer -
2165 * i.e. it points to where additional new data will be added. We loop
2166 * here until the logical beginning equals the logical end (or in
2167 * other words, until the ring-buffer is empty).
2168 */
2169 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2170
2171 /* get pointer to this buffer's header structure */
2172 packet_ptr = sc->mem_ring +
2173 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2174
2175 /*
2176 * The byte count includes a 4 byte header that was added by
2177 * the NIC.
2178 */
2179 if (sc->mem_shared)
2180 packet_hdr = *(struct ed_ring *) packet_ptr;
2181 else
2182 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2183 sizeof(packet_hdr));
2184 len = packet_hdr.count;
2185 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2186 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2187 /*
2188 * Length is a wild value. There's a good chance that
2189 * this was caused by the NIC being old and buggy.
2190 * The bug is that the length low byte is duplicated in
2191 * the high byte. Try to recalculate the length based on
2192 * the pointer to the next packet.
2193 */
2194 /*
2195 * NOTE: sc->next_packet is pointing at the current packet.
2196 */
2197 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2198 if (packet_hdr.next_packet >= sc->next_packet) {
2199 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2200 } else {
2201 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2202 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2203 }
2204 /*
2205 * because buffers are aligned on 256-byte boundary,
2206 * the length computed above is off by 256 in almost
2207 * all cases. Fix it...
2208 */
2209 if (len & 0xff)
2210 len -= 256 ;
2211 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2212 + sizeof(struct ed_ring)))
2213 sc->mibdata.dot3StatsFrameTooLongs++;
2214 }
2215 /*
2216 * Be fairly liberal about what we allow as a "reasonable" length
2217 * so that a [crufty] packet will make it to BPF (and can thus
2218 * be analyzed). Note that all that is really important is that
2219 * we have a length that will fit into one mbuf cluster or less;
2220 * the upper layer protocols can then figure out the length from
2221 * their own length field(s).
2222 * But make sure that we have at least a full ethernet header
2223 * or we would be unable to call ether_input() later.
2224 */
2225 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2226 (len <= MCLBYTES) &&
2227 (packet_hdr.next_packet >= sc->rec_page_start) &&
2228 (packet_hdr.next_packet < sc->rec_page_stop)) {
2229 /*
2230 * Go get packet.
2231 */
2232 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2233 len - sizeof(struct ed_ring));
2234 ifp->if_ipackets++;
2235 } else {
2236 /*
2237 * Really BAD. The ring pointers are corrupted.
2238 */
2239 log(LOG_ERR,
2240 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2241 ifp->if_unit, len);
2242 ifp->if_ierrors++;
2243 ed_reset(ifp);
2244 return;
2245 }
2246
2247 /*
2248 * Update next packet pointer
2249 */
2250 sc->next_packet = packet_hdr.next_packet;
2251
2252 /*
2253 * Update NIC boundry pointer - being careful to keep it one
2254 * buffer behind. (as recommended by NS databook)
2255 */
2256 boundry = sc->next_packet - 1;
2257 if (boundry < sc->rec_page_start)
2258 boundry = sc->rec_page_stop - 1;
2259
2260 /*
2261 * Set NIC to page 0 registers to update boundry register
2262 */
2263 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2264
2265 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2266
2267 /*
2268 * Set NIC to page 1 registers before looping to top (prepare
2269 * to get 'CURR' current pointer)
2270 */
2271 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2272 }
2273}
2274
2275/*
2276 * Ethernet interface interrupt processor
2277 */
2278void
2279edintr(arg)
2280 void *arg;
2281{
2282 struct ed_softc *sc = (struct ed_softc*) arg;
2283 struct ifnet *ifp = (struct ifnet *)sc;
2284 u_char isr;
2285 int count;
2286
2287 if (sc->gone)
2288 return;
2289 /*
2290 * Set NIC to page 0 registers
2291 */
2292 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2293
2294 /*
2295 * loop until there are no more new interrupts. When the card
2296 * goes away, the hardware will read back 0xff. Looking at
2297 * the interrupts, it would appear that 0xff is impossible,
2298 * or at least extremely unlikely.
2299 */
2300 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
2301
2302 /*
2303 * reset all the bits that we are 'acknowledging' by writing a
2304 * '1' to each bit position that was set (writing a '1'
2305 * *clears* the bit)
2306 */
2307 ed_nic_outb(sc, ED_P0_ISR, isr);
2308
2309 /*
2310 * XXX workaround for AX88190
2311 * We limit this to 5000 iterations. At 1us per inb/outb,
2312 * this translates to about 15ms, which should be plenty
2313 * of time, and also gives protection in the card eject
2314 * case.
2315 */
2316 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2317 count = 5000; /* 15ms */
2318 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
2319 ed_nic_outb(sc, ED_P0_ISR,0);
2320 ed_nic_outb(sc, ED_P0_ISR,isr);
2321 }
2322 if (count == 0)
2323 break;
2324 }
2325
2326 /*
2327 * Handle transmitter interrupts. Handle these first because
2328 * the receiver will reset the board under some conditions.
2329 */
2330 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2331 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2332
2333 /*
2334 * Check for transmit error. If a TX completed with an
2335 * error, we end up throwing the packet away. Really
2336 * the only error that is possible is excessive
2337 * collisions, and in this case it is best to allow
2338 * the automatic mechanisms of TCP to backoff the
2339 * flow. Of course, with UDP we're screwed, but this
2340 * is expected when a network is heavily loaded.
2341 */
2342 (void) ed_nic_inb(sc, ED_P0_TSR);
2343 if (isr & ED_ISR_TXE) {
2344 u_char tsr;
2345
2346 /*
2347 * Excessive collisions (16)
2348 */
2349 tsr = ed_nic_inb(sc, ED_P0_TSR);
2350 if ((tsr & ED_TSR_ABT)
2351 && (collisions == 0)) {
2352
2353 /*
2354 * When collisions total 16, the
2355 * P0_NCR will indicate 0, and the
2356 * TSR_ABT is set.
2357 */
2358 collisions = 16;
2359 sc->mibdata.dot3StatsExcessiveCollisions++;
2360 sc->mibdata.dot3StatsCollFrequencies[15]++;
2361 }
2362 if (tsr & ED_TSR_OWC)
2363 sc->mibdata.dot3StatsLateCollisions++;
2364 if (tsr & ED_TSR_CDH)
2365 sc->mibdata.dot3StatsSQETestErrors++;
2366 if (tsr & ED_TSR_CRS)
2367 sc->mibdata.dot3StatsCarrierSenseErrors++;
2368 if (tsr & ED_TSR_FU)
2369 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2370
2371 /*
2372 * update output errors counter
2373 */
2374 ifp->if_oerrors++;
2375 } else {
2376
2377 /*
2378 * Update total number of successfully
2379 * transmitted packets.
2380 */
2381 ifp->if_opackets++;
2382 }
2383
2384 /*
2385 * reset tx busy and output active flags
2386 */
2387 sc->xmit_busy = 0;
2388 ifp->if_flags &= ~IFF_OACTIVE;
2389
2390 /*
2391 * clear watchdog timer
2392 */
2393 ifp->if_timer = 0;
2394
2395 /*
2396 * Add in total number of collisions on last
2397 * transmission.
2398 */
2399 ifp->if_collisions += collisions;
2400 switch(collisions) {
2401 case 0:
2402 case 16:
2403 break;
2404 case 1:
2405 sc->mibdata.dot3StatsSingleCollisionFrames++;
2406 sc->mibdata.dot3StatsCollFrequencies[0]++;
2407 break;
2408 default:
2409 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2410 sc->mibdata.
2411 dot3StatsCollFrequencies[collisions-1]
2412 ++;
2413 break;
2414 }
2415
2416 /*
2417 * Decrement buffer in-use count if not zero (can only
2418 * be zero if a transmitter interrupt occured while
2419 * not actually transmitting). If data is ready to
2420 * transmit, start it transmitting, otherwise defer
2421 * until after handling receiver
2422 */
2423 if (sc->txb_inuse && --sc->txb_inuse)
2424 ed_xmit(sc);
2425 }
2426
2427 /*
2428 * Handle receiver interrupts
2429 */
2430 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2431
2432 /*
2433 * Overwrite warning. In order to make sure that a
2434 * lockup of the local DMA hasn't occurred, we reset
2435 * and re-init the NIC. The NSC manual suggests only a
2436 * partial reset/re-init is necessary - but some chips
2437 * seem to want more. The DMA lockup has been seen
2438 * only with early rev chips - Methinks this bug was
2439 * fixed in later revs. -DG
2440 */
2441 if (isr & ED_ISR_OVW) {
2442 ifp->if_ierrors++;
2443#ifdef DIAGNOSTIC
2444 log(LOG_WARNING,
2445 "ed%d: warning - receiver ring buffer overrun\n",
2446 ifp->if_unit);
2447#endif
2448
2449 /*
2450 * Stop/reset/re-init NIC
2451 */
2452 ed_reset(ifp);
2453 } else {
2454
2455 /*
2456 * Receiver Error. One or more of: CRC error,
2457 * frame alignment error FIFO overrun, or
2458 * missed packet.
2459 */
2460 if (isr & ED_ISR_RXE) {
2461 u_char rsr;
2462 rsr = ed_nic_inb(sc, ED_P0_RSR);
2463 if (rsr & ED_RSR_CRC)
2464 sc->mibdata.dot3StatsFCSErrors++;
2465 if (rsr & ED_RSR_FAE)
2466 sc->mibdata.dot3StatsAlignmentErrors++;
2467 if (rsr & ED_RSR_FO)
2468 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2469 ifp->if_ierrors++;
2470#ifdef ED_DEBUG
2471 if_printf(ifp, "receive error %x\n",
2472 ed_nic_inb(sc, ED_P0_RSR));
2473#endif
2474 }
2475
2476 /*
2477 * Go get the packet(s) XXX - Doing this on an
2478 * error is dubious because there shouldn't be
2479 * any data to get (we've configured the
2480 * interface to not accept packets with
2481 * errors).
2482 */
2483
2484 /*
2485 * Enable 16bit access to shared memory first
2486 * on WD/SMC boards.
2487 */
2488 if (sc->isa16bit &&
2489 (sc->vendor == ED_VENDOR_WD_SMC)) {
2490
2491 ed_asic_outb(sc, ED_WD_LAAR,
2492 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2493 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2494 ed_asic_outb(sc, ED_WD_MSR,
2495 ED_WD_MSR_MENB);
2496 }
2497 }
2498 ed_rint(sc);
2499
2500 /* disable 16bit access */
2501 if (sc->isa16bit &&
2502 (sc->vendor == ED_VENDOR_WD_SMC)) {
2503
2504 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2505 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2506 }
2507 ed_asic_outb(sc, ED_WD_LAAR,
2508 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2509 }
2510 }
2511 }
2512
2513 /*
2514 * If it looks like the transmitter can take more data,
2515 * attempt to start output on the interface. This is done
2516 * after handling the receiver to give the receiver priority.
2517 */
2518 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2519 ed_start(ifp);
2520
2521 /*
2522 * return NIC CR to standard state: page 0, remote DMA
2523 * complete, start (toggling the TXP bit off, even if was just
2524 * set in the transmit routine, is *okay* - it is 'edge'
2525 * triggered from low to high)
2526 */
2527 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2528
2529 /*
2530 * If the Network Talley Counters overflow, read them to reset
2531 * them. It appears that old 8390's won't clear the ISR flag
2532 * otherwise - resulting in an infinite loop.
2533 */
2534 if (isr & ED_ISR_CNT) {
2535 (void) ed_nic_inb(sc, ED_P0_CNTR0);
2536 (void) ed_nic_inb(sc, ED_P0_CNTR1);
2537 (void) ed_nic_inb(sc, ED_P0_CNTR2);
2538 }
2539 }
2540}
2541
2542/*
2543 * Process an ioctl request. This code needs some work - it looks
2544 * pretty ugly.
2545 */
2546static int
2547ed_ioctl(ifp, command, data)
2548 register struct ifnet *ifp;
2549 u_long command;
2550 caddr_t data;
2551{
2552 struct ed_softc *sc = ifp->if_softc;
2553#ifndef ED_NO_MIIBUS
2554 struct ifreq *ifr = (struct ifreq *)data;
2555 struct mii_data *mii;
2556#endif
2557 int s, error = 0;
2558
2559 if (sc == NULL || sc->gone) {
2560 ifp->if_flags &= ~IFF_RUNNING;
2561 return ENXIO;
2562 }
2563 s = splimp();
2564
2565 switch (command) {
2566 case SIOCSIFFLAGS:
2567
2568 /*
2569 * If the interface is marked up and stopped, then start it.
2570 * If it is marked down and running, then stop it.
2571 */
2572 if (ifp->if_flags & IFF_UP) {
2573 if ((ifp->if_flags & IFF_RUNNING) == 0)
2574 ed_init(sc);
2575 } else {
2576 if (ifp->if_flags & IFF_RUNNING) {
2577 ed_stop(sc);
2578 ifp->if_flags &= ~IFF_RUNNING;
2579 }
2580 }
2581
2582 /*
2583 * Promiscuous flag may have changed, so reprogram the RCR.
2584 */
2585 ed_setrcr(sc);
2586
2587 /*
2588 * An unfortunate hack to provide the (required) software
2589 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2590 * disables the tranceiver if set.
2591 */
2592 if (sc->vendor == ED_VENDOR_3COM) {
2593 if (ifp->if_flags & IFF_ALTPHYS) {
2594 ed_asic_outb(sc, ED_3COM_CR, 0);
2595 } else {
2596 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2597 }
2598 } else if (sc->vendor == ED_VENDOR_HP)
2599 ed_hpp_set_physical_link(sc);
2600 break;
2601
2602 case SIOCADDMULTI:
2603 case SIOCDELMULTI:
2604 /*
2605 * Multicast list has changed; set the hardware filter
2606 * accordingly.
2607 */
2608 ed_setrcr(sc);
2609 error = 0;
2610 break;
2611
2612#ifndef ED_NO_MIIBUS
2613 case SIOCGIFMEDIA:
2614 case SIOCSIFMEDIA:
2615 if (sc->miibus == NULL) {
2616 error = EINVAL;
2617 break;
2618 }
2619 mii = device_get_softc(sc->miibus);
2620 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2621 break;
2622#endif
2623
2624 default:
2625 error = ether_ioctl(ifp, command, data);
2626 }
2627 (void) splx(s);
2628 return (error);
2629}
2630
2631/*
2632 * Given a source and destination address, copy 'amount' of a packet from
2633 * the ring buffer into a linear destination buffer. Takes into account
2634 * ring-wrap.
2635 */
2636static __inline char *
2637ed_ring_copy(sc, src, dst, amount)
2638 struct ed_softc *sc;
2639 char *src;
2640 char *dst;
2641 u_short amount;
2642{
2643 u_short tmp_amount;
2644
2645 /* does copy wrap to lower addr in ring buffer? */
2646 if (src + amount > sc->mem_end) {
2647 tmp_amount = sc->mem_end - src;
2648
2649 /* copy amount up to end of NIC memory */
2650 if (sc->mem_shared)
2651 bcopy(src, dst, tmp_amount);
2652 else
2653 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2654
2655 amount -= tmp_amount;
2656 src = sc->mem_ring;
2657 dst += tmp_amount;
2658 }
2659 if (sc->mem_shared)
2660 bcopy(src, dst, amount);
2661 else
2662 ed_pio_readmem(sc, (int)src, dst, amount);
2663
2664 return (src + amount);
2665}
2666
2667/*
2668 * Retreive packet from shared memory and send to the next level up via
2669 * ether_input().
2670 */
2671static void
2672ed_get_packet(sc, buf, len)
2673 struct ed_softc *sc;
2674 char *buf;
2675 u_short len;
2676{
2677 struct ifnet *ifp = &sc->arpcom.ac_if;
2678 struct ether_header *eh;
2679 struct mbuf *m;
2680
2681 /* Allocate a header mbuf */
2682 MGETHDR(m, M_DONTWAIT, MT_DATA);
2683 if (m == NULL)
2684 return;
2685 m->m_pkthdr.rcvif = ifp;
2686 m->m_pkthdr.len = m->m_len = len;
2687
2688 /*
2689 * We always put the received packet in a single buffer -
2690 * either with just an mbuf header or in a cluster attached
2691 * to the header. The +2 is to compensate for the alignment
2692 * fixup below.
2693 */
2694 if ((len + 2) > MHLEN) {
2695 /* Attach an mbuf cluster */
2696 MCLGET(m, M_DONTWAIT);
2697
2698 /* Insist on getting a cluster */
2699 if ((m->m_flags & M_EXT) == 0) {
2700 m_freem(m);
2701 return;
2702 }
2703 }
2704
2705 /*
2706 * The +2 is to longword align the start of the real packet.
2707 * This is important for NFS.
2708 */
2709 m->m_data += 2;
2710 eh = mtod(m, struct ether_header *);
2711
2712 /*
2713 * Don't read in the entire packet if we know we're going to drop it
2714 * and no bpf is active.
2715 */
2716 if (!ifp->if_bpf && BDG_ACTIVE( (ifp) ) ) {
2717 struct ifnet *bif;
2718
2719 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
2720 bif = bridge_in_ptr(ifp, eh) ;
2721 if (bif == BDG_DROP) {
2722 m_freem(m);
2723 return;
2724 }
2725 if (len > ETHER_HDR_LEN)
2726 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2727 (char *)(eh + 1), len - ETHER_HDR_LEN);
2728 } else
2729 /*
2730 * Get packet, including link layer address, from interface.
2731 */
2732 ed_ring_copy(sc, buf, (char *)eh, len);
2733
2734 m->m_pkthdr.len = m->m_len = len;
2735
2736 (*ifp->if_input)(ifp, m);
2737}
2738
2739/*
2740 * Supporting routines
2741 */
2742
2743/*
2744 * Given a NIC memory source address and a host memory destination
2745 * address, copy 'amount' from NIC to host using Programmed I/O.
2746 * The 'amount' is rounded up to a word - okay as long as mbufs
2747 * are word sized.
2748 * This routine is currently Novell-specific.
2749 */
2750void
2751ed_pio_readmem(sc, src, dst, amount)
2752 struct ed_softc *sc;
2753 int src;
2754 unsigned char *dst;
2755 unsigned short amount;
2756{
2757 /* HP PC Lan+ cards need special handling */
2758 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2759 ed_hpp_readmem(sc, src, dst, amount);
2760 return;
2761 }
2762
2763 /* Regular Novell cards */
2764 /* select page 0 registers */
2765 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2766
2767 /* round up to a word */
2768 if (amount & 1)
2769 ++amount;
2770
2771 /* set up DMA byte count */
2772 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2773 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2774
2775 /* set up source address in NIC mem */
2776 ed_nic_outb(sc, ED_P0_RSAR0, src);
2777 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2778
2779 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2780
2781 if (sc->isa16bit) {
2782 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2783 } else {
2784 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2785 }
2786}
2787
2788/*
2789 * Stripped down routine for writing a linear buffer to NIC memory.
2790 * Only used in the probe routine to test the memory. 'len' must
2791 * be even.
2792 */
2793void
2794ed_pio_writemem(sc, src, dst, len)
2795 struct ed_softc *sc;
2796 char *src;
2797 unsigned short dst;
2798 unsigned short len;
2799{
2800 int maxwait = 200; /* about 240us */
2801
2802 /* select page 0 registers */
2803 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2804
2805 /* reset remote DMA complete flag */
2806 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2807
2808 /* set up DMA byte count */
2809 ed_nic_outb(sc, ED_P0_RBCR0, len);
2810 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2811
2812 /* set up destination address in NIC mem */
2813 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2814 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2815
2816 /* set remote DMA write */
2817 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2818
2819 if (sc->isa16bit) {
2820 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2821 } else {
2822 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2823 }
2824
2825 /*
2826 * Wait for remote DMA complete. This is necessary because on the
2827 * transmit side, data is handled internally by the NIC in bursts and
2828 * we can't start another remote DMA until this one completes. Not
2829 * waiting causes really bad things to happen - like the NIC
2830 * irrecoverably jamming the ISA bus.
2831 */
2832 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2833}
2834
2835/*
2836 * Write an mbuf chain to the destination NIC memory address using
2837 * programmed I/O.
2838 */
2839static u_short
2840ed_pio_write_mbufs(sc, m, dst)
2841 struct ed_softc *sc;
2842 struct mbuf *m;
2843 int dst;
2844{
2845 struct ifnet *ifp = (struct ifnet *)sc;
2846 unsigned short total_len, dma_len;
2847 struct mbuf *mp;
2848 int maxwait = 200; /* about 240us */
2849
2850 /* HP PC Lan+ cards need special handling */
2851 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2852 return ed_hpp_write_mbufs(sc, m, dst);
2853 }
2854
2855 /* Regular Novell cards */
2856 /* First, count up the total number of bytes to copy */
2857 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2858 total_len += mp->m_len;
2859
2860 dma_len = total_len;
2861 if (sc->isa16bit && (dma_len & 1))
2862 dma_len++;
2863
2864 /* select page 0 registers */
2865 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2866
2867 /* reset remote DMA complete flag */
2868 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2869
2870 /* set up DMA byte count */
2871 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2872 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2873
2874 /* set up destination address in NIC mem */
2875 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2876 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2877
2878 /* set remote DMA write */
2879 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2880
2881 /*
2882 * Transfer the mbuf chain to the NIC memory.
2883 * 16-bit cards require that data be transferred as words, and only words.
2884 * So that case requires some extra code to patch over odd-length mbufs.
2885 */
2886
2887 if (!sc->isa16bit) {
2888 /* NE1000s are easy */
2889 while (m) {
2890 if (m->m_len) {
2891 ed_asic_outsb(sc, ED_NOVELL_DATA,
2892 m->m_data, m->m_len);
2893 }
2894 m = m->m_next;
2895 }
2896 } else {
2897 /* NE2000s are a pain */
2898 unsigned char *data;
2899 int len, wantbyte;
2900 unsigned char savebyte[2];
2901
2902 wantbyte = 0;
2903
2904 while (m) {
2905 len = m->m_len;
2906 if (len) {
2907 data = mtod(m, caddr_t);
2908 /* finish the last word */
2909 if (wantbyte) {
2910 savebyte[1] = *data;
2911 ed_asic_outw(sc, ED_NOVELL_DATA,
2912 *(u_short *)savebyte);
2913 data++;
2914 len--;
2915 wantbyte = 0;
2916 }
2917 /* output contiguous words */
2918 if (len > 1) {
2919 ed_asic_outsw(sc, ED_NOVELL_DATA,
2920 data, len >> 1);
2921 data += len & ~1;
2922 len &= 1;
2923 }
2924 /* save last byte, if necessary */
2925 if (len == 1) {
2926 savebyte[0] = *data;
2927 wantbyte = 1;
2928 }
2929 }
2930 m = m->m_next;
2931 }
2932 /* spit last byte */
2933 if (wantbyte) {
2934 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
2935 }
2936 }
2937
2938 /*
2939 * Wait for remote DMA complete. This is necessary because on the
2940 * transmit side, data is handled internally by the NIC in bursts and
2941 * we can't start another remote DMA until this one completes. Not
2942 * waiting causes really bad things to happen - like the NIC
2943 * irrecoverably jamming the ISA bus.
2944 */
2945 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2946
2947 if (!maxwait) {
2948 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2949 ifp->if_unit);
2950 ed_reset(ifp);
2951 return(0);
2952 }
2953 return (total_len);
2954}
2955
2956/*
2957 * Support routines to handle the HP PC Lan+ card.
2958 */
2959
2960/*
2961 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2962 * IO.
2963 */
2964
2965static void
2966ed_hpp_readmem(sc, src, dst, amount)
2967 struct ed_softc *sc;
2968 unsigned short src;
2969 unsigned char *dst;
2970 unsigned short amount;
2971{
2972
2973 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
2974
2975
2976 /* Program the source address in RAM */
2977 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
2978
2979 /*
2980 * The HP PC Lan+ card supports word reads as well as
2981 * a memory mapped i/o port that is aliased to every
2982 * even address on the board.
2983 */
2984
2985 if (sc->hpp_mem_start) {
2986
2987 /* Enable memory mapped access. */
2988 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
2989 ~(ED_HPP_OPTION_MEM_DISABLE |
2990 ED_HPP_OPTION_BOOT_ROM_ENB));
2991
2992 if (use_32bit_access && (amount > 3)) {
2993 u_int32_t *dl = (u_int32_t *) dst;
2994 volatile u_int32_t *const sl =
2995 (u_int32_t *) sc->hpp_mem_start;
2996 u_int32_t *const fence = dl + (amount >> 2);
2997
2998 /* Copy out NIC data. We could probably write this
2999 as a `movsl'. The currently generated code is lousy.
3000 */
3001
3002 while (dl < fence)
3003 *dl++ = *sl;
3004
3005 dst += (amount & ~3);
3006 amount &= 3;
3007
3008 }
3009
3010 /* Finish off any words left, as a series of short reads */
3011 if (amount > 1) {
3012 u_short *d = (u_short *) dst;
3013 volatile u_short *const s =
3014 (u_short *) sc->hpp_mem_start;
3015 u_short *const fence = d + (amount >> 1);
3016
3017 /* Copy out NIC data. */
3018
3019 while (d < fence)
3020 *d++ = *s;
3021
3022 dst += (amount & ~1);
3023 amount &= 1;
3024 }
3025
3026 /*
3027 * read in a byte; however we need to always read 16 bits
3028 * at a time or the hardware gets into a funny state
3029 */
3030
3031 if (amount == 1) {
3032 /* need to read in a short and copy LSB */
3033 volatile u_short *const s =
3034 (volatile u_short *) sc->hpp_mem_start;
3035
3036 *dst = (*s) & 0xFF;
3037 }
3038
3039 /* Restore Boot ROM access. */
3040
3041 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3042
3043
3044 } else {
3045 /* Read in data using the I/O port */
3046 if (use_32bit_access && (amount > 3)) {
3047 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3048 dst += (amount & ~3);
3049 amount &= 3;
3050 }
3051 if (amount > 1) {
3052 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3053 dst += (amount & ~1);
3054 amount &= 1;
3055 }
3056 if (amount == 1) { /* read in a short and keep the LSB */
3057 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3058 }
3059 }
3060}
3061
3062/*
3063 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3064 * IO.
3065 * Only used in the probe routine to test the memory. 'len' must
3066 * be even.
3067 */
3068static void
3069ed_hpp_writemem(sc, src, dst, len)
3070 struct ed_softc *sc;
3071 unsigned char *src;
3072 unsigned short dst;
3073 unsigned short len;
3074{
3075 /* reset remote DMA complete flag */
3076 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3077
3078 /* program the write address in RAM */
3079 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3080
3081 if (sc->hpp_mem_start) {
3082 u_short *s = (u_short *) src;
3083 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3084 u_short *const fence = s + (len >> 1);
3085
3086 /*
3087 * Enable memory mapped access.
3088 */
3089
3090 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3091 ~(ED_HPP_OPTION_MEM_DISABLE |
3092 ED_HPP_OPTION_BOOT_ROM_ENB));
3093
3094 /*
3095 * Copy to NIC memory.
3096 */
3097
3098 while (s < fence)
3099 *d = *s++;
3100
3101 /*
3102 * Restore Boot ROM access.
3103 */
3104
3105 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3106
3107 } else {
3108 /* write data using I/O writes */
3109 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3110 }
3111}
3112
3113/*
3114 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3115 * outsw() or via the memory mapped interface to the same register.
3116 * Writes have to be in word units; byte accesses won't work and may cause
3117 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
3118 * allows it.
3119 */
3120
3121static u_short
3122ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3123{
3124 int len, wantbyte;
3125 unsigned short total_len;
3126 unsigned char savebyte[2];
3127 volatile u_short * const d =
3128 (volatile u_short *) sc->hpp_mem_start;
3129 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3130
3131 /* select page 0 registers */
3132 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3133
3134 /* reset remote DMA complete flag */
3135 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3136
3137 /* program the write address in RAM */
3138 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3139
3140 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3141 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3142 ~(ED_HPP_OPTION_MEM_DISABLE |
3143 ED_HPP_OPTION_BOOT_ROM_ENB));
3144
3145 wantbyte = 0;
3146 total_len = 0;
3147
3148 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3149 while (m) {
3150 total_len += (len = m->m_len);
3151 if (len) {
3152 caddr_t data = mtod(m, caddr_t);
3153 /* finish the last word of the previous mbuf */
3154 if (wantbyte) {
3155 savebyte[1] = *data;
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