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if_em.c (155911) if_em.c (157566)
1/**************************************************************************
2
3Copyright (c) 2001-2005, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

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26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
1/**************************************************************************
2
3Copyright (c) 2001-2005, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

--- 17 unchanged lines hidden (view full) ---

26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
34/*$FreeBSD: head/sys/dev/em/if_em.c 155911 2006-02-22 14:11:16Z glebius $*/
34/*$FreeBSD: head/sys/dev/em/if_em.c 157566 2006-04-06 17:09:03Z glebius $*/
35
36#ifdef HAVE_KERNEL_OPTION_HEADERS
37#include "opt_device_polling.h"
38#endif
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/bus.h>

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80 * Set this to one to display debug statistics
81 *********************************************************************/
82int em_display_debug_stats = 0;
83
84/*********************************************************************
85 * Driver version
86 *********************************************************************/
87
35
36#ifdef HAVE_KERNEL_OPTION_HEADERS
37#include "opt_device_polling.h"
38#endif
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/bus.h>

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80 * Set this to one to display debug statistics
81 *********************************************************************/
82int em_display_debug_stats = 0;
83
84/*********************************************************************
85 * Driver version
86 *********************************************************************/
87
88char em_driver_version[] = "Version - 3.2.18";
88char em_driver_version[] = "Version - 5.1.5";
89
90
91/*********************************************************************
92 * PCI Device ID Table
93 *
94 * Used by probe to select devices to load on
95 * Last field stores an index into em_strings
96 * Last entry must be all 0s

--- 37 unchanged lines hidden (view full) ---

134 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
135 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
136 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
137 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
138 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
139 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
140 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0},
141 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
89
90
91/*********************************************************************
92 * PCI Device ID Table
93 *
94 * Used by probe to select devices to load on
95 * Last field stores an index into em_strings
96 * Last entry must be all 0s

--- 37 unchanged lines hidden (view full) ---

134 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
135 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
136 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
137 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
138 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
139 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
140 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0},
141 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
142 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,
143 PCI_ANY_ID, PCI_ANY_ID, 0},
142
143 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0},
144 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
145 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0},
146
147 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
148 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
149 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
150
151 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
152 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
153 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
144
145 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0},
146 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
147 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0},
148
149 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
150 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
151 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
152
153 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
154 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
155 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
156 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0},
154
155 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0},
156 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0},
157 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0},
157
158 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0},
159 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0},
160 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0},
161 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT,
162 PCI_ANY_ID, PCI_ANY_ID, 0},
163 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT,
164 PCI_ANY_ID, PCI_ANY_ID, 0},
158
159 /* required last entry */
160 { 0, 0, 0, 0, 0}
161};
162
163/*********************************************************************
164 * Table of branding strings for all supported NICs.
165 *********************************************************************/

--- 365 unchanged lines hidden (view full) ---

531 em_allocate_intr(sc);
532
533 /* Initialize statistics */
534 em_clear_hw_cntrs(&sc->hw);
535 em_update_stats_counters(sc);
536 sc->hw.get_link_status = 1;
537 em_update_link_status(sc);
538
165
166 /* required last entry */
167 { 0, 0, 0, 0, 0}
168};
169
170/*********************************************************************
171 * Table of branding strings for all supported NICs.
172 *********************************************************************/

--- 365 unchanged lines hidden (view full) ---

538 em_allocate_intr(sc);
539
540 /* Initialize statistics */
541 em_clear_hw_cntrs(&sc->hw);
542 em_update_stats_counters(sc);
543 sc->hw.get_link_status = 1;
544 em_update_link_status(sc);
545
546 /* Indicate SOL/IDER usage */
547 if (em_check_phy_reset_block(&sc->hw))
548 device_printf(dev,
549 "PHY reset is blocked due to SOL/IDER session.\n");
550
539 /* Identify 82544 on PCIX */
540 em_get_bus_info(&sc->hw);
541 if(sc->hw.bus_type == em_bus_type_pcix && sc->hw.mac_type == em_82544)
542 sc->pcix_82544 = TRUE;
543 else
544 sc->pcix_82544 = FALSE;
545
546 INIT_DEBUGOUT("em_attach: end");

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725 *
726 * return 0 on success, positive on failure
727 **********************************************************************/
728
729static int
730em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
731{
732 struct em_softc *sc = ifp->if_softc;
551 /* Identify 82544 on PCIX */
552 em_get_bus_info(&sc->hw);
553 if(sc->hw.bus_type == em_bus_type_pcix && sc->hw.mac_type == em_82544)
554 sc->pcix_82544 = TRUE;
555 else
556 sc->pcix_82544 = FALSE;
557
558 INIT_DEBUGOUT("em_attach: end");

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737 *
738 * return 0 on success, positive on failure
739 **********************************************************************/
740
741static int
742em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
743{
744 struct em_softc *sc = ifp->if_softc;
733 struct ifreq *ifr = (struct ifreq *)data;
745 struct ifreq *ifr = (struct ifreq *)data;
734 int error = 0;
735
736 if (sc->in_detach)
737 return (error);
738
739 switch (command) {
740 case SIOCSIFADDR:
741 case SIOCGIFADDR:
742 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)");
743 ether_ioctl(ifp, command, data);
744 break;
745 case SIOCSIFMTU:
746 {
747 int max_frame_size;
746 int error = 0;
747
748 if (sc->in_detach)
749 return (error);
750
751 switch (command) {
752 case SIOCSIFADDR:
753 case SIOCGIFADDR:
754 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)");
755 ether_ioctl(ifp, command, data);
756 break;
757 case SIOCSIFMTU:
758 {
759 int max_frame_size;
760 uint16_t eeprom_data = 0;
748
749 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
750
751 switch (sc->hw.mac_type) {
761
762 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
763
764 switch (sc->hw.mac_type) {
765 case em_82573:
766 /*
767 * 82573 only supports jumbo frames
768 * if ASPM is disabled.
769 */
770 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 1,
771 &eeprom_data);
772 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
773 max_frame_size = ETHER_MAX_LEN;
774 break;
775 }
776 /* Allow Jumbo frames - fall thru */
752 case em_82571:
753 case em_82572:
777 case em_82571:
778 case em_82572:
754 max_frame_size = 10500;
779 case em_80003es2lan: /* Limit Jumbo Frame size */
780 max_frame_size = 9234;
755 break;
781 break;
756 case em_82573:
757 /* 82573 does not support jumbo frames. */
758 max_frame_size = ETHER_MAX_LEN;
759 break;
760 default:
761 max_frame_size = MAX_JUMBO_FRAME_SIZE;
762 }
763 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
764 ETHER_CRC_LEN) {
765 error = EINVAL;
766 break;
767 }

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928 if (sc->hw.max_frame_size > EM_RXBUFFER_8192)
929 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
930 else
931 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
932 sc->tx_fifo_head = 0;
933 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
934 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
935 break;
782 default:
783 max_frame_size = MAX_JUMBO_FRAME_SIZE;
784 }
785 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
786 ETHER_CRC_LEN) {
787 error = EINVAL;
788 break;
789 }

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950 if (sc->hw.max_frame_size > EM_RXBUFFER_8192)
951 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
952 else
953 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
954 sc->tx_fifo_head = 0;
955 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
956 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
957 break;
958 case em_80003es2lan: /* 80003es2lan: Total Packet Buffer is 48K */
936 case em_82571: /* 82571: Total Packet Buffer is 48K */
937 case em_82572: /* 82572: Total Packet Buffer is 48K */
938 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
939 break;
940 case em_82573: /* 82573: Total Packet Buffer is 32K */
941 /* Jumbo frames not supported */
942 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
943 break;

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2073 * by 1500.
2074 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2075 */
2076 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 );
2077
2078 sc->hw.fc_high_water = rx_buffer_size -
2079 roundup2(sc->hw.max_frame_size, 1024);
2080 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500;
959 case em_82571: /* 82571: Total Packet Buffer is 48K */
960 case em_82572: /* 82572: Total Packet Buffer is 48K */
961 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
962 break;
963 case em_82573: /* 82573: Total Packet Buffer is 32K */
964 /* Jumbo frames not supported */
965 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
966 break;

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2096 * by 1500.
2097 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2098 */
2099 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 );
2100
2101 sc->hw.fc_high_water = rx_buffer_size -
2102 roundup2(sc->hw.max_frame_size, 1024);
2103 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500;
2081 sc->hw.fc_pause_time = 0x1000;
2104 if (sc->hw.mac_type == em_80003es2lan)
2105 sc->hw.fc_pause_time = 0xFFFF;
2106 else
2107 sc->hw.fc_pause_time = 0x1000;
2082 sc->hw.fc_send_xon = TRUE;
2083 sc->hw.fc = em_fc_full;
2084
2085 if (em_init_hw(&sc->hw) < 0) {
2086 device_printf(dev, "Hardware Initialization Failed");
2087 return (EIO);
2088 }
2089

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2397/*********************************************************************
2398 *
2399 * Enable transmit unit.
2400 *
2401 **********************************************************************/
2402static void
2403em_initialize_transmit_unit(struct em_softc *sc)
2404{
2108 sc->hw.fc_send_xon = TRUE;
2109 sc->hw.fc = em_fc_full;
2110
2111 if (em_init_hw(&sc->hw) < 0) {
2112 device_printf(dev, "Hardware Initialization Failed");
2113 return (EIO);
2114 }
2115

--- 307 unchanged lines hidden (view full) ---

2423/*********************************************************************
2424 *
2425 * Enable transmit unit.
2426 *
2427 **********************************************************************/
2428static void
2429em_initialize_transmit_unit(struct em_softc *sc)
2430{
2405 uint32_t reg_tctl;
2431 uint32_t reg_tctl, tarc;
2406 uint32_t reg_tipg = 0;
2407 uint64_t bus_addr;
2408
2409 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2410 /* Setup the Base and Length of the Tx Descriptor Ring */
2411 bus_addr = sc->txdma.dma_paddr;
2412 E1000_WRITE_REG(&sc->hw, TDBAL, (uint32_t)bus_addr);
2413 E1000_WRITE_REG(&sc->hw, TDBAH, (uint32_t)(bus_addr >> 32));

--- 11 unchanged lines hidden (view full) ---

2425 /* Set the default values for the Tx Inter Packet Gap timer */
2426 switch (sc->hw.mac_type) {
2427 case em_82542_rev2_0:
2428 case em_82542_rev2_1:
2429 reg_tipg = DEFAULT_82542_TIPG_IPGT;
2430 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2431 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2432 break;
2432 uint32_t reg_tipg = 0;
2433 uint64_t bus_addr;
2434
2435 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2436 /* Setup the Base and Length of the Tx Descriptor Ring */
2437 bus_addr = sc->txdma.dma_paddr;
2438 E1000_WRITE_REG(&sc->hw, TDBAL, (uint32_t)bus_addr);
2439 E1000_WRITE_REG(&sc->hw, TDBAH, (uint32_t)(bus_addr >> 32));

--- 11 unchanged lines hidden (view full) ---

2451 /* Set the default values for the Tx Inter Packet Gap timer */
2452 switch (sc->hw.mac_type) {
2453 case em_82542_rev2_0:
2454 case em_82542_rev2_1:
2455 reg_tipg = DEFAULT_82542_TIPG_IPGT;
2456 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2457 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2458 break;
2459 case em_80003es2lan:
2460 reg_tipg = DEFAULT_82543_TIPG_IPGR1;
2461 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2462 E1000_TIPG_IPGR2_SHIFT;
2463 break;
2433 default:
2434 if (sc->hw.media_type == em_media_type_fiber)
2435 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2436 else
2437 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2438 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2439 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2440 }

--- 10 unchanged lines hidden (view full) ---

2451 reg_tctl |= E1000_TCTL_MULR;
2452 if (sc->link_duplex == 1) {
2453 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2454 } else {
2455 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2456 }
2457 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl);
2458
2464 default:
2465 if (sc->hw.media_type == em_media_type_fiber)
2466 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2467 else
2468 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2469 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2470 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2471 }

--- 10 unchanged lines hidden (view full) ---

2482 reg_tctl |= E1000_TCTL_MULR;
2483 if (sc->link_duplex == 1) {
2484 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2485 } else {
2486 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2487 }
2488 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl);
2489
2490 if (sc->hw.mac_type == em_82571 || sc->hw.mac_type == em_82572) {
2491 tarc = E1000_READ_REG(&sc->hw, TARC0);
2492 tarc |= ((1 << 25) | (1 << 21));
2493 E1000_WRITE_REG(&sc->hw, TARC0, tarc);
2494 tarc = E1000_READ_REG(&sc->hw, TARC1);
2495 tarc |= (1 << 25);
2496 if (reg_tctl & E1000_TCTL_MULR)
2497 tarc &= ~(1 << 28);
2498 else
2499 tarc |= (1 << 28);
2500 E1000_WRITE_REG(&sc->hw, TARC1, tarc);
2501 } else if (sc->hw.mac_type == em_80003es2lan) {
2502 tarc = E1000_READ_REG(&sc->hw, TARC0);
2503 tarc |= 1;
2504 if (sc->hw.media_type == em_media_type_internal_serdes)
2505 tarc |= (1 << 20);
2506 E1000_WRITE_REG(&sc->hw, TARC0, tarc);
2507 tarc = E1000_READ_REG(&sc->hw, TARC1);
2508 tarc |= 1;
2509 E1000_WRITE_REG(&sc->hw, TARC1, tarc);
2510 }
2511
2459 /* Setup Transmit Descriptor Settings for this adapter */
2460 sc->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS;
2461
2462 if (sc->tx_int_delay.value > 0)
2463 sc->txd_cmd |= E1000_TXD_CMD_IDE;
2464}
2465
2466/*********************************************************************

--- 1159 unchanged lines hidden --- 		2512 /* Setup Transmit Descriptor Settings for this adapter */
2513 sc->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS;
2514
2515 if (sc->tx_int_delay.value > 0)
2516 sc->txd_cmd |= E1000_TXD_CMD_IDE;
2517}
2518
2519/*********************************************************************

--- 1159 unchanged lines hidden ---