1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 *
| 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 *
|
25 * $FreeBSD: head/sys/dev/drm2/i915/intel_drv.h 235783 2012-05-22 11:07:44Z kib $
| 25 * $FreeBSD: head/sys/dev/drm2/i915/intel_drv.h 254797 2013-08-24 16:50:47Z dumbbell $
|
26 */
27
28#ifndef DRM_INTEL_DRV_H
29#define DRM_INTEL_DRV_H
30
31#include <dev/drm2/i915/i915_drm.h>
32#include <dev/drm2/i915/i915_drv.h>
33#include <dev/drm2/drm_crtc.h>
34#include <dev/drm2/drm_crtc_helper.h>
35#include <dev/drm2/drm_fb_helper.h>
36
37#define _intel_wait_for(DEV, COND, MS, W, WMSG) \
38({ \
39 int end, ret; \
40 \
41 end = ticks + (MS) * hz / 1000; \
42 ret = 0; \
43 \
44 while (!(COND)) { \
45 if (time_after(ticks, end)) { \
46 ret = -ETIMEDOUT; \
47 break; \
48 } \
49 if (W) \
50 pause((WMSG), 1); \
51 else \
52 DELAY(1000); \
53 } \
54 \
55 ret; \
56})
57
58#define KHz(x) (1000*x)
59#define MHz(x) KHz(1000*x)
60
61/* store information about an Ixxx DVO */
62/* The i830->i865 use multiple DVOs with multiple i2cs */
63/* the i915, i945 have a single sDVO i2c bus - which is different */
64#define MAX_OUTPUTS 6
65/* maximum connectors per crtcs in the mode set */
66#define INTELFB_CONN_LIMIT 4
67
68#define INTEL_I2C_BUS_DVO 1
69#define INTEL_I2C_BUS_SDVO 2
70
71/* these are outputs from the chip - integrated only
72 external chips are via DVO or SDVO output */
73#define INTEL_OUTPUT_UNUSED 0
74#define INTEL_OUTPUT_ANALOG 1
75#define INTEL_OUTPUT_DVO 2
76#define INTEL_OUTPUT_SDVO 3
77#define INTEL_OUTPUT_LVDS 4
78#define INTEL_OUTPUT_TVOUT 5
79#define INTEL_OUTPUT_HDMI 6
80#define INTEL_OUTPUT_DISPLAYPORT 7
81#define INTEL_OUTPUT_EDP 8
82
83/* Intel Pipe Clone Bit */
84#define INTEL_HDMIB_CLONE_BIT 1
85#define INTEL_HDMIC_CLONE_BIT 2
86#define INTEL_HDMID_CLONE_BIT 3
87#define INTEL_HDMIE_CLONE_BIT 4
88#define INTEL_HDMIF_CLONE_BIT 5
89#define INTEL_SDVO_NON_TV_CLONE_BIT 6
90#define INTEL_SDVO_TV_CLONE_BIT 7
91#define INTEL_SDVO_LVDS_CLONE_BIT 8
92#define INTEL_ANALOG_CLONE_BIT 9
93#define INTEL_TV_CLONE_BIT 10
94#define INTEL_DP_B_CLONE_BIT 11
95#define INTEL_DP_C_CLONE_BIT 12
96#define INTEL_DP_D_CLONE_BIT 13
97#define INTEL_LVDS_CLONE_BIT 14
98#define INTEL_DVO_TMDS_CLONE_BIT 15
99#define INTEL_DVO_LVDS_CLONE_BIT 16
100#define INTEL_EDP_CLONE_BIT 17
101
102#define INTEL_DVO_CHIP_NONE 0
103#define INTEL_DVO_CHIP_LVDS 1
104#define INTEL_DVO_CHIP_TMDS 2
105#define INTEL_DVO_CHIP_TVOUT 4
106
107/* drm_display_mode->private_flags */
108#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
109#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
110#define INTEL_MODE_DP_FORCE_6BPC (0x10)
111/* This flag must be set by the encoder's mode_fixup if it changes the crtc
112 * timings in the mode to prevent the crtc fixup from overwriting them.
113 * Currently only lvds needs that. */
114#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
115
116static inline void
117intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
118 int multiplier)
119{
120 mode->clock *= multiplier;
121 mode->private_flags |= multiplier;
122}
123
124static inline int
125intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
126{
127 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
128}
129
130struct intel_framebuffer {
131 struct drm_framebuffer base;
132 struct drm_i915_gem_object *obj;
133};
134
135struct intel_fbdev {
136 struct drm_fb_helper helper;
137 struct intel_framebuffer ifb;
138 struct list_head fbdev_list;
139 struct drm_display_mode *our_mode;
140};
141
142struct intel_encoder {
143 struct drm_encoder base;
144 int type;
145 bool needs_tv_clock;
146 void (*hot_plug)(struct intel_encoder *);
147 int crtc_mask;
148 int clone_mask;
149};
150
151struct intel_connector {
152 struct drm_connector base;
153 struct intel_encoder *encoder;
154};
155
156struct intel_crtc {
157 struct drm_crtc base;
158 enum pipe pipe;
159 enum plane plane;
160 u8 lut_r[256], lut_g[256], lut_b[256];
161 int dpms_mode;
162 bool active; /* is the crtc on? independent of the dpms mode */
163 bool busy; /* is scanout buffer being updated frequently? */
164 struct callout idle_callout;
165 bool lowfreq_avail;
166 struct intel_overlay *overlay;
167 struct intel_unpin_work *unpin_work;
168 int fdi_lanes;
169
170 struct drm_i915_gem_object *cursor_bo;
171 uint32_t cursor_addr;
172 int16_t cursor_x, cursor_y;
173 int16_t cursor_width, cursor_height;
174 bool cursor_visible;
175 unsigned int bpp;
176
177 bool no_pll; /* tertiary pipe for IVB */
178 bool use_pll_a;
179};
180
181struct intel_plane {
182 struct drm_plane base;
183 enum pipe pipe;
184 struct drm_i915_gem_object *obj;
185 bool primary_disabled;
186 int max_downscale;
187 u32 lut_r[1024], lut_g[1024], lut_b[1024];
188 void (*update_plane)(struct drm_plane *plane,
189 struct drm_framebuffer *fb,
190 struct drm_i915_gem_object *obj,
191 int crtc_x, int crtc_y,
192 unsigned int crtc_w, unsigned int crtc_h,
193 uint32_t x, uint32_t y,
194 uint32_t src_w, uint32_t src_h);
195 void (*disable_plane)(struct drm_plane *plane);
196 int (*update_colorkey)(struct drm_plane *plane,
197 struct drm_intel_sprite_colorkey *key);
198 void (*get_colorkey)(struct drm_plane *plane,
199 struct drm_intel_sprite_colorkey *key);
200};
201
202#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
203#define to_intel_connector(x) container_of(x, struct intel_connector, base)
204#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
205#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
206#define to_intel_plane(x) container_of(x, struct intel_plane, base)
207
208#define DIP_HEADER_SIZE 5
209
210#define DIP_TYPE_AVI 0x82
211#define DIP_VERSION_AVI 0x2
212#define DIP_LEN_AVI 13
213
214#define DIP_TYPE_SPD 0x83
215#define DIP_VERSION_SPD 0x1
216#define DIP_LEN_SPD 25
217#define DIP_SPD_UNKNOWN 0
218#define DIP_SPD_DSTB 0x1
219#define DIP_SPD_DVDP 0x2
220#define DIP_SPD_DVHS 0x3
221#define DIP_SPD_HDDVR 0x4
222#define DIP_SPD_DVC 0x5
223#define DIP_SPD_DSC 0x6
224#define DIP_SPD_VCD 0x7
225#define DIP_SPD_GAME 0x8
226#define DIP_SPD_PC 0x9
227#define DIP_SPD_BD 0xa
228#define DIP_SPD_SCD 0xb
229
230struct dip_infoframe {
231 uint8_t type; /* HB0 */
232 uint8_t ver; /* HB1 */
233 uint8_t len; /* HB2 - body len, not including checksum */
234 uint8_t ecc; /* Header ECC */
235 uint8_t checksum; /* PB0 */
236 union {
237 struct {
238 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
239 uint8_t Y_A_B_S;
240 /* PB2 - C 7:6, M 5:4, R 3:0 */
241 uint8_t C_M_R;
242 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
243 uint8_t ITC_EC_Q_SC;
244 /* PB4 - VIC 6:0 */
245 uint8_t VIC;
246 /* PB5 - PR 3:0 */
247 uint8_t PR;
248 /* PB6 to PB13 */
249 uint16_t top_bar_end;
250 uint16_t bottom_bar_start;
251 uint16_t left_bar_end;
252 uint16_t right_bar_start;
253 } avi;
254 struct {
255 uint8_t vn[8];
256 uint8_t pd[16];
257 uint8_t sdi;
258 } spd;
259 uint8_t payload[27];
260 } __attribute__ ((packed)) body;
261} __attribute__((packed));
262
263static inline struct drm_crtc *
264intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
265{
266 struct drm_i915_private *dev_priv = dev->dev_private;
267 return dev_priv->pipe_to_crtc_mapping[pipe];
268}
269
270static inline struct drm_crtc *
271intel_get_crtc_for_plane(struct drm_device *dev, int plane)
272{
273 struct drm_i915_private *dev_priv = dev->dev_private;
274 return dev_priv->plane_to_crtc_mapping[plane];
275}
276
277struct intel_unpin_work {
278 struct task task;
279 struct drm_device *dev;
280 struct drm_i915_gem_object *old_fb_obj;
281 struct drm_i915_gem_object *pending_flip_obj;
282 struct drm_pending_vblank_event *event;
283 int pending;
284 bool enable_stall_check;
285};
286
287struct intel_fbc_work {
288 struct timeout_task task;
289 struct drm_crtc *crtc;
290 struct drm_framebuffer *fb;
291 int interval;
292};
293
294int intel_ddc_get_modes(struct drm_connector *c, device_t adapter);
295extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);
296
297extern void intel_attach_force_audio_property(struct drm_connector *connector);
298extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
299
300extern void intel_crt_init(struct drm_device *dev);
301extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
302void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
303extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
304extern void intel_dvo_init(struct drm_device *dev);
305extern void intel_tv_init(struct drm_device *dev);
306extern void intel_mark_busy(struct drm_device *dev,
307 struct drm_i915_gem_object *obj);
308extern bool intel_lvds_init(struct drm_device *dev);
309extern void intel_dp_init(struct drm_device *dev, int dp_reg);
310void
311intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
312 struct drm_display_mode *adjusted_mode);
313extern bool intel_dpd_is_edp(struct drm_device *dev);
314extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
315extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
316extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
317
318/* intel_panel.c */
319extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
320 struct drm_display_mode *adjusted_mode);
321extern void intel_pch_panel_fitting(struct drm_device *dev,
322 int fitting_mode,
| 26 */
27
28#ifndef DRM_INTEL_DRV_H
29#define DRM_INTEL_DRV_H
30
31#include <dev/drm2/i915/i915_drm.h>
32#include <dev/drm2/i915/i915_drv.h>
33#include <dev/drm2/drm_crtc.h>
34#include <dev/drm2/drm_crtc_helper.h>
35#include <dev/drm2/drm_fb_helper.h>
36
37#define _intel_wait_for(DEV, COND, MS, W, WMSG) \
38({ \
39 int end, ret; \
40 \
41 end = ticks + (MS) * hz / 1000; \
42 ret = 0; \
43 \
44 while (!(COND)) { \
45 if (time_after(ticks, end)) { \
46 ret = -ETIMEDOUT; \
47 break; \
48 } \
49 if (W) \
50 pause((WMSG), 1); \
51 else \
52 DELAY(1000); \
53 } \
54 \
55 ret; \
56})
57
58#define KHz(x) (1000*x)
59#define MHz(x) KHz(1000*x)
60
61/* store information about an Ixxx DVO */
62/* The i830->i865 use multiple DVOs with multiple i2cs */
63/* the i915, i945 have a single sDVO i2c bus - which is different */
64#define MAX_OUTPUTS 6
65/* maximum connectors per crtcs in the mode set */
66#define INTELFB_CONN_LIMIT 4
67
68#define INTEL_I2C_BUS_DVO 1
69#define INTEL_I2C_BUS_SDVO 2
70
71/* these are outputs from the chip - integrated only
72 external chips are via DVO or SDVO output */
73#define INTEL_OUTPUT_UNUSED 0
74#define INTEL_OUTPUT_ANALOG 1
75#define INTEL_OUTPUT_DVO 2
76#define INTEL_OUTPUT_SDVO 3
77#define INTEL_OUTPUT_LVDS 4
78#define INTEL_OUTPUT_TVOUT 5
79#define INTEL_OUTPUT_HDMI 6
80#define INTEL_OUTPUT_DISPLAYPORT 7
81#define INTEL_OUTPUT_EDP 8
82
83/* Intel Pipe Clone Bit */
84#define INTEL_HDMIB_CLONE_BIT 1
85#define INTEL_HDMIC_CLONE_BIT 2
86#define INTEL_HDMID_CLONE_BIT 3
87#define INTEL_HDMIE_CLONE_BIT 4
88#define INTEL_HDMIF_CLONE_BIT 5
89#define INTEL_SDVO_NON_TV_CLONE_BIT 6
90#define INTEL_SDVO_TV_CLONE_BIT 7
91#define INTEL_SDVO_LVDS_CLONE_BIT 8
92#define INTEL_ANALOG_CLONE_BIT 9
93#define INTEL_TV_CLONE_BIT 10
94#define INTEL_DP_B_CLONE_BIT 11
95#define INTEL_DP_C_CLONE_BIT 12
96#define INTEL_DP_D_CLONE_BIT 13
97#define INTEL_LVDS_CLONE_BIT 14
98#define INTEL_DVO_TMDS_CLONE_BIT 15
99#define INTEL_DVO_LVDS_CLONE_BIT 16
100#define INTEL_EDP_CLONE_BIT 17
101
102#define INTEL_DVO_CHIP_NONE 0
103#define INTEL_DVO_CHIP_LVDS 1
104#define INTEL_DVO_CHIP_TMDS 2
105#define INTEL_DVO_CHIP_TVOUT 4
106
107/* drm_display_mode->private_flags */
108#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
109#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
110#define INTEL_MODE_DP_FORCE_6BPC (0x10)
111/* This flag must be set by the encoder's mode_fixup if it changes the crtc
112 * timings in the mode to prevent the crtc fixup from overwriting them.
113 * Currently only lvds needs that. */
114#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
115
116static inline void
117intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
118 int multiplier)
119{
120 mode->clock *= multiplier;
121 mode->private_flags |= multiplier;
122}
123
124static inline int
125intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
126{
127 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
128}
129
130struct intel_framebuffer {
131 struct drm_framebuffer base;
132 struct drm_i915_gem_object *obj;
133};
134
135struct intel_fbdev {
136 struct drm_fb_helper helper;
137 struct intel_framebuffer ifb;
138 struct list_head fbdev_list;
139 struct drm_display_mode *our_mode;
140};
141
142struct intel_encoder {
143 struct drm_encoder base;
144 int type;
145 bool needs_tv_clock;
146 void (*hot_plug)(struct intel_encoder *);
147 int crtc_mask;
148 int clone_mask;
149};
150
151struct intel_connector {
152 struct drm_connector base;
153 struct intel_encoder *encoder;
154};
155
156struct intel_crtc {
157 struct drm_crtc base;
158 enum pipe pipe;
159 enum plane plane;
160 u8 lut_r[256], lut_g[256], lut_b[256];
161 int dpms_mode;
162 bool active; /* is the crtc on? independent of the dpms mode */
163 bool busy; /* is scanout buffer being updated frequently? */
164 struct callout idle_callout;
165 bool lowfreq_avail;
166 struct intel_overlay *overlay;
167 struct intel_unpin_work *unpin_work;
168 int fdi_lanes;
169
170 struct drm_i915_gem_object *cursor_bo;
171 uint32_t cursor_addr;
172 int16_t cursor_x, cursor_y;
173 int16_t cursor_width, cursor_height;
174 bool cursor_visible;
175 unsigned int bpp;
176
177 bool no_pll; /* tertiary pipe for IVB */
178 bool use_pll_a;
179};
180
181struct intel_plane {
182 struct drm_plane base;
183 enum pipe pipe;
184 struct drm_i915_gem_object *obj;
185 bool primary_disabled;
186 int max_downscale;
187 u32 lut_r[1024], lut_g[1024], lut_b[1024];
188 void (*update_plane)(struct drm_plane *plane,
189 struct drm_framebuffer *fb,
190 struct drm_i915_gem_object *obj,
191 int crtc_x, int crtc_y,
192 unsigned int crtc_w, unsigned int crtc_h,
193 uint32_t x, uint32_t y,
194 uint32_t src_w, uint32_t src_h);
195 void (*disable_plane)(struct drm_plane *plane);
196 int (*update_colorkey)(struct drm_plane *plane,
197 struct drm_intel_sprite_colorkey *key);
198 void (*get_colorkey)(struct drm_plane *plane,
199 struct drm_intel_sprite_colorkey *key);
200};
201
202#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
203#define to_intel_connector(x) container_of(x, struct intel_connector, base)
204#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
205#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
206#define to_intel_plane(x) container_of(x, struct intel_plane, base)
207
208#define DIP_HEADER_SIZE 5
209
210#define DIP_TYPE_AVI 0x82
211#define DIP_VERSION_AVI 0x2
212#define DIP_LEN_AVI 13
213
214#define DIP_TYPE_SPD 0x83
215#define DIP_VERSION_SPD 0x1
216#define DIP_LEN_SPD 25
217#define DIP_SPD_UNKNOWN 0
218#define DIP_SPD_DSTB 0x1
219#define DIP_SPD_DVDP 0x2
220#define DIP_SPD_DVHS 0x3
221#define DIP_SPD_HDDVR 0x4
222#define DIP_SPD_DVC 0x5
223#define DIP_SPD_DSC 0x6
224#define DIP_SPD_VCD 0x7
225#define DIP_SPD_GAME 0x8
226#define DIP_SPD_PC 0x9
227#define DIP_SPD_BD 0xa
228#define DIP_SPD_SCD 0xb
229
230struct dip_infoframe {
231 uint8_t type; /* HB0 */
232 uint8_t ver; /* HB1 */
233 uint8_t len; /* HB2 - body len, not including checksum */
234 uint8_t ecc; /* Header ECC */
235 uint8_t checksum; /* PB0 */
236 union {
237 struct {
238 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
239 uint8_t Y_A_B_S;
240 /* PB2 - C 7:6, M 5:4, R 3:0 */
241 uint8_t C_M_R;
242 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
243 uint8_t ITC_EC_Q_SC;
244 /* PB4 - VIC 6:0 */
245 uint8_t VIC;
246 /* PB5 - PR 3:0 */
247 uint8_t PR;
248 /* PB6 to PB13 */
249 uint16_t top_bar_end;
250 uint16_t bottom_bar_start;
251 uint16_t left_bar_end;
252 uint16_t right_bar_start;
253 } avi;
254 struct {
255 uint8_t vn[8];
256 uint8_t pd[16];
257 uint8_t sdi;
258 } spd;
259 uint8_t payload[27];
260 } __attribute__ ((packed)) body;
261} __attribute__((packed));
262
263static inline struct drm_crtc *
264intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
265{
266 struct drm_i915_private *dev_priv = dev->dev_private;
267 return dev_priv->pipe_to_crtc_mapping[pipe];
268}
269
270static inline struct drm_crtc *
271intel_get_crtc_for_plane(struct drm_device *dev, int plane)
272{
273 struct drm_i915_private *dev_priv = dev->dev_private;
274 return dev_priv->plane_to_crtc_mapping[plane];
275}
276
277struct intel_unpin_work {
278 struct task task;
279 struct drm_device *dev;
280 struct drm_i915_gem_object *old_fb_obj;
281 struct drm_i915_gem_object *pending_flip_obj;
282 struct drm_pending_vblank_event *event;
283 int pending;
284 bool enable_stall_check;
285};
286
287struct intel_fbc_work {
288 struct timeout_task task;
289 struct drm_crtc *crtc;
290 struct drm_framebuffer *fb;
291 int interval;
292};
293
294int intel_ddc_get_modes(struct drm_connector *c, device_t adapter);
295extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);
296
297extern void intel_attach_force_audio_property(struct drm_connector *connector);
298extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
299
300extern void intel_crt_init(struct drm_device *dev);
301extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
302void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
303extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
304extern void intel_dvo_init(struct drm_device *dev);
305extern void intel_tv_init(struct drm_device *dev);
306extern void intel_mark_busy(struct drm_device *dev,
307 struct drm_i915_gem_object *obj);
308extern bool intel_lvds_init(struct drm_device *dev);
309extern void intel_dp_init(struct drm_device *dev, int dp_reg);
310void
311intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
312 struct drm_display_mode *adjusted_mode);
313extern bool intel_dpd_is_edp(struct drm_device *dev);
314extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
315extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
316extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
317
318/* intel_panel.c */
319extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
320 struct drm_display_mode *adjusted_mode);
321extern void intel_pch_panel_fitting(struct drm_device *dev,
322 int fitting_mode,
|
323 struct drm_display_mode *mode,
| 323 const struct drm_display_mode *mode,
|
324 struct drm_display_mode *adjusted_mode);
325extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
326extern u32 intel_panel_get_backlight(struct drm_device *dev);
327extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
328extern int intel_panel_setup_backlight(struct drm_device *dev);
329extern void intel_panel_enable_backlight(struct drm_device *dev);
330extern void intel_panel_disable_backlight(struct drm_device *dev);
331extern void intel_panel_destroy_backlight(struct drm_device *dev);
332extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
333
334extern void intel_crtc_load_lut(struct drm_crtc *crtc);
335extern void intel_encoder_prepare(struct drm_encoder *encoder);
336extern void intel_encoder_commit(struct drm_encoder *encoder);
337extern void intel_encoder_destroy(struct drm_encoder *encoder);
338
339static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
340{
341 return to_intel_connector(connector)->encoder;
342}
343
344extern void intel_connector_attach_encoder(struct intel_connector *connector,
345 struct intel_encoder *encoder);
346extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
347
348extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
349 struct drm_crtc *crtc);
350int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
351 struct drm_file *file_priv);
352extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
353extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
354
355struct intel_load_detect_pipe {
356 struct drm_framebuffer *release_fb;
357 bool load_detect_temp;
358 int dpms_mode;
359};
360extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
361 struct drm_connector *connector,
362 struct drm_display_mode *mode,
363 struct intel_load_detect_pipe *old);
364extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
365 struct drm_connector *connector,
366 struct intel_load_detect_pipe *old);
367
368extern void intelfb_restore(void);
369extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
370 u16 blue, int regno);
371extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
372 u16 *blue, int regno);
373extern void intel_enable_clock_gating(struct drm_device *dev);
374extern void ironlake_enable_drps(struct drm_device *dev);
375extern void ironlake_disable_drps(struct drm_device *dev);
376extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
377extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
378extern void gen6_disable_rps(struct drm_device *dev);
379extern void intel_init_emon(struct drm_device *dev);
380
381extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
382 struct drm_i915_gem_object *obj,
383 struct intel_ring_buffer *pipelined);
384extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
385
386extern int intel_framebuffer_init(struct drm_device *dev,
387 struct intel_framebuffer *ifb,
388 struct drm_mode_fb_cmd2 *mode_cmd,
389 struct drm_i915_gem_object *obj);
390extern int intel_fbdev_init(struct drm_device *dev);
391extern void intel_fbdev_fini(struct drm_device *dev);
392
393extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
394extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
395extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
396
397extern void intel_setup_overlay(struct drm_device *dev);
398extern void intel_cleanup_overlay(struct drm_device *dev);
399extern int intel_overlay_switch_off(struct intel_overlay *overlay);
400extern int intel_overlay_put_image(struct drm_device *dev, void *data,
401 struct drm_file *file_priv);
402extern int intel_overlay_attrs(struct drm_device *dev, void *data,
403 struct drm_file *file_priv);
404
405extern void intel_fb_output_poll_changed(struct drm_device *dev);
406extern void intel_fb_restore_mode(struct drm_device *dev);
407
408extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
409 bool state);
410#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
411#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
412
413extern void intel_init_clock_gating(struct drm_device *dev);
414extern void intel_write_eld(struct drm_encoder *encoder,
415 struct drm_display_mode *mode);
416extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
417
418/* For use by IVB LP watermark workaround in intel_sprite.c */
419extern void sandybridge_update_wm(struct drm_device *dev);
420extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
421 uint32_t sprite_width,
422 int pixel_size);
423extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
424 struct drm_file *file_priv);
425extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
426 struct drm_file *file_priv);
427
428#endif
| 324 struct drm_display_mode *adjusted_mode);
325extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
326extern u32 intel_panel_get_backlight(struct drm_device *dev);
327extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
328extern int intel_panel_setup_backlight(struct drm_device *dev);
329extern void intel_panel_enable_backlight(struct drm_device *dev);
330extern void intel_panel_disable_backlight(struct drm_device *dev);
331extern void intel_panel_destroy_backlight(struct drm_device *dev);
332extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
333
334extern void intel_crtc_load_lut(struct drm_crtc *crtc);
335extern void intel_encoder_prepare(struct drm_encoder *encoder);
336extern void intel_encoder_commit(struct drm_encoder *encoder);
337extern void intel_encoder_destroy(struct drm_encoder *encoder);
338
339static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
340{
341 return to_intel_connector(connector)->encoder;
342}
343
344extern void intel_connector_attach_encoder(struct intel_connector *connector,
345 struct intel_encoder *encoder);
346extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
347
348extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
349 struct drm_crtc *crtc);
350int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
351 struct drm_file *file_priv);
352extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
353extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
354
355struct intel_load_detect_pipe {
356 struct drm_framebuffer *release_fb;
357 bool load_detect_temp;
358 int dpms_mode;
359};
360extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
361 struct drm_connector *connector,
362 struct drm_display_mode *mode,
363 struct intel_load_detect_pipe *old);
364extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
365 struct drm_connector *connector,
366 struct intel_load_detect_pipe *old);
367
368extern void intelfb_restore(void);
369extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
370 u16 blue, int regno);
371extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
372 u16 *blue, int regno);
373extern void intel_enable_clock_gating(struct drm_device *dev);
374extern void ironlake_enable_drps(struct drm_device *dev);
375extern void ironlake_disable_drps(struct drm_device *dev);
376extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
377extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
378extern void gen6_disable_rps(struct drm_device *dev);
379extern void intel_init_emon(struct drm_device *dev);
380
381extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
382 struct drm_i915_gem_object *obj,
383 struct intel_ring_buffer *pipelined);
384extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
385
386extern int intel_framebuffer_init(struct drm_device *dev,
387 struct intel_framebuffer *ifb,
388 struct drm_mode_fb_cmd2 *mode_cmd,
389 struct drm_i915_gem_object *obj);
390extern int intel_fbdev_init(struct drm_device *dev);
391extern void intel_fbdev_fini(struct drm_device *dev);
392
393extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
394extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
395extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
396
397extern void intel_setup_overlay(struct drm_device *dev);
398extern void intel_cleanup_overlay(struct drm_device *dev);
399extern int intel_overlay_switch_off(struct intel_overlay *overlay);
400extern int intel_overlay_put_image(struct drm_device *dev, void *data,
401 struct drm_file *file_priv);
402extern int intel_overlay_attrs(struct drm_device *dev, void *data,
403 struct drm_file *file_priv);
404
405extern void intel_fb_output_poll_changed(struct drm_device *dev);
406extern void intel_fb_restore_mode(struct drm_device *dev);
407
408extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
409 bool state);
410#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
411#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
412
413extern void intel_init_clock_gating(struct drm_device *dev);
414extern void intel_write_eld(struct drm_encoder *encoder,
415 struct drm_display_mode *mode);
416extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
417
418/* For use by IVB LP watermark workaround in intel_sprite.c */
419extern void sandybridge_update_wm(struct drm_device *dev);
420extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
421 uint32_t sprite_width,
422 int pixel_size);
423extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
424 struct drm_file *file_priv);
425extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
426 struct drm_file *file_priv);
427
428#endif
|