29
30#include <dev/drm2/drmP.h>
31#include <dev/drm2/drm.h>
32#include <dev/drm2/i915/i915_drm.h>
33#include <dev/drm2/i915/i915_drv.h>
34#include <dev/drm2/i915/intel_drv.h>
35#include <dev/drm2/drm_edid.h>
36#include <dev/drm2/drm_dp_helper.h>
37#include <dev/drm2/drm_crtc_helper.h>
38#include <sys/kdb.h>
39#include <sys/limits.h>
40
41#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
42
43bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
44static void intel_update_watermarks(struct drm_device *dev);
45static void intel_increase_pllclock(struct drm_crtc *crtc);
46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58} intel_clock_t;
59
60typedef struct {
61 int min, max;
62} intel_range_t;
63
64typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
76};
77
78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
81static bool
82intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
83 int target, int refclk, intel_clock_t *match_clock,
84 intel_clock_t *best_clock);
85static bool
86intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *match_clock,
88 intel_clock_t *best_clock);
89
90static bool
91intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *match_clock,
93 intel_clock_t *best_clock);
94static bool
95intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *match_clock,
97 intel_clock_t *best_clock);
98
99static inline u32 /* units of 100MHz */
100intel_fdi_link_freq(struct drm_device *dev)
101{
102 if (IS_GEN5(dev)) {
103 struct drm_i915_private *dev_priv = dev->dev_private;
104 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
105 } else
106 return 27;
107}
108
109static const intel_limit_t intel_limits_i8xx_dvo = {
110 .dot = { .min = 25000, .max = 350000 },
111 .vco = { .min = 930000, .max = 1400000 },
112 .n = { .min = 3, .max = 16 },
113 .m = { .min = 96, .max = 140 },
114 .m1 = { .min = 18, .max = 26 },
115 .m2 = { .min = 6, .max = 16 },
116 .p = { .min = 4, .max = 128 },
117 .p1 = { .min = 2, .max = 33 },
118 .p2 = { .dot_limit = 165000,
119 .p2_slow = 4, .p2_fast = 2 },
120 .find_pll = intel_find_best_PLL,
121};
122
123static const intel_limit_t intel_limits_i8xx_lvds = {
124 .dot = { .min = 25000, .max = 350000 },
125 .vco = { .min = 930000, .max = 1400000 },
126 .n = { .min = 3, .max = 16 },
127 .m = { .min = 96, .max = 140 },
128 .m1 = { .min = 18, .max = 26 },
129 .m2 = { .min = 6, .max = 16 },
130 .p = { .min = 4, .max = 128 },
131 .p1 = { .min = 1, .max = 6 },
132 .p2 = { .dot_limit = 165000,
133 .p2_slow = 14, .p2_fast = 7 },
134 .find_pll = intel_find_best_PLL,
135};
136
137static const intel_limit_t intel_limits_i9xx_sdvo = {
138 .dot = { .min = 20000, .max = 400000 },
139 .vco = { .min = 1400000, .max = 2800000 },
140 .n = { .min = 1, .max = 6 },
141 .m = { .min = 70, .max = 120 },
142 .m1 = { .min = 10, .max = 22 },
143 .m2 = { .min = 5, .max = 9 },
144 .p = { .min = 5, .max = 80 },
145 .p1 = { .min = 1, .max = 8 },
146 .p2 = { .dot_limit = 200000,
147 .p2_slow = 10, .p2_fast = 5 },
148 .find_pll = intel_find_best_PLL,
149};
150
151static const intel_limit_t intel_limits_i9xx_lvds = {
152 .dot = { .min = 20000, .max = 400000 },
153 .vco = { .min = 1400000, .max = 2800000 },
154 .n = { .min = 1, .max = 6 },
155 .m = { .min = 70, .max = 120 },
156 .m1 = { .min = 10, .max = 22 },
157 .m2 = { .min = 5, .max = 9 },
158 .p = { .min = 7, .max = 98 },
159 .p1 = { .min = 1, .max = 8 },
160 .p2 = { .dot_limit = 112000,
161 .p2_slow = 14, .p2_fast = 7 },
162 .find_pll = intel_find_best_PLL,
163};
164
165
166static const intel_limit_t intel_limits_g4x_sdvo = {
167 .dot = { .min = 25000, .max = 270000 },
168 .vco = { .min = 1750000, .max = 3500000},
169 .n = { .min = 1, .max = 4 },
170 .m = { .min = 104, .max = 138 },
171 .m1 = { .min = 17, .max = 23 },
172 .m2 = { .min = 5, .max = 11 },
173 .p = { .min = 10, .max = 30 },
174 .p1 = { .min = 1, .max = 3},
175 .p2 = { .dot_limit = 270000,
176 .p2_slow = 10,
177 .p2_fast = 10
178 },
179 .find_pll = intel_g4x_find_best_PLL,
180};
181
182static const intel_limit_t intel_limits_g4x_hdmi = {
183 .dot = { .min = 22000, .max = 400000 },
184 .vco = { .min = 1750000, .max = 3500000},
185 .n = { .min = 1, .max = 4 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 16, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 5, .max = 80 },
190 .p1 = { .min = 1, .max = 8},
191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 10, .p2_fast = 5 },
193 .find_pll = intel_g4x_find_best_PLL,
194};
195
196static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
197 .dot = { .min = 20000, .max = 115000 },
198 .vco = { .min = 1750000, .max = 3500000 },
199 .n = { .min = 1, .max = 3 },
200 .m = { .min = 104, .max = 138 },
201 .m1 = { .min = 17, .max = 23 },
202 .m2 = { .min = 5, .max = 11 },
203 .p = { .min = 28, .max = 112 },
204 .p1 = { .min = 2, .max = 8 },
205 .p2 = { .dot_limit = 0,
206 .p2_slow = 14, .p2_fast = 14
207 },
208 .find_pll = intel_g4x_find_best_PLL,
209};
210
211static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
212 .dot = { .min = 80000, .max = 224000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 14, .max = 42 },
219 .p1 = { .min = 2, .max = 6 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 7, .p2_fast = 7
222 },
223 .find_pll = intel_g4x_find_best_PLL,
224};
225
226static const intel_limit_t intel_limits_g4x_display_port = {
227 .dot = { .min = 161670, .max = 227000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 2 },
230 .m = { .min = 97, .max = 108 },
231 .m1 = { .min = 0x10, .max = 0x12 },
232 .m2 = { .min = 0x05, .max = 0x06 },
233 .p = { .min = 10, .max = 20 },
234 .p1 = { .min = 1, .max = 2},
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 10, .p2_fast = 10 },
237 .find_pll = intel_find_pll_g4x_dp,
238};
239
240static const intel_limit_t intel_limits_pineview_sdvo = {
241 .dot = { .min = 20000, .max = 400000},
242 .vco = { .min = 1700000, .max = 3500000 },
243 /* Pineview's Ncounter is a ring counter */
244 .n = { .min = 3, .max = 6 },
245 .m = { .min = 2, .max = 256 },
246 /* Pineview only has one combined m divider, which we treat as m2. */
247 .m1 = { .min = 0, .max = 0 },
248 .m2 = { .min = 0, .max = 254 },
249 .p = { .min = 5, .max = 80 },
250 .p1 = { .min = 1, .max = 8 },
251 .p2 = { .dot_limit = 200000,
252 .p2_slow = 10, .p2_fast = 5 },
253 .find_pll = intel_find_best_PLL,
254};
255
256static const intel_limit_t intel_limits_pineview_lvds = {
257 .dot = { .min = 20000, .max = 400000 },
258 .vco = { .min = 1700000, .max = 3500000 },
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 .m1 = { .min = 0, .max = 0 },
262 .m2 = { .min = 0, .max = 254 },
263 .p = { .min = 7, .max = 112 },
264 .p1 = { .min = 1, .max = 8 },
265 .p2 = { .dot_limit = 112000,
266 .p2_slow = 14, .p2_fast = 14 },
267 .find_pll = intel_find_best_PLL,
268};
269
270/* Ironlake / Sandybridge
271 *
272 * We calculate clock using (register_value + 2) for N/M1/M2, so here
273 * the range value for them is (actual_value - 2).
274 */
275static const intel_limit_t intel_limits_ironlake_dac = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 1760000, .max = 3510000 },
278 .n = { .min = 1, .max = 5 },
279 .m = { .min = 79, .max = 127 },
280 .m1 = { .min = 12, .max = 22 },
281 .m2 = { .min = 5, .max = 9 },
282 .p = { .min = 5, .max = 80 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 225000,
285 .p2_slow = 10, .p2_fast = 5 },
286 .find_pll = intel_g4x_find_best_PLL,
287};
288
289static const intel_limit_t intel_limits_ironlake_single_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 1760000, .max = 3510000 },
292 .n = { .min = 1, .max = 3 },
293 .m = { .min = 79, .max = 118 },
294 .m1 = { .min = 12, .max = 22 },
295 .m2 = { .min = 5, .max = 9 },
296 .p = { .min = 28, .max = 112 },
297 .p1 = { .min = 2, .max = 8 },
298 .p2 = { .dot_limit = 225000,
299 .p2_slow = 14, .p2_fast = 14 },
300 .find_pll = intel_g4x_find_best_PLL,
301};
302
303static const intel_limit_t intel_limits_ironlake_dual_lvds = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 56 },
311 .p1 = { .min = 2, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
314 .find_pll = intel_g4x_find_best_PLL,
315};
316
317/* LVDS 100mhz refclk limits. */
318static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 2 },
322 .m = { .min = 79, .max = 126 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 14, .p2_fast = 14 },
329 .find_pll = intel_g4x_find_best_PLL,
330};
331
332static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
333 .dot = { .min = 25000, .max = 350000 },
334 .vco = { .min = 1760000, .max = 3510000 },
335 .n = { .min = 1, .max = 3 },
336 .m = { .min = 79, .max = 126 },
337 .m1 = { .min = 12, .max = 22 },
338 .m2 = { .min = 5, .max = 9 },
339 .p = { .min = 14, .max = 42 },
340 .p1 = { .min = 2, .max = 6 },
341 .p2 = { .dot_limit = 225000,
342 .p2_slow = 7, .p2_fast = 7 },
343 .find_pll = intel_g4x_find_best_PLL,
344};
345
346static const intel_limit_t intel_limits_ironlake_display_port = {
347 .dot = { .min = 25000, .max = 350000 },
348 .vco = { .min = 1760000, .max = 3510000},
349 .n = { .min = 1, .max = 2 },
350 .m = { .min = 81, .max = 90 },
351 .m1 = { .min = 12, .max = 22 },
352 .m2 = { .min = 5, .max = 9 },
353 .p = { .min = 10, .max = 20 },
354 .p1 = { .min = 1, .max = 2},
355 .p2 = { .dot_limit = 0,
356 .p2_slow = 10, .p2_fast = 10 },
357 .find_pll = intel_find_pll_ironlake_dp,
358};
359
360static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
361 int refclk)
362{
363 struct drm_device *dev = crtc->dev;
364 struct drm_i915_private *dev_priv = dev->dev_private;
365 const intel_limit_t *limit;
366
367 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
368 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
369 LVDS_CLKB_POWER_UP) {
370 /* LVDS dual channel */
371 if (refclk == 100000)
372 limit = &intel_limits_ironlake_dual_lvds_100m;
373 else
374 limit = &intel_limits_ironlake_dual_lvds;
375 } else {
376 if (refclk == 100000)
377 limit = &intel_limits_ironlake_single_lvds_100m;
378 else
379 limit = &intel_limits_ironlake_single_lvds;
380 }
381 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
382 HAS_eDP)
383 limit = &intel_limits_ironlake_display_port;
384 else
385 limit = &intel_limits_ironlake_dac;
386
387 return limit;
388}
389
390static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
391{
392 struct drm_device *dev = crtc->dev;
393 struct drm_i915_private *dev_priv = dev->dev_private;
394 const intel_limit_t *limit;
395
396 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
397 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
398 LVDS_CLKB_POWER_UP)
399 /* LVDS with dual channel */
400 limit = &intel_limits_g4x_dual_channel_lvds;
401 else
402 /* LVDS with dual channel */
403 limit = &intel_limits_g4x_single_channel_lvds;
404 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
405 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
406 limit = &intel_limits_g4x_hdmi;
407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
408 limit = &intel_limits_g4x_sdvo;
409 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
410 limit = &intel_limits_g4x_display_port;
411 } else /* The option is for other outputs */
412 limit = &intel_limits_i9xx_sdvo;
413
414 return limit;
415}
416
417static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
418{
419 struct drm_device *dev = crtc->dev;
420 const intel_limit_t *limit;
421
422 if (HAS_PCH_SPLIT(dev))
423 limit = intel_ironlake_limit(crtc, refclk);
424 else if (IS_G4X(dev)) {
425 limit = intel_g4x_limit(crtc);
426 } else if (IS_PINEVIEW(dev)) {
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
428 limit = &intel_limits_pineview_lvds;
429 else
430 limit = &intel_limits_pineview_sdvo;
431 } else if (!IS_GEN2(dev)) {
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
433 limit = &intel_limits_i9xx_lvds;
434 else
435 limit = &intel_limits_i9xx_sdvo;
436 } else {
437 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
438 limit = &intel_limits_i8xx_lvds;
439 else
440 limit = &intel_limits_i8xx_dvo;
441 }
442 return limit;
443}
444
445/* m1 is reserved as 0 in Pineview, n is a ring counter */
446static void pineview_clock(int refclk, intel_clock_t *clock)
447{
448 clock->m = clock->m2 + 2;
449 clock->p = clock->p1 * clock->p2;
450 clock->vco = refclk * clock->m / clock->n;
451 clock->dot = clock->vco / clock->p;
452}
453
454static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
455{
456 if (IS_PINEVIEW(dev)) {
457 pineview_clock(refclk, clock);
458 return;
459 }
460 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
461 clock->p = clock->p1 * clock->p2;
462 clock->vco = refclk * clock->m / (clock->n + 2);
463 clock->dot = clock->vco / clock->p;
464}
465
466/**
467 * Returns whether any output on the specified pipe is of the specified type
468 */
469bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
470{
471 struct drm_device *dev = crtc->dev;
472 struct drm_mode_config *mode_config = &dev->mode_config;
473 struct intel_encoder *encoder;
474
475 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
476 if (encoder->base.crtc == crtc && encoder->type == type)
477 return true;
478
479 return false;
480}
481
482#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
483/**
484 * Returns whether the given set of divisors are valid for a given refclk with
485 * the given connectors.
486 */
487
488static bool intel_PLL_is_valid(struct drm_device *dev,
489 const intel_limit_t *limit,
490 const intel_clock_t *clock)
491{
492 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
493 INTELPllInvalid("p1 out of range\n");
494 if (clock->p < limit->p.min || limit->p.max < clock->p)
495 INTELPllInvalid("p out of range\n");
496 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
497 INTELPllInvalid("m2 out of range\n");
498 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
499 INTELPllInvalid("m1 out of range\n");
500 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
501 INTELPllInvalid("m1 <= m2\n");
502 if (clock->m < limit->m.min || limit->m.max < clock->m)
503 INTELPllInvalid("m out of range\n");
504 if (clock->n < limit->n.min || limit->n.max < clock->n)
505 INTELPllInvalid("n out of range\n");
506 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
507 INTELPllInvalid("vco out of range\n");
508 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
509 * connector, etc., rather than just a single range.
510 */
511 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
512 INTELPllInvalid("dot out of range\n");
513
514 return true;
515}
516
517static bool
518intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
519 int target, int refclk, intel_clock_t *match_clock,
520 intel_clock_t *best_clock)
521
522{
523 struct drm_device *dev = crtc->dev;
524 struct drm_i915_private *dev_priv = dev->dev_private;
525 intel_clock_t clock;
526 int err = target;
527
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
529 (I915_READ(LVDS)) != 0) {
530 /*
531 * For LVDS, if the panel is on, just rely on its current
532 * settings for dual-channel. We haven't figured out how to
533 * reliably set up different single/dual channel state, if we
534 * even can.
535 */
536 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
537 LVDS_CLKB_POWER_UP)
538 clock.p2 = limit->p2.p2_fast;
539 else
540 clock.p2 = limit->p2.p2_slow;
541 } else {
542 if (target < limit->p2.dot_limit)
543 clock.p2 = limit->p2.p2_slow;
544 else
545 clock.p2 = limit->p2.p2_fast;
546 }
547
548 memset(best_clock, 0, sizeof(*best_clock));
549
550 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
551 clock.m1++) {
552 for (clock.m2 = limit->m2.min;
553 clock.m2 <= limit->m2.max; clock.m2++) {
554 /* m1 is always 0 in Pineview */
555 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
556 break;
557 for (clock.n = limit->n.min;
558 clock.n <= limit->n.max; clock.n++) {
559 for (clock.p1 = limit->p1.min;
560 clock.p1 <= limit->p1.max; clock.p1++) {
561 int this_err;
562
563 intel_clock(dev, refclk, &clock);
564 if (!intel_PLL_is_valid(dev, limit,
565 &clock))
566 continue;
567 if (match_clock &&
568 clock.p != match_clock->p)
569 continue;
570
571 this_err = abs(clock.dot - target);
572 if (this_err < err) {
573 *best_clock = clock;
574 err = this_err;
575 }
576 }
577 }
578 }
579 }
580
581 return (err != target);
582}
583
584static bool
585intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
586 int target, int refclk, intel_clock_t *match_clock,
587 intel_clock_t *best_clock)
588{
589 struct drm_device *dev = crtc->dev;
590 struct drm_i915_private *dev_priv = dev->dev_private;
591 intel_clock_t clock;
592 int max_n;
593 bool found;
594 /* approximately equals target * 0.00585 */
595 int err_most = (target >> 8) + (target >> 9);
596 found = false;
597
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
599 int lvds_reg;
600
601 if (HAS_PCH_SPLIT(dev))
602 lvds_reg = PCH_LVDS;
603 else
604 lvds_reg = LVDS;
605 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
606 LVDS_CLKB_POWER_UP)
607 clock.p2 = limit->p2.p2_fast;
608 else
609 clock.p2 = limit->p2.p2_slow;
610 } else {
611 if (target < limit->p2.dot_limit)
612 clock.p2 = limit->p2.p2_slow;
613 else
614 clock.p2 = limit->p2.p2_fast;
615 }
616
617 memset(best_clock, 0, sizeof(*best_clock));
618 max_n = limit->n.max;
619 /* based on hardware requirement, prefer smaller n to precision */
620 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
621 /* based on hardware requirement, prefere larger m1,m2 */
622 for (clock.m1 = limit->m1.max;
623 clock.m1 >= limit->m1.min; clock.m1--) {
624 for (clock.m2 = limit->m2.max;
625 clock.m2 >= limit->m2.min; clock.m2--) {
626 for (clock.p1 = limit->p1.max;
627 clock.p1 >= limit->p1.min; clock.p1--) {
628 int this_err;
629
630 intel_clock(dev, refclk, &clock);
631 if (!intel_PLL_is_valid(dev, limit,
632 &clock))
633 continue;
634 if (match_clock &&
635 clock.p != match_clock->p)
636 continue;
637
638 this_err = abs(clock.dot - target);
639 if (this_err < err_most) {
640 *best_clock = clock;
641 err_most = this_err;
642 max_n = clock.n;
643 found = true;
644 }
645 }
646 }
647 }
648 }
649 return found;
650}
651
652static bool
653intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
654 int target, int refclk, intel_clock_t *match_clock,
655 intel_clock_t *best_clock)
656{
657 struct drm_device *dev = crtc->dev;
658 intel_clock_t clock;
659
660 if (target < 200000) {
661 clock.n = 1;
662 clock.p1 = 2;
663 clock.p2 = 10;
664 clock.m1 = 12;
665 clock.m2 = 9;
666 } else {
667 clock.n = 2;
668 clock.p1 = 1;
669 clock.p2 = 10;
670 clock.m1 = 14;
671 clock.m2 = 8;
672 }
673 intel_clock(dev, refclk, &clock);
674 memcpy(best_clock, &clock, sizeof(intel_clock_t));
675 return true;
676}
677
678/* DisplayPort has only two frequencies, 162MHz and 270MHz */
679static bool
680intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
681 int target, int refclk, intel_clock_t *match_clock,
682 intel_clock_t *best_clock)
683{
684 intel_clock_t clock;
685 if (target < 200000) {
686 clock.p1 = 2;
687 clock.p2 = 10;
688 clock.n = 2;
689 clock.m1 = 23;
690 clock.m2 = 8;
691 } else {
692 clock.p1 = 1;
693 clock.p2 = 10;
694 clock.n = 1;
695 clock.m1 = 14;
696 clock.m2 = 2;
697 }
698 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
699 clock.p = (clock.p1 * clock.p2);
700 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
701 clock.vco = 0;
702 memcpy(best_clock, &clock, sizeof(intel_clock_t));
703 return true;
704}
705
706/**
707 * intel_wait_for_vblank - wait for vblank on a given pipe
708 * @dev: drm device
709 * @pipe: pipe to wait for
710 *
711 * Wait for vblank to occur on a given pipe. Needed for various bits of
712 * mode setting code.
713 */
714void intel_wait_for_vblank(struct drm_device *dev, int pipe)
715{
716 struct drm_i915_private *dev_priv = dev->dev_private;
717 int pipestat_reg = PIPESTAT(pipe);
718
719 /* Clear existing vblank status. Note this will clear any other
720 * sticky status fields as well.
721 *
722 * This races with i915_driver_irq_handler() with the result
723 * that either function could miss a vblank event. Here it is not
724 * fatal, as we will either wait upon the next vblank interrupt or
725 * timeout. Generally speaking intel_wait_for_vblank() is only
726 * called during modeset at which time the GPU should be idle and
727 * should *not* be performing page flips and thus not waiting on
728 * vblanks...
729 * Currently, the result of us stealing a vblank from the irq
730 * handler is that a single frame will be skipped during swapbuffers.
731 */
732 I915_WRITE(pipestat_reg,
733 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
734
735 /* Wait for vblank interrupt bit to set */
736 if (_intel_wait_for(dev,
737 I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS,
738 50, 1, "915vbl"))
739 DRM_DEBUG_KMS("vblank wait timed out\n");
740}
741
742/*
743 * intel_wait_for_pipe_off - wait for pipe to turn off
744 * @dev: drm device
745 * @pipe: pipe to wait for
746 *
747 * After disabling a pipe, we can't wait for vblank in the usual way,
748 * spinning on the vblank interrupt status bit, since we won't actually
749 * see an interrupt when the pipe is disabled.
750 *
751 * On Gen4 and above:
752 * wait for the pipe register state bit to turn off
753 *
754 * Otherwise:
755 * wait for the display line value to settle (it usually
756 * ends up stopping at the start of the next frame).
757 *
758 */
759void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
760{
761 struct drm_i915_private *dev_priv = dev->dev_private;
762
763 if (INTEL_INFO(dev)->gen >= 4) {
764 int reg = PIPECONF(pipe);
765
766 /* Wait for the Pipe State to go off */
767 if (_intel_wait_for(dev,
768 (I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 100,
769 1, "915pip"))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
771 } else {
772 u32 last_line;
773 int reg = PIPEDSL(pipe);
774 unsigned long timeout = jiffies + msecs_to_jiffies(100);
775
776 /* Wait for the display line to settle */
777 do {
778 last_line = I915_READ(reg) & DSL_LINEMASK;
779 DELAY(5000);
780 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
781 time_after(timeout, jiffies));
782 if (time_after(jiffies, timeout))
783 DRM_DEBUG_KMS("pipe_off wait timed out\n");
784 }
785}
786
787static const char *state_string(bool enabled)
788{
789 return enabled ? "on" : "off";
790}
791
792/* Only for pre-ILK configs */
793static void assert_pll(struct drm_i915_private *dev_priv,
794 enum pipe pipe, bool state)
795{
796 int reg;
797 u32 val;
798 bool cur_state;
799
800 reg = DPLL(pipe);
801 val = I915_READ(reg);
802 cur_state = !!(val & DPLL_VCO_ENABLE);
803 if (cur_state != state)
804 printf("PLL state assertion failure (expected %s, current %s)\n",
805 state_string(state), state_string(cur_state));
806}
807#define assert_pll_enabled(d, p) assert_pll(d, p, true)
808#define assert_pll_disabled(d, p) assert_pll(d, p, false)
809
810/* For ILK+ */
811static void assert_pch_pll(struct drm_i915_private *dev_priv,
812 enum pipe pipe, bool state)
813{
814 int reg;
815 u32 val;
816 bool cur_state;
817
818 if (HAS_PCH_CPT(dev_priv->dev)) {
819 u32 pch_dpll;
820
821 pch_dpll = I915_READ(PCH_DPLL_SEL);
822
823 /* Make sure the selected PLL is enabled to the transcoder */
824 KASSERT(((pch_dpll >> (4 * pipe)) & 8) != 0,
825 ("transcoder %d PLL not enabled\n", pipe));
826
827 /* Convert the transcoder pipe number to a pll pipe number */
828 pipe = (pch_dpll >> (4 * pipe)) & 1;
829 }
830
831 reg = PCH_DPLL(pipe);
832 val = I915_READ(reg);
833 cur_state = !!(val & DPLL_VCO_ENABLE);
834 if (cur_state != state)
835 printf("PCH PLL state assertion failure (expected %s, current %s)\n",
836 state_string(state), state_string(cur_state));
837}
838#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
839#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
840
841static void assert_fdi_tx(struct drm_i915_private *dev_priv,
842 enum pipe pipe, bool state)
843{
844 int reg;
845 u32 val;
846 bool cur_state;
847
848 reg = FDI_TX_CTL(pipe);
849 val = I915_READ(reg);
850 cur_state = !!(val & FDI_TX_ENABLE);
851 if (cur_state != state)
852 printf("FDI TX state assertion failure (expected %s, current %s)\n",
853 state_string(state), state_string(cur_state));
854}
855#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
856#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
857
858static void assert_fdi_rx(struct drm_i915_private *dev_priv,
859 enum pipe pipe, bool state)
860{
861 int reg;
862 u32 val;
863 bool cur_state;
864
865 reg = FDI_RX_CTL(pipe);
866 val = I915_READ(reg);
867 cur_state = !!(val & FDI_RX_ENABLE);
868 if (cur_state != state)
869 printf("FDI RX state assertion failure (expected %s, current %s)\n",
870 state_string(state), state_string(cur_state));
871}
872#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
873#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
874
875static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
876 enum pipe pipe)
877{
878 int reg;
879 u32 val;
880
881 /* ILK FDI PLL is always enabled */
882 if (dev_priv->info->gen == 5)
883 return;
884
885 reg = FDI_TX_CTL(pipe);
886 val = I915_READ(reg);
887 if (!(val & FDI_TX_PLL_ENABLE))
888 printf("FDI TX PLL assertion failure, should be active but is disabled\n");
889}
890
891static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
892 enum pipe pipe)
893{
894 int reg;
895 u32 val;
896
897 reg = FDI_RX_CTL(pipe);
898 val = I915_READ(reg);
899 if (!(val & FDI_RX_PLL_ENABLE))
900 printf("FDI RX PLL assertion failure, should be active but is disabled\n");
901}
902
903static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905{
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
909 bool locked = true;
910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 if (panel_pipe == pipe && locked)
928 printf("panel assertion failure, pipe %c regs locked\n",
929 pipe_name(pipe));
930}
931
932void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
934{
935 int reg;
936 u32 val;
937 bool cur_state;
938
939 /* if we need the pipe A quirk it must be always on */
940 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941 state = true;
942
943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
945 cur_state = !!(val & PIPECONF_ENABLE);
946 if (cur_state != state)
947 printf("pipe %c assertion failure (expected %s, current %s)\n",
948 pipe_name(pipe), state_string(state), state_string(cur_state));
949}
950
951static void assert_plane(struct drm_i915_private *dev_priv,
952 enum plane plane, bool state)
953{
954 int reg;
955 u32 val;
956 bool cur_state;
957
958 reg = DSPCNTR(plane);
959 val = I915_READ(reg);
960 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961 if (cur_state != state)
962 printf("plane %c assertion failure, (expected %s, current %s)\n",
963 plane_name(plane), state_string(state), state_string(cur_state));
964}
965
966#define assert_plane_enabled(d, p) assert_plane(d, p, true)
967#define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
969static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971{
972 int reg, i;
973 u32 val;
974 int cur_pipe;
975
976 /* Planes are fixed to pipes on ILK+ */
977 if (HAS_PCH_SPLIT(dev_priv->dev)) {
978 reg = DSPCNTR(pipe);
979 val = I915_READ(reg);
980 if ((val & DISPLAY_PLANE_ENABLE) != 0)
981 printf("plane %c assertion failure, should be disabled but not\n",
982 plane_name(pipe));
983 return;
984 }
985
986 /* Need to check both planes against the pipe */
987 for (i = 0; i < 2; i++) {
988 reg = DSPCNTR(i);
989 val = I915_READ(reg);
990 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991 DISPPLANE_SEL_PIPE_SHIFT;
992 if ((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe)
993 printf("plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i), pipe_name(pipe));
995 }
996}
997
998static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999{
1000 u32 val;
1001 bool enabled;
1002
1003 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK));
1006 if (!enabled)
1007 printf("PCH refclk assertion failure, should be active but is disabled\n");
1008}
1009
1010static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1011 enum pipe pipe)
1012{
1013 int reg;
1014 u32 val;
1015 bool enabled;
1016
1017 reg = TRANSCONF(pipe);
1018 val = I915_READ(reg);
1019 enabled = !!(val & TRANS_ENABLE);
1020 if (enabled)
1021 printf("transcoder assertion failed, should be off on pipe %c but is still active\n",
1022 pipe_name(pipe));
1023}
1024
1025static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1026 enum pipe pipe, u32 val)
1027{
1028 if ((val & PORT_ENABLE) == 0)
1029 return false;
1030
1031 if (HAS_PCH_CPT(dev_priv->dev)) {
1032 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1033 return false;
1034 } else {
1035 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1036 return false;
1037 }
1038 return true;
1039}
1040
1041static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1042 enum pipe pipe, u32 val)
1043{
1044 if ((val & LVDS_PORT_EN) == 0)
1045 return false;
1046
1047 if (HAS_PCH_CPT(dev_priv->dev)) {
1048 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1049 return false;
1050 } else {
1051 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1052 return false;
1053 }
1054 return true;
1055}
1056
1057static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1058 enum pipe pipe, u32 val)
1059{
1060 if ((val & ADPA_DAC_ENABLE) == 0)
1061 return false;
1062 if (HAS_PCH_CPT(dev_priv->dev)) {
1063 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1064 return false;
1065 } else {
1066 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1067 return false;
1068 }
1069 return true;
1070}
1071
1072static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, u32 port_sel, u32 val)
1074{
1075 if ((val & DP_PORT_EN) == 0)
1076 return false;
1077
1078 if (HAS_PCH_CPT(dev_priv->dev)) {
1079 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1080 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1081 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1082 return false;
1083 } else {
1084 if ((val & DP_PIPE_MASK) != (pipe << 30))
1085 return false;
1086 }
1087 return true;
1088}
1089
1090static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1091 enum pipe pipe, int reg, u32 port_sel)
1092{
1093 u32 val = I915_READ(reg);
1094 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val))
1095 printf("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1096 reg, pipe_name(pipe));
1097}
1098
1099static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1100 enum pipe pipe, int reg)
1101{
1102 u32 val = I915_READ(reg);
1103 if (hdmi_pipe_enabled(dev_priv, val, pipe))
1104 printf("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1105 reg, pipe_name(pipe));
1106}
1107
1108static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1109 enum pipe pipe)
1110{
1111 int reg;
1112 u32 val;
1113
1114 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1115 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1116 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1117
1118 reg = PCH_ADPA;
1119 val = I915_READ(reg);
1120 if (adpa_pipe_enabled(dev_priv, val, pipe))
1121 printf("PCH VGA enabled on transcoder %c, should be disabled\n",
1122 pipe_name(pipe));
1123
1124 reg = PCH_LVDS;
1125 val = I915_READ(reg);
1126 if (lvds_pipe_enabled(dev_priv, val, pipe))
1127 printf("PCH LVDS enabled on transcoder %c, should be disabled\n",
1128 pipe_name(pipe));
1129
1130 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1131 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1132 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1133}
1134
1135/**
1136 * intel_enable_pll - enable a PLL
1137 * @dev_priv: i915 private structure
1138 * @pipe: pipe PLL to enable
1139 *
1140 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1141 * make sure the PLL reg is writable first though, since the panel write
1142 * protect mechanism may be enabled.
1143 *
1144 * Note! This is for pre-ILK only.
1145 */
1146static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* No really, not for ILK+ */
1152 KASSERT(dev_priv->info->gen < 5, ("Wrong device gen"));
1153
1154 /* PLL is protected by panel, make sure we can write it */
1155 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1156 assert_panel_unlocked(dev_priv, pipe);
1157
1158 reg = DPLL(pipe);
1159 val = I915_READ(reg);
1160 val |= DPLL_VCO_ENABLE;
1161
1162 /* We do this three times for luck */
1163 I915_WRITE(reg, val);
1164 POSTING_READ(reg);
1165 DELAY(150); /* wait for warmup */
1166 I915_WRITE(reg, val);
1167 POSTING_READ(reg);
1168 DELAY(150); /* wait for warmup */
1169 I915_WRITE(reg, val);
1170 POSTING_READ(reg);
1171 DELAY(150); /* wait for warmup */
1172}
1173
1174/**
1175 * intel_disable_pll - disable a PLL
1176 * @dev_priv: i915 private structure
1177 * @pipe: pipe PLL to disable
1178 *
1179 * Disable the PLL for @pipe, making sure the pipe is off first.
1180 *
1181 * Note! This is for pre-ILK only.
1182 */
1183static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1184{
1185 int reg;
1186 u32 val;
1187
1188 /* Don't disable pipe A or pipe A PLLs if needed */
1189 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1190 return;
1191
1192 /* Make sure the pipe isn't still relying on us */
1193 assert_pipe_disabled(dev_priv, pipe);
1194
1195 reg = DPLL(pipe);
1196 val = I915_READ(reg);
1197 val &= ~DPLL_VCO_ENABLE;
1198 I915_WRITE(reg, val);
1199 POSTING_READ(reg);
1200}
1201
1202/**
1203 * intel_enable_pch_pll - enable PCH PLL
1204 * @dev_priv: i915 private structure
1205 * @pipe: pipe PLL to enable
1206 *
1207 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1208 * drives the transcoder clock.
1209 */
1210static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1211 enum pipe pipe)
1212{
1213 int reg;
1214 u32 val;
1215
1216 if (pipe > 1)
1217 return;
1218
1219 /* PCH only available on ILK+ */
1220 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1221
1222 /* PCH refclock must be enabled first */
1223 assert_pch_refclk_enabled(dev_priv);
1224
1225 reg = PCH_DPLL(pipe);
1226 val = I915_READ(reg);
1227 val |= DPLL_VCO_ENABLE;
1228 I915_WRITE(reg, val);
1229 POSTING_READ(reg);
1230 DELAY(200);
1231}
1232
1233static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1234 enum pipe pipe)
1235{
1236 int reg;
1237 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1238 pll_sel = TRANSC_DPLL_ENABLE;
1239
1240 if (pipe > 1)
1241 return;
1242
1243 /* PCH only available on ILK+ */
1244 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1245
1246 /* Make sure transcoder isn't still depending on us */
1247 assert_transcoder_disabled(dev_priv, pipe);
1248
1249 if (pipe == 0)
1250 pll_sel |= TRANSC_DPLLA_SEL;
1251 else if (pipe == 1)
1252 pll_sel |= TRANSC_DPLLB_SEL;
1253
1254
1255 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1256 return;
1257
1258 reg = PCH_DPLL(pipe);
1259 val = I915_READ(reg);
1260 val &= ~DPLL_VCO_ENABLE;
1261 I915_WRITE(reg, val);
1262 POSTING_READ(reg);
1263 DELAY(200);
1264}
1265
1266static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1267 enum pipe pipe)
1268{
1269 int reg;
1270 u32 val, pipeconf_val;
1271 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1272
1273 /* PCH only available on ILK+ */
1274 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1275
1276 /* Make sure PCH DPLL is enabled */
1277 assert_pch_pll_enabled(dev_priv, pipe);
1278
1279 /* FDI must be feeding us bits for PCH ports */
1280 assert_fdi_tx_enabled(dev_priv, pipe);
1281 assert_fdi_rx_enabled(dev_priv, pipe);
1282
1283
1284 reg = TRANSCONF(pipe);
1285 val = I915_READ(reg);
1286 pipeconf_val = I915_READ(PIPECONF(pipe));
1287
1288 if (HAS_PCH_IBX(dev_priv->dev)) {
1289 /*
1290 * make the BPC in transcoder be consistent with
1291 * that in pipeconf reg.
1292 */
1293 val &= ~PIPE_BPC_MASK;
1294 val |= pipeconf_val & PIPE_BPC_MASK;
1295 }
1296
1297 val &= ~TRANS_INTERLACE_MASK;
1298 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1299 if (HAS_PCH_IBX(dev_priv->dev) &&
1300 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1301 val |= TRANS_LEGACY_INTERLACED_ILK;
1302 else
1303 val |= TRANS_INTERLACED;
1304 else
1305 val |= TRANS_PROGRESSIVE;
1306
1307 I915_WRITE(reg, val | TRANS_ENABLE);
1308 if (_intel_wait_for(dev_priv->dev, I915_READ(reg) & TRANS_STATE_ENABLE,
1309 100, 1, "915trc"))
1310 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1311}
1312
1313static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1314 enum pipe pipe)
1315{
1316 int reg;
1317 u32 val;
1318
1319 /* FDI relies on the transcoder */
1320 assert_fdi_tx_disabled(dev_priv, pipe);
1321 assert_fdi_rx_disabled(dev_priv, pipe);
1322
1323 /* Ports must be off as well */
1324 assert_pch_ports_disabled(dev_priv, pipe);
1325
1326 reg = TRANSCONF(pipe);
1327 val = I915_READ(reg);
1328 val &= ~TRANS_ENABLE;
1329 I915_WRITE(reg, val);
1330 /* wait for PCH transcoder off, transcoder state */
1331 if (_intel_wait_for(dev_priv->dev,
1332 (I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50,
1333 1, "915trd"))
1334 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1335}
1336
1337/**
1338 * intel_enable_pipe - enable a pipe, asserting requirements
1339 * @dev_priv: i915 private structure
1340 * @pipe: pipe to enable
1341 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1342 *
1343 * Enable @pipe, making sure that various hardware specific requirements
1344 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1345 *
1346 * @pipe should be %PIPE_A or %PIPE_B.
1347 *
1348 * Will wait until the pipe is actually running (i.e. first vblank) before
1349 * returning.
1350 */
1351static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1352 bool pch_port)
1353{
1354 int reg;
1355 u32 val;
1356
1357 /*
1358 * A pipe without a PLL won't actually be able to drive bits from
1359 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1360 * need the check.
1361 */
1362 if (!HAS_PCH_SPLIT(dev_priv->dev))
1363 assert_pll_enabled(dev_priv, pipe);
1364 else {
1365 if (pch_port) {
1366 /* if driving the PCH, we need FDI enabled */
1367 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1368 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1369 }
1370 /* FIXME: assert CPU port conditions for SNB+ */
1371 }
1372
1373 reg = PIPECONF(pipe);
1374 val = I915_READ(reg);
1375 if (val & PIPECONF_ENABLE)
1376 return;
1377
1378 I915_WRITE(reg, val | PIPECONF_ENABLE);
1379 intel_wait_for_vblank(dev_priv->dev, pipe);
1380}
1381
1382/**
1383 * intel_disable_pipe - disable a pipe, asserting requirements
1384 * @dev_priv: i915 private structure
1385 * @pipe: pipe to disable
1386 *
1387 * Disable @pipe, making sure that various hardware specific requirements
1388 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1389 *
1390 * @pipe should be %PIPE_A or %PIPE_B.
1391 *
1392 * Will wait until the pipe has shut down before returning.
1393 */
1394static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1395 enum pipe pipe)
1396{
1397 int reg;
1398 u32 val;
1399
1400 /*
1401 * Make sure planes won't keep trying to pump pixels to us,
1402 * or we might hang the display.
1403 */
1404 assert_planes_disabled(dev_priv, pipe);
1405
1406 /* Don't disable pipe A or pipe A PLLs if needed */
1407 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1408 return;
1409
1410 reg = PIPECONF(pipe);
1411 val = I915_READ(reg);
1412 if ((val & PIPECONF_ENABLE) == 0)
1413 return;
1414
1415 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1416 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1417}
1418
1419/*
1420 * Plane regs are double buffered, going from enabled->disabled needs a
1421 * trigger in order to latch. The display address reg provides this.
1422 */
1423static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1424 enum plane plane)
1425{
1426 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1427 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1428}
1429
1430/**
1431 * intel_enable_plane - enable a display plane on a given pipe
1432 * @dev_priv: i915 private structure
1433 * @plane: plane to enable
1434 * @pipe: pipe being fed
1435 *
1436 * Enable @plane on @pipe, making sure that @pipe is running first.
1437 */
1438static void intel_enable_plane(struct drm_i915_private *dev_priv,
1439 enum plane plane, enum pipe pipe)
1440{
1441 int reg;
1442 u32 val;
1443
1444 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1445 assert_pipe_enabled(dev_priv, pipe);
1446
1447 reg = DSPCNTR(plane);
1448 val = I915_READ(reg);
1449 if (val & DISPLAY_PLANE_ENABLE)
1450 return;
1451
1452 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1453 intel_flush_display_plane(dev_priv, plane);
1454 intel_wait_for_vblank(dev_priv->dev, pipe);
1455}
1456
1457/**
1458 * intel_disable_plane - disable a display plane
1459 * @dev_priv: i915 private structure
1460 * @plane: plane to disable
1461 * @pipe: pipe consuming the data
1462 *
1463 * Disable @plane; should be an independent operation.
1464 */
1465static void intel_disable_plane(struct drm_i915_private *dev_priv,
1466 enum plane plane, enum pipe pipe)
1467{
1468 int reg;
1469 u32 val;
1470
1471 reg = DSPCNTR(plane);
1472 val = I915_READ(reg);
1473 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1474 return;
1475
1476 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1477 intel_flush_display_plane(dev_priv, plane);
1478 intel_wait_for_vblank(dev_priv->dev, pipe);
1479}
1480
1481static void disable_pch_dp(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, int reg, u32 port_sel)
1483{
1484 u32 val = I915_READ(reg);
1485 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1486 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1487 I915_WRITE(reg, val & ~DP_PORT_EN);
1488 }
1489}
1490
1491static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1492 enum pipe pipe, int reg)
1493{
1494 u32 val = I915_READ(reg);
1495 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1496 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1497 reg, pipe);
1498 I915_WRITE(reg, val & ~PORT_ENABLE);
1499 }
1500}
1501
1502/* Disable any ports connected to this transcoder */
1503static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1504 enum pipe pipe)
1505{
1506 u32 reg, val;
1507
1508 val = I915_READ(PCH_PP_CONTROL);
1509 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1510
1511 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1512 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1513 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1514
1515 reg = PCH_ADPA;
1516 val = I915_READ(reg);
1517 if (adpa_pipe_enabled(dev_priv, val, pipe))
1518 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1519
1520 reg = PCH_LVDS;
1521 val = I915_READ(reg);
1522 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1523 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1524 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1525 POSTING_READ(reg);
1526 DELAY(100);
1527 }
1528
1529 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1530 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1531 disable_pch_hdmi(dev_priv, pipe, HDMID);
1532}
1533
1534static void i8xx_disable_fbc(struct drm_device *dev)
1535{
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 u32 fbc_ctl;
1538
1539 /* Disable compression */
1540 fbc_ctl = I915_READ(FBC_CONTROL);
1541 if ((fbc_ctl & FBC_CTL_EN) == 0)
1542 return;
1543
1544 fbc_ctl &= ~FBC_CTL_EN;
1545 I915_WRITE(FBC_CONTROL, fbc_ctl);
1546
1547 /* Wait for compressing bit to clear */
1548 if (_intel_wait_for(dev,
1549 (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10,
1550 1, "915fbd")) {
1551 DRM_DEBUG_KMS("FBC idle timed out\n");
1552 return;
1553 }
1554
1555 DRM_DEBUG_KMS("disabled FBC\n");
1556}
1557
1558static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1559{
1560 struct drm_device *dev = crtc->dev;
1561 struct drm_i915_private *dev_priv = dev->dev_private;
1562 struct drm_framebuffer *fb = crtc->fb;
1563 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1564 struct drm_i915_gem_object *obj = intel_fb->obj;
1565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1566 int cfb_pitch;
1567 int plane, i;
1568 u32 fbc_ctl, fbc_ctl2;
1569
1570 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1571 if (fb->pitches[0] < cfb_pitch)
1572 cfb_pitch = fb->pitches[0];
1573
1574 /* FBC_CTL wants 64B units */
1575 cfb_pitch = (cfb_pitch / 64) - 1;
1576 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1577
1578 /* Clear old tags */
1579 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1580 I915_WRITE(FBC_TAG + (i * 4), 0);
1581
1582 /* Set it up... */
1583 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1584 fbc_ctl2 |= plane;
1585 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1586 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1587
1588 /* enable it... */
1589 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1590 if (IS_I945GM(dev))
1591 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1592 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1593 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1594 fbc_ctl |= obj->fence_reg;
1595 I915_WRITE(FBC_CONTROL, fbc_ctl);
1596
1597 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1598 cfb_pitch, crtc->y, intel_crtc->plane);
1599}
1600
1601static bool i8xx_fbc_enabled(struct drm_device *dev)
1602{
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604
1605 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1606}
1607
1608static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1609{
1610 struct drm_device *dev = crtc->dev;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 struct drm_framebuffer *fb = crtc->fb;
1613 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1614 struct drm_i915_gem_object *obj = intel_fb->obj;
1615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1616 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1617 unsigned long stall_watermark = 200;
1618 u32 dpfc_ctl;
1619
1620 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1621 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1622 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1623
1624 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1625 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1626 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1627 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1628
1629 /* enable it... */
1630 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1631
1632 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1633}
1634
1635static void g4x_disable_fbc(struct drm_device *dev)
1636{
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 u32 dpfc_ctl;
1639
1640 /* Disable compression */
1641 dpfc_ctl = I915_READ(DPFC_CONTROL);
1642 if (dpfc_ctl & DPFC_CTL_EN) {
1643 dpfc_ctl &= ~DPFC_CTL_EN;
1644 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1645
1646 DRM_DEBUG_KMS("disabled FBC\n");
1647 }
1648}
1649
1650static bool g4x_fbc_enabled(struct drm_device *dev)
1651{
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653
1654 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1655}
1656
1657static void sandybridge_blit_fbc_update(struct drm_device *dev)
1658{
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660 u32 blt_ecoskpd;
1661
1662 /* Make sure blitter notifies FBC of writes */
1663 gen6_gt_force_wake_get(dev_priv);
1664 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1665 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1666 GEN6_BLITTER_LOCK_SHIFT;
1667 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1668 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1669 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1670 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1671 GEN6_BLITTER_LOCK_SHIFT);
1672 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1673 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1674 gen6_gt_force_wake_put(dev_priv);
1675}
1676
1677static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1678{
1679 struct drm_device *dev = crtc->dev;
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 struct drm_framebuffer *fb = crtc->fb;
1682 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1683 struct drm_i915_gem_object *obj = intel_fb->obj;
1684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1685 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1686 unsigned long stall_watermark = 200;
1687 u32 dpfc_ctl;
1688
1689 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1690 dpfc_ctl &= DPFC_RESERVED;
1691 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1692 /* Set persistent mode for front-buffer rendering, ala X. */
1693 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1694 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1695 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1696
1697 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1698 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1699 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1700 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1701 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1702 /* enable it... */
1703 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1704
1705 if (IS_GEN6(dev)) {
1706 I915_WRITE(SNB_DPFC_CTL_SA,
1707 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1708 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1709 sandybridge_blit_fbc_update(dev);
1710 }
1711
1712 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1713}
1714
1715static void ironlake_disable_fbc(struct drm_device *dev)
1716{
1717 struct drm_i915_private *dev_priv = dev->dev_private;
1718 u32 dpfc_ctl;
1719
1720 /* Disable compression */
1721 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1722 if (dpfc_ctl & DPFC_CTL_EN) {
1723 dpfc_ctl &= ~DPFC_CTL_EN;
1724 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1725
1726 DRM_DEBUG_KMS("disabled FBC\n");
1727 }
1728}
1729
1730static bool ironlake_fbc_enabled(struct drm_device *dev)
1731{
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733
1734 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1735}
1736
1737bool intel_fbc_enabled(struct drm_device *dev)
1738{
1739 struct drm_i915_private *dev_priv = dev->dev_private;
1740
1741 if (!dev_priv->display.fbc_enabled)
1742 return false;
1743
1744 return dev_priv->display.fbc_enabled(dev);
1745}
1746
1747static void intel_fbc_work_fn(void *arg, int pending)
1748{
1749 struct intel_fbc_work *work = arg;
1750 struct drm_device *dev = work->crtc->dev;
1751 struct drm_i915_private *dev_priv = dev->dev_private;
1752
1753 DRM_LOCK(dev);
1754 if (work == dev_priv->fbc_work) {
1755 /* Double check that we haven't switched fb without cancelling
1756 * the prior work.
1757 */
1758 if (work->crtc->fb == work->fb) {
1759 dev_priv->display.enable_fbc(work->crtc,
1760 work->interval);
1761
1762 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1763 dev_priv->cfb_fb = work->crtc->fb->base.id;
1764 dev_priv->cfb_y = work->crtc->y;
1765 }
1766
1767 dev_priv->fbc_work = NULL;
1768 }
1769 DRM_UNLOCK(dev);
1770
1771 free(work, DRM_MEM_KMS);
1772}
1773
1774static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1775{
1776 u_int pending;
1777
1778 if (dev_priv->fbc_work == NULL)
1779 return;
1780
1781 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1782
1783 /* Synchronisation is provided by struct_mutex and checking of
1784 * dev_priv->fbc_work, so we can perform the cancellation
1785 * entirely asynchronously.
1786 */
1787 if (taskqueue_cancel_timeout(dev_priv->tq, &dev_priv->fbc_work->task,
1788 &pending) == 0)
1789 /* tasklet was killed before being run, clean up */
1790 free(dev_priv->fbc_work, DRM_MEM_KMS);
1791
1792 /* Mark the work as no longer wanted so that if it does
1793 * wake-up (because the work was already running and waiting
1794 * for our mutex), it will discover that is no longer
1795 * necessary to run.
1796 */
1797 dev_priv->fbc_work = NULL;
1798}
1799
1800static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1801{
1802 struct intel_fbc_work *work;
1803 struct drm_device *dev = crtc->dev;
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805
1806 if (!dev_priv->display.enable_fbc)
1807 return;
1808
1809 intel_cancel_fbc_work(dev_priv);
1810
1811 work = malloc(sizeof(*work), DRM_MEM_KMS, M_WAITOK | M_ZERO);
1812 work->crtc = crtc;
1813 work->fb = crtc->fb;
1814 work->interval = interval;
1815 TIMEOUT_TASK_INIT(dev_priv->tq, &work->task, 0, intel_fbc_work_fn,
1816 work);
1817
1818 dev_priv->fbc_work = work;
1819
1820 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1821
1822 /* Delay the actual enabling to let pageflipping cease and the
1823 * display to settle before starting the compression. Note that
1824 * this delay also serves a second purpose: it allows for a
1825 * vblank to pass after disabling the FBC before we attempt
1826 * to modify the control registers.
1827 *
1828 * A more complicated solution would involve tracking vblanks
1829 * following the termination of the page-flipping sequence
1830 * and indeed performing the enable as a co-routine and not
1831 * waiting synchronously upon the vblank.
1832 */
1833 taskqueue_enqueue_timeout(dev_priv->tq, &work->task,
1834 msecs_to_jiffies(50));
1835}
1836
1837void intel_disable_fbc(struct drm_device *dev)
1838{
1839 struct drm_i915_private *dev_priv = dev->dev_private;
1840
1841 intel_cancel_fbc_work(dev_priv);
1842
1843 if (!dev_priv->display.disable_fbc)
1844 return;
1845
1846 dev_priv->display.disable_fbc(dev);
1847 dev_priv->cfb_plane = -1;
1848}
1849
1850/**
1851 * intel_update_fbc - enable/disable FBC as needed
1852 * @dev: the drm_device
1853 *
1854 * Set up the framebuffer compression hardware at mode set time. We
1855 * enable it if possible:
1856 * - plane A only (on pre-965)
1857 * - no pixel mulitply/line duplication
1858 * - no alpha buffer discard
1859 * - no dual wide
1860 * - framebuffer <= 2048 in width, 1536 in height
1861 *
1862 * We can't assume that any compression will take place (worst case),
1863 * so the compressed buffer has to be the same size as the uncompressed
1864 * one. It also must reside (along with the line length buffer) in
1865 * stolen memory.
1866 *
1867 * We need to enable/disable FBC on a global basis.
1868 */
1869static void intel_update_fbc(struct drm_device *dev)
1870{
1871 struct drm_i915_private *dev_priv = dev->dev_private;
1872 struct drm_crtc *crtc = NULL, *tmp_crtc;
1873 struct intel_crtc *intel_crtc;
1874 struct drm_framebuffer *fb;
1875 struct intel_framebuffer *intel_fb;
1876 struct drm_i915_gem_object *obj;
1877 int enable_fbc;
1878
1879 DRM_DEBUG_KMS("\n");
1880
1881 if (!i915_powersave)
1882 return;
1883
1884 if (!I915_HAS_FBC(dev))
1885 return;
1886
1887 /*
1888 * If FBC is already on, we just have to verify that we can
1889 * keep it that way...
1890 * Need to disable if:
1891 * - more than one pipe is active
1892 * - changing FBC params (stride, fence, mode)
1893 * - new fb is too large to fit in compressed buffer
1894 * - going to an unsupported config (interlace, pixel multiply, etc.)
1895 */
1896 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1897 if (tmp_crtc->enabled && tmp_crtc->fb) {
1898 if (crtc) {
1899 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1900 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1901 goto out_disable;
1902 }
1903 crtc = tmp_crtc;
1904 }
1905 }
1906
1907 if (!crtc || crtc->fb == NULL) {
1908 DRM_DEBUG_KMS("no output, disabling\n");
1909 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1910 goto out_disable;
1911 }
1912
1913 intel_crtc = to_intel_crtc(crtc);
1914 fb = crtc->fb;
1915 intel_fb = to_intel_framebuffer(fb);
1916 obj = intel_fb->obj;
1917
1918 enable_fbc = i915_enable_fbc;
1919 if (enable_fbc < 0) {
1920 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1921 enable_fbc = 1;
1922 if (INTEL_INFO(dev)->gen <= 6)
1923 enable_fbc = 0;
1924 }
1925 if (!enable_fbc) {
1926 DRM_DEBUG_KMS("fbc disabled per module param\n");
1927 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1928 goto out_disable;
1929 }
1930 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1931 DRM_DEBUG_KMS("framebuffer too large, disabling "
1932 "compression\n");
1933 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1934 goto out_disable;
1935 }
1936 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1937 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1938 DRM_DEBUG_KMS("mode incompatible with compression, "
1939 "disabling\n");
1940 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1941 goto out_disable;
1942 }
1943 if ((crtc->mode.hdisplay > 2048) ||
1944 (crtc->mode.vdisplay > 1536)) {
1945 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1946 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1947 goto out_disable;
1948 }
1949 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1950 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1951 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1952 goto out_disable;
1953 }
1954 if (obj->tiling_mode != I915_TILING_X ||
1955 obj->fence_reg == I915_FENCE_REG_NONE) {
1956 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1957 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1958 goto out_disable;
1959 }
1960
1961 /* If the kernel debugger is active, always disable compression */
1962 if (kdb_active)
1963 goto out_disable;
1964
1965 /* If the scanout has not changed, don't modify the FBC settings.
1966 * Note that we make the fundamental assumption that the fb->obj
1967 * cannot be unpinned (and have its GTT offset and fence revoked)
1968 * without first being decoupled from the scanout and FBC disabled.
1969 */
1970 if (dev_priv->cfb_plane == intel_crtc->plane &&
1971 dev_priv->cfb_fb == fb->base.id &&
1972 dev_priv->cfb_y == crtc->y)
1973 return;
1974
1975 if (intel_fbc_enabled(dev)) {
1976 /* We update FBC along two paths, after changing fb/crtc
1977 * configuration (modeswitching) and after page-flipping
1978 * finishes. For the latter, we know that not only did
1979 * we disable the FBC at the start of the page-flip
1980 * sequence, but also more than one vblank has passed.
1981 *
1982 * For the former case of modeswitching, it is possible
1983 * to switch between two FBC valid configurations
1984 * instantaneously so we do need to disable the FBC
1985 * before we can modify its control registers. We also
1986 * have to wait for the next vblank for that to take
1987 * effect. However, since we delay enabling FBC we can
1988 * assume that a vblank has passed since disabling and
1989 * that we can safely alter the registers in the deferred
1990 * callback.
1991 *
1992 * In the scenario that we go from a valid to invalid
1993 * and then back to valid FBC configuration we have
1994 * no strict enforcement that a vblank occurred since
1995 * disabling the FBC. However, along all current pipe
1996 * disabling paths we do need to wait for a vblank at
1997 * some point. And we wait before enabling FBC anyway.
1998 */
1999 DRM_DEBUG_KMS("disabling active FBC for update\n");
2000 intel_disable_fbc(dev);
2001 }
2002
2003 intel_enable_fbc(crtc, 500);
2004 return;
2005
2006out_disable:
2007 /* Multiple disables should be harmless */
2008 if (intel_fbc_enabled(dev)) {
2009 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2010 intel_disable_fbc(dev);
2011 }
2012}
2013
2014int
2015intel_pin_and_fence_fb_obj(struct drm_device *dev,
2016 struct drm_i915_gem_object *obj,
2017 struct intel_ring_buffer *pipelined)
2018{
2019 struct drm_i915_private *dev_priv = dev->dev_private;
2020 u32 alignment;
2021 int ret;
2022
2023 alignment = 0; /* shut gcc */
2024 switch (obj->tiling_mode) {
2025 case I915_TILING_NONE:
2026 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2027 alignment = 128 * 1024;
2028 else if (INTEL_INFO(dev)->gen >= 4)
2029 alignment = 4 * 1024;
2030 else
2031 alignment = 64 * 1024;
2032 break;
2033 case I915_TILING_X:
2034 /* pin() will align the object as required by fence */
2035 alignment = 0;
2036 break;
2037 case I915_TILING_Y:
2038 /* FIXME: Is this true? */
2039 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2040 return -EINVAL;
2041 default:
2042 KASSERT(0, ("Wrong tiling for fb obj"));
2043 }
2044
2045 dev_priv->mm.interruptible = false;
2046 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2047 if (ret)
2048 goto err_interruptible;
2049
2050 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2051 * fence, whereas 965+ only requires a fence if using
2052 * framebuffer compression. For simplicity, we always install
2053 * a fence as the cost is not that onerous.
2054 */
2055 if (obj->tiling_mode != I915_TILING_NONE) {
2056 ret = i915_gem_object_get_fence(obj, pipelined);
2057 if (ret)
2058 goto err_unpin;
2059
2060 i915_gem_object_pin_fence(obj);
2061 }
2062
2063 dev_priv->mm.interruptible = true;
2064 return 0;
2065
2066err_unpin:
2067 i915_gem_object_unpin(obj);
2068err_interruptible:
2069 dev_priv->mm.interruptible = true;
2070 return ret;
2071}
2072
2073void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2074{
2075 i915_gem_object_unpin_fence(obj);
2076 i915_gem_object_unpin(obj);
2077}
2078
2079static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2080 int x, int y)
2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
2088 unsigned long Start, Offset;
2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
2095 break;
2096 default:
2097 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2098 return -EINVAL;
2099 }
2100
2101 intel_fb = to_intel_framebuffer(fb);
2102 obj = intel_fb->obj;
2103
2104 reg = DSPCNTR(plane);
2105 dspcntr = I915_READ(reg);
2106 /* Mask out pixel format bits in case we change it */
2107 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2108 switch (fb->bits_per_pixel) {
2109 case 8:
2110 dspcntr |= DISPPLANE_8BPP;
2111 break;
2112 case 16:
2113 if (fb->depth == 15)
2114 dspcntr |= DISPPLANE_15_16BPP;
2115 else
2116 dspcntr |= DISPPLANE_16BPP;
2117 break;
2118 case 24:
2119 case 32:
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 break;
2122 default:
2123 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2124 return -EINVAL;
2125 }
2126 if (INTEL_INFO(dev)->gen >= 4) {
2127 if (obj->tiling_mode != I915_TILING_NONE)
2128 dspcntr |= DISPPLANE_TILED;
2129 else
2130 dspcntr &= ~DISPPLANE_TILED;
2131 }
2132
2133 I915_WRITE(reg, dspcntr);
2134
2135 Start = obj->gtt_offset;
2136 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2137
2138 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2139 Start, Offset, x, y, fb->pitches[0]);
2140 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2141 if (INTEL_INFO(dev)->gen >= 4) {
2142 I915_WRITE(DSPSURF(plane), Start);
2143 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2144 I915_WRITE(DSPADDR(plane), Offset);
2145 } else
2146 I915_WRITE(DSPADDR(plane), Start + Offset);
2147 POSTING_READ(reg);
2148
2149 return (0);
2150}
2151
2152static int ironlake_update_plane(struct drm_crtc *crtc,
2153 struct drm_framebuffer *fb, int x, int y)
2154{
2155 struct drm_device *dev = crtc->dev;
2156 struct drm_i915_private *dev_priv = dev->dev_private;
2157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2158 struct intel_framebuffer *intel_fb;
2159 struct drm_i915_gem_object *obj;
2160 int plane = intel_crtc->plane;
2161 unsigned long Start, Offset;
2162 u32 dspcntr;
2163 u32 reg;
2164
2165 switch (plane) {
2166 case 0:
2167 case 1:
2168 case 2:
2169 break;
2170 default:
2171 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2172 return -EINVAL;
2173 }
2174
2175 intel_fb = to_intel_framebuffer(fb);
2176 obj = intel_fb->obj;
2177
2178 reg = DSPCNTR(plane);
2179 dspcntr = I915_READ(reg);
2180 /* Mask out pixel format bits in case we change it */
2181 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2182 switch (fb->bits_per_pixel) {
2183 case 8:
2184 dspcntr |= DISPPLANE_8BPP;
2185 break;
2186 case 16:
2187 if (fb->depth != 16) {
2188 DRM_ERROR("bpp 16, depth %d\n", fb->depth);
2189 return -EINVAL;
2190 }
2191
2192 dspcntr |= DISPPLANE_16BPP;
2193 break;
2194 case 24:
2195 case 32:
2196 if (fb->depth == 24)
2197 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2198 else if (fb->depth == 30)
2199 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2200 else {
2201 DRM_ERROR("bpp %d depth %d\n", fb->bits_per_pixel,
2202 fb->depth);
2203 return -EINVAL;
2204 }
2205 break;
2206 default:
2207 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2208 return -EINVAL;
2209 }
2210
2211 if (obj->tiling_mode != I915_TILING_NONE)
2212 dspcntr |= DISPPLANE_TILED;
2213 else
2214 dspcntr &= ~DISPPLANE_TILED;
2215
2216 /* must disable */
2217 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2218
2219 I915_WRITE(reg, dspcntr);
2220
2221 Start = obj->gtt_offset;
2222 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2223
2224 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2225 Start, Offset, x, y, fb->pitches[0]);
2226 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2227 I915_WRITE(DSPSURF(plane), Start);
2228 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2229 I915_WRITE(DSPADDR(plane), Offset);
2230 POSTING_READ(reg);
2231
2232 return 0;
2233}
2234
2235/* Assume fb object is pinned & idle & fenced and just update base pointers */
2236static int
2237intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2238 int x, int y, enum mode_set_atomic state)
2239{
2240 struct drm_device *dev = crtc->dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 int ret;
2243
2244 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2245 if (ret)
2246 return ret;
2247
2248 intel_update_fbc(dev);
2249 intel_increase_pllclock(crtc);
2250
2251 return 0;
2252}
2253
2254static int
2255intel_finish_fb(struct drm_framebuffer *old_fb)
2256{
2257 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2258 struct drm_device *dev = obj->base.dev;
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 bool was_interruptible = dev_priv->mm.interruptible;
2261 int ret;
2262
2263 mtx_lock(&dev->event_lock);
2264 while (!atomic_read(&dev_priv->mm.wedged) &&
2265 atomic_read(&obj->pending_flip) != 0) {
2266 msleep(&obj->pending_flip, &dev->event_lock,
2267 0, "915flp", 0);
2268 }
2269 mtx_unlock(&dev->event_lock);
2270
2271 /* Big Hammer, we also need to ensure that any pending
2272 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2273 * current scanout is retired before unpinning the old
2274 * framebuffer.
2275 *
2276 * This should only fail upon a hung GPU, in which case we
2277 * can safely continue.
2278 */
2279 dev_priv->mm.interruptible = false;
2280 ret = i915_gem_object_finish_gpu(obj);
2281 dev_priv->mm.interruptible = was_interruptible;
2282 return ret;
2283}
2284
2285static int
2286intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2287 struct drm_framebuffer *old_fb)
2288{
2289 struct drm_device *dev = crtc->dev;
2290#if 0
2291 struct drm_i915_master_private *master_priv;
2292#else
2293 drm_i915_private_t *dev_priv = dev->dev_private;
2294#endif
2295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2296 int ret;
2297
2298 /* no fb bound */
2299 if (!crtc->fb) {
2300 DRM_ERROR("No FB bound\n");
2301 return 0;
2302 }
2303
2304 switch (intel_crtc->plane) {
2305 case 0:
2306 case 1:
2307 break;
2308 case 2:
2309 if (IS_IVYBRIDGE(dev))
2310 break;
2311 /* fall through otherwise */
2312 default:
2313 DRM_ERROR("no plane for crtc\n");
2314 return -EINVAL;
2315 }
2316
2317 DRM_LOCK(dev);
2318 ret = intel_pin_and_fence_fb_obj(dev,
2319 to_intel_framebuffer(crtc->fb)->obj,
2320 NULL);
2321 if (ret != 0) {
2322 DRM_UNLOCK(dev);
2323 DRM_ERROR("pin & fence failed\n");
2324 return ret;
2325 }
2326
2327 if (old_fb)
2328 intel_finish_fb(old_fb);
2329
2330 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2331 LEAVE_ATOMIC_MODE_SET);
2332 if (ret) {
2333 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2334 DRM_UNLOCK(dev);
2335 DRM_ERROR("failed to update base address\n");
2336 return ret;
2337 }
2338
2339 if (old_fb) {
2340 intel_wait_for_vblank(dev, intel_crtc->pipe);
2341 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2342 }
2343
2344 DRM_UNLOCK(dev);
2345
2346#if 0
2347 if (!dev->primary->master)
2348 return 0;
2349
2350 master_priv = dev->primary->master->driver_priv;
2351 if (!master_priv->sarea_priv)
2352 return 0;
2353
2354 if (intel_crtc->pipe) {
2355 master_priv->sarea_priv->pipeB_x = x;
2356 master_priv->sarea_priv->pipeB_y = y;
2357 } else {
2358 master_priv->sarea_priv->pipeA_x = x;
2359 master_priv->sarea_priv->pipeA_y = y;
2360 }
2361#else
2362
2363 if (!dev_priv->sarea_priv)
2364 return 0;
2365
2366 if (intel_crtc->pipe) {
2367 dev_priv->sarea_priv->planeB_x = x;
2368 dev_priv->sarea_priv->planeB_y = y;
2369 } else {
2370 dev_priv->sarea_priv->planeA_x = x;
2371 dev_priv->sarea_priv->planeA_y = y;
2372 }
2373#endif
2374
2375 return 0;
2376}
2377
2378static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2379{
2380 struct drm_device *dev = crtc->dev;
2381 struct drm_i915_private *dev_priv = dev->dev_private;
2382 u32 dpa_ctl;
2383
2384 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2385 dpa_ctl = I915_READ(DP_A);
2386 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2387
2388 if (clock < 200000) {
2389 u32 temp;
2390 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2391 /* workaround for 160Mhz:
2392 1) program 0x4600c bits 15:0 = 0x8124
2393 2) program 0x46010 bit 0 = 1
2394 3) program 0x46034 bit 24 = 1
2395 4) program 0x64000 bit 14 = 1
2396 */
2397 temp = I915_READ(0x4600c);
2398 temp &= 0xffff0000;
2399 I915_WRITE(0x4600c, temp | 0x8124);
2400
2401 temp = I915_READ(0x46010);
2402 I915_WRITE(0x46010, temp | 1);
2403
2404 temp = I915_READ(0x46034);
2405 I915_WRITE(0x46034, temp | (1 << 24));
2406 } else {
2407 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2408 }
2409 I915_WRITE(DP_A, dpa_ctl);
2410
2411 POSTING_READ(DP_A);
2412 DELAY(500);
2413}
2414
2415static void intel_fdi_normal_train(struct drm_crtc *crtc)
2416{
2417 struct drm_device *dev = crtc->dev;
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2420 int pipe = intel_crtc->pipe;
2421 u32 reg, temp;
2422
2423 /* enable normal train */
2424 reg = FDI_TX_CTL(pipe);
2425 temp = I915_READ(reg);
2426 if (IS_IVYBRIDGE(dev)) {
2427 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2428 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2429 } else {
2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2432 }
2433 I915_WRITE(reg, temp);
2434
2435 reg = FDI_RX_CTL(pipe);
2436 temp = I915_READ(reg);
2437 if (HAS_PCH_CPT(dev)) {
2438 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2439 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2440 } else {
2441 temp &= ~FDI_LINK_TRAIN_NONE;
2442 temp |= FDI_LINK_TRAIN_NONE;
2443 }
2444 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2445
2446 /* wait one idle pattern time */
2447 POSTING_READ(reg);
2448 DELAY(1000);
2449
2450 /* IVB wants error correction enabled */
2451 if (IS_IVYBRIDGE(dev))
2452 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2453 FDI_FE_ERRC_ENABLE);
2454}
2455
2456static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2457{
2458 struct drm_i915_private *dev_priv = dev->dev_private;
2459 u32 flags = I915_READ(SOUTH_CHICKEN1);
2460
2461 flags |= FDI_PHASE_SYNC_OVR(pipe);
2462 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2463 flags |= FDI_PHASE_SYNC_EN(pipe);
2464 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2465 POSTING_READ(SOUTH_CHICKEN1);
2466}
2467
2468/* The FDI link training functions for ILK/Ibexpeak. */
2469static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2470{
2471 struct drm_device *dev = crtc->dev;
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2474 int pipe = intel_crtc->pipe;
2475 int plane = intel_crtc->plane;
2476 u32 reg, temp, tries;
2477
2478 /* FDI needs bits from pipe & plane first */
2479 assert_pipe_enabled(dev_priv, pipe);
2480 assert_plane_enabled(dev_priv, plane);
2481
2482 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2483 for train result */
2484 reg = FDI_RX_IMR(pipe);
2485 temp = I915_READ(reg);
2486 temp &= ~FDI_RX_SYMBOL_LOCK;
2487 temp &= ~FDI_RX_BIT_LOCK;
2488 I915_WRITE(reg, temp);
2489 I915_READ(reg);
2490 DELAY(150);
2491
2492 /* enable CPU FDI TX and PCH FDI RX */
2493 reg = FDI_TX_CTL(pipe);
2494 temp = I915_READ(reg);
2495 temp &= ~(7 << 19);
2496 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2497 temp &= ~FDI_LINK_TRAIN_NONE;
2498 temp |= FDI_LINK_TRAIN_PATTERN_1;
2499 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2500
2501 reg = FDI_RX_CTL(pipe);
2502 temp = I915_READ(reg);
2503 temp &= ~FDI_LINK_TRAIN_NONE;
2504 temp |= FDI_LINK_TRAIN_PATTERN_1;
2505 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2506
2507 POSTING_READ(reg);
2508 DELAY(150);
2509
2510 /* Ironlake workaround, enable clock pointer after FDI enable*/
2511 if (HAS_PCH_IBX(dev)) {
2512 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2513 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2514 FDI_RX_PHASE_SYNC_POINTER_EN);
2515 }
2516
2517 reg = FDI_RX_IIR(pipe);
2518 for (tries = 0; tries < 5; tries++) {
2519 temp = I915_READ(reg);
2520 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521
2522 if ((temp & FDI_RX_BIT_LOCK)) {
2523 DRM_DEBUG_KMS("FDI train 1 done.\n");
2524 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2525 break;
2526 }
2527 }
2528 if (tries == 5)
2529 DRM_ERROR("FDI train 1 fail!\n");
2530
2531 /* Train 2 */
2532 reg = FDI_TX_CTL(pipe);
2533 temp = I915_READ(reg);
2534 temp &= ~FDI_LINK_TRAIN_NONE;
2535 temp |= FDI_LINK_TRAIN_PATTERN_2;
2536 I915_WRITE(reg, temp);
2537
2538 reg = FDI_RX_CTL(pipe);
2539 temp = I915_READ(reg);
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_2;
2542 I915_WRITE(reg, temp);
2543
2544 POSTING_READ(reg);
2545 DELAY(150);
2546
2547 reg = FDI_RX_IIR(pipe);
2548 for (tries = 0; tries < 5; tries++) {
2549 temp = I915_READ(reg);
2550 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2551
2552 if (temp & FDI_RX_SYMBOL_LOCK) {
2553 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2554 DRM_DEBUG_KMS("FDI train 2 done.\n");
2555 break;
2556 }
2557 }
2558 if (tries == 5)
2559 DRM_ERROR("FDI train 2 fail!\n");
2560
2561 DRM_DEBUG_KMS("FDI train done\n");
2562
2563}
2564
2565static const int snb_b_fdi_train_param[] = {
2566 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2567 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2568 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2569 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2570};
2571
2572/* The FDI link training functions for SNB/Cougarpoint. */
2573static void gen6_fdi_link_train(struct drm_crtc *crtc)
2574{
2575 struct drm_device *dev = crtc->dev;
2576 struct drm_i915_private *dev_priv = dev->dev_private;
2577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2578 int pipe = intel_crtc->pipe;
2579 u32 reg, temp, i;
2580
2581 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2582 for train result */
2583 reg = FDI_RX_IMR(pipe);
2584 temp = I915_READ(reg);
2585 temp &= ~FDI_RX_SYMBOL_LOCK;
2586 temp &= ~FDI_RX_BIT_LOCK;
2587 I915_WRITE(reg, temp);
2588
2589 POSTING_READ(reg);
2590 DELAY(150);
2591
2592 /* enable CPU FDI TX and PCH FDI RX */
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~(7 << 19);
2596 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2597 temp &= ~FDI_LINK_TRAIN_NONE;
2598 temp |= FDI_LINK_TRAIN_PATTERN_1;
2599 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2600 /* SNB-B */
2601 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2602 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2603
2604 reg = FDI_RX_CTL(pipe);
2605 temp = I915_READ(reg);
2606 if (HAS_PCH_CPT(dev)) {
2607 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2608 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2609 } else {
2610 temp &= ~FDI_LINK_TRAIN_NONE;
2611 temp |= FDI_LINK_TRAIN_PATTERN_1;
2612 }
2613 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2614
2615 POSTING_READ(reg);
2616 DELAY(150);
2617
2618 if (HAS_PCH_CPT(dev))
2619 cpt_phase_pointer_enable(dev, pipe);
2620
2621 for (i = 0; i < 4; i++) {
2622 reg = FDI_TX_CTL(pipe);
2623 temp = I915_READ(reg);
2624 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2625 temp |= snb_b_fdi_train_param[i];
2626 I915_WRITE(reg, temp);
2627
2628 POSTING_READ(reg);
2629 DELAY(500);
2630
2631 reg = FDI_RX_IIR(pipe);
2632 temp = I915_READ(reg);
2633 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2634
2635 if (temp & FDI_RX_BIT_LOCK) {
2636 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2637 DRM_DEBUG_KMS("FDI train 1 done.\n");
2638 break;
2639 }
2640 }
2641 if (i == 4)
2642 DRM_ERROR("FDI train 1 fail!\n");
2643
2644 /* Train 2 */
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_NONE;
2648 temp |= FDI_LINK_TRAIN_PATTERN_2;
2649 if (IS_GEN6(dev)) {
2650 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2651 /* SNB-B */
2652 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2653 }
2654 I915_WRITE(reg, temp);
2655
2656 reg = FDI_RX_CTL(pipe);
2657 temp = I915_READ(reg);
2658 if (HAS_PCH_CPT(dev)) {
2659 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2660 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2661 } else {
2662 temp &= ~FDI_LINK_TRAIN_NONE;
2663 temp |= FDI_LINK_TRAIN_PATTERN_2;
2664 }
2665 I915_WRITE(reg, temp);
2666
2667 POSTING_READ(reg);
2668 DELAY(150);
2669
2670 for (i = 0; i < 4; i++) {
2671 reg = FDI_TX_CTL(pipe);
2672 temp = I915_READ(reg);
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= snb_b_fdi_train_param[i];
2675 I915_WRITE(reg, temp);
2676
2677 POSTING_READ(reg);
2678 DELAY(500);
2679
2680 reg = FDI_RX_IIR(pipe);
2681 temp = I915_READ(reg);
2682 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2683
2684 if (temp & FDI_RX_SYMBOL_LOCK) {
2685 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2686 DRM_DEBUG_KMS("FDI train 2 done.\n");
2687 break;
2688 }
2689 }
2690 if (i == 4)
2691 DRM_ERROR("FDI train 2 fail!\n");
2692
2693 DRM_DEBUG_KMS("FDI train done.\n");
2694}
2695
2696/* Manual link training for Ivy Bridge A0 parts */
2697static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2698{
2699 struct drm_device *dev = crtc->dev;
2700 struct drm_i915_private *dev_priv = dev->dev_private;
2701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2702 int pipe = intel_crtc->pipe;
2703 u32 reg, temp, i;
2704
2705 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2706 for train result */
2707 reg = FDI_RX_IMR(pipe);
2708 temp = I915_READ(reg);
2709 temp &= ~FDI_RX_SYMBOL_LOCK;
2710 temp &= ~FDI_RX_BIT_LOCK;
2711 I915_WRITE(reg, temp);
2712
2713 POSTING_READ(reg);
2714 DELAY(150);
2715
2716 /* enable CPU FDI TX and PCH FDI RX */
2717 reg = FDI_TX_CTL(pipe);
2718 temp = I915_READ(reg);
2719 temp &= ~(7 << 19);
2720 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2721 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2722 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2725 temp |= FDI_COMPOSITE_SYNC;
2726 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2727
2728 reg = FDI_RX_CTL(pipe);
2729 temp = I915_READ(reg);
2730 temp &= ~FDI_LINK_TRAIN_AUTO;
2731 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2732 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2733 temp |= FDI_COMPOSITE_SYNC;
2734 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2735
2736 POSTING_READ(reg);
2737 DELAY(150);
2738
2739 for (i = 0; i < 4; i++) {
2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743 temp |= snb_b_fdi_train_param[i];
2744 I915_WRITE(reg, temp);
2745
2746 POSTING_READ(reg);
2747 DELAY(500);
2748
2749 reg = FDI_RX_IIR(pipe);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753 if (temp & FDI_RX_BIT_LOCK ||
2754 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2755 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2756 DRM_DEBUG_KMS("FDI train 1 done.\n");
2757 break;
2758 }
2759 }
2760 if (i == 4)
2761 DRM_ERROR("FDI train 1 fail!\n");
2762
2763 /* Train 2 */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2767 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2768 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2769 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2770 I915_WRITE(reg, temp);
2771
2772 reg = FDI_RX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2775 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2776 I915_WRITE(reg, temp);
2777
2778 POSTING_READ(reg);
2779 DELAY(150);
2780
2781 for (i = 0; i < 4; i++ ) {
2782 reg = FDI_TX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2785 temp |= snb_b_fdi_train_param[i];
2786 I915_WRITE(reg, temp);
2787
2788 POSTING_READ(reg);
2789 DELAY(500);
2790
2791 reg = FDI_RX_IIR(pipe);
2792 temp = I915_READ(reg);
2793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2794
2795 if (temp & FDI_RX_SYMBOL_LOCK) {
2796 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2797 DRM_DEBUG_KMS("FDI train 2 done.\n");
2798 break;
2799 }
2800 }
2801 if (i == 4)
2802 DRM_ERROR("FDI train 2 fail!\n");
2803
2804 DRM_DEBUG_KMS("FDI train done.\n");
2805}
2806
2807static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2808{
2809 struct drm_device *dev = crtc->dev;
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2812 int pipe = intel_crtc->pipe;
2813 u32 reg, temp;
2814
2815 /* Write the TU size bits so error detection works */
2816 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2817 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2818
2819 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2820 reg = FDI_RX_CTL(pipe);
2821 temp = I915_READ(reg);
2822 temp &= ~((0x7 << 19) | (0x7 << 16));
2823 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2824 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2825 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2826
2827 POSTING_READ(reg);
2828 DELAY(200);
2829
2830 /* Switch from Rawclk to PCDclk */
2831 temp = I915_READ(reg);
2832 I915_WRITE(reg, temp | FDI_PCDCLK);
2833
2834 POSTING_READ(reg);
2835 DELAY(200);
2836
2837 /* Enable CPU FDI TX PLL, always on for Ironlake */
2838 reg = FDI_TX_CTL(pipe);
2839 temp = I915_READ(reg);
2840 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2841 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2842
2843 POSTING_READ(reg);
2844 DELAY(100);
2845 }
2846}
2847
2848static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2849{
2850 struct drm_i915_private *dev_priv = dev->dev_private;
2851 u32 flags = I915_READ(SOUTH_CHICKEN1);
2852
2853 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2854 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2855 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2856 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2857 POSTING_READ(SOUTH_CHICKEN1);
2858}
2859
2860static void ironlake_fdi_disable(struct drm_crtc *crtc)
2861{
2862 struct drm_device *dev = crtc->dev;
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2865 int pipe = intel_crtc->pipe;
2866 u32 reg, temp;
2867
2868 /* disable CPU FDI tx and PCH FDI rx */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2872 POSTING_READ(reg);
2873
2874 reg = FDI_RX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 temp &= ~(0x7 << 16);
2877 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2878 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2879
2880 POSTING_READ(reg);
2881 DELAY(100);
2882
2883 /* Ironlake workaround, disable clock pointer after downing FDI */
2884 if (HAS_PCH_IBX(dev)) {
2885 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2886 I915_WRITE(FDI_RX_CHICKEN(pipe),
2887 I915_READ(FDI_RX_CHICKEN(pipe) &
2888 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2889 } else if (HAS_PCH_CPT(dev)) {
2890 cpt_phase_pointer_disable(dev, pipe);
2891 }
2892
2893 /* still set train pattern 1 */
2894 reg = FDI_TX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 temp &= ~FDI_LINK_TRAIN_NONE;
2897 temp |= FDI_LINK_TRAIN_PATTERN_1;
2898 I915_WRITE(reg, temp);
2899
2900 reg = FDI_RX_CTL(pipe);
2901 temp = I915_READ(reg);
2902 if (HAS_PCH_CPT(dev)) {
2903 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2904 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2905 } else {
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908 }
2909 /* BPC in FDI rx is consistent with that in PIPECONF */
2910 temp &= ~(0x07 << 16);
2911 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2912 I915_WRITE(reg, temp);
2913
2914 POSTING_READ(reg);
2915 DELAY(100);
2916}
2917
2918/*
2919 * When we disable a pipe, we need to clear any pending scanline wait events
2920 * to avoid hanging the ring, which we assume we are waiting on.
2921 */
2922static void intel_clear_scanline_wait(struct drm_device *dev)
2923{
2924 struct drm_i915_private *dev_priv = dev->dev_private;
2925 struct intel_ring_buffer *ring;
2926 u32 tmp;
2927
2928 if (IS_GEN2(dev))
2929 /* Can't break the hang on i8xx */
2930 return;
2931
2932 ring = LP_RING(dev_priv);
2933 tmp = I915_READ_CTL(ring);
2934 if (tmp & RING_WAIT)
2935 I915_WRITE_CTL(ring, tmp);
2936}
2937
2938static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2939{
2940 struct drm_i915_gem_object *obj;
2941 struct drm_i915_private *dev_priv;
2942 struct drm_device *dev;
2943
2944 if (crtc->fb == NULL)
2945 return;
2946
2947 obj = to_intel_framebuffer(crtc->fb)->obj;
2948 dev = crtc->dev;
2949 dev_priv = dev->dev_private;
2950 mtx_lock(&dev->event_lock);
2951 while (atomic_read(&obj->pending_flip) != 0)
2952 msleep(&obj->pending_flip, &dev->event_lock, 0, "915wfl", 0);
2953 mtx_unlock(&dev->event_lock);
2954}
2955
2956static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2957{
2958 struct drm_device *dev = crtc->dev;
2959 struct drm_mode_config *mode_config = &dev->mode_config;
2960 struct intel_encoder *encoder;
2961
2962 /*
2963 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2964 * must be driven by its own crtc; no sharing is possible.
2965 */
2966 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2967 if (encoder->base.crtc != crtc)
2968 continue;
2969
2970 switch (encoder->type) {
2971 case INTEL_OUTPUT_EDP:
2972 if (!intel_encoder_is_pch_edp(&encoder->base))
2973 return false;
2974 continue;
2975 }
2976 }
2977
2978 return true;
2979}
2980
2981/*
2982 * Enable PCH resources required for PCH ports:
2983 * - PCH PLLs
2984 * - FDI training & RX/TX
2985 * - update transcoder timings
2986 * - DP transcoding bits
2987 * - transcoder
2988 */
2989static void ironlake_pch_enable(struct drm_crtc *crtc)
2990{
2991 struct drm_device *dev = crtc->dev;
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2994 int pipe = intel_crtc->pipe;
2995 u32 reg, temp, transc_sel;
2996
2997 /* For PCH output, training FDI link */
2998 dev_priv->display.fdi_link_train(crtc);
2999
3000 intel_enable_pch_pll(dev_priv, pipe);
3001
3002 if (HAS_PCH_CPT(dev)) {
3003 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
3004 TRANSC_DPLLB_SEL;
3005
3006 /* Be sure PCH DPLL SEL is set */
3007 temp = I915_READ(PCH_DPLL_SEL);
3008 if (pipe == 0) {
3009 temp &= ~(TRANSA_DPLLB_SEL);
3010 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3011 } else if (pipe == 1) {
3012 temp &= ~(TRANSB_DPLLB_SEL);
3013 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3014 } else if (pipe == 2) {
3015 temp &= ~(TRANSC_DPLLB_SEL);
3016 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
3017 }
3018 I915_WRITE(PCH_DPLL_SEL, temp);
3019 }
3020
3021 /* set transcoder timing, panel must allow it */
3022 assert_panel_unlocked(dev_priv, pipe);
3023 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3024 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3025 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3026
3027 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3028 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3029 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3030 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3031
3032 intel_fdi_normal_train(crtc);
3033
3034 /* For PCH DP, enable TRANS_DP_CTL */
3035 if (HAS_PCH_CPT(dev) &&
3036 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3037 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3038 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3039 reg = TRANS_DP_CTL(pipe);
3040 temp = I915_READ(reg);
3041 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3042 TRANS_DP_SYNC_MASK |
3043 TRANS_DP_BPC_MASK);
3044 temp |= (TRANS_DP_OUTPUT_ENABLE |
3045 TRANS_DP_ENH_FRAMING);
3046 temp |= bpc << 9; /* same format but at 11:9 */
3047
3048 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3049 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3050 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3051 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3052
3053 switch (intel_trans_dp_port_sel(crtc)) {
3054 case PCH_DP_B:
3055 temp |= TRANS_DP_PORT_SEL_B;
3056 break;
3057 case PCH_DP_C:
3058 temp |= TRANS_DP_PORT_SEL_C;
3059 break;
3060 case PCH_DP_D:
3061 temp |= TRANS_DP_PORT_SEL_D;
3062 break;
3063 default:
3064 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3065 temp |= TRANS_DP_PORT_SEL_B;
3066 break;
3067 }
3068
3069 I915_WRITE(reg, temp);
3070 }
3071
3072 intel_enable_transcoder(dev_priv, pipe);
3073}
3074
3075void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3076{
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3079 u32 temp;
3080
3081 temp = I915_READ(dslreg);
3082 DELAY(500);
3083 if (_intel_wait_for(dev, I915_READ(dslreg) != temp, 5, 1, "915cp1")) {
3084 /* Without this, mode sets may fail silently on FDI */
3085 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3086 DELAY(250);
3087 I915_WRITE(tc2reg, 0);
3088 if (_intel_wait_for(dev, I915_READ(dslreg) != temp, 5, 1,
3089 "915cp2"))
3090 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3091 }
3092}
3093
3094static void ironlake_crtc_enable(struct drm_crtc *crtc)
3095{
3096 struct drm_device *dev = crtc->dev;
3097 struct drm_i915_private *dev_priv = dev->dev_private;
3098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3099 int pipe = intel_crtc->pipe;
3100 int plane = intel_crtc->plane;
3101 u32 temp;
3102 bool is_pch_port;
3103
3104 if (intel_crtc->active)
3105 return;
3106
3107 intel_crtc->active = true;
3108 intel_update_watermarks(dev);
3109
3110 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3111 temp = I915_READ(PCH_LVDS);
3112 if ((temp & LVDS_PORT_EN) == 0)
3113 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3114 }
3115
3116 is_pch_port = intel_crtc_driving_pch(crtc);
3117
3118 if (is_pch_port)
3119 ironlake_fdi_pll_enable(crtc);
3120 else
3121 ironlake_fdi_disable(crtc);
3122
3123 /* Enable panel fitting for LVDS */
3124 if (dev_priv->pch_pf_size &&
3125 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3126 /* Force use of hard-coded filter coefficients
3127 * as some pre-programmed values are broken,
3128 * e.g. x201.
3129 */
3130 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3131 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3132 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3133 }
3134
3135 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3136 intel_enable_plane(dev_priv, plane, pipe);
3137
3138 if (is_pch_port)
3139 ironlake_pch_enable(crtc);
3140
3141 intel_crtc_load_lut(crtc);
3142
3143 DRM_LOCK(dev);
3144 intel_update_fbc(dev);
3145 DRM_UNLOCK(dev);
3146
3147 intel_crtc_update_cursor(crtc, true);
3148}
3149
3150static void ironlake_crtc_disable(struct drm_crtc *crtc)
3151{
3152 struct drm_device *dev = crtc->dev;
3153 struct drm_i915_private *dev_priv = dev->dev_private;
3154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3155 int pipe = intel_crtc->pipe;
3156 int plane = intel_crtc->plane;
3157 u32 reg, temp;
3158
3159 if (!intel_crtc->active)
3160 return;
3161
3162 intel_crtc_wait_for_pending_flips(crtc);
3163 drm_vblank_off(dev, pipe);
3164 intel_crtc_update_cursor(crtc, false);
3165
3166 intel_disable_plane(dev_priv, plane, pipe);
3167
3168 if (dev_priv->cfb_plane == plane)
3169 intel_disable_fbc(dev);
3170
3171 intel_disable_pipe(dev_priv, pipe);
3172
3173 /* Disable PF */
3174 I915_WRITE(PF_CTL(pipe), 0);
3175 I915_WRITE(PF_WIN_SZ(pipe), 0);
3176
3177 ironlake_fdi_disable(crtc);
3178
3179 /* This is a horrible layering violation; we should be doing this in
3180 * the connector/encoder ->prepare instead, but we don't always have
3181 * enough information there about the config to know whether it will
3182 * actually be necessary or just cause undesired flicker.
3183 */
3184 intel_disable_pch_ports(dev_priv, pipe);
3185
3186 intel_disable_transcoder(dev_priv, pipe);
3187
3188 if (HAS_PCH_CPT(dev)) {
3189 /* disable TRANS_DP_CTL */
3190 reg = TRANS_DP_CTL(pipe);
3191 temp = I915_READ(reg);
3192 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3193 temp |= TRANS_DP_PORT_SEL_NONE;
3194 I915_WRITE(reg, temp);
3195
3196 /* disable DPLL_SEL */
3197 temp = I915_READ(PCH_DPLL_SEL);
3198 switch (pipe) {
3199 case 0:
3200 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3201 break;
3202 case 1:
3203 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3204 break;
3205 case 2:
3206 /* C shares PLL A or B */
3207 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3208 break;
3209 default:
3210 KASSERT(1, ("Wrong pipe %d", pipe)); /* wtf */
3211 }
3212 I915_WRITE(PCH_DPLL_SEL, temp);
3213 }
3214
3215 /* disable PCH DPLL */
3216 if (!intel_crtc->no_pll)
3217 intel_disable_pch_pll(dev_priv, pipe);
3218
3219 /* Switch from PCDclk to Rawclk */
3220 reg = FDI_RX_CTL(pipe);
3221 temp = I915_READ(reg);
3222 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3223
3224 /* Disable CPU FDI TX PLL */
3225 reg = FDI_TX_CTL(pipe);
3226 temp = I915_READ(reg);
3227 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3228
3229 POSTING_READ(reg);
3230 DELAY(100);
3231
3232 reg = FDI_RX_CTL(pipe);
3233 temp = I915_READ(reg);
3234 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3235
3236 /* Wait for the clocks to turn off. */
3237 POSTING_READ(reg);
3238 DELAY(100);
3239
3240 intel_crtc->active = false;
3241 intel_update_watermarks(dev);
3242
3243 DRM_LOCK(dev);
3244 intel_update_fbc(dev);
3245 intel_clear_scanline_wait(dev);
3246 DRM_UNLOCK(dev);
3247}
3248
3249static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3250{
3251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3252 int pipe = intel_crtc->pipe;
3253 int plane = intel_crtc->plane;
3254
3255 /* XXX: When our outputs are all unaware of DPMS modes other than off
3256 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3257 */
3258 switch (mode) {
3259 case DRM_MODE_DPMS_ON:
3260 case DRM_MODE_DPMS_STANDBY:
3261 case DRM_MODE_DPMS_SUSPEND:
3262 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3263 ironlake_crtc_enable(crtc);
3264 break;
3265
3266 case DRM_MODE_DPMS_OFF:
3267 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3268 ironlake_crtc_disable(crtc);
3269 break;
3270 }
3271}
3272
3273static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3274{
3275 if (!enable && intel_crtc->overlay) {
3276 struct drm_device *dev = intel_crtc->base.dev;
3277 struct drm_i915_private *dev_priv = dev->dev_private;
3278
3279 DRM_LOCK(dev);
3280 dev_priv->mm.interruptible = false;
3281 (void) intel_overlay_switch_off(intel_crtc->overlay);
3282 dev_priv->mm.interruptible = true;
3283 DRM_UNLOCK(dev);
3284 }
3285
3286 /* Let userspace switch the overlay on again. In most cases userspace
3287 * has to recompute where to put it anyway.
3288 */
3289}
3290
3291static void i9xx_crtc_enable(struct drm_crtc *crtc)
3292{
3293 struct drm_device *dev = crtc->dev;
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296 int pipe = intel_crtc->pipe;
3297 int plane = intel_crtc->plane;
3298
3299 if (intel_crtc->active)
3300 return;
3301
3302 intel_crtc->active = true;
3303 intel_update_watermarks(dev);
3304
3305 intel_enable_pll(dev_priv, pipe);
3306 intel_enable_pipe(dev_priv, pipe, false);
3307 intel_enable_plane(dev_priv, plane, pipe);
3308
3309 intel_crtc_load_lut(crtc);
3310 intel_update_fbc(dev);
3311
3312 /* Give the overlay scaler a chance to enable if it's on this pipe */
3313 intel_crtc_dpms_overlay(intel_crtc, true);
3314 intel_crtc_update_cursor(crtc, true);
3315}
3316
3317static void i9xx_crtc_disable(struct drm_crtc *crtc)
3318{
3319 struct drm_device *dev = crtc->dev;
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3322 int pipe = intel_crtc->pipe;
3323 int plane = intel_crtc->plane;
3324
3325 if (!intel_crtc->active)
3326 return;
3327
3328 /* Give the overlay scaler a chance to disable if it's on this pipe */
3329 intel_crtc_wait_for_pending_flips(crtc);
3330 drm_vblank_off(dev, pipe);
3331 intel_crtc_dpms_overlay(intel_crtc, false);
3332 intel_crtc_update_cursor(crtc, false);
3333
3334 if (dev_priv->cfb_plane == plane)
3335 intel_disable_fbc(dev);
3336
3337 intel_disable_plane(dev_priv, plane, pipe);
3338 intel_disable_pipe(dev_priv, pipe);
3339 intel_disable_pll(dev_priv, pipe);
3340
3341 intel_crtc->active = false;
3342 intel_update_fbc(dev);
3343 intel_update_watermarks(dev);
3344 intel_clear_scanline_wait(dev);
3345}
3346
3347static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3348{
3349 /* XXX: When our outputs are all unaware of DPMS modes other than off
3350 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3351 */
3352 switch (mode) {
3353 case DRM_MODE_DPMS_ON:
3354 case DRM_MODE_DPMS_STANDBY:
3355 case DRM_MODE_DPMS_SUSPEND:
3356 i9xx_crtc_enable(crtc);
3357 break;
3358 case DRM_MODE_DPMS_OFF:
3359 i9xx_crtc_disable(crtc);
3360 break;
3361 }
3362}
3363
3364/**
3365 * Sets the power management mode of the pipe and plane.
3366 */
3367static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3368{
3369 struct drm_device *dev = crtc->dev;
3370 struct drm_i915_private *dev_priv = dev->dev_private;
3371#if 0
3372 struct drm_i915_master_private *master_priv;
3373#endif
3374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3375 int pipe = intel_crtc->pipe;
3376 bool enabled;
3377
3378 if (intel_crtc->dpms_mode == mode)
3379 return;
3380
3381 intel_crtc->dpms_mode = mode;
3382
3383 dev_priv->display.dpms(crtc, mode);
3384
3385#if 0
3386 if (!dev->primary->master)
3387 return;
3388
3389 master_priv = dev->primary->master->driver_priv;
3390 if (!master_priv->sarea_priv)
3391 return;
3392#else
3393 if (!dev_priv->sarea_priv)
3394 return;
3395#endif
3396
3397 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3398
3399 switch (pipe) {
3400 case 0:
3401#if 0
3402 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3403 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3404#else
3405 dev_priv->sarea_priv->planeA_w = enabled ? crtc->mode.hdisplay : 0;
3406 dev_priv->sarea_priv->planeA_h = enabled ? crtc->mode.vdisplay : 0;
3407#endif
3408 break;
3409 case 1:
3410#if 0
3411 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3412 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3413#else
3414 dev_priv->sarea_priv->planeB_w = enabled ? crtc->mode.hdisplay : 0;
3415 dev_priv->sarea_priv->planeB_h = enabled ? crtc->mode.vdisplay : 0;
3416#endif
3417 break;
3418 default:
3419 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3420 break;
3421 }
3422}
3423
3424static void intel_crtc_disable(struct drm_crtc *crtc)
3425{
3426 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3427 struct drm_device *dev = crtc->dev;
3428
3429 /* Flush any pending WAITs before we disable the pipe. Note that
3430 * we need to drop the struct_mutex in order to acquire it again
3431 * during the lowlevel dpms routines around a couple of the
3432 * operations. It does not look trivial nor desirable to move
3433 * that locking higher. So instead we leave a window for the
3434 * submission of further commands on the fb before we can actually
3435 * disable it. This race with userspace exists anyway, and we can
3436 * only rely on the pipe being disabled by userspace after it
3437 * receives the hotplug notification and has flushed any pending
3438 * batches.
3439 */
3440 if (crtc->fb) {
3441 DRM_LOCK(dev);
3442 intel_finish_fb(crtc->fb);
3443 DRM_UNLOCK(dev);
3444 }
3445
3446 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3447 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3448 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3449
3450 if (crtc->fb) {
3451 DRM_LOCK(dev);
3452 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3453 DRM_UNLOCK(dev);
3454 }
3455}
3456
3457/* Prepare for a mode set.
3458 *
3459 * Note we could be a lot smarter here. We need to figure out which outputs
3460 * will be enabled, which disabled (in short, how the config will changes)
3461 * and perform the minimum necessary steps to accomplish that, e.g. updating
3462 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3463 * panel fitting is in the proper state, etc.
3464 */
3465static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3466{
3467 i9xx_crtc_disable(crtc);
3468}
3469
3470static void i9xx_crtc_commit(struct drm_crtc *crtc)
3471{
3472 i9xx_crtc_enable(crtc);
3473}
3474
3475static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3476{
3477 ironlake_crtc_disable(crtc);
3478}
3479
3480static void ironlake_crtc_commit(struct drm_crtc *crtc)
3481{
3482 ironlake_crtc_enable(crtc);
3483}
3484
3485void intel_encoder_prepare(struct drm_encoder *encoder)
3486{
3487 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3488 /* lvds has its own version of prepare see intel_lvds_prepare */
3489 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3490}
3491
3492void intel_encoder_commit(struct drm_encoder *encoder)
3493{
3494 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3495 struct drm_device *dev = encoder->dev;
3496 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3497 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3498
3499 /* lvds has its own version of commit see intel_lvds_commit */
3500 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3501
3502 if (HAS_PCH_CPT(dev))
3503 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3504}
3505
3506void intel_encoder_destroy(struct drm_encoder *encoder)
3507{
3508 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3509
3510 drm_encoder_cleanup(encoder);
3511 free(intel_encoder, DRM_MEM_KMS);
3512}
3513
3514static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
| 29
30#include <dev/drm2/drmP.h>
31#include <dev/drm2/drm.h>
32#include <dev/drm2/i915/i915_drm.h>
33#include <dev/drm2/i915/i915_drv.h>
34#include <dev/drm2/i915/intel_drv.h>
35#include <dev/drm2/drm_edid.h>
36#include <dev/drm2/drm_dp_helper.h>
37#include <dev/drm2/drm_crtc_helper.h>
38#include <sys/kdb.h>
39#include <sys/limits.h>
40
41#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
42
43bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
44static void intel_update_watermarks(struct drm_device *dev);
45static void intel_increase_pllclock(struct drm_crtc *crtc);
46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58} intel_clock_t;
59
60typedef struct {
61 int min, max;
62} intel_range_t;
63
64typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
76};
77
78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
81static bool
82intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
83 int target, int refclk, intel_clock_t *match_clock,
84 intel_clock_t *best_clock);
85static bool
86intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *match_clock,
88 intel_clock_t *best_clock);
89
90static bool
91intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *match_clock,
93 intel_clock_t *best_clock);
94static bool
95intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *match_clock,
97 intel_clock_t *best_clock);
98
99static inline u32 /* units of 100MHz */
100intel_fdi_link_freq(struct drm_device *dev)
101{
102 if (IS_GEN5(dev)) {
103 struct drm_i915_private *dev_priv = dev->dev_private;
104 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
105 } else
106 return 27;
107}
108
109static const intel_limit_t intel_limits_i8xx_dvo = {
110 .dot = { .min = 25000, .max = 350000 },
111 .vco = { .min = 930000, .max = 1400000 },
112 .n = { .min = 3, .max = 16 },
113 .m = { .min = 96, .max = 140 },
114 .m1 = { .min = 18, .max = 26 },
115 .m2 = { .min = 6, .max = 16 },
116 .p = { .min = 4, .max = 128 },
117 .p1 = { .min = 2, .max = 33 },
118 .p2 = { .dot_limit = 165000,
119 .p2_slow = 4, .p2_fast = 2 },
120 .find_pll = intel_find_best_PLL,
121};
122
123static const intel_limit_t intel_limits_i8xx_lvds = {
124 .dot = { .min = 25000, .max = 350000 },
125 .vco = { .min = 930000, .max = 1400000 },
126 .n = { .min = 3, .max = 16 },
127 .m = { .min = 96, .max = 140 },
128 .m1 = { .min = 18, .max = 26 },
129 .m2 = { .min = 6, .max = 16 },
130 .p = { .min = 4, .max = 128 },
131 .p1 = { .min = 1, .max = 6 },
132 .p2 = { .dot_limit = 165000,
133 .p2_slow = 14, .p2_fast = 7 },
134 .find_pll = intel_find_best_PLL,
135};
136
137static const intel_limit_t intel_limits_i9xx_sdvo = {
138 .dot = { .min = 20000, .max = 400000 },
139 .vco = { .min = 1400000, .max = 2800000 },
140 .n = { .min = 1, .max = 6 },
141 .m = { .min = 70, .max = 120 },
142 .m1 = { .min = 10, .max = 22 },
143 .m2 = { .min = 5, .max = 9 },
144 .p = { .min = 5, .max = 80 },
145 .p1 = { .min = 1, .max = 8 },
146 .p2 = { .dot_limit = 200000,
147 .p2_slow = 10, .p2_fast = 5 },
148 .find_pll = intel_find_best_PLL,
149};
150
151static const intel_limit_t intel_limits_i9xx_lvds = {
152 .dot = { .min = 20000, .max = 400000 },
153 .vco = { .min = 1400000, .max = 2800000 },
154 .n = { .min = 1, .max = 6 },
155 .m = { .min = 70, .max = 120 },
156 .m1 = { .min = 10, .max = 22 },
157 .m2 = { .min = 5, .max = 9 },
158 .p = { .min = 7, .max = 98 },
159 .p1 = { .min = 1, .max = 8 },
160 .p2 = { .dot_limit = 112000,
161 .p2_slow = 14, .p2_fast = 7 },
162 .find_pll = intel_find_best_PLL,
163};
164
165
166static const intel_limit_t intel_limits_g4x_sdvo = {
167 .dot = { .min = 25000, .max = 270000 },
168 .vco = { .min = 1750000, .max = 3500000},
169 .n = { .min = 1, .max = 4 },
170 .m = { .min = 104, .max = 138 },
171 .m1 = { .min = 17, .max = 23 },
172 .m2 = { .min = 5, .max = 11 },
173 .p = { .min = 10, .max = 30 },
174 .p1 = { .min = 1, .max = 3},
175 .p2 = { .dot_limit = 270000,
176 .p2_slow = 10,
177 .p2_fast = 10
178 },
179 .find_pll = intel_g4x_find_best_PLL,
180};
181
182static const intel_limit_t intel_limits_g4x_hdmi = {
183 .dot = { .min = 22000, .max = 400000 },
184 .vco = { .min = 1750000, .max = 3500000},
185 .n = { .min = 1, .max = 4 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 16, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 5, .max = 80 },
190 .p1 = { .min = 1, .max = 8},
191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 10, .p2_fast = 5 },
193 .find_pll = intel_g4x_find_best_PLL,
194};
195
196static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
197 .dot = { .min = 20000, .max = 115000 },
198 .vco = { .min = 1750000, .max = 3500000 },
199 .n = { .min = 1, .max = 3 },
200 .m = { .min = 104, .max = 138 },
201 .m1 = { .min = 17, .max = 23 },
202 .m2 = { .min = 5, .max = 11 },
203 .p = { .min = 28, .max = 112 },
204 .p1 = { .min = 2, .max = 8 },
205 .p2 = { .dot_limit = 0,
206 .p2_slow = 14, .p2_fast = 14
207 },
208 .find_pll = intel_g4x_find_best_PLL,
209};
210
211static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
212 .dot = { .min = 80000, .max = 224000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 14, .max = 42 },
219 .p1 = { .min = 2, .max = 6 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 7, .p2_fast = 7
222 },
223 .find_pll = intel_g4x_find_best_PLL,
224};
225
226static const intel_limit_t intel_limits_g4x_display_port = {
227 .dot = { .min = 161670, .max = 227000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 2 },
230 .m = { .min = 97, .max = 108 },
231 .m1 = { .min = 0x10, .max = 0x12 },
232 .m2 = { .min = 0x05, .max = 0x06 },
233 .p = { .min = 10, .max = 20 },
234 .p1 = { .min = 1, .max = 2},
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 10, .p2_fast = 10 },
237 .find_pll = intel_find_pll_g4x_dp,
238};
239
240static const intel_limit_t intel_limits_pineview_sdvo = {
241 .dot = { .min = 20000, .max = 400000},
242 .vco = { .min = 1700000, .max = 3500000 },
243 /* Pineview's Ncounter is a ring counter */
244 .n = { .min = 3, .max = 6 },
245 .m = { .min = 2, .max = 256 },
246 /* Pineview only has one combined m divider, which we treat as m2. */
247 .m1 = { .min = 0, .max = 0 },
248 .m2 = { .min = 0, .max = 254 },
249 .p = { .min = 5, .max = 80 },
250 .p1 = { .min = 1, .max = 8 },
251 .p2 = { .dot_limit = 200000,
252 .p2_slow = 10, .p2_fast = 5 },
253 .find_pll = intel_find_best_PLL,
254};
255
256static const intel_limit_t intel_limits_pineview_lvds = {
257 .dot = { .min = 20000, .max = 400000 },
258 .vco = { .min = 1700000, .max = 3500000 },
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 .m1 = { .min = 0, .max = 0 },
262 .m2 = { .min = 0, .max = 254 },
263 .p = { .min = 7, .max = 112 },
264 .p1 = { .min = 1, .max = 8 },
265 .p2 = { .dot_limit = 112000,
266 .p2_slow = 14, .p2_fast = 14 },
267 .find_pll = intel_find_best_PLL,
268};
269
270/* Ironlake / Sandybridge
271 *
272 * We calculate clock using (register_value + 2) for N/M1/M2, so here
273 * the range value for them is (actual_value - 2).
274 */
275static const intel_limit_t intel_limits_ironlake_dac = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 1760000, .max = 3510000 },
278 .n = { .min = 1, .max = 5 },
279 .m = { .min = 79, .max = 127 },
280 .m1 = { .min = 12, .max = 22 },
281 .m2 = { .min = 5, .max = 9 },
282 .p = { .min = 5, .max = 80 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 225000,
285 .p2_slow = 10, .p2_fast = 5 },
286 .find_pll = intel_g4x_find_best_PLL,
287};
288
289static const intel_limit_t intel_limits_ironlake_single_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 1760000, .max = 3510000 },
292 .n = { .min = 1, .max = 3 },
293 .m = { .min = 79, .max = 118 },
294 .m1 = { .min = 12, .max = 22 },
295 .m2 = { .min = 5, .max = 9 },
296 .p = { .min = 28, .max = 112 },
297 .p1 = { .min = 2, .max = 8 },
298 .p2 = { .dot_limit = 225000,
299 .p2_slow = 14, .p2_fast = 14 },
300 .find_pll = intel_g4x_find_best_PLL,
301};
302
303static const intel_limit_t intel_limits_ironlake_dual_lvds = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 56 },
311 .p1 = { .min = 2, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
314 .find_pll = intel_g4x_find_best_PLL,
315};
316
317/* LVDS 100mhz refclk limits. */
318static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 2 },
322 .m = { .min = 79, .max = 126 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 14, .p2_fast = 14 },
329 .find_pll = intel_g4x_find_best_PLL,
330};
331
332static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
333 .dot = { .min = 25000, .max = 350000 },
334 .vco = { .min = 1760000, .max = 3510000 },
335 .n = { .min = 1, .max = 3 },
336 .m = { .min = 79, .max = 126 },
337 .m1 = { .min = 12, .max = 22 },
338 .m2 = { .min = 5, .max = 9 },
339 .p = { .min = 14, .max = 42 },
340 .p1 = { .min = 2, .max = 6 },
341 .p2 = { .dot_limit = 225000,
342 .p2_slow = 7, .p2_fast = 7 },
343 .find_pll = intel_g4x_find_best_PLL,
344};
345
346static const intel_limit_t intel_limits_ironlake_display_port = {
347 .dot = { .min = 25000, .max = 350000 },
348 .vco = { .min = 1760000, .max = 3510000},
349 .n = { .min = 1, .max = 2 },
350 .m = { .min = 81, .max = 90 },
351 .m1 = { .min = 12, .max = 22 },
352 .m2 = { .min = 5, .max = 9 },
353 .p = { .min = 10, .max = 20 },
354 .p1 = { .min = 1, .max = 2},
355 .p2 = { .dot_limit = 0,
356 .p2_slow = 10, .p2_fast = 10 },
357 .find_pll = intel_find_pll_ironlake_dp,
358};
359
360static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
361 int refclk)
362{
363 struct drm_device *dev = crtc->dev;
364 struct drm_i915_private *dev_priv = dev->dev_private;
365 const intel_limit_t *limit;
366
367 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
368 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
369 LVDS_CLKB_POWER_UP) {
370 /* LVDS dual channel */
371 if (refclk == 100000)
372 limit = &intel_limits_ironlake_dual_lvds_100m;
373 else
374 limit = &intel_limits_ironlake_dual_lvds;
375 } else {
376 if (refclk == 100000)
377 limit = &intel_limits_ironlake_single_lvds_100m;
378 else
379 limit = &intel_limits_ironlake_single_lvds;
380 }
381 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
382 HAS_eDP)
383 limit = &intel_limits_ironlake_display_port;
384 else
385 limit = &intel_limits_ironlake_dac;
386
387 return limit;
388}
389
390static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
391{
392 struct drm_device *dev = crtc->dev;
393 struct drm_i915_private *dev_priv = dev->dev_private;
394 const intel_limit_t *limit;
395
396 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
397 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
398 LVDS_CLKB_POWER_UP)
399 /* LVDS with dual channel */
400 limit = &intel_limits_g4x_dual_channel_lvds;
401 else
402 /* LVDS with dual channel */
403 limit = &intel_limits_g4x_single_channel_lvds;
404 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
405 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
406 limit = &intel_limits_g4x_hdmi;
407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
408 limit = &intel_limits_g4x_sdvo;
409 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
410 limit = &intel_limits_g4x_display_port;
411 } else /* The option is for other outputs */
412 limit = &intel_limits_i9xx_sdvo;
413
414 return limit;
415}
416
417static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
418{
419 struct drm_device *dev = crtc->dev;
420 const intel_limit_t *limit;
421
422 if (HAS_PCH_SPLIT(dev))
423 limit = intel_ironlake_limit(crtc, refclk);
424 else if (IS_G4X(dev)) {
425 limit = intel_g4x_limit(crtc);
426 } else if (IS_PINEVIEW(dev)) {
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
428 limit = &intel_limits_pineview_lvds;
429 else
430 limit = &intel_limits_pineview_sdvo;
431 } else if (!IS_GEN2(dev)) {
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
433 limit = &intel_limits_i9xx_lvds;
434 else
435 limit = &intel_limits_i9xx_sdvo;
436 } else {
437 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
438 limit = &intel_limits_i8xx_lvds;
439 else
440 limit = &intel_limits_i8xx_dvo;
441 }
442 return limit;
443}
444
445/* m1 is reserved as 0 in Pineview, n is a ring counter */
446static void pineview_clock(int refclk, intel_clock_t *clock)
447{
448 clock->m = clock->m2 + 2;
449 clock->p = clock->p1 * clock->p2;
450 clock->vco = refclk * clock->m / clock->n;
451 clock->dot = clock->vco / clock->p;
452}
453
454static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
455{
456 if (IS_PINEVIEW(dev)) {
457 pineview_clock(refclk, clock);
458 return;
459 }
460 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
461 clock->p = clock->p1 * clock->p2;
462 clock->vco = refclk * clock->m / (clock->n + 2);
463 clock->dot = clock->vco / clock->p;
464}
465
466/**
467 * Returns whether any output on the specified pipe is of the specified type
468 */
469bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
470{
471 struct drm_device *dev = crtc->dev;
472 struct drm_mode_config *mode_config = &dev->mode_config;
473 struct intel_encoder *encoder;
474
475 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
476 if (encoder->base.crtc == crtc && encoder->type == type)
477 return true;
478
479 return false;
480}
481
482#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
483/**
484 * Returns whether the given set of divisors are valid for a given refclk with
485 * the given connectors.
486 */
487
488static bool intel_PLL_is_valid(struct drm_device *dev,
489 const intel_limit_t *limit,
490 const intel_clock_t *clock)
491{
492 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
493 INTELPllInvalid("p1 out of range\n");
494 if (clock->p < limit->p.min || limit->p.max < clock->p)
495 INTELPllInvalid("p out of range\n");
496 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
497 INTELPllInvalid("m2 out of range\n");
498 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
499 INTELPllInvalid("m1 out of range\n");
500 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
501 INTELPllInvalid("m1 <= m2\n");
502 if (clock->m < limit->m.min || limit->m.max < clock->m)
503 INTELPllInvalid("m out of range\n");
504 if (clock->n < limit->n.min || limit->n.max < clock->n)
505 INTELPllInvalid("n out of range\n");
506 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
507 INTELPllInvalid("vco out of range\n");
508 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
509 * connector, etc., rather than just a single range.
510 */
511 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
512 INTELPllInvalid("dot out of range\n");
513
514 return true;
515}
516
517static bool
518intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
519 int target, int refclk, intel_clock_t *match_clock,
520 intel_clock_t *best_clock)
521
522{
523 struct drm_device *dev = crtc->dev;
524 struct drm_i915_private *dev_priv = dev->dev_private;
525 intel_clock_t clock;
526 int err = target;
527
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
529 (I915_READ(LVDS)) != 0) {
530 /*
531 * For LVDS, if the panel is on, just rely on its current
532 * settings for dual-channel. We haven't figured out how to
533 * reliably set up different single/dual channel state, if we
534 * even can.
535 */
536 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
537 LVDS_CLKB_POWER_UP)
538 clock.p2 = limit->p2.p2_fast;
539 else
540 clock.p2 = limit->p2.p2_slow;
541 } else {
542 if (target < limit->p2.dot_limit)
543 clock.p2 = limit->p2.p2_slow;
544 else
545 clock.p2 = limit->p2.p2_fast;
546 }
547
548 memset(best_clock, 0, sizeof(*best_clock));
549
550 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
551 clock.m1++) {
552 for (clock.m2 = limit->m2.min;
553 clock.m2 <= limit->m2.max; clock.m2++) {
554 /* m1 is always 0 in Pineview */
555 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
556 break;
557 for (clock.n = limit->n.min;
558 clock.n <= limit->n.max; clock.n++) {
559 for (clock.p1 = limit->p1.min;
560 clock.p1 <= limit->p1.max; clock.p1++) {
561 int this_err;
562
563 intel_clock(dev, refclk, &clock);
564 if (!intel_PLL_is_valid(dev, limit,
565 &clock))
566 continue;
567 if (match_clock &&
568 clock.p != match_clock->p)
569 continue;
570
571 this_err = abs(clock.dot - target);
572 if (this_err < err) {
573 *best_clock = clock;
574 err = this_err;
575 }
576 }
577 }
578 }
579 }
580
581 return (err != target);
582}
583
584static bool
585intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
586 int target, int refclk, intel_clock_t *match_clock,
587 intel_clock_t *best_clock)
588{
589 struct drm_device *dev = crtc->dev;
590 struct drm_i915_private *dev_priv = dev->dev_private;
591 intel_clock_t clock;
592 int max_n;
593 bool found;
594 /* approximately equals target * 0.00585 */
595 int err_most = (target >> 8) + (target >> 9);
596 found = false;
597
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
599 int lvds_reg;
600
601 if (HAS_PCH_SPLIT(dev))
602 lvds_reg = PCH_LVDS;
603 else
604 lvds_reg = LVDS;
605 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
606 LVDS_CLKB_POWER_UP)
607 clock.p2 = limit->p2.p2_fast;
608 else
609 clock.p2 = limit->p2.p2_slow;
610 } else {
611 if (target < limit->p2.dot_limit)
612 clock.p2 = limit->p2.p2_slow;
613 else
614 clock.p2 = limit->p2.p2_fast;
615 }
616
617 memset(best_clock, 0, sizeof(*best_clock));
618 max_n = limit->n.max;
619 /* based on hardware requirement, prefer smaller n to precision */
620 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
621 /* based on hardware requirement, prefere larger m1,m2 */
622 for (clock.m1 = limit->m1.max;
623 clock.m1 >= limit->m1.min; clock.m1--) {
624 for (clock.m2 = limit->m2.max;
625 clock.m2 >= limit->m2.min; clock.m2--) {
626 for (clock.p1 = limit->p1.max;
627 clock.p1 >= limit->p1.min; clock.p1--) {
628 int this_err;
629
630 intel_clock(dev, refclk, &clock);
631 if (!intel_PLL_is_valid(dev, limit,
632 &clock))
633 continue;
634 if (match_clock &&
635 clock.p != match_clock->p)
636 continue;
637
638 this_err = abs(clock.dot - target);
639 if (this_err < err_most) {
640 *best_clock = clock;
641 err_most = this_err;
642 max_n = clock.n;
643 found = true;
644 }
645 }
646 }
647 }
648 }
649 return found;
650}
651
652static bool
653intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
654 int target, int refclk, intel_clock_t *match_clock,
655 intel_clock_t *best_clock)
656{
657 struct drm_device *dev = crtc->dev;
658 intel_clock_t clock;
659
660 if (target < 200000) {
661 clock.n = 1;
662 clock.p1 = 2;
663 clock.p2 = 10;
664 clock.m1 = 12;
665 clock.m2 = 9;
666 } else {
667 clock.n = 2;
668 clock.p1 = 1;
669 clock.p2 = 10;
670 clock.m1 = 14;
671 clock.m2 = 8;
672 }
673 intel_clock(dev, refclk, &clock);
674 memcpy(best_clock, &clock, sizeof(intel_clock_t));
675 return true;
676}
677
678/* DisplayPort has only two frequencies, 162MHz and 270MHz */
679static bool
680intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
681 int target, int refclk, intel_clock_t *match_clock,
682 intel_clock_t *best_clock)
683{
684 intel_clock_t clock;
685 if (target < 200000) {
686 clock.p1 = 2;
687 clock.p2 = 10;
688 clock.n = 2;
689 clock.m1 = 23;
690 clock.m2 = 8;
691 } else {
692 clock.p1 = 1;
693 clock.p2 = 10;
694 clock.n = 1;
695 clock.m1 = 14;
696 clock.m2 = 2;
697 }
698 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
699 clock.p = (clock.p1 * clock.p2);
700 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
701 clock.vco = 0;
702 memcpy(best_clock, &clock, sizeof(intel_clock_t));
703 return true;
704}
705
706/**
707 * intel_wait_for_vblank - wait for vblank on a given pipe
708 * @dev: drm device
709 * @pipe: pipe to wait for
710 *
711 * Wait for vblank to occur on a given pipe. Needed for various bits of
712 * mode setting code.
713 */
714void intel_wait_for_vblank(struct drm_device *dev, int pipe)
715{
716 struct drm_i915_private *dev_priv = dev->dev_private;
717 int pipestat_reg = PIPESTAT(pipe);
718
719 /* Clear existing vblank status. Note this will clear any other
720 * sticky status fields as well.
721 *
722 * This races with i915_driver_irq_handler() with the result
723 * that either function could miss a vblank event. Here it is not
724 * fatal, as we will either wait upon the next vblank interrupt or
725 * timeout. Generally speaking intel_wait_for_vblank() is only
726 * called during modeset at which time the GPU should be idle and
727 * should *not* be performing page flips and thus not waiting on
728 * vblanks...
729 * Currently, the result of us stealing a vblank from the irq
730 * handler is that a single frame will be skipped during swapbuffers.
731 */
732 I915_WRITE(pipestat_reg,
733 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
734
735 /* Wait for vblank interrupt bit to set */
736 if (_intel_wait_for(dev,
737 I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS,
738 50, 1, "915vbl"))
739 DRM_DEBUG_KMS("vblank wait timed out\n");
740}
741
742/*
743 * intel_wait_for_pipe_off - wait for pipe to turn off
744 * @dev: drm device
745 * @pipe: pipe to wait for
746 *
747 * After disabling a pipe, we can't wait for vblank in the usual way,
748 * spinning on the vblank interrupt status bit, since we won't actually
749 * see an interrupt when the pipe is disabled.
750 *
751 * On Gen4 and above:
752 * wait for the pipe register state bit to turn off
753 *
754 * Otherwise:
755 * wait for the display line value to settle (it usually
756 * ends up stopping at the start of the next frame).
757 *
758 */
759void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
760{
761 struct drm_i915_private *dev_priv = dev->dev_private;
762
763 if (INTEL_INFO(dev)->gen >= 4) {
764 int reg = PIPECONF(pipe);
765
766 /* Wait for the Pipe State to go off */
767 if (_intel_wait_for(dev,
768 (I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 100,
769 1, "915pip"))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
771 } else {
772 u32 last_line;
773 int reg = PIPEDSL(pipe);
774 unsigned long timeout = jiffies + msecs_to_jiffies(100);
775
776 /* Wait for the display line to settle */
777 do {
778 last_line = I915_READ(reg) & DSL_LINEMASK;
779 DELAY(5000);
780 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
781 time_after(timeout, jiffies));
782 if (time_after(jiffies, timeout))
783 DRM_DEBUG_KMS("pipe_off wait timed out\n");
784 }
785}
786
787static const char *state_string(bool enabled)
788{
789 return enabled ? "on" : "off";
790}
791
792/* Only for pre-ILK configs */
793static void assert_pll(struct drm_i915_private *dev_priv,
794 enum pipe pipe, bool state)
795{
796 int reg;
797 u32 val;
798 bool cur_state;
799
800 reg = DPLL(pipe);
801 val = I915_READ(reg);
802 cur_state = !!(val & DPLL_VCO_ENABLE);
803 if (cur_state != state)
804 printf("PLL state assertion failure (expected %s, current %s)\n",
805 state_string(state), state_string(cur_state));
806}
807#define assert_pll_enabled(d, p) assert_pll(d, p, true)
808#define assert_pll_disabled(d, p) assert_pll(d, p, false)
809
810/* For ILK+ */
811static void assert_pch_pll(struct drm_i915_private *dev_priv,
812 enum pipe pipe, bool state)
813{
814 int reg;
815 u32 val;
816 bool cur_state;
817
818 if (HAS_PCH_CPT(dev_priv->dev)) {
819 u32 pch_dpll;
820
821 pch_dpll = I915_READ(PCH_DPLL_SEL);
822
823 /* Make sure the selected PLL is enabled to the transcoder */
824 KASSERT(((pch_dpll >> (4 * pipe)) & 8) != 0,
825 ("transcoder %d PLL not enabled\n", pipe));
826
827 /* Convert the transcoder pipe number to a pll pipe number */
828 pipe = (pch_dpll >> (4 * pipe)) & 1;
829 }
830
831 reg = PCH_DPLL(pipe);
832 val = I915_READ(reg);
833 cur_state = !!(val & DPLL_VCO_ENABLE);
834 if (cur_state != state)
835 printf("PCH PLL state assertion failure (expected %s, current %s)\n",
836 state_string(state), state_string(cur_state));
837}
838#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
839#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
840
841static void assert_fdi_tx(struct drm_i915_private *dev_priv,
842 enum pipe pipe, bool state)
843{
844 int reg;
845 u32 val;
846 bool cur_state;
847
848 reg = FDI_TX_CTL(pipe);
849 val = I915_READ(reg);
850 cur_state = !!(val & FDI_TX_ENABLE);
851 if (cur_state != state)
852 printf("FDI TX state assertion failure (expected %s, current %s)\n",
853 state_string(state), state_string(cur_state));
854}
855#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
856#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
857
858static void assert_fdi_rx(struct drm_i915_private *dev_priv,
859 enum pipe pipe, bool state)
860{
861 int reg;
862 u32 val;
863 bool cur_state;
864
865 reg = FDI_RX_CTL(pipe);
866 val = I915_READ(reg);
867 cur_state = !!(val & FDI_RX_ENABLE);
868 if (cur_state != state)
869 printf("FDI RX state assertion failure (expected %s, current %s)\n",
870 state_string(state), state_string(cur_state));
871}
872#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
873#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
874
875static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
876 enum pipe pipe)
877{
878 int reg;
879 u32 val;
880
881 /* ILK FDI PLL is always enabled */
882 if (dev_priv->info->gen == 5)
883 return;
884
885 reg = FDI_TX_CTL(pipe);
886 val = I915_READ(reg);
887 if (!(val & FDI_TX_PLL_ENABLE))
888 printf("FDI TX PLL assertion failure, should be active but is disabled\n");
889}
890
891static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
892 enum pipe pipe)
893{
894 int reg;
895 u32 val;
896
897 reg = FDI_RX_CTL(pipe);
898 val = I915_READ(reg);
899 if (!(val & FDI_RX_PLL_ENABLE))
900 printf("FDI RX PLL assertion failure, should be active but is disabled\n");
901}
902
903static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905{
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
909 bool locked = true;
910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 if (panel_pipe == pipe && locked)
928 printf("panel assertion failure, pipe %c regs locked\n",
929 pipe_name(pipe));
930}
931
932void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
934{
935 int reg;
936 u32 val;
937 bool cur_state;
938
939 /* if we need the pipe A quirk it must be always on */
940 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941 state = true;
942
943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
945 cur_state = !!(val & PIPECONF_ENABLE);
946 if (cur_state != state)
947 printf("pipe %c assertion failure (expected %s, current %s)\n",
948 pipe_name(pipe), state_string(state), state_string(cur_state));
949}
950
951static void assert_plane(struct drm_i915_private *dev_priv,
952 enum plane plane, bool state)
953{
954 int reg;
955 u32 val;
956 bool cur_state;
957
958 reg = DSPCNTR(plane);
959 val = I915_READ(reg);
960 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961 if (cur_state != state)
962 printf("plane %c assertion failure, (expected %s, current %s)\n",
963 plane_name(plane), state_string(state), state_string(cur_state));
964}
965
966#define assert_plane_enabled(d, p) assert_plane(d, p, true)
967#define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
969static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971{
972 int reg, i;
973 u32 val;
974 int cur_pipe;
975
976 /* Planes are fixed to pipes on ILK+ */
977 if (HAS_PCH_SPLIT(dev_priv->dev)) {
978 reg = DSPCNTR(pipe);
979 val = I915_READ(reg);
980 if ((val & DISPLAY_PLANE_ENABLE) != 0)
981 printf("plane %c assertion failure, should be disabled but not\n",
982 plane_name(pipe));
983 return;
984 }
985
986 /* Need to check both planes against the pipe */
987 for (i = 0; i < 2; i++) {
988 reg = DSPCNTR(i);
989 val = I915_READ(reg);
990 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991 DISPPLANE_SEL_PIPE_SHIFT;
992 if ((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe)
993 printf("plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i), pipe_name(pipe));
995 }
996}
997
998static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999{
1000 u32 val;
1001 bool enabled;
1002
1003 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK));
1006 if (!enabled)
1007 printf("PCH refclk assertion failure, should be active but is disabled\n");
1008}
1009
1010static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1011 enum pipe pipe)
1012{
1013 int reg;
1014 u32 val;
1015 bool enabled;
1016
1017 reg = TRANSCONF(pipe);
1018 val = I915_READ(reg);
1019 enabled = !!(val & TRANS_ENABLE);
1020 if (enabled)
1021 printf("transcoder assertion failed, should be off on pipe %c but is still active\n",
1022 pipe_name(pipe));
1023}
1024
1025static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1026 enum pipe pipe, u32 val)
1027{
1028 if ((val & PORT_ENABLE) == 0)
1029 return false;
1030
1031 if (HAS_PCH_CPT(dev_priv->dev)) {
1032 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1033 return false;
1034 } else {
1035 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1036 return false;
1037 }
1038 return true;
1039}
1040
1041static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1042 enum pipe pipe, u32 val)
1043{
1044 if ((val & LVDS_PORT_EN) == 0)
1045 return false;
1046
1047 if (HAS_PCH_CPT(dev_priv->dev)) {
1048 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1049 return false;
1050 } else {
1051 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1052 return false;
1053 }
1054 return true;
1055}
1056
1057static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1058 enum pipe pipe, u32 val)
1059{
1060 if ((val & ADPA_DAC_ENABLE) == 0)
1061 return false;
1062 if (HAS_PCH_CPT(dev_priv->dev)) {
1063 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1064 return false;
1065 } else {
1066 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1067 return false;
1068 }
1069 return true;
1070}
1071
1072static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, u32 port_sel, u32 val)
1074{
1075 if ((val & DP_PORT_EN) == 0)
1076 return false;
1077
1078 if (HAS_PCH_CPT(dev_priv->dev)) {
1079 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1080 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1081 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1082 return false;
1083 } else {
1084 if ((val & DP_PIPE_MASK) != (pipe << 30))
1085 return false;
1086 }
1087 return true;
1088}
1089
1090static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1091 enum pipe pipe, int reg, u32 port_sel)
1092{
1093 u32 val = I915_READ(reg);
1094 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val))
1095 printf("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1096 reg, pipe_name(pipe));
1097}
1098
1099static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1100 enum pipe pipe, int reg)
1101{
1102 u32 val = I915_READ(reg);
1103 if (hdmi_pipe_enabled(dev_priv, val, pipe))
1104 printf("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1105 reg, pipe_name(pipe));
1106}
1107
1108static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1109 enum pipe pipe)
1110{
1111 int reg;
1112 u32 val;
1113
1114 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1115 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1116 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1117
1118 reg = PCH_ADPA;
1119 val = I915_READ(reg);
1120 if (adpa_pipe_enabled(dev_priv, val, pipe))
1121 printf("PCH VGA enabled on transcoder %c, should be disabled\n",
1122 pipe_name(pipe));
1123
1124 reg = PCH_LVDS;
1125 val = I915_READ(reg);
1126 if (lvds_pipe_enabled(dev_priv, val, pipe))
1127 printf("PCH LVDS enabled on transcoder %c, should be disabled\n",
1128 pipe_name(pipe));
1129
1130 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1131 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1132 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1133}
1134
1135/**
1136 * intel_enable_pll - enable a PLL
1137 * @dev_priv: i915 private structure
1138 * @pipe: pipe PLL to enable
1139 *
1140 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1141 * make sure the PLL reg is writable first though, since the panel write
1142 * protect mechanism may be enabled.
1143 *
1144 * Note! This is for pre-ILK only.
1145 */
1146static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* No really, not for ILK+ */
1152 KASSERT(dev_priv->info->gen < 5, ("Wrong device gen"));
1153
1154 /* PLL is protected by panel, make sure we can write it */
1155 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1156 assert_panel_unlocked(dev_priv, pipe);
1157
1158 reg = DPLL(pipe);
1159 val = I915_READ(reg);
1160 val |= DPLL_VCO_ENABLE;
1161
1162 /* We do this three times for luck */
1163 I915_WRITE(reg, val);
1164 POSTING_READ(reg);
1165 DELAY(150); /* wait for warmup */
1166 I915_WRITE(reg, val);
1167 POSTING_READ(reg);
1168 DELAY(150); /* wait for warmup */
1169 I915_WRITE(reg, val);
1170 POSTING_READ(reg);
1171 DELAY(150); /* wait for warmup */
1172}
1173
1174/**
1175 * intel_disable_pll - disable a PLL
1176 * @dev_priv: i915 private structure
1177 * @pipe: pipe PLL to disable
1178 *
1179 * Disable the PLL for @pipe, making sure the pipe is off first.
1180 *
1181 * Note! This is for pre-ILK only.
1182 */
1183static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1184{
1185 int reg;
1186 u32 val;
1187
1188 /* Don't disable pipe A or pipe A PLLs if needed */
1189 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1190 return;
1191
1192 /* Make sure the pipe isn't still relying on us */
1193 assert_pipe_disabled(dev_priv, pipe);
1194
1195 reg = DPLL(pipe);
1196 val = I915_READ(reg);
1197 val &= ~DPLL_VCO_ENABLE;
1198 I915_WRITE(reg, val);
1199 POSTING_READ(reg);
1200}
1201
1202/**
1203 * intel_enable_pch_pll - enable PCH PLL
1204 * @dev_priv: i915 private structure
1205 * @pipe: pipe PLL to enable
1206 *
1207 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1208 * drives the transcoder clock.
1209 */
1210static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1211 enum pipe pipe)
1212{
1213 int reg;
1214 u32 val;
1215
1216 if (pipe > 1)
1217 return;
1218
1219 /* PCH only available on ILK+ */
1220 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1221
1222 /* PCH refclock must be enabled first */
1223 assert_pch_refclk_enabled(dev_priv);
1224
1225 reg = PCH_DPLL(pipe);
1226 val = I915_READ(reg);
1227 val |= DPLL_VCO_ENABLE;
1228 I915_WRITE(reg, val);
1229 POSTING_READ(reg);
1230 DELAY(200);
1231}
1232
1233static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1234 enum pipe pipe)
1235{
1236 int reg;
1237 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1238 pll_sel = TRANSC_DPLL_ENABLE;
1239
1240 if (pipe > 1)
1241 return;
1242
1243 /* PCH only available on ILK+ */
1244 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1245
1246 /* Make sure transcoder isn't still depending on us */
1247 assert_transcoder_disabled(dev_priv, pipe);
1248
1249 if (pipe == 0)
1250 pll_sel |= TRANSC_DPLLA_SEL;
1251 else if (pipe == 1)
1252 pll_sel |= TRANSC_DPLLB_SEL;
1253
1254
1255 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1256 return;
1257
1258 reg = PCH_DPLL(pipe);
1259 val = I915_READ(reg);
1260 val &= ~DPLL_VCO_ENABLE;
1261 I915_WRITE(reg, val);
1262 POSTING_READ(reg);
1263 DELAY(200);
1264}
1265
1266static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1267 enum pipe pipe)
1268{
1269 int reg;
1270 u32 val, pipeconf_val;
1271 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1272
1273 /* PCH only available on ILK+ */
1274 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1275
1276 /* Make sure PCH DPLL is enabled */
1277 assert_pch_pll_enabled(dev_priv, pipe);
1278
1279 /* FDI must be feeding us bits for PCH ports */
1280 assert_fdi_tx_enabled(dev_priv, pipe);
1281 assert_fdi_rx_enabled(dev_priv, pipe);
1282
1283
1284 reg = TRANSCONF(pipe);
1285 val = I915_READ(reg);
1286 pipeconf_val = I915_READ(PIPECONF(pipe));
1287
1288 if (HAS_PCH_IBX(dev_priv->dev)) {
1289 /*
1290 * make the BPC in transcoder be consistent with
1291 * that in pipeconf reg.
1292 */
1293 val &= ~PIPE_BPC_MASK;
1294 val |= pipeconf_val & PIPE_BPC_MASK;
1295 }
1296
1297 val &= ~TRANS_INTERLACE_MASK;
1298 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1299 if (HAS_PCH_IBX(dev_priv->dev) &&
1300 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1301 val |= TRANS_LEGACY_INTERLACED_ILK;
1302 else
1303 val |= TRANS_INTERLACED;
1304 else
1305 val |= TRANS_PROGRESSIVE;
1306
1307 I915_WRITE(reg, val | TRANS_ENABLE);
1308 if (_intel_wait_for(dev_priv->dev, I915_READ(reg) & TRANS_STATE_ENABLE,
1309 100, 1, "915trc"))
1310 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1311}
1312
1313static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1314 enum pipe pipe)
1315{
1316 int reg;
1317 u32 val;
1318
1319 /* FDI relies on the transcoder */
1320 assert_fdi_tx_disabled(dev_priv, pipe);
1321 assert_fdi_rx_disabled(dev_priv, pipe);
1322
1323 /* Ports must be off as well */
1324 assert_pch_ports_disabled(dev_priv, pipe);
1325
1326 reg = TRANSCONF(pipe);
1327 val = I915_READ(reg);
1328 val &= ~TRANS_ENABLE;
1329 I915_WRITE(reg, val);
1330 /* wait for PCH transcoder off, transcoder state */
1331 if (_intel_wait_for(dev_priv->dev,
1332 (I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50,
1333 1, "915trd"))
1334 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1335}
1336
1337/**
1338 * intel_enable_pipe - enable a pipe, asserting requirements
1339 * @dev_priv: i915 private structure
1340 * @pipe: pipe to enable
1341 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1342 *
1343 * Enable @pipe, making sure that various hardware specific requirements
1344 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1345 *
1346 * @pipe should be %PIPE_A or %PIPE_B.
1347 *
1348 * Will wait until the pipe is actually running (i.e. first vblank) before
1349 * returning.
1350 */
1351static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1352 bool pch_port)
1353{
1354 int reg;
1355 u32 val;
1356
1357 /*
1358 * A pipe without a PLL won't actually be able to drive bits from
1359 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1360 * need the check.
1361 */
1362 if (!HAS_PCH_SPLIT(dev_priv->dev))
1363 assert_pll_enabled(dev_priv, pipe);
1364 else {
1365 if (pch_port) {
1366 /* if driving the PCH, we need FDI enabled */
1367 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1368 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1369 }
1370 /* FIXME: assert CPU port conditions for SNB+ */
1371 }
1372
1373 reg = PIPECONF(pipe);
1374 val = I915_READ(reg);
1375 if (val & PIPECONF_ENABLE)
1376 return;
1377
1378 I915_WRITE(reg, val | PIPECONF_ENABLE);
1379 intel_wait_for_vblank(dev_priv->dev, pipe);
1380}
1381
1382/**
1383 * intel_disable_pipe - disable a pipe, asserting requirements
1384 * @dev_priv: i915 private structure
1385 * @pipe: pipe to disable
1386 *
1387 * Disable @pipe, making sure that various hardware specific requirements
1388 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1389 *
1390 * @pipe should be %PIPE_A or %PIPE_B.
1391 *
1392 * Will wait until the pipe has shut down before returning.
1393 */
1394static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1395 enum pipe pipe)
1396{
1397 int reg;
1398 u32 val;
1399
1400 /*
1401 * Make sure planes won't keep trying to pump pixels to us,
1402 * or we might hang the display.
1403 */
1404 assert_planes_disabled(dev_priv, pipe);
1405
1406 /* Don't disable pipe A or pipe A PLLs if needed */
1407 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1408 return;
1409
1410 reg = PIPECONF(pipe);
1411 val = I915_READ(reg);
1412 if ((val & PIPECONF_ENABLE) == 0)
1413 return;
1414
1415 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1416 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1417}
1418
1419/*
1420 * Plane regs are double buffered, going from enabled->disabled needs a
1421 * trigger in order to latch. The display address reg provides this.
1422 */
1423static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1424 enum plane plane)
1425{
1426 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1427 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1428}
1429
1430/**
1431 * intel_enable_plane - enable a display plane on a given pipe
1432 * @dev_priv: i915 private structure
1433 * @plane: plane to enable
1434 * @pipe: pipe being fed
1435 *
1436 * Enable @plane on @pipe, making sure that @pipe is running first.
1437 */
1438static void intel_enable_plane(struct drm_i915_private *dev_priv,
1439 enum plane plane, enum pipe pipe)
1440{
1441 int reg;
1442 u32 val;
1443
1444 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1445 assert_pipe_enabled(dev_priv, pipe);
1446
1447 reg = DSPCNTR(plane);
1448 val = I915_READ(reg);
1449 if (val & DISPLAY_PLANE_ENABLE)
1450 return;
1451
1452 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1453 intel_flush_display_plane(dev_priv, plane);
1454 intel_wait_for_vblank(dev_priv->dev, pipe);
1455}
1456
1457/**
1458 * intel_disable_plane - disable a display plane
1459 * @dev_priv: i915 private structure
1460 * @plane: plane to disable
1461 * @pipe: pipe consuming the data
1462 *
1463 * Disable @plane; should be an independent operation.
1464 */
1465static void intel_disable_plane(struct drm_i915_private *dev_priv,
1466 enum plane plane, enum pipe pipe)
1467{
1468 int reg;
1469 u32 val;
1470
1471 reg = DSPCNTR(plane);
1472 val = I915_READ(reg);
1473 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1474 return;
1475
1476 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1477 intel_flush_display_plane(dev_priv, plane);
1478 intel_wait_for_vblank(dev_priv->dev, pipe);
1479}
1480
1481static void disable_pch_dp(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, int reg, u32 port_sel)
1483{
1484 u32 val = I915_READ(reg);
1485 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1486 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1487 I915_WRITE(reg, val & ~DP_PORT_EN);
1488 }
1489}
1490
1491static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1492 enum pipe pipe, int reg)
1493{
1494 u32 val = I915_READ(reg);
1495 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1496 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1497 reg, pipe);
1498 I915_WRITE(reg, val & ~PORT_ENABLE);
1499 }
1500}
1501
1502/* Disable any ports connected to this transcoder */
1503static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1504 enum pipe pipe)
1505{
1506 u32 reg, val;
1507
1508 val = I915_READ(PCH_PP_CONTROL);
1509 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1510
1511 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1512 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1513 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1514
1515 reg = PCH_ADPA;
1516 val = I915_READ(reg);
1517 if (adpa_pipe_enabled(dev_priv, val, pipe))
1518 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1519
1520 reg = PCH_LVDS;
1521 val = I915_READ(reg);
1522 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1523 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1524 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1525 POSTING_READ(reg);
1526 DELAY(100);
1527 }
1528
1529 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1530 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1531 disable_pch_hdmi(dev_priv, pipe, HDMID);
1532}
1533
1534static void i8xx_disable_fbc(struct drm_device *dev)
1535{
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 u32 fbc_ctl;
1538
1539 /* Disable compression */
1540 fbc_ctl = I915_READ(FBC_CONTROL);
1541 if ((fbc_ctl & FBC_CTL_EN) == 0)
1542 return;
1543
1544 fbc_ctl &= ~FBC_CTL_EN;
1545 I915_WRITE(FBC_CONTROL, fbc_ctl);
1546
1547 /* Wait for compressing bit to clear */
1548 if (_intel_wait_for(dev,
1549 (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10,
1550 1, "915fbd")) {
1551 DRM_DEBUG_KMS("FBC idle timed out\n");
1552 return;
1553 }
1554
1555 DRM_DEBUG_KMS("disabled FBC\n");
1556}
1557
1558static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1559{
1560 struct drm_device *dev = crtc->dev;
1561 struct drm_i915_private *dev_priv = dev->dev_private;
1562 struct drm_framebuffer *fb = crtc->fb;
1563 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1564 struct drm_i915_gem_object *obj = intel_fb->obj;
1565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1566 int cfb_pitch;
1567 int plane, i;
1568 u32 fbc_ctl, fbc_ctl2;
1569
1570 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1571 if (fb->pitches[0] < cfb_pitch)
1572 cfb_pitch = fb->pitches[0];
1573
1574 /* FBC_CTL wants 64B units */
1575 cfb_pitch = (cfb_pitch / 64) - 1;
1576 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1577
1578 /* Clear old tags */
1579 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1580 I915_WRITE(FBC_TAG + (i * 4), 0);
1581
1582 /* Set it up... */
1583 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1584 fbc_ctl2 |= plane;
1585 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1586 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1587
1588 /* enable it... */
1589 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1590 if (IS_I945GM(dev))
1591 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1592 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1593 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1594 fbc_ctl |= obj->fence_reg;
1595 I915_WRITE(FBC_CONTROL, fbc_ctl);
1596
1597 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1598 cfb_pitch, crtc->y, intel_crtc->plane);
1599}
1600
1601static bool i8xx_fbc_enabled(struct drm_device *dev)
1602{
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604
1605 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1606}
1607
1608static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1609{
1610 struct drm_device *dev = crtc->dev;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 struct drm_framebuffer *fb = crtc->fb;
1613 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1614 struct drm_i915_gem_object *obj = intel_fb->obj;
1615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1616 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1617 unsigned long stall_watermark = 200;
1618 u32 dpfc_ctl;
1619
1620 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1621 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1622 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1623
1624 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1625 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1626 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1627 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1628
1629 /* enable it... */
1630 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1631
1632 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1633}
1634
1635static void g4x_disable_fbc(struct drm_device *dev)
1636{
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 u32 dpfc_ctl;
1639
1640 /* Disable compression */
1641 dpfc_ctl = I915_READ(DPFC_CONTROL);
1642 if (dpfc_ctl & DPFC_CTL_EN) {
1643 dpfc_ctl &= ~DPFC_CTL_EN;
1644 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1645
1646 DRM_DEBUG_KMS("disabled FBC\n");
1647 }
1648}
1649
1650static bool g4x_fbc_enabled(struct drm_device *dev)
1651{
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653
1654 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1655}
1656
1657static void sandybridge_blit_fbc_update(struct drm_device *dev)
1658{
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660 u32 blt_ecoskpd;
1661
1662 /* Make sure blitter notifies FBC of writes */
1663 gen6_gt_force_wake_get(dev_priv);
1664 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1665 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1666 GEN6_BLITTER_LOCK_SHIFT;
1667 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1668 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1669 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1670 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1671 GEN6_BLITTER_LOCK_SHIFT);
1672 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1673 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1674 gen6_gt_force_wake_put(dev_priv);
1675}
1676
1677static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1678{
1679 struct drm_device *dev = crtc->dev;
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 struct drm_framebuffer *fb = crtc->fb;
1682 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1683 struct drm_i915_gem_object *obj = intel_fb->obj;
1684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1685 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1686 unsigned long stall_watermark = 200;
1687 u32 dpfc_ctl;
1688
1689 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1690 dpfc_ctl &= DPFC_RESERVED;
1691 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1692 /* Set persistent mode for front-buffer rendering, ala X. */
1693 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1694 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1695 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1696
1697 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1698 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1699 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1700 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1701 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1702 /* enable it... */
1703 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1704
1705 if (IS_GEN6(dev)) {
1706 I915_WRITE(SNB_DPFC_CTL_SA,
1707 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1708 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1709 sandybridge_blit_fbc_update(dev);
1710 }
1711
1712 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1713}
1714
1715static void ironlake_disable_fbc(struct drm_device *dev)
1716{
1717 struct drm_i915_private *dev_priv = dev->dev_private;
1718 u32 dpfc_ctl;
1719
1720 /* Disable compression */
1721 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1722 if (dpfc_ctl & DPFC_CTL_EN) {
1723 dpfc_ctl &= ~DPFC_CTL_EN;
1724 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1725
1726 DRM_DEBUG_KMS("disabled FBC\n");
1727 }
1728}
1729
1730static bool ironlake_fbc_enabled(struct drm_device *dev)
1731{
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733
1734 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1735}
1736
1737bool intel_fbc_enabled(struct drm_device *dev)
1738{
1739 struct drm_i915_private *dev_priv = dev->dev_private;
1740
1741 if (!dev_priv->display.fbc_enabled)
1742 return false;
1743
1744 return dev_priv->display.fbc_enabled(dev);
1745}
1746
1747static void intel_fbc_work_fn(void *arg, int pending)
1748{
1749 struct intel_fbc_work *work = arg;
1750 struct drm_device *dev = work->crtc->dev;
1751 struct drm_i915_private *dev_priv = dev->dev_private;
1752
1753 DRM_LOCK(dev);
1754 if (work == dev_priv->fbc_work) {
1755 /* Double check that we haven't switched fb without cancelling
1756 * the prior work.
1757 */
1758 if (work->crtc->fb == work->fb) {
1759 dev_priv->display.enable_fbc(work->crtc,
1760 work->interval);
1761
1762 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1763 dev_priv->cfb_fb = work->crtc->fb->base.id;
1764 dev_priv->cfb_y = work->crtc->y;
1765 }
1766
1767 dev_priv->fbc_work = NULL;
1768 }
1769 DRM_UNLOCK(dev);
1770
1771 free(work, DRM_MEM_KMS);
1772}
1773
1774static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1775{
1776 u_int pending;
1777
1778 if (dev_priv->fbc_work == NULL)
1779 return;
1780
1781 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1782
1783 /* Synchronisation is provided by struct_mutex and checking of
1784 * dev_priv->fbc_work, so we can perform the cancellation
1785 * entirely asynchronously.
1786 */
1787 if (taskqueue_cancel_timeout(dev_priv->tq, &dev_priv->fbc_work->task,
1788 &pending) == 0)
1789 /* tasklet was killed before being run, clean up */
1790 free(dev_priv->fbc_work, DRM_MEM_KMS);
1791
1792 /* Mark the work as no longer wanted so that if it does
1793 * wake-up (because the work was already running and waiting
1794 * for our mutex), it will discover that is no longer
1795 * necessary to run.
1796 */
1797 dev_priv->fbc_work = NULL;
1798}
1799
1800static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1801{
1802 struct intel_fbc_work *work;
1803 struct drm_device *dev = crtc->dev;
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805
1806 if (!dev_priv->display.enable_fbc)
1807 return;
1808
1809 intel_cancel_fbc_work(dev_priv);
1810
1811 work = malloc(sizeof(*work), DRM_MEM_KMS, M_WAITOK | M_ZERO);
1812 work->crtc = crtc;
1813 work->fb = crtc->fb;
1814 work->interval = interval;
1815 TIMEOUT_TASK_INIT(dev_priv->tq, &work->task, 0, intel_fbc_work_fn,
1816 work);
1817
1818 dev_priv->fbc_work = work;
1819
1820 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1821
1822 /* Delay the actual enabling to let pageflipping cease and the
1823 * display to settle before starting the compression. Note that
1824 * this delay also serves a second purpose: it allows for a
1825 * vblank to pass after disabling the FBC before we attempt
1826 * to modify the control registers.
1827 *
1828 * A more complicated solution would involve tracking vblanks
1829 * following the termination of the page-flipping sequence
1830 * and indeed performing the enable as a co-routine and not
1831 * waiting synchronously upon the vblank.
1832 */
1833 taskqueue_enqueue_timeout(dev_priv->tq, &work->task,
1834 msecs_to_jiffies(50));
1835}
1836
1837void intel_disable_fbc(struct drm_device *dev)
1838{
1839 struct drm_i915_private *dev_priv = dev->dev_private;
1840
1841 intel_cancel_fbc_work(dev_priv);
1842
1843 if (!dev_priv->display.disable_fbc)
1844 return;
1845
1846 dev_priv->display.disable_fbc(dev);
1847 dev_priv->cfb_plane = -1;
1848}
1849
1850/**
1851 * intel_update_fbc - enable/disable FBC as needed
1852 * @dev: the drm_device
1853 *
1854 * Set up the framebuffer compression hardware at mode set time. We
1855 * enable it if possible:
1856 * - plane A only (on pre-965)
1857 * - no pixel mulitply/line duplication
1858 * - no alpha buffer discard
1859 * - no dual wide
1860 * - framebuffer <= 2048 in width, 1536 in height
1861 *
1862 * We can't assume that any compression will take place (worst case),
1863 * so the compressed buffer has to be the same size as the uncompressed
1864 * one. It also must reside (along with the line length buffer) in
1865 * stolen memory.
1866 *
1867 * We need to enable/disable FBC on a global basis.
1868 */
1869static void intel_update_fbc(struct drm_device *dev)
1870{
1871 struct drm_i915_private *dev_priv = dev->dev_private;
1872 struct drm_crtc *crtc = NULL, *tmp_crtc;
1873 struct intel_crtc *intel_crtc;
1874 struct drm_framebuffer *fb;
1875 struct intel_framebuffer *intel_fb;
1876 struct drm_i915_gem_object *obj;
1877 int enable_fbc;
1878
1879 DRM_DEBUG_KMS("\n");
1880
1881 if (!i915_powersave)
1882 return;
1883
1884 if (!I915_HAS_FBC(dev))
1885 return;
1886
1887 /*
1888 * If FBC is already on, we just have to verify that we can
1889 * keep it that way...
1890 * Need to disable if:
1891 * - more than one pipe is active
1892 * - changing FBC params (stride, fence, mode)
1893 * - new fb is too large to fit in compressed buffer
1894 * - going to an unsupported config (interlace, pixel multiply, etc.)
1895 */
1896 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1897 if (tmp_crtc->enabled && tmp_crtc->fb) {
1898 if (crtc) {
1899 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1900 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1901 goto out_disable;
1902 }
1903 crtc = tmp_crtc;
1904 }
1905 }
1906
1907 if (!crtc || crtc->fb == NULL) {
1908 DRM_DEBUG_KMS("no output, disabling\n");
1909 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1910 goto out_disable;
1911 }
1912
1913 intel_crtc = to_intel_crtc(crtc);
1914 fb = crtc->fb;
1915 intel_fb = to_intel_framebuffer(fb);
1916 obj = intel_fb->obj;
1917
1918 enable_fbc = i915_enable_fbc;
1919 if (enable_fbc < 0) {
1920 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1921 enable_fbc = 1;
1922 if (INTEL_INFO(dev)->gen <= 6)
1923 enable_fbc = 0;
1924 }
1925 if (!enable_fbc) {
1926 DRM_DEBUG_KMS("fbc disabled per module param\n");
1927 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1928 goto out_disable;
1929 }
1930 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1931 DRM_DEBUG_KMS("framebuffer too large, disabling "
1932 "compression\n");
1933 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1934 goto out_disable;
1935 }
1936 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1937 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1938 DRM_DEBUG_KMS("mode incompatible with compression, "
1939 "disabling\n");
1940 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1941 goto out_disable;
1942 }
1943 if ((crtc->mode.hdisplay > 2048) ||
1944 (crtc->mode.vdisplay > 1536)) {
1945 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1946 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1947 goto out_disable;
1948 }
1949 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1950 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1951 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1952 goto out_disable;
1953 }
1954 if (obj->tiling_mode != I915_TILING_X ||
1955 obj->fence_reg == I915_FENCE_REG_NONE) {
1956 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1957 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1958 goto out_disable;
1959 }
1960
1961 /* If the kernel debugger is active, always disable compression */
1962 if (kdb_active)
1963 goto out_disable;
1964
1965 /* If the scanout has not changed, don't modify the FBC settings.
1966 * Note that we make the fundamental assumption that the fb->obj
1967 * cannot be unpinned (and have its GTT offset and fence revoked)
1968 * without first being decoupled from the scanout and FBC disabled.
1969 */
1970 if (dev_priv->cfb_plane == intel_crtc->plane &&
1971 dev_priv->cfb_fb == fb->base.id &&
1972 dev_priv->cfb_y == crtc->y)
1973 return;
1974
1975 if (intel_fbc_enabled(dev)) {
1976 /* We update FBC along two paths, after changing fb/crtc
1977 * configuration (modeswitching) and after page-flipping
1978 * finishes. For the latter, we know that not only did
1979 * we disable the FBC at the start of the page-flip
1980 * sequence, but also more than one vblank has passed.
1981 *
1982 * For the former case of modeswitching, it is possible
1983 * to switch between two FBC valid configurations
1984 * instantaneously so we do need to disable the FBC
1985 * before we can modify its control registers. We also
1986 * have to wait for the next vblank for that to take
1987 * effect. However, since we delay enabling FBC we can
1988 * assume that a vblank has passed since disabling and
1989 * that we can safely alter the registers in the deferred
1990 * callback.
1991 *
1992 * In the scenario that we go from a valid to invalid
1993 * and then back to valid FBC configuration we have
1994 * no strict enforcement that a vblank occurred since
1995 * disabling the FBC. However, along all current pipe
1996 * disabling paths we do need to wait for a vblank at
1997 * some point. And we wait before enabling FBC anyway.
1998 */
1999 DRM_DEBUG_KMS("disabling active FBC for update\n");
2000 intel_disable_fbc(dev);
2001 }
2002
2003 intel_enable_fbc(crtc, 500);
2004 return;
2005
2006out_disable:
2007 /* Multiple disables should be harmless */
2008 if (intel_fbc_enabled(dev)) {
2009 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2010 intel_disable_fbc(dev);
2011 }
2012}
2013
2014int
2015intel_pin_and_fence_fb_obj(struct drm_device *dev,
2016 struct drm_i915_gem_object *obj,
2017 struct intel_ring_buffer *pipelined)
2018{
2019 struct drm_i915_private *dev_priv = dev->dev_private;
2020 u32 alignment;
2021 int ret;
2022
2023 alignment = 0; /* shut gcc */
2024 switch (obj->tiling_mode) {
2025 case I915_TILING_NONE:
2026 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2027 alignment = 128 * 1024;
2028 else if (INTEL_INFO(dev)->gen >= 4)
2029 alignment = 4 * 1024;
2030 else
2031 alignment = 64 * 1024;
2032 break;
2033 case I915_TILING_X:
2034 /* pin() will align the object as required by fence */
2035 alignment = 0;
2036 break;
2037 case I915_TILING_Y:
2038 /* FIXME: Is this true? */
2039 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2040 return -EINVAL;
2041 default:
2042 KASSERT(0, ("Wrong tiling for fb obj"));
2043 }
2044
2045 dev_priv->mm.interruptible = false;
2046 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2047 if (ret)
2048 goto err_interruptible;
2049
2050 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2051 * fence, whereas 965+ only requires a fence if using
2052 * framebuffer compression. For simplicity, we always install
2053 * a fence as the cost is not that onerous.
2054 */
2055 if (obj->tiling_mode != I915_TILING_NONE) {
2056 ret = i915_gem_object_get_fence(obj, pipelined);
2057 if (ret)
2058 goto err_unpin;
2059
2060 i915_gem_object_pin_fence(obj);
2061 }
2062
2063 dev_priv->mm.interruptible = true;
2064 return 0;
2065
2066err_unpin:
2067 i915_gem_object_unpin(obj);
2068err_interruptible:
2069 dev_priv->mm.interruptible = true;
2070 return ret;
2071}
2072
2073void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2074{
2075 i915_gem_object_unpin_fence(obj);
2076 i915_gem_object_unpin(obj);
2077}
2078
2079static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2080 int x, int y)
2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
2088 unsigned long Start, Offset;
2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
2095 break;
2096 default:
2097 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2098 return -EINVAL;
2099 }
2100
2101 intel_fb = to_intel_framebuffer(fb);
2102 obj = intel_fb->obj;
2103
2104 reg = DSPCNTR(plane);
2105 dspcntr = I915_READ(reg);
2106 /* Mask out pixel format bits in case we change it */
2107 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2108 switch (fb->bits_per_pixel) {
2109 case 8:
2110 dspcntr |= DISPPLANE_8BPP;
2111 break;
2112 case 16:
2113 if (fb->depth == 15)
2114 dspcntr |= DISPPLANE_15_16BPP;
2115 else
2116 dspcntr |= DISPPLANE_16BPP;
2117 break;
2118 case 24:
2119 case 32:
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 break;
2122 default:
2123 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2124 return -EINVAL;
2125 }
2126 if (INTEL_INFO(dev)->gen >= 4) {
2127 if (obj->tiling_mode != I915_TILING_NONE)
2128 dspcntr |= DISPPLANE_TILED;
2129 else
2130 dspcntr &= ~DISPPLANE_TILED;
2131 }
2132
2133 I915_WRITE(reg, dspcntr);
2134
2135 Start = obj->gtt_offset;
2136 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2137
2138 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2139 Start, Offset, x, y, fb->pitches[0]);
2140 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2141 if (INTEL_INFO(dev)->gen >= 4) {
2142 I915_WRITE(DSPSURF(plane), Start);
2143 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2144 I915_WRITE(DSPADDR(plane), Offset);
2145 } else
2146 I915_WRITE(DSPADDR(plane), Start + Offset);
2147 POSTING_READ(reg);
2148
2149 return (0);
2150}
2151
2152static int ironlake_update_plane(struct drm_crtc *crtc,
2153 struct drm_framebuffer *fb, int x, int y)
2154{
2155 struct drm_device *dev = crtc->dev;
2156 struct drm_i915_private *dev_priv = dev->dev_private;
2157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2158 struct intel_framebuffer *intel_fb;
2159 struct drm_i915_gem_object *obj;
2160 int plane = intel_crtc->plane;
2161 unsigned long Start, Offset;
2162 u32 dspcntr;
2163 u32 reg;
2164
2165 switch (plane) {
2166 case 0:
2167 case 1:
2168 case 2:
2169 break;
2170 default:
2171 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2172 return -EINVAL;
2173 }
2174
2175 intel_fb = to_intel_framebuffer(fb);
2176 obj = intel_fb->obj;
2177
2178 reg = DSPCNTR(plane);
2179 dspcntr = I915_READ(reg);
2180 /* Mask out pixel format bits in case we change it */
2181 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2182 switch (fb->bits_per_pixel) {
2183 case 8:
2184 dspcntr |= DISPPLANE_8BPP;
2185 break;
2186 case 16:
2187 if (fb->depth != 16) {
2188 DRM_ERROR("bpp 16, depth %d\n", fb->depth);
2189 return -EINVAL;
2190 }
2191
2192 dspcntr |= DISPPLANE_16BPP;
2193 break;
2194 case 24:
2195 case 32:
2196 if (fb->depth == 24)
2197 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2198 else if (fb->depth == 30)
2199 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2200 else {
2201 DRM_ERROR("bpp %d depth %d\n", fb->bits_per_pixel,
2202 fb->depth);
2203 return -EINVAL;
2204 }
2205 break;
2206 default:
2207 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2208 return -EINVAL;
2209 }
2210
2211 if (obj->tiling_mode != I915_TILING_NONE)
2212 dspcntr |= DISPPLANE_TILED;
2213 else
2214 dspcntr &= ~DISPPLANE_TILED;
2215
2216 /* must disable */
2217 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2218
2219 I915_WRITE(reg, dspcntr);
2220
2221 Start = obj->gtt_offset;
2222 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2223
2224 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2225 Start, Offset, x, y, fb->pitches[0]);
2226 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2227 I915_WRITE(DSPSURF(plane), Start);
2228 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2229 I915_WRITE(DSPADDR(plane), Offset);
2230 POSTING_READ(reg);
2231
2232 return 0;
2233}
2234
2235/* Assume fb object is pinned & idle & fenced and just update base pointers */
2236static int
2237intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2238 int x, int y, enum mode_set_atomic state)
2239{
2240 struct drm_device *dev = crtc->dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 int ret;
2243
2244 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2245 if (ret)
2246 return ret;
2247
2248 intel_update_fbc(dev);
2249 intel_increase_pllclock(crtc);
2250
2251 return 0;
2252}
2253
2254static int
2255intel_finish_fb(struct drm_framebuffer *old_fb)
2256{
2257 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2258 struct drm_device *dev = obj->base.dev;
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 bool was_interruptible = dev_priv->mm.interruptible;
2261 int ret;
2262
2263 mtx_lock(&dev->event_lock);
2264 while (!atomic_read(&dev_priv->mm.wedged) &&
2265 atomic_read(&obj->pending_flip) != 0) {
2266 msleep(&obj->pending_flip, &dev->event_lock,
2267 0, "915flp", 0);
2268 }
2269 mtx_unlock(&dev->event_lock);
2270
2271 /* Big Hammer, we also need to ensure that any pending
2272 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2273 * current scanout is retired before unpinning the old
2274 * framebuffer.
2275 *
2276 * This should only fail upon a hung GPU, in which case we
2277 * can safely continue.
2278 */
2279 dev_priv->mm.interruptible = false;
2280 ret = i915_gem_object_finish_gpu(obj);
2281 dev_priv->mm.interruptible = was_interruptible;
2282 return ret;
2283}
2284
2285static int
2286intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2287 struct drm_framebuffer *old_fb)
2288{
2289 struct drm_device *dev = crtc->dev;
2290#if 0
2291 struct drm_i915_master_private *master_priv;
2292#else
2293 drm_i915_private_t *dev_priv = dev->dev_private;
2294#endif
2295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2296 int ret;
2297
2298 /* no fb bound */
2299 if (!crtc->fb) {
2300 DRM_ERROR("No FB bound\n");
2301 return 0;
2302 }
2303
2304 switch (intel_crtc->plane) {
2305 case 0:
2306 case 1:
2307 break;
2308 case 2:
2309 if (IS_IVYBRIDGE(dev))
2310 break;
2311 /* fall through otherwise */
2312 default:
2313 DRM_ERROR("no plane for crtc\n");
2314 return -EINVAL;
2315 }
2316
2317 DRM_LOCK(dev);
2318 ret = intel_pin_and_fence_fb_obj(dev,
2319 to_intel_framebuffer(crtc->fb)->obj,
2320 NULL);
2321 if (ret != 0) {
2322 DRM_UNLOCK(dev);
2323 DRM_ERROR("pin & fence failed\n");
2324 return ret;
2325 }
2326
2327 if (old_fb)
2328 intel_finish_fb(old_fb);
2329
2330 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2331 LEAVE_ATOMIC_MODE_SET);
2332 if (ret) {
2333 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2334 DRM_UNLOCK(dev);
2335 DRM_ERROR("failed to update base address\n");
2336 return ret;
2337 }
2338
2339 if (old_fb) {
2340 intel_wait_for_vblank(dev, intel_crtc->pipe);
2341 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2342 }
2343
2344 DRM_UNLOCK(dev);
2345
2346#if 0
2347 if (!dev->primary->master)
2348 return 0;
2349
2350 master_priv = dev->primary->master->driver_priv;
2351 if (!master_priv->sarea_priv)
2352 return 0;
2353
2354 if (intel_crtc->pipe) {
2355 master_priv->sarea_priv->pipeB_x = x;
2356 master_priv->sarea_priv->pipeB_y = y;
2357 } else {
2358 master_priv->sarea_priv->pipeA_x = x;
2359 master_priv->sarea_priv->pipeA_y = y;
2360 }
2361#else
2362
2363 if (!dev_priv->sarea_priv)
2364 return 0;
2365
2366 if (intel_crtc->pipe) {
2367 dev_priv->sarea_priv->planeB_x = x;
2368 dev_priv->sarea_priv->planeB_y = y;
2369 } else {
2370 dev_priv->sarea_priv->planeA_x = x;
2371 dev_priv->sarea_priv->planeA_y = y;
2372 }
2373#endif
2374
2375 return 0;
2376}
2377
2378static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2379{
2380 struct drm_device *dev = crtc->dev;
2381 struct drm_i915_private *dev_priv = dev->dev_private;
2382 u32 dpa_ctl;
2383
2384 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2385 dpa_ctl = I915_READ(DP_A);
2386 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2387
2388 if (clock < 200000) {
2389 u32 temp;
2390 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2391 /* workaround for 160Mhz:
2392 1) program 0x4600c bits 15:0 = 0x8124
2393 2) program 0x46010 bit 0 = 1
2394 3) program 0x46034 bit 24 = 1
2395 4) program 0x64000 bit 14 = 1
2396 */
2397 temp = I915_READ(0x4600c);
2398 temp &= 0xffff0000;
2399 I915_WRITE(0x4600c, temp | 0x8124);
2400
2401 temp = I915_READ(0x46010);
2402 I915_WRITE(0x46010, temp | 1);
2403
2404 temp = I915_READ(0x46034);
2405 I915_WRITE(0x46034, temp | (1 << 24));
2406 } else {
2407 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2408 }
2409 I915_WRITE(DP_A, dpa_ctl);
2410
2411 POSTING_READ(DP_A);
2412 DELAY(500);
2413}
2414
2415static void intel_fdi_normal_train(struct drm_crtc *crtc)
2416{
2417 struct drm_device *dev = crtc->dev;
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2420 int pipe = intel_crtc->pipe;
2421 u32 reg, temp;
2422
2423 /* enable normal train */
2424 reg = FDI_TX_CTL(pipe);
2425 temp = I915_READ(reg);
2426 if (IS_IVYBRIDGE(dev)) {
2427 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2428 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2429 } else {
2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2432 }
2433 I915_WRITE(reg, temp);
2434
2435 reg = FDI_RX_CTL(pipe);
2436 temp = I915_READ(reg);
2437 if (HAS_PCH_CPT(dev)) {
2438 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2439 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2440 } else {
2441 temp &= ~FDI_LINK_TRAIN_NONE;
2442 temp |= FDI_LINK_TRAIN_NONE;
2443 }
2444 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2445
2446 /* wait one idle pattern time */
2447 POSTING_READ(reg);
2448 DELAY(1000);
2449
2450 /* IVB wants error correction enabled */
2451 if (IS_IVYBRIDGE(dev))
2452 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2453 FDI_FE_ERRC_ENABLE);
2454}
2455
2456static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2457{
2458 struct drm_i915_private *dev_priv = dev->dev_private;
2459 u32 flags = I915_READ(SOUTH_CHICKEN1);
2460
2461 flags |= FDI_PHASE_SYNC_OVR(pipe);
2462 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2463 flags |= FDI_PHASE_SYNC_EN(pipe);
2464 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2465 POSTING_READ(SOUTH_CHICKEN1);
2466}
2467
2468/* The FDI link training functions for ILK/Ibexpeak. */
2469static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2470{
2471 struct drm_device *dev = crtc->dev;
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2474 int pipe = intel_crtc->pipe;
2475 int plane = intel_crtc->plane;
2476 u32 reg, temp, tries;
2477
2478 /* FDI needs bits from pipe & plane first */
2479 assert_pipe_enabled(dev_priv, pipe);
2480 assert_plane_enabled(dev_priv, plane);
2481
2482 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2483 for train result */
2484 reg = FDI_RX_IMR(pipe);
2485 temp = I915_READ(reg);
2486 temp &= ~FDI_RX_SYMBOL_LOCK;
2487 temp &= ~FDI_RX_BIT_LOCK;
2488 I915_WRITE(reg, temp);
2489 I915_READ(reg);
2490 DELAY(150);
2491
2492 /* enable CPU FDI TX and PCH FDI RX */
2493 reg = FDI_TX_CTL(pipe);
2494 temp = I915_READ(reg);
2495 temp &= ~(7 << 19);
2496 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2497 temp &= ~FDI_LINK_TRAIN_NONE;
2498 temp |= FDI_LINK_TRAIN_PATTERN_1;
2499 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2500
2501 reg = FDI_RX_CTL(pipe);
2502 temp = I915_READ(reg);
2503 temp &= ~FDI_LINK_TRAIN_NONE;
2504 temp |= FDI_LINK_TRAIN_PATTERN_1;
2505 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2506
2507 POSTING_READ(reg);
2508 DELAY(150);
2509
2510 /* Ironlake workaround, enable clock pointer after FDI enable*/
2511 if (HAS_PCH_IBX(dev)) {
2512 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2513 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2514 FDI_RX_PHASE_SYNC_POINTER_EN);
2515 }
2516
2517 reg = FDI_RX_IIR(pipe);
2518 for (tries = 0; tries < 5; tries++) {
2519 temp = I915_READ(reg);
2520 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521
2522 if ((temp & FDI_RX_BIT_LOCK)) {
2523 DRM_DEBUG_KMS("FDI train 1 done.\n");
2524 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2525 break;
2526 }
2527 }
2528 if (tries == 5)
2529 DRM_ERROR("FDI train 1 fail!\n");
2530
2531 /* Train 2 */
2532 reg = FDI_TX_CTL(pipe);
2533 temp = I915_READ(reg);
2534 temp &= ~FDI_LINK_TRAIN_NONE;
2535 temp |= FDI_LINK_TRAIN_PATTERN_2;
2536 I915_WRITE(reg, temp);
2537
2538 reg = FDI_RX_CTL(pipe);
2539 temp = I915_READ(reg);
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_2;
2542 I915_WRITE(reg, temp);
2543
2544 POSTING_READ(reg);
2545 DELAY(150);
2546
2547 reg = FDI_RX_IIR(pipe);
2548 for (tries = 0; tries < 5; tries++) {
2549 temp = I915_READ(reg);
2550 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2551
2552 if (temp & FDI_RX_SYMBOL_LOCK) {
2553 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2554 DRM_DEBUG_KMS("FDI train 2 done.\n");
2555 break;
2556 }
2557 }
2558 if (tries == 5)
2559 DRM_ERROR("FDI train 2 fail!\n");
2560
2561 DRM_DEBUG_KMS("FDI train done\n");
2562
2563}
2564
2565static const int snb_b_fdi_train_param[] = {
2566 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2567 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2568 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2569 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2570};
2571
2572/* The FDI link training functions for SNB/Cougarpoint. */
2573static void gen6_fdi_link_train(struct drm_crtc *crtc)
2574{
2575 struct drm_device *dev = crtc->dev;
2576 struct drm_i915_private *dev_priv = dev->dev_private;
2577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2578 int pipe = intel_crtc->pipe;
2579 u32 reg, temp, i;
2580
2581 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2582 for train result */
2583 reg = FDI_RX_IMR(pipe);
2584 temp = I915_READ(reg);
2585 temp &= ~FDI_RX_SYMBOL_LOCK;
2586 temp &= ~FDI_RX_BIT_LOCK;
2587 I915_WRITE(reg, temp);
2588
2589 POSTING_READ(reg);
2590 DELAY(150);
2591
2592 /* enable CPU FDI TX and PCH FDI RX */
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~(7 << 19);
2596 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2597 temp &= ~FDI_LINK_TRAIN_NONE;
2598 temp |= FDI_LINK_TRAIN_PATTERN_1;
2599 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2600 /* SNB-B */
2601 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2602 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2603
2604 reg = FDI_RX_CTL(pipe);
2605 temp = I915_READ(reg);
2606 if (HAS_PCH_CPT(dev)) {
2607 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2608 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2609 } else {
2610 temp &= ~FDI_LINK_TRAIN_NONE;
2611 temp |= FDI_LINK_TRAIN_PATTERN_1;
2612 }
2613 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2614
2615 POSTING_READ(reg);
2616 DELAY(150);
2617
2618 if (HAS_PCH_CPT(dev))
2619 cpt_phase_pointer_enable(dev, pipe);
2620
2621 for (i = 0; i < 4; i++) {
2622 reg = FDI_TX_CTL(pipe);
2623 temp = I915_READ(reg);
2624 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2625 temp |= snb_b_fdi_train_param[i];
2626 I915_WRITE(reg, temp);
2627
2628 POSTING_READ(reg);
2629 DELAY(500);
2630
2631 reg = FDI_RX_IIR(pipe);
2632 temp = I915_READ(reg);
2633 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2634
2635 if (temp & FDI_RX_BIT_LOCK) {
2636 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2637 DRM_DEBUG_KMS("FDI train 1 done.\n");
2638 break;
2639 }
2640 }
2641 if (i == 4)
2642 DRM_ERROR("FDI train 1 fail!\n");
2643
2644 /* Train 2 */
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_NONE;
2648 temp |= FDI_LINK_TRAIN_PATTERN_2;
2649 if (IS_GEN6(dev)) {
2650 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2651 /* SNB-B */
2652 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2653 }
2654 I915_WRITE(reg, temp);
2655
2656 reg = FDI_RX_CTL(pipe);
2657 temp = I915_READ(reg);
2658 if (HAS_PCH_CPT(dev)) {
2659 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2660 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2661 } else {
2662 temp &= ~FDI_LINK_TRAIN_NONE;
2663 temp |= FDI_LINK_TRAIN_PATTERN_2;
2664 }
2665 I915_WRITE(reg, temp);
2666
2667 POSTING_READ(reg);
2668 DELAY(150);
2669
2670 for (i = 0; i < 4; i++) {
2671 reg = FDI_TX_CTL(pipe);
2672 temp = I915_READ(reg);
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= snb_b_fdi_train_param[i];
2675 I915_WRITE(reg, temp);
2676
2677 POSTING_READ(reg);
2678 DELAY(500);
2679
2680 reg = FDI_RX_IIR(pipe);
2681 temp = I915_READ(reg);
2682 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2683
2684 if (temp & FDI_RX_SYMBOL_LOCK) {
2685 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2686 DRM_DEBUG_KMS("FDI train 2 done.\n");
2687 break;
2688 }
2689 }
2690 if (i == 4)
2691 DRM_ERROR("FDI train 2 fail!\n");
2692
2693 DRM_DEBUG_KMS("FDI train done.\n");
2694}
2695
2696/* Manual link training for Ivy Bridge A0 parts */
2697static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2698{
2699 struct drm_device *dev = crtc->dev;
2700 struct drm_i915_private *dev_priv = dev->dev_private;
2701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2702 int pipe = intel_crtc->pipe;
2703 u32 reg, temp, i;
2704
2705 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2706 for train result */
2707 reg = FDI_RX_IMR(pipe);
2708 temp = I915_READ(reg);
2709 temp &= ~FDI_RX_SYMBOL_LOCK;
2710 temp &= ~FDI_RX_BIT_LOCK;
2711 I915_WRITE(reg, temp);
2712
2713 POSTING_READ(reg);
2714 DELAY(150);
2715
2716 /* enable CPU FDI TX and PCH FDI RX */
2717 reg = FDI_TX_CTL(pipe);
2718 temp = I915_READ(reg);
2719 temp &= ~(7 << 19);
2720 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2721 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2722 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2725 temp |= FDI_COMPOSITE_SYNC;
2726 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2727
2728 reg = FDI_RX_CTL(pipe);
2729 temp = I915_READ(reg);
2730 temp &= ~FDI_LINK_TRAIN_AUTO;
2731 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2732 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2733 temp |= FDI_COMPOSITE_SYNC;
2734 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2735
2736 POSTING_READ(reg);
2737 DELAY(150);
2738
2739 for (i = 0; i < 4; i++) {
2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743 temp |= snb_b_fdi_train_param[i];
2744 I915_WRITE(reg, temp);
2745
2746 POSTING_READ(reg);
2747 DELAY(500);
2748
2749 reg = FDI_RX_IIR(pipe);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753 if (temp & FDI_RX_BIT_LOCK ||
2754 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2755 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2756 DRM_DEBUG_KMS("FDI train 1 done.\n");
2757 break;
2758 }
2759 }
2760 if (i == 4)
2761 DRM_ERROR("FDI train 1 fail!\n");
2762
2763 /* Train 2 */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2767 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2768 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2769 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2770 I915_WRITE(reg, temp);
2771
2772 reg = FDI_RX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2775 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2776 I915_WRITE(reg, temp);
2777
2778 POSTING_READ(reg);
2779 DELAY(150);
2780
2781 for (i = 0; i < 4; i++ ) {
2782 reg = FDI_TX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2785 temp |= snb_b_fdi_train_param[i];
2786 I915_WRITE(reg, temp);
2787
2788 POSTING_READ(reg);
2789 DELAY(500);
2790
2791 reg = FDI_RX_IIR(pipe);
2792 temp = I915_READ(reg);
2793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2794
2795 if (temp & FDI_RX_SYMBOL_LOCK) {
2796 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2797 DRM_DEBUG_KMS("FDI train 2 done.\n");
2798 break;
2799 }
2800 }
2801 if (i == 4)
2802 DRM_ERROR("FDI train 2 fail!\n");
2803
2804 DRM_DEBUG_KMS("FDI train done.\n");
2805}
2806
2807static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2808{
2809 struct drm_device *dev = crtc->dev;
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2812 int pipe = intel_crtc->pipe;
2813 u32 reg, temp;
2814
2815 /* Write the TU size bits so error detection works */
2816 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2817 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2818
2819 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2820 reg = FDI_RX_CTL(pipe);
2821 temp = I915_READ(reg);
2822 temp &= ~((0x7 << 19) | (0x7 << 16));
2823 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2824 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2825 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2826
2827 POSTING_READ(reg);
2828 DELAY(200);
2829
2830 /* Switch from Rawclk to PCDclk */
2831 temp = I915_READ(reg);
2832 I915_WRITE(reg, temp | FDI_PCDCLK);
2833
2834 POSTING_READ(reg);
2835 DELAY(200);
2836
2837 /* Enable CPU FDI TX PLL, always on for Ironlake */
2838 reg = FDI_TX_CTL(pipe);
2839 temp = I915_READ(reg);
2840 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2841 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2842
2843 POSTING_READ(reg);
2844 DELAY(100);
2845 }
2846}
2847
2848static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2849{
2850 struct drm_i915_private *dev_priv = dev->dev_private;
2851 u32 flags = I915_READ(SOUTH_CHICKEN1);
2852
2853 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2854 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2855 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2856 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2857 POSTING_READ(SOUTH_CHICKEN1);
2858}
2859
2860static void ironlake_fdi_disable(struct drm_crtc *crtc)
2861{
2862 struct drm_device *dev = crtc->dev;
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2865 int pipe = intel_crtc->pipe;
2866 u32 reg, temp;
2867
2868 /* disable CPU FDI tx and PCH FDI rx */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2872 POSTING_READ(reg);
2873
2874 reg = FDI_RX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 temp &= ~(0x7 << 16);
2877 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2878 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2879
2880 POSTING_READ(reg);
2881 DELAY(100);
2882
2883 /* Ironlake workaround, disable clock pointer after downing FDI */
2884 if (HAS_PCH_IBX(dev)) {
2885 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2886 I915_WRITE(FDI_RX_CHICKEN(pipe),
2887 I915_READ(FDI_RX_CHICKEN(pipe) &
2888 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2889 } else if (HAS_PCH_CPT(dev)) {
2890 cpt_phase_pointer_disable(dev, pipe);
2891 }
2892
2893 /* still set train pattern 1 */
2894 reg = FDI_TX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 temp &= ~FDI_LINK_TRAIN_NONE;
2897 temp |= FDI_LINK_TRAIN_PATTERN_1;
2898 I915_WRITE(reg, temp);
2899
2900 reg = FDI_RX_CTL(pipe);
2901 temp = I915_READ(reg);
2902 if (HAS_PCH_CPT(dev)) {
2903 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2904 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2905 } else {
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908 }
2909 /* BPC in FDI rx is consistent with that in PIPECONF */
2910 temp &= ~(0x07 << 16);
2911 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2912 I915_WRITE(reg, temp);
2913
2914 POSTING_READ(reg);
2915 DELAY(100);
2916}
2917
2918/*
2919 * When we disable a pipe, we need to clear any pending scanline wait events
2920 * to avoid hanging the ring, which we assume we are waiting on.
2921 */
2922static void intel_clear_scanline_wait(struct drm_device *dev)
2923{
2924 struct drm_i915_private *dev_priv = dev->dev_private;
2925 struct intel_ring_buffer *ring;
2926 u32 tmp;
2927
2928 if (IS_GEN2(dev))
2929 /* Can't break the hang on i8xx */
2930 return;
2931
2932 ring = LP_RING(dev_priv);
2933 tmp = I915_READ_CTL(ring);
2934 if (tmp & RING_WAIT)
2935 I915_WRITE_CTL(ring, tmp);
2936}
2937
2938static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2939{
2940 struct drm_i915_gem_object *obj;
2941 struct drm_i915_private *dev_priv;
2942 struct drm_device *dev;
2943
2944 if (crtc->fb == NULL)
2945 return;
2946
2947 obj = to_intel_framebuffer(crtc->fb)->obj;
2948 dev = crtc->dev;
2949 dev_priv = dev->dev_private;
2950 mtx_lock(&dev->event_lock);
2951 while (atomic_read(&obj->pending_flip) != 0)
2952 msleep(&obj->pending_flip, &dev->event_lock, 0, "915wfl", 0);
2953 mtx_unlock(&dev->event_lock);
2954}
2955
2956static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2957{
2958 struct drm_device *dev = crtc->dev;
2959 struct drm_mode_config *mode_config = &dev->mode_config;
2960 struct intel_encoder *encoder;
2961
2962 /*
2963 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2964 * must be driven by its own crtc; no sharing is possible.
2965 */
2966 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2967 if (encoder->base.crtc != crtc)
2968 continue;
2969
2970 switch (encoder->type) {
2971 case INTEL_OUTPUT_EDP:
2972 if (!intel_encoder_is_pch_edp(&encoder->base))
2973 return false;
2974 continue;
2975 }
2976 }
2977
2978 return true;
2979}
2980
2981/*
2982 * Enable PCH resources required for PCH ports:
2983 * - PCH PLLs
2984 * - FDI training & RX/TX
2985 * - update transcoder timings
2986 * - DP transcoding bits
2987 * - transcoder
2988 */
2989static void ironlake_pch_enable(struct drm_crtc *crtc)
2990{
2991 struct drm_device *dev = crtc->dev;
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2994 int pipe = intel_crtc->pipe;
2995 u32 reg, temp, transc_sel;
2996
2997 /* For PCH output, training FDI link */
2998 dev_priv->display.fdi_link_train(crtc);
2999
3000 intel_enable_pch_pll(dev_priv, pipe);
3001
3002 if (HAS_PCH_CPT(dev)) {
3003 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
3004 TRANSC_DPLLB_SEL;
3005
3006 /* Be sure PCH DPLL SEL is set */
3007 temp = I915_READ(PCH_DPLL_SEL);
3008 if (pipe == 0) {
3009 temp &= ~(TRANSA_DPLLB_SEL);
3010 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3011 } else if (pipe == 1) {
3012 temp &= ~(TRANSB_DPLLB_SEL);
3013 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3014 } else if (pipe == 2) {
3015 temp &= ~(TRANSC_DPLLB_SEL);
3016 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
3017 }
3018 I915_WRITE(PCH_DPLL_SEL, temp);
3019 }
3020
3021 /* set transcoder timing, panel must allow it */
3022 assert_panel_unlocked(dev_priv, pipe);
3023 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3024 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3025 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3026
3027 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3028 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3029 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3030 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3031
3032 intel_fdi_normal_train(crtc);
3033
3034 /* For PCH DP, enable TRANS_DP_CTL */
3035 if (HAS_PCH_CPT(dev) &&
3036 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3037 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3038 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3039 reg = TRANS_DP_CTL(pipe);
3040 temp = I915_READ(reg);
3041 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3042 TRANS_DP_SYNC_MASK |
3043 TRANS_DP_BPC_MASK);
3044 temp |= (TRANS_DP_OUTPUT_ENABLE |
3045 TRANS_DP_ENH_FRAMING);
3046 temp |= bpc << 9; /* same format but at 11:9 */
3047
3048 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3049 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3050 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3051 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3052
3053 switch (intel_trans_dp_port_sel(crtc)) {
3054 case PCH_DP_B:
3055 temp |= TRANS_DP_PORT_SEL_B;
3056 break;
3057 case PCH_DP_C:
3058 temp |= TRANS_DP_PORT_SEL_C;
3059 break;
3060 case PCH_DP_D:
3061 temp |= TRANS_DP_PORT_SEL_D;
3062 break;
3063 default:
3064 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3065 temp |= TRANS_DP_PORT_SEL_B;
3066 break;
3067 }
3068
3069 I915_WRITE(reg, temp);
3070 }
3071
3072 intel_enable_transcoder(dev_priv, pipe);
3073}
3074
3075void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3076{
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3079 u32 temp;
3080
3081 temp = I915_READ(dslreg);
3082 DELAY(500);
3083 if (_intel_wait_for(dev, I915_READ(dslreg) != temp, 5, 1, "915cp1")) {
3084 /* Without this, mode sets may fail silently on FDI */
3085 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3086 DELAY(250);
3087 I915_WRITE(tc2reg, 0);
3088 if (_intel_wait_for(dev, I915_READ(dslreg) != temp, 5, 1,
3089 "915cp2"))
3090 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3091 }
3092}
3093
3094static void ironlake_crtc_enable(struct drm_crtc *crtc)
3095{
3096 struct drm_device *dev = crtc->dev;
3097 struct drm_i915_private *dev_priv = dev->dev_private;
3098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3099 int pipe = intel_crtc->pipe;
3100 int plane = intel_crtc->plane;
3101 u32 temp;
3102 bool is_pch_port;
3103
3104 if (intel_crtc->active)
3105 return;
3106
3107 intel_crtc->active = true;
3108 intel_update_watermarks(dev);
3109
3110 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3111 temp = I915_READ(PCH_LVDS);
3112 if ((temp & LVDS_PORT_EN) == 0)
3113 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3114 }
3115
3116 is_pch_port = intel_crtc_driving_pch(crtc);
3117
3118 if (is_pch_port)
3119 ironlake_fdi_pll_enable(crtc);
3120 else
3121 ironlake_fdi_disable(crtc);
3122
3123 /* Enable panel fitting for LVDS */
3124 if (dev_priv->pch_pf_size &&
3125 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3126 /* Force use of hard-coded filter coefficients
3127 * as some pre-programmed values are broken,
3128 * e.g. x201.
3129 */
3130 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3131 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3132 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3133 }
3134
3135 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3136 intel_enable_plane(dev_priv, plane, pipe);
3137
3138 if (is_pch_port)
3139 ironlake_pch_enable(crtc);
3140
3141 intel_crtc_load_lut(crtc);
3142
3143 DRM_LOCK(dev);
3144 intel_update_fbc(dev);
3145 DRM_UNLOCK(dev);
3146
3147 intel_crtc_update_cursor(crtc, true);
3148}
3149
3150static void ironlake_crtc_disable(struct drm_crtc *crtc)
3151{
3152 struct drm_device *dev = crtc->dev;
3153 struct drm_i915_private *dev_priv = dev->dev_private;
3154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3155 int pipe = intel_crtc->pipe;
3156 int plane = intel_crtc->plane;
3157 u32 reg, temp;
3158
3159 if (!intel_crtc->active)
3160 return;
3161
3162 intel_crtc_wait_for_pending_flips(crtc);
3163 drm_vblank_off(dev, pipe);
3164 intel_crtc_update_cursor(crtc, false);
3165
3166 intel_disable_plane(dev_priv, plane, pipe);
3167
3168 if (dev_priv->cfb_plane == plane)
3169 intel_disable_fbc(dev);
3170
3171 intel_disable_pipe(dev_priv, pipe);
3172
3173 /* Disable PF */
3174 I915_WRITE(PF_CTL(pipe), 0);
3175 I915_WRITE(PF_WIN_SZ(pipe), 0);
3176
3177 ironlake_fdi_disable(crtc);
3178
3179 /* This is a horrible layering violation; we should be doing this in
3180 * the connector/encoder ->prepare instead, but we don't always have
3181 * enough information there about the config to know whether it will
3182 * actually be necessary or just cause undesired flicker.
3183 */
3184 intel_disable_pch_ports(dev_priv, pipe);
3185
3186 intel_disable_transcoder(dev_priv, pipe);
3187
3188 if (HAS_PCH_CPT(dev)) {
3189 /* disable TRANS_DP_CTL */
3190 reg = TRANS_DP_CTL(pipe);
3191 temp = I915_READ(reg);
3192 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3193 temp |= TRANS_DP_PORT_SEL_NONE;
3194 I915_WRITE(reg, temp);
3195
3196 /* disable DPLL_SEL */
3197 temp = I915_READ(PCH_DPLL_SEL);
3198 switch (pipe) {
3199 case 0:
3200 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3201 break;
3202 case 1:
3203 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3204 break;
3205 case 2:
3206 /* C shares PLL A or B */
3207 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3208 break;
3209 default:
3210 KASSERT(1, ("Wrong pipe %d", pipe)); /* wtf */
3211 }
3212 I915_WRITE(PCH_DPLL_SEL, temp);
3213 }
3214
3215 /* disable PCH DPLL */
3216 if (!intel_crtc->no_pll)
3217 intel_disable_pch_pll(dev_priv, pipe);
3218
3219 /* Switch from PCDclk to Rawclk */
3220 reg = FDI_RX_CTL(pipe);
3221 temp = I915_READ(reg);
3222 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3223
3224 /* Disable CPU FDI TX PLL */
3225 reg = FDI_TX_CTL(pipe);
3226 temp = I915_READ(reg);
3227 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3228
3229 POSTING_READ(reg);
3230 DELAY(100);
3231
3232 reg = FDI_RX_CTL(pipe);
3233 temp = I915_READ(reg);
3234 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3235
3236 /* Wait for the clocks to turn off. */
3237 POSTING_READ(reg);
3238 DELAY(100);
3239
3240 intel_crtc->active = false;
3241 intel_update_watermarks(dev);
3242
3243 DRM_LOCK(dev);
3244 intel_update_fbc(dev);
3245 intel_clear_scanline_wait(dev);
3246 DRM_UNLOCK(dev);
3247}
3248
3249static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3250{
3251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3252 int pipe = intel_crtc->pipe;
3253 int plane = intel_crtc->plane;
3254
3255 /* XXX: When our outputs are all unaware of DPMS modes other than off
3256 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3257 */
3258 switch (mode) {
3259 case DRM_MODE_DPMS_ON:
3260 case DRM_MODE_DPMS_STANDBY:
3261 case DRM_MODE_DPMS_SUSPEND:
3262 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3263 ironlake_crtc_enable(crtc);
3264 break;
3265
3266 case DRM_MODE_DPMS_OFF:
3267 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3268 ironlake_crtc_disable(crtc);
3269 break;
3270 }
3271}
3272
3273static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3274{
3275 if (!enable && intel_crtc->overlay) {
3276 struct drm_device *dev = intel_crtc->base.dev;
3277 struct drm_i915_private *dev_priv = dev->dev_private;
3278
3279 DRM_LOCK(dev);
3280 dev_priv->mm.interruptible = false;
3281 (void) intel_overlay_switch_off(intel_crtc->overlay);
3282 dev_priv->mm.interruptible = true;
3283 DRM_UNLOCK(dev);
3284 }
3285
3286 /* Let userspace switch the overlay on again. In most cases userspace
3287 * has to recompute where to put it anyway.
3288 */
3289}
3290
3291static void i9xx_crtc_enable(struct drm_crtc *crtc)
3292{
3293 struct drm_device *dev = crtc->dev;
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296 int pipe = intel_crtc->pipe;
3297 int plane = intel_crtc->plane;
3298
3299 if (intel_crtc->active)
3300 return;
3301
3302 intel_crtc->active = true;
3303 intel_update_watermarks(dev);
3304
3305 intel_enable_pll(dev_priv, pipe);
3306 intel_enable_pipe(dev_priv, pipe, false);
3307 intel_enable_plane(dev_priv, plane, pipe);
3308
3309 intel_crtc_load_lut(crtc);
3310 intel_update_fbc(dev);
3311
3312 /* Give the overlay scaler a chance to enable if it's on this pipe */
3313 intel_crtc_dpms_overlay(intel_crtc, true);
3314 intel_crtc_update_cursor(crtc, true);
3315}
3316
3317static void i9xx_crtc_disable(struct drm_crtc *crtc)
3318{
3319 struct drm_device *dev = crtc->dev;
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3322 int pipe = intel_crtc->pipe;
3323 int plane = intel_crtc->plane;
3324
3325 if (!intel_crtc->active)
3326 return;
3327
3328 /* Give the overlay scaler a chance to disable if it's on this pipe */
3329 intel_crtc_wait_for_pending_flips(crtc);
3330 drm_vblank_off(dev, pipe);
3331 intel_crtc_dpms_overlay(intel_crtc, false);
3332 intel_crtc_update_cursor(crtc, false);
3333
3334 if (dev_priv->cfb_plane == plane)
3335 intel_disable_fbc(dev);
3336
3337 intel_disable_plane(dev_priv, plane, pipe);
3338 intel_disable_pipe(dev_priv, pipe);
3339 intel_disable_pll(dev_priv, pipe);
3340
3341 intel_crtc->active = false;
3342 intel_update_fbc(dev);
3343 intel_update_watermarks(dev);
3344 intel_clear_scanline_wait(dev);
3345}
3346
3347static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3348{
3349 /* XXX: When our outputs are all unaware of DPMS modes other than off
3350 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3351 */
3352 switch (mode) {
3353 case DRM_MODE_DPMS_ON:
3354 case DRM_MODE_DPMS_STANDBY:
3355 case DRM_MODE_DPMS_SUSPEND:
3356 i9xx_crtc_enable(crtc);
3357 break;
3358 case DRM_MODE_DPMS_OFF:
3359 i9xx_crtc_disable(crtc);
3360 break;
3361 }
3362}
3363
3364/**
3365 * Sets the power management mode of the pipe and plane.
3366 */
3367static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3368{
3369 struct drm_device *dev = crtc->dev;
3370 struct drm_i915_private *dev_priv = dev->dev_private;
3371#if 0
3372 struct drm_i915_master_private *master_priv;
3373#endif
3374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3375 int pipe = intel_crtc->pipe;
3376 bool enabled;
3377
3378 if (intel_crtc->dpms_mode == mode)
3379 return;
3380
3381 intel_crtc->dpms_mode = mode;
3382
3383 dev_priv->display.dpms(crtc, mode);
3384
3385#if 0
3386 if (!dev->primary->master)
3387 return;
3388
3389 master_priv = dev->primary->master->driver_priv;
3390 if (!master_priv->sarea_priv)
3391 return;
3392#else
3393 if (!dev_priv->sarea_priv)
3394 return;
3395#endif
3396
3397 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3398
3399 switch (pipe) {
3400 case 0:
3401#if 0
3402 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3403 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3404#else
3405 dev_priv->sarea_priv->planeA_w = enabled ? crtc->mode.hdisplay : 0;
3406 dev_priv->sarea_priv->planeA_h = enabled ? crtc->mode.vdisplay : 0;
3407#endif
3408 break;
3409 case 1:
3410#if 0
3411 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3412 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3413#else
3414 dev_priv->sarea_priv->planeB_w = enabled ? crtc->mode.hdisplay : 0;
3415 dev_priv->sarea_priv->planeB_h = enabled ? crtc->mode.vdisplay : 0;
3416#endif
3417 break;
3418 default:
3419 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3420 break;
3421 }
3422}
3423
3424static void intel_crtc_disable(struct drm_crtc *crtc)
3425{
3426 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3427 struct drm_device *dev = crtc->dev;
3428
3429 /* Flush any pending WAITs before we disable the pipe. Note that
3430 * we need to drop the struct_mutex in order to acquire it again
3431 * during the lowlevel dpms routines around a couple of the
3432 * operations. It does not look trivial nor desirable to move
3433 * that locking higher. So instead we leave a window for the
3434 * submission of further commands on the fb before we can actually
3435 * disable it. This race with userspace exists anyway, and we can
3436 * only rely on the pipe being disabled by userspace after it
3437 * receives the hotplug notification and has flushed any pending
3438 * batches.
3439 */
3440 if (crtc->fb) {
3441 DRM_LOCK(dev);
3442 intel_finish_fb(crtc->fb);
3443 DRM_UNLOCK(dev);
3444 }
3445
3446 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3447 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3448 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3449
3450 if (crtc->fb) {
3451 DRM_LOCK(dev);
3452 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3453 DRM_UNLOCK(dev);
3454 }
3455}
3456
3457/* Prepare for a mode set.
3458 *
3459 * Note we could be a lot smarter here. We need to figure out which outputs
3460 * will be enabled, which disabled (in short, how the config will changes)
3461 * and perform the minimum necessary steps to accomplish that, e.g. updating
3462 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3463 * panel fitting is in the proper state, etc.
3464 */
3465static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3466{
3467 i9xx_crtc_disable(crtc);
3468}
3469
3470static void i9xx_crtc_commit(struct drm_crtc *crtc)
3471{
3472 i9xx_crtc_enable(crtc);
3473}
3474
3475static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3476{
3477 ironlake_crtc_disable(crtc);
3478}
3479
3480static void ironlake_crtc_commit(struct drm_crtc *crtc)
3481{
3482 ironlake_crtc_enable(crtc);
3483}
3484
3485void intel_encoder_prepare(struct drm_encoder *encoder)
3486{
3487 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3488 /* lvds has its own version of prepare see intel_lvds_prepare */
3489 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3490}
3491
3492void intel_encoder_commit(struct drm_encoder *encoder)
3493{
3494 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3495 struct drm_device *dev = encoder->dev;
3496 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3497 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3498
3499 /* lvds has its own version of commit see intel_lvds_commit */
3500 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3501
3502 if (HAS_PCH_CPT(dev))
3503 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3504}
3505
3506void intel_encoder_destroy(struct drm_encoder *encoder)
3507{
3508 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3509
3510 drm_encoder_cleanup(encoder);
3511 free(intel_encoder, DRM_MEM_KMS);
3512}
3513
3514static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
|
3516 struct drm_display_mode *adjusted_mode)
3517{
3518 struct drm_device *dev = crtc->dev;
3519
3520 if (HAS_PCH_SPLIT(dev)) {
3521 /* FDI link clock is fixed at 2.7G */
3522 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3523 return false;
3524 }
3525
3526 /* All interlaced capable intel hw wants timings in frames. Note though
3527 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3528 * timings, so we need to be careful not to clobber these.*/
3529 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3530 drm_mode_set_crtcinfo(adjusted_mode, 0);
3531
3532 return true;
3533}
3534
3535static int i945_get_display_clock_speed(struct drm_device *dev)
3536{
3537 return 400000;
3538}
3539
3540static int i915_get_display_clock_speed(struct drm_device *dev)
3541{
3542 return 333000;
3543}
3544
3545static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3546{
3547 return 200000;
3548}
3549
3550static int i915gm_get_display_clock_speed(struct drm_device *dev)
3551{
3552 u16 gcfgc = 0;
3553
3554 gcfgc = pci_read_config(dev->device, GCFGC, 2);
3555
3556 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3557 return 133000;
3558 else {
3559 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3560 case GC_DISPLAY_CLOCK_333_MHZ:
3561 return 333000;
3562 default:
3563 case GC_DISPLAY_CLOCK_190_200_MHZ:
3564 return 190000;
3565 }
3566 }
3567}
3568
3569static int i865_get_display_clock_speed(struct drm_device *dev)
3570{
3571 return 266000;
3572}
3573
3574static int i855_get_display_clock_speed(struct drm_device *dev)
3575{
3576 u16 hpllcc = 0;
3577 /* Assume that the hardware is in the high speed state. This
3578 * should be the default.
3579 */
3580 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3581 case GC_CLOCK_133_200:
3582 case GC_CLOCK_100_200:
3583 return 200000;
3584 case GC_CLOCK_166_250:
3585 return 250000;
3586 case GC_CLOCK_100_133:
3587 return 133000;
3588 }
3589
3590 /* Shouldn't happen */
3591 return 0;
3592}
3593
3594static int i830_get_display_clock_speed(struct drm_device *dev)
3595{
3596 return 133000;
3597}
3598
3599struct fdi_m_n {
3600 u32 tu;
3601 u32 gmch_m;
3602 u32 gmch_n;
3603 u32 link_m;
3604 u32 link_n;
3605};
3606
3607static void
3608fdi_reduce_ratio(u32 *num, u32 *den)
3609{
3610 while (*num > 0xffffff || *den > 0xffffff) {
3611 *num >>= 1;
3612 *den >>= 1;
3613 }
3614}
3615
3616static void
3617ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3618 int link_clock, struct fdi_m_n *m_n)
3619{
3620 m_n->tu = 64; /* default size */
3621
3622 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3623 m_n->gmch_m = bits_per_pixel * pixel_clock;
3624 m_n->gmch_n = link_clock * nlanes * 8;
3625 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3626
3627 m_n->link_m = pixel_clock;
3628 m_n->link_n = link_clock;
3629 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3630}
3631
3632
3633struct intel_watermark_params {
3634 unsigned long fifo_size;
3635 unsigned long max_wm;
3636 unsigned long default_wm;
3637 unsigned long guard_size;
3638 unsigned long cacheline_size;
3639};
3640
3641/* Pineview has different values for various configs */
3642static const struct intel_watermark_params pineview_display_wm = {
3643 PINEVIEW_DISPLAY_FIFO,
3644 PINEVIEW_MAX_WM,
3645 PINEVIEW_DFT_WM,
3646 PINEVIEW_GUARD_WM,
3647 PINEVIEW_FIFO_LINE_SIZE
3648};
3649static const struct intel_watermark_params pineview_display_hplloff_wm = {
3650 PINEVIEW_DISPLAY_FIFO,
3651 PINEVIEW_MAX_WM,
3652 PINEVIEW_DFT_HPLLOFF_WM,
3653 PINEVIEW_GUARD_WM,
3654 PINEVIEW_FIFO_LINE_SIZE
3655};
3656static const struct intel_watermark_params pineview_cursor_wm = {
3657 PINEVIEW_CURSOR_FIFO,
3658 PINEVIEW_CURSOR_MAX_WM,
3659 PINEVIEW_CURSOR_DFT_WM,
3660 PINEVIEW_CURSOR_GUARD_WM,
3661 PINEVIEW_FIFO_LINE_SIZE,
3662};
3663static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3664 PINEVIEW_CURSOR_FIFO,
3665 PINEVIEW_CURSOR_MAX_WM,
3666 PINEVIEW_CURSOR_DFT_WM,
3667 PINEVIEW_CURSOR_GUARD_WM,
3668 PINEVIEW_FIFO_LINE_SIZE
3669};
3670static const struct intel_watermark_params g4x_wm_info = {
3671 G4X_FIFO_SIZE,
3672 G4X_MAX_WM,
3673 G4X_MAX_WM,
3674 2,
3675 G4X_FIFO_LINE_SIZE,
3676};
3677static const struct intel_watermark_params g4x_cursor_wm_info = {
3678 I965_CURSOR_FIFO,
3679 I965_CURSOR_MAX_WM,
3680 I965_CURSOR_DFT_WM,
3681 2,
3682 G4X_FIFO_LINE_SIZE,
3683};
3684static const struct intel_watermark_params i965_cursor_wm_info = {
3685 I965_CURSOR_FIFO,
3686 I965_CURSOR_MAX_WM,
3687 I965_CURSOR_DFT_WM,
3688 2,
3689 I915_FIFO_LINE_SIZE,
3690};
3691static const struct intel_watermark_params i945_wm_info = {
3692 I945_FIFO_SIZE,
3693 I915_MAX_WM,
3694 1,
3695 2,
3696 I915_FIFO_LINE_SIZE
3697};
3698static const struct intel_watermark_params i915_wm_info = {
3699 I915_FIFO_SIZE,
3700 I915_MAX_WM,
3701 1,
3702 2,
3703 I915_FIFO_LINE_SIZE
3704};
3705static const struct intel_watermark_params i855_wm_info = {
3706 I855GM_FIFO_SIZE,
3707 I915_MAX_WM,
3708 1,
3709 2,
3710 I830_FIFO_LINE_SIZE
3711};
3712static const struct intel_watermark_params i830_wm_info = {
3713 I830_FIFO_SIZE,
3714 I915_MAX_WM,
3715 1,
3716 2,
3717 I830_FIFO_LINE_SIZE
3718};
3719
3720static const struct intel_watermark_params ironlake_display_wm_info = {
3721 ILK_DISPLAY_FIFO,
3722 ILK_DISPLAY_MAXWM,
3723 ILK_DISPLAY_DFTWM,
3724 2,
3725 ILK_FIFO_LINE_SIZE
3726};
3727static const struct intel_watermark_params ironlake_cursor_wm_info = {
3728 ILK_CURSOR_FIFO,
3729 ILK_CURSOR_MAXWM,
3730 ILK_CURSOR_DFTWM,
3731 2,
3732 ILK_FIFO_LINE_SIZE
3733};
3734static const struct intel_watermark_params ironlake_display_srwm_info = {
3735 ILK_DISPLAY_SR_FIFO,
3736 ILK_DISPLAY_MAX_SRWM,
3737 ILK_DISPLAY_DFT_SRWM,
3738 2,
3739 ILK_FIFO_LINE_SIZE
3740};
3741static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3742 ILK_CURSOR_SR_FIFO,
3743 ILK_CURSOR_MAX_SRWM,
3744 ILK_CURSOR_DFT_SRWM,
3745 2,
3746 ILK_FIFO_LINE_SIZE
3747};
3748
3749static const struct intel_watermark_params sandybridge_display_wm_info = {
3750 SNB_DISPLAY_FIFO,
3751 SNB_DISPLAY_MAXWM,
3752 SNB_DISPLAY_DFTWM,
3753 2,
3754 SNB_FIFO_LINE_SIZE
3755};
3756static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3757 SNB_CURSOR_FIFO,
3758 SNB_CURSOR_MAXWM,
3759 SNB_CURSOR_DFTWM,
3760 2,
3761 SNB_FIFO_LINE_SIZE
3762};
3763static const struct intel_watermark_params sandybridge_display_srwm_info = {
3764 SNB_DISPLAY_SR_FIFO,
3765 SNB_DISPLAY_MAX_SRWM,
3766 SNB_DISPLAY_DFT_SRWM,
3767 2,
3768 SNB_FIFO_LINE_SIZE
3769};
3770static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3771 SNB_CURSOR_SR_FIFO,
3772 SNB_CURSOR_MAX_SRWM,
3773 SNB_CURSOR_DFT_SRWM,
3774 2,
3775 SNB_FIFO_LINE_SIZE
3776};
3777
3778
3779/**
3780 * intel_calculate_wm - calculate watermark level
3781 * @clock_in_khz: pixel clock
3782 * @wm: chip FIFO params
3783 * @pixel_size: display pixel size
3784 * @latency_ns: memory latency for the platform
3785 *
3786 * Calculate the watermark level (the level at which the display plane will
3787 * start fetching from memory again). Each chip has a different display
3788 * FIFO size and allocation, so the caller needs to figure that out and pass
3789 * in the correct intel_watermark_params structure.
3790 *
3791 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3792 * on the pixel size. When it reaches the watermark level, it'll start
3793 * fetching FIFO line sized based chunks from memory until the FIFO fills
3794 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3795 * will occur, and a display engine hang could result.
3796 */
3797static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3798 const struct intel_watermark_params *wm,
3799 int fifo_size,
3800 int pixel_size,
3801 unsigned long latency_ns)
3802{
3803 long entries_required, wm_size;
3804
3805 /*
3806 * Note: we need to make sure we don't overflow for various clock &
3807 * latency values.
3808 * clocks go from a few thousand to several hundred thousand.
3809 * latency is usually a few thousand
3810 */
3811 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3812 1000;
3813 entries_required = howmany(entries_required, wm->cacheline_size);
3814
3815 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3816
3817 wm_size = fifo_size - (entries_required + wm->guard_size);
3818
3819 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3820
3821 /* Don't promote wm_size to unsigned... */
3822 if (wm_size > (long)wm->max_wm)
3823 wm_size = wm->max_wm;
3824 if (wm_size <= 0)
3825 wm_size = wm->default_wm;
3826 return wm_size;
3827}
3828
3829struct cxsr_latency {
3830 int is_desktop;
3831 int is_ddr3;
3832 unsigned long fsb_freq;
3833 unsigned long mem_freq;
3834 unsigned long display_sr;
3835 unsigned long display_hpll_disable;
3836 unsigned long cursor_sr;
3837 unsigned long cursor_hpll_disable;
3838};
3839
3840static const struct cxsr_latency cxsr_latency_table[] = {
3841 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3842 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3843 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3844 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3845 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3846
3847 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3848 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3849 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3850 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3851 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3852
3853 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3854 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3855 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3856 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3857 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3858
3859 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3860 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3861 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3862 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3863 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3864
3865 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3866 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3867 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3868 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3869 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3870
3871 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3872 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3873 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3874 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3875 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3876};
3877
3878static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3879 int is_ddr3,
3880 int fsb,
3881 int mem)
3882{
3883 const struct cxsr_latency *latency;
3884 int i;
3885
3886 if (fsb == 0 || mem == 0)
3887 return NULL;
3888
3889 for (i = 0; i < DRM_ARRAY_SIZE(cxsr_latency_table); i++) {
3890 latency = &cxsr_latency_table[i];
3891 if (is_desktop == latency->is_desktop &&
3892 is_ddr3 == latency->is_ddr3 &&
3893 fsb == latency->fsb_freq && mem == latency->mem_freq)
3894 return latency;
3895 }
3896
3897 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3898
3899 return NULL;
3900}
3901
3902static void pineview_disable_cxsr(struct drm_device *dev)
3903{
3904 struct drm_i915_private *dev_priv = dev->dev_private;
3905
3906 /* deactivate cxsr */
3907 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3908}
3909
3910/*
3911 * Latency for FIFO fetches is dependent on several factors:
3912 * - memory configuration (speed, channels)
3913 * - chipset
3914 * - current MCH state
3915 * It can be fairly high in some situations, so here we assume a fairly
3916 * pessimal value. It's a tradeoff between extra memory fetches (if we
3917 * set this value too high, the FIFO will fetch frequently to stay full)
3918 * and power consumption (set it too low to save power and we might see
3919 * FIFO underruns and display "flicker").
3920 *
3921 * A value of 5us seems to be a good balance; safe for very low end
3922 * platforms but not overly aggressive on lower latency configs.
3923 */
3924static const int latency_ns = 5000;
3925
3926static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3927{
3928 struct drm_i915_private *dev_priv = dev->dev_private;
3929 uint32_t dsparb = I915_READ(DSPARB);
3930 int size;
3931
3932 size = dsparb & 0x7f;
3933 if (plane)
3934 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3935
3936 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3937 plane ? "B" : "A", size);
3938
3939 return size;
3940}
3941
3942static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3943{
3944 struct drm_i915_private *dev_priv = dev->dev_private;
3945 uint32_t dsparb = I915_READ(DSPARB);
3946 int size;
3947
3948 size = dsparb & 0x1ff;
3949 if (plane)
3950 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3951 size >>= 1; /* Convert to cachelines */
3952
3953 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3954 plane ? "B" : "A", size);
3955
3956 return size;
3957}
3958
3959static int i845_get_fifo_size(struct drm_device *dev, int plane)
3960{
3961 struct drm_i915_private *dev_priv = dev->dev_private;
3962 uint32_t dsparb = I915_READ(DSPARB);
3963 int size;
3964
3965 size = dsparb & 0x7f;
3966 size >>= 2; /* Convert to cachelines */
3967
3968 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3969 plane ? "B" : "A",
3970 size);
3971
3972 return size;
3973}
3974
3975static int i830_get_fifo_size(struct drm_device *dev, int plane)
3976{
3977 struct drm_i915_private *dev_priv = dev->dev_private;
3978 uint32_t dsparb = I915_READ(DSPARB);
3979 int size;
3980
3981 size = dsparb & 0x7f;
3982 size >>= 1; /* Convert to cachelines */
3983
3984 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3985 plane ? "B" : "A", size);
3986
3987 return size;
3988}
3989
3990static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3991{
3992 struct drm_crtc *crtc, *enabled = NULL;
3993
3994 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3995 if (crtc->enabled && crtc->fb) {
3996 if (enabled)
3997 return NULL;
3998 enabled = crtc;
3999 }
4000 }
4001
4002 return enabled;
4003}
4004
4005static void pineview_update_wm(struct drm_device *dev)
4006{
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 struct drm_crtc *crtc;
4009 const struct cxsr_latency *latency;
4010 u32 reg;
4011 unsigned long wm;
4012
4013 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
4014 dev_priv->fsb_freq, dev_priv->mem_freq);
4015 if (!latency) {
4016 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
4017 pineview_disable_cxsr(dev);
4018 return;
4019 }
4020
4021 crtc = single_enabled_crtc(dev);
4022 if (crtc) {
4023 int clock = crtc->mode.clock;
4024 int pixel_size = crtc->fb->bits_per_pixel / 8;
4025
4026 /* Display SR */
4027 wm = intel_calculate_wm(clock, &pineview_display_wm,
4028 pineview_display_wm.fifo_size,
4029 pixel_size, latency->display_sr);
4030 reg = I915_READ(DSPFW1);
4031 reg &= ~DSPFW_SR_MASK;
4032 reg |= wm << DSPFW_SR_SHIFT;
4033 I915_WRITE(DSPFW1, reg);
4034 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
4035
4036 /* cursor SR */
4037 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
4038 pineview_display_wm.fifo_size,
4039 pixel_size, latency->cursor_sr);
4040 reg = I915_READ(DSPFW3);
4041 reg &= ~DSPFW_CURSOR_SR_MASK;
4042 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
4043 I915_WRITE(DSPFW3, reg);
4044
4045 /* Display HPLL off SR */
4046 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4047 pineview_display_hplloff_wm.fifo_size,
4048 pixel_size, latency->display_hpll_disable);
4049 reg = I915_READ(DSPFW3);
4050 reg &= ~DSPFW_HPLL_SR_MASK;
4051 reg |= wm & DSPFW_HPLL_SR_MASK;
4052 I915_WRITE(DSPFW3, reg);
4053
4054 /* cursor HPLL off SR */
4055 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4056 pineview_display_hplloff_wm.fifo_size,
4057 pixel_size, latency->cursor_hpll_disable);
4058 reg = I915_READ(DSPFW3);
4059 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4060 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4061 I915_WRITE(DSPFW3, reg);
4062 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4063
4064 /* activate cxsr */
4065 I915_WRITE(DSPFW3,
4066 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4067 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4068 } else {
4069 pineview_disable_cxsr(dev);
4070 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4071 }
4072}
4073
4074static bool g4x_compute_wm0(struct drm_device *dev,
4075 int plane,
4076 const struct intel_watermark_params *display,
4077 int display_latency_ns,
4078 const struct intel_watermark_params *cursor,
4079 int cursor_latency_ns,
4080 int *plane_wm,
4081 int *cursor_wm)
4082{
4083 struct drm_crtc *crtc;
4084 int htotal, hdisplay, clock, pixel_size;
4085 int line_time_us, line_count;
4086 int entries, tlb_miss;
4087
4088 crtc = intel_get_crtc_for_plane(dev, plane);
4089 if (crtc->fb == NULL || !crtc->enabled) {
4090 *cursor_wm = cursor->guard_size;
4091 *plane_wm = display->guard_size;
4092 return false;
4093 }
4094
4095 htotal = crtc->mode.htotal;
4096 hdisplay = crtc->mode.hdisplay;
4097 clock = crtc->mode.clock;
4098 pixel_size = crtc->fb->bits_per_pixel / 8;
4099
4100 /* Use the small buffer method to calculate plane watermark */
4101 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4102 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4103 if (tlb_miss > 0)
4104 entries += tlb_miss;
4105 entries = howmany(entries, display->cacheline_size);
4106 *plane_wm = entries + display->guard_size;
4107 if (*plane_wm > (int)display->max_wm)
4108 *plane_wm = display->max_wm;
4109
4110 /* Use the large buffer method to calculate cursor watermark */
4111 line_time_us = ((htotal * 1000) / clock);
4112 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4113 entries = line_count * 64 * pixel_size;
4114 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4115 if (tlb_miss > 0)
4116 entries += tlb_miss;
4117 entries = howmany(entries, cursor->cacheline_size);
4118 *cursor_wm = entries + cursor->guard_size;
4119 if (*cursor_wm > (int)cursor->max_wm)
4120 *cursor_wm = (int)cursor->max_wm;
4121
4122 return true;
4123}
4124
4125/*
4126 * Check the wm result.
4127 *
4128 * If any calculated watermark values is larger than the maximum value that
4129 * can be programmed into the associated watermark register, that watermark
4130 * must be disabled.
4131 */
4132static bool g4x_check_srwm(struct drm_device *dev,
4133 int display_wm, int cursor_wm,
4134 const struct intel_watermark_params *display,
4135 const struct intel_watermark_params *cursor)
4136{
4137 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4138 display_wm, cursor_wm);
4139
4140 if (display_wm > display->max_wm) {
4141 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4142 display_wm, display->max_wm);
4143 return false;
4144 }
4145
4146 if (cursor_wm > cursor->max_wm) {
4147 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4148 cursor_wm, cursor->max_wm);
4149 return false;
4150 }
4151
4152 if (!(display_wm || cursor_wm)) {
4153 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4154 return false;
4155 }
4156
4157 return true;
4158}
4159
4160static bool g4x_compute_srwm(struct drm_device *dev,
4161 int plane,
4162 int latency_ns,
4163 const struct intel_watermark_params *display,
4164 const struct intel_watermark_params *cursor,
4165 int *display_wm, int *cursor_wm)
4166{
4167 struct drm_crtc *crtc;
4168 int hdisplay, htotal, pixel_size, clock;
4169 unsigned long line_time_us;
4170 int line_count, line_size;
4171 int small, large;
4172 int entries;
4173
4174 if (!latency_ns) {
4175 *display_wm = *cursor_wm = 0;
4176 return false;
4177 }
4178
4179 crtc = intel_get_crtc_for_plane(dev, plane);
4180 hdisplay = crtc->mode.hdisplay;
4181 htotal = crtc->mode.htotal;
4182 clock = crtc->mode.clock;
4183 pixel_size = crtc->fb->bits_per_pixel / 8;
4184
4185 line_time_us = (htotal * 1000) / clock;
4186 line_count = (latency_ns / line_time_us + 1000) / 1000;
4187 line_size = hdisplay * pixel_size;
4188
4189 /* Use the minimum of the small and large buffer method for primary */
4190 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4191 large = line_count * line_size;
4192
4193 entries = howmany(min(small, large), display->cacheline_size);
4194 *display_wm = entries + display->guard_size;
4195
4196 /* calculate the self-refresh watermark for display cursor */
4197 entries = line_count * pixel_size * 64;
4198 entries = howmany(entries, cursor->cacheline_size);
4199 *cursor_wm = entries + cursor->guard_size;
4200
4201 return g4x_check_srwm(dev,
4202 *display_wm, *cursor_wm,
4203 display, cursor);
4204}
4205
4206#define single_plane_enabled(mask) ((mask) != 0 && powerof2(mask))
4207
4208static void g4x_update_wm(struct drm_device *dev)
4209{
4210 static const int sr_latency_ns = 12000;
4211 struct drm_i915_private *dev_priv = dev->dev_private;
4212 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4213 int plane_sr, cursor_sr;
4214 unsigned int enabled = 0;
4215
4216 if (g4x_compute_wm0(dev, 0,
4217 &g4x_wm_info, latency_ns,
4218 &g4x_cursor_wm_info, latency_ns,
4219 &planea_wm, &cursora_wm))
4220 enabled |= 1;
4221
4222 if (g4x_compute_wm0(dev, 1,
4223 &g4x_wm_info, latency_ns,
4224 &g4x_cursor_wm_info, latency_ns,
4225 &planeb_wm, &cursorb_wm))
4226 enabled |= 2;
4227
4228 plane_sr = cursor_sr = 0;
4229 if (single_plane_enabled(enabled) &&
4230 g4x_compute_srwm(dev, ffs(enabled) - 1,
4231 sr_latency_ns,
4232 &g4x_wm_info,
4233 &g4x_cursor_wm_info,
4234 &plane_sr, &cursor_sr))
4235 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4236 else
4237 I915_WRITE(FW_BLC_SELF,
4238 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4239
4240 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4241 planea_wm, cursora_wm,
4242 planeb_wm, cursorb_wm,
4243 plane_sr, cursor_sr);
4244
4245 I915_WRITE(DSPFW1,
4246 (plane_sr << DSPFW_SR_SHIFT) |
4247 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4248 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4249 planea_wm);
4250 I915_WRITE(DSPFW2,
4251 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4252 (cursora_wm << DSPFW_CURSORA_SHIFT));
4253 /* HPLL off in SR has some issues on G4x... disable it */
4254 I915_WRITE(DSPFW3,
4255 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4256 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4257}
4258
4259static void i965_update_wm(struct drm_device *dev)
4260{
4261 struct drm_i915_private *dev_priv = dev->dev_private;
4262 struct drm_crtc *crtc;
4263 int srwm = 1;
4264 int cursor_sr = 16;
4265
4266 /* Calc sr entries for one plane configs */
4267 crtc = single_enabled_crtc(dev);
4268 if (crtc) {
4269 /* self-refresh has much higher latency */
4270 static const int sr_latency_ns = 12000;
4271 int clock = crtc->mode.clock;
4272 int htotal = crtc->mode.htotal;
4273 int hdisplay = crtc->mode.hdisplay;
4274 int pixel_size = crtc->fb->bits_per_pixel / 8;
4275 unsigned long line_time_us;
4276 int entries;
4277
4278 line_time_us = ((htotal * 1000) / clock);
4279
4280 /* Use ns/us then divide to preserve precision */
4281 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4282 pixel_size * hdisplay;
4283 entries = howmany(entries, I915_FIFO_LINE_SIZE);
4284 srwm = I965_FIFO_SIZE - entries;
4285 if (srwm < 0)
4286 srwm = 1;
4287 srwm &= 0x1ff;
4288 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4289 entries, srwm);
4290
4291 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4292 pixel_size * 64;
4293 entries = howmany(entries, i965_cursor_wm_info.cacheline_size);
4294 cursor_sr = i965_cursor_wm_info.fifo_size -
4295 (entries + i965_cursor_wm_info.guard_size);
4296
4297 if (cursor_sr > i965_cursor_wm_info.max_wm)
4298 cursor_sr = i965_cursor_wm_info.max_wm;
4299
4300 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4301 "cursor %d\n", srwm, cursor_sr);
4302
4303 if (IS_CRESTLINE(dev))
4304 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4305 } else {
4306 /* Turn off self refresh if both pipes are enabled */
4307 if (IS_CRESTLINE(dev))
4308 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4309 & ~FW_BLC_SELF_EN);
4310 }
4311
4312 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4313 srwm);
4314
4315 /* 965 has limitations... */
4316 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4317 (8 << 16) | (8 << 8) | (8 << 0));
4318 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4319 /* update cursor SR watermark */
4320 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4321}
4322
4323static void i9xx_update_wm(struct drm_device *dev)
4324{
4325 struct drm_i915_private *dev_priv = dev->dev_private;
4326 const struct intel_watermark_params *wm_info;
4327 uint32_t fwater_lo;
4328 uint32_t fwater_hi;
4329 int cwm, srwm = 1;
4330 int fifo_size;
4331 int planea_wm, planeb_wm;
4332 struct drm_crtc *crtc, *enabled = NULL;
4333
4334 if (IS_I945GM(dev))
4335 wm_info = &i945_wm_info;
4336 else if (!IS_GEN2(dev))
4337 wm_info = &i915_wm_info;
4338 else
4339 wm_info = &i855_wm_info;
4340
4341 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4342 crtc = intel_get_crtc_for_plane(dev, 0);
4343 if (crtc->enabled && crtc->fb) {
4344 planea_wm = intel_calculate_wm(crtc->mode.clock,
4345 wm_info, fifo_size,
4346 crtc->fb->bits_per_pixel / 8,
4347 latency_ns);
4348 enabled = crtc;
4349 } else
4350 planea_wm = fifo_size - wm_info->guard_size;
4351
4352 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4353 crtc = intel_get_crtc_for_plane(dev, 1);
4354 if (crtc->enabled && crtc->fb) {
4355 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4356 wm_info, fifo_size,
4357 crtc->fb->bits_per_pixel / 8,
4358 latency_ns);
4359 if (enabled == NULL)
4360 enabled = crtc;
4361 else
4362 enabled = NULL;
4363 } else
4364 planeb_wm = fifo_size - wm_info->guard_size;
4365
4366 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4367
4368 /*
4369 * Overlay gets an aggressive default since video jitter is bad.
4370 */
4371 cwm = 2;
4372
4373 /* Play safe and disable self-refresh before adjusting watermarks. */
4374 if (IS_I945G(dev) || IS_I945GM(dev))
4375 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4376 else if (IS_I915GM(dev))
4377 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4378
4379 /* Calc sr entries for one plane configs */
4380 if (HAS_FW_BLC(dev) && enabled) {
4381 /* self-refresh has much higher latency */
4382 static const int sr_latency_ns = 6000;
4383 int clock = enabled->mode.clock;
4384 int htotal = enabled->mode.htotal;
4385 int hdisplay = enabled->mode.hdisplay;
4386 int pixel_size = enabled->fb->bits_per_pixel / 8;
4387 unsigned long line_time_us;
4388 int entries;
4389
4390 line_time_us = (htotal * 1000) / clock;
4391
4392 /* Use ns/us then divide to preserve precision */
4393 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4394 pixel_size * hdisplay;
4395 entries = howmany(entries, wm_info->cacheline_size);
4396 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4397 srwm = wm_info->fifo_size - entries;
4398 if (srwm < 0)
4399 srwm = 1;
4400
4401 if (IS_I945G(dev) || IS_I945GM(dev))
4402 I915_WRITE(FW_BLC_SELF,
4403 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4404 else if (IS_I915GM(dev))
4405 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4406 }
4407
4408 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4409 planea_wm, planeb_wm, cwm, srwm);
4410
4411 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4412 fwater_hi = (cwm & 0x1f);
4413
4414 /* Set request length to 8 cachelines per fetch */
4415 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4416 fwater_hi = fwater_hi | (1 << 8);
4417
4418 I915_WRITE(FW_BLC, fwater_lo);
4419 I915_WRITE(FW_BLC2, fwater_hi);
4420
4421 if (HAS_FW_BLC(dev)) {
4422 if (enabled) {
4423 if (IS_I945G(dev) || IS_I945GM(dev))
4424 I915_WRITE(FW_BLC_SELF,
4425 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4426 else if (IS_I915GM(dev))
4427 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4428 DRM_DEBUG_KMS("memory self refresh enabled\n");
4429 } else
4430 DRM_DEBUG_KMS("memory self refresh disabled\n");
4431 }
4432}
4433
4434static void i830_update_wm(struct drm_device *dev)
4435{
4436 struct drm_i915_private *dev_priv = dev->dev_private;
4437 struct drm_crtc *crtc;
4438 uint32_t fwater_lo;
4439 int planea_wm;
4440
4441 crtc = single_enabled_crtc(dev);
4442 if (crtc == NULL)
4443 return;
4444
4445 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4446 dev_priv->display.get_fifo_size(dev, 0),
4447 crtc->fb->bits_per_pixel / 8,
4448 latency_ns);
4449 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4450 fwater_lo |= (3<<8) | planea_wm;
4451
4452 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4453
4454 I915_WRITE(FW_BLC, fwater_lo);
4455}
4456
4457#define ILK_LP0_PLANE_LATENCY 700
4458#define ILK_LP0_CURSOR_LATENCY 1300
4459
4460/*
4461 * Check the wm result.
4462 *
4463 * If any calculated watermark values is larger than the maximum value that
4464 * can be programmed into the associated watermark register, that watermark
4465 * must be disabled.
4466 */
4467static bool ironlake_check_srwm(struct drm_device *dev, int level,
4468 int fbc_wm, int display_wm, int cursor_wm,
4469 const struct intel_watermark_params *display,
4470 const struct intel_watermark_params *cursor)
4471{
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473
4474 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4475 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4476
4477 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4478 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4479 fbc_wm, SNB_FBC_MAX_SRWM, level);
4480
4481 /* fbc has it's own way to disable FBC WM */
4482 I915_WRITE(DISP_ARB_CTL,
4483 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4484 return false;
4485 }
4486
4487 if (display_wm > display->max_wm) {
4488 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4489 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4490 return false;
4491 }
4492
4493 if (cursor_wm > cursor->max_wm) {
4494 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4495 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4496 return false;
4497 }
4498
4499 if (!(fbc_wm || display_wm || cursor_wm)) {
4500 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4501 return false;
4502 }
4503
4504 return true;
4505}
4506
4507/*
4508 * Compute watermark values of WM[1-3],
4509 */
4510static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4511 int latency_ns,
4512 const struct intel_watermark_params *display,
4513 const struct intel_watermark_params *cursor,
4514 int *fbc_wm, int *display_wm, int *cursor_wm)
4515{
4516 struct drm_crtc *crtc;
4517 unsigned long line_time_us;
4518 int hdisplay, htotal, pixel_size, clock;
4519 int line_count, line_size;
4520 int small, large;
4521 int entries;
4522
4523 if (!latency_ns) {
4524 *fbc_wm = *display_wm = *cursor_wm = 0;
4525 return false;
4526 }
4527
4528 crtc = intel_get_crtc_for_plane(dev, plane);
4529 hdisplay = crtc->mode.hdisplay;
4530 htotal = crtc->mode.htotal;
4531 clock = crtc->mode.clock;
4532 pixel_size = crtc->fb->bits_per_pixel / 8;
4533
4534 line_time_us = (htotal * 1000) / clock;
4535 line_count = (latency_ns / line_time_us + 1000) / 1000;
4536 line_size = hdisplay * pixel_size;
4537
4538 /* Use the minimum of the small and large buffer method for primary */
4539 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4540 large = line_count * line_size;
4541
4542 entries = howmany(min(small, large), display->cacheline_size);
4543 *display_wm = entries + display->guard_size;
4544
4545 /*
4546 * Spec says:
4547 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4548 */
4549 *fbc_wm = howmany(*display_wm * 64, line_size) + 2;
4550
4551 /* calculate the self-refresh watermark for display cursor */
4552 entries = line_count * pixel_size * 64;
4553 entries = howmany(entries, cursor->cacheline_size);
4554 *cursor_wm = entries + cursor->guard_size;
4555
4556 return ironlake_check_srwm(dev, level,
4557 *fbc_wm, *display_wm, *cursor_wm,
4558 display, cursor);
4559}
4560
4561static void ironlake_update_wm(struct drm_device *dev)
4562{
4563 struct drm_i915_private *dev_priv = dev->dev_private;
4564 int fbc_wm, plane_wm, cursor_wm;
4565 unsigned int enabled;
4566
4567 enabled = 0;
4568 if (g4x_compute_wm0(dev, 0,
4569 &ironlake_display_wm_info,
4570 ILK_LP0_PLANE_LATENCY,
4571 &ironlake_cursor_wm_info,
4572 ILK_LP0_CURSOR_LATENCY,
4573 &plane_wm, &cursor_wm)) {
4574 I915_WRITE(WM0_PIPEA_ILK,
4575 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4576 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4577 " plane %d, " "cursor: %d\n",
4578 plane_wm, cursor_wm);
4579 enabled |= 1;
4580 }
4581
4582 if (g4x_compute_wm0(dev, 1,
4583 &ironlake_display_wm_info,
4584 ILK_LP0_PLANE_LATENCY,
4585 &ironlake_cursor_wm_info,
4586 ILK_LP0_CURSOR_LATENCY,
4587 &plane_wm, &cursor_wm)) {
4588 I915_WRITE(WM0_PIPEB_ILK,
4589 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4590 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4591 " plane %d, cursor: %d\n",
4592 plane_wm, cursor_wm);
4593 enabled |= 2;
4594 }
4595
4596 /*
4597 * Calculate and update the self-refresh watermark only when one
4598 * display plane is used.
4599 */
4600 I915_WRITE(WM3_LP_ILK, 0);
4601 I915_WRITE(WM2_LP_ILK, 0);
4602 I915_WRITE(WM1_LP_ILK, 0);
4603
4604 if (!single_plane_enabled(enabled))
4605 return;
4606 enabled = ffs(enabled) - 1;
4607
4608 /* WM1 */
4609 if (!ironlake_compute_srwm(dev, 1, enabled,
4610 ILK_READ_WM1_LATENCY() * 500,
4611 &ironlake_display_srwm_info,
4612 &ironlake_cursor_srwm_info,
4613 &fbc_wm, &plane_wm, &cursor_wm))
4614 return;
4615
4616 I915_WRITE(WM1_LP_ILK,
4617 WM1_LP_SR_EN |
4618 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4619 (fbc_wm << WM1_LP_FBC_SHIFT) |
4620 (plane_wm << WM1_LP_SR_SHIFT) |
4621 cursor_wm);
4622
4623 /* WM2 */
4624 if (!ironlake_compute_srwm(dev, 2, enabled,
4625 ILK_READ_WM2_LATENCY() * 500,
4626 &ironlake_display_srwm_info,
4627 &ironlake_cursor_srwm_info,
4628 &fbc_wm, &plane_wm, &cursor_wm))
4629 return;
4630
4631 I915_WRITE(WM2_LP_ILK,
4632 WM2_LP_EN |
4633 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4634 (fbc_wm << WM1_LP_FBC_SHIFT) |
4635 (plane_wm << WM1_LP_SR_SHIFT) |
4636 cursor_wm);
4637
4638 /*
4639 * WM3 is unsupported on ILK, probably because we don't have latency
4640 * data for that power state
4641 */
4642}
4643
4644void sandybridge_update_wm(struct drm_device *dev)
4645{
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4647 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4648 u32 val;
4649 int fbc_wm, plane_wm, cursor_wm;
4650 unsigned int enabled;
4651
4652 enabled = 0;
4653 if (g4x_compute_wm0(dev, 0,
4654 &sandybridge_display_wm_info, latency,
4655 &sandybridge_cursor_wm_info, latency,
4656 &plane_wm, &cursor_wm)) {
4657 val = I915_READ(WM0_PIPEA_ILK);
4658 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4659 I915_WRITE(WM0_PIPEA_ILK, val |
4660 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4661 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4662 " plane %d, " "cursor: %d\n",
4663 plane_wm, cursor_wm);
4664 enabled |= 1;
4665 }
4666
4667 if (g4x_compute_wm0(dev, 1,
4668 &sandybridge_display_wm_info, latency,
4669 &sandybridge_cursor_wm_info, latency,
4670 &plane_wm, &cursor_wm)) {
4671 val = I915_READ(WM0_PIPEB_ILK);
4672 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4673 I915_WRITE(WM0_PIPEB_ILK, val |
4674 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4675 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4676 " plane %d, cursor: %d\n",
4677 plane_wm, cursor_wm);
4678 enabled |= 2;
4679 }
4680
4681 /* IVB has 3 pipes */
4682 if (IS_IVYBRIDGE(dev) &&
4683 g4x_compute_wm0(dev, 2,
4684 &sandybridge_display_wm_info, latency,
4685 &sandybridge_cursor_wm_info, latency,
4686 &plane_wm, &cursor_wm)) {
4687 val = I915_READ(WM0_PIPEC_IVB);
4688 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4689 I915_WRITE(WM0_PIPEC_IVB, val |
4690 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4691 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4692 " plane %d, cursor: %d\n",
4693 plane_wm, cursor_wm);
4694 enabled |= 3;
4695 }
4696
4697 /*
4698 * Calculate and update the self-refresh watermark only when one
4699 * display plane is used.
4700 *
4701 * SNB support 3 levels of watermark.
4702 *
4703 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4704 * and disabled in the descending order
4705 *
4706 */
4707 I915_WRITE(WM3_LP_ILK, 0);
4708 I915_WRITE(WM2_LP_ILK, 0);
4709 I915_WRITE(WM1_LP_ILK, 0);
4710
4711 if (!single_plane_enabled(enabled) ||
4712 dev_priv->sprite_scaling_enabled)
4713 return;
4714 enabled = ffs(enabled) - 1;
4715
4716 /* WM1 */
4717 if (!ironlake_compute_srwm(dev, 1, enabled,
4718 SNB_READ_WM1_LATENCY() * 500,
4719 &sandybridge_display_srwm_info,
4720 &sandybridge_cursor_srwm_info,
4721 &fbc_wm, &plane_wm, &cursor_wm))
4722 return;
4723
4724 I915_WRITE(WM1_LP_ILK,
4725 WM1_LP_SR_EN |
4726 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4727 (fbc_wm << WM1_LP_FBC_SHIFT) |
4728 (plane_wm << WM1_LP_SR_SHIFT) |
4729 cursor_wm);
4730
4731 /* WM2 */
4732 if (!ironlake_compute_srwm(dev, 2, enabled,
4733 SNB_READ_WM2_LATENCY() * 500,
4734 &sandybridge_display_srwm_info,
4735 &sandybridge_cursor_srwm_info,
4736 &fbc_wm, &plane_wm, &cursor_wm))
4737 return;
4738
4739 I915_WRITE(WM2_LP_ILK,
4740 WM2_LP_EN |
4741 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4742 (fbc_wm << WM1_LP_FBC_SHIFT) |
4743 (plane_wm << WM1_LP_SR_SHIFT) |
4744 cursor_wm);
4745
4746 /* WM3 */
4747 if (!ironlake_compute_srwm(dev, 3, enabled,
4748 SNB_READ_WM3_LATENCY() * 500,
4749 &sandybridge_display_srwm_info,
4750 &sandybridge_cursor_srwm_info,
4751 &fbc_wm, &plane_wm, &cursor_wm))
4752 return;
4753
4754 I915_WRITE(WM3_LP_ILK,
4755 WM3_LP_EN |
4756 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4757 (fbc_wm << WM1_LP_FBC_SHIFT) |
4758 (plane_wm << WM1_LP_SR_SHIFT) |
4759 cursor_wm);
4760}
4761
4762static bool
4763sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4764 uint32_t sprite_width, int pixel_size,
4765 const struct intel_watermark_params *display,
4766 int display_latency_ns, int *sprite_wm)
4767{
4768 struct drm_crtc *crtc;
4769 int clock;
4770 int entries, tlb_miss;
4771
4772 crtc = intel_get_crtc_for_plane(dev, plane);
4773 if (crtc->fb == NULL || !crtc->enabled) {
4774 *sprite_wm = display->guard_size;
4775 return false;
4776 }
4777
4778 clock = crtc->mode.clock;
4779
4780 /* Use the small buffer method to calculate the sprite watermark */
4781 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4782 tlb_miss = display->fifo_size*display->cacheline_size -
4783 sprite_width * 8;
4784 if (tlb_miss > 0)
4785 entries += tlb_miss;
4786 entries = howmany(entries, display->cacheline_size);
4787 *sprite_wm = entries + display->guard_size;
4788 if (*sprite_wm > (int)display->max_wm)
4789 *sprite_wm = display->max_wm;
4790
4791 return true;
4792}
4793
4794static bool
4795sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4796 uint32_t sprite_width, int pixel_size,
4797 const struct intel_watermark_params *display,
4798 int latency_ns, int *sprite_wm)
4799{
4800 struct drm_crtc *crtc;
4801 unsigned long line_time_us;
4802 int clock;
4803 int line_count, line_size;
4804 int small, large;
4805 int entries;
4806
4807 if (!latency_ns) {
4808 *sprite_wm = 0;
4809 return false;
4810 }
4811
4812 crtc = intel_get_crtc_for_plane(dev, plane);
4813 clock = crtc->mode.clock;
4814 if (!clock) {
4815 *sprite_wm = 0;
4816 return false;
4817 }
4818
4819 line_time_us = (sprite_width * 1000) / clock;
4820 if (!line_time_us) {
4821 *sprite_wm = 0;
4822 return false;
4823 }
4824
4825 line_count = (latency_ns / line_time_us + 1000) / 1000;
4826 line_size = sprite_width * pixel_size;
4827
4828 /* Use the minimum of the small and large buffer method for primary */
4829 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4830 large = line_count * line_size;
4831
4832 entries = howmany(min(small, large), display->cacheline_size);
4833 *sprite_wm = entries + display->guard_size;
4834
4835 return *sprite_wm > 0x3ff ? false : true;
4836}
4837
4838static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4839 uint32_t sprite_width, int pixel_size)
4840{
4841 struct drm_i915_private *dev_priv = dev->dev_private;
4842 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4843 u32 val;
4844 int sprite_wm, reg;
4845 int ret;
4846
4847 switch (pipe) {
4848 case 0:
4849 reg = WM0_PIPEA_ILK;
4850 break;
4851 case 1:
4852 reg = WM0_PIPEB_ILK;
4853 break;
4854 case 2:
4855 reg = WM0_PIPEC_IVB;
4856 break;
4857 default:
4858 return; /* bad pipe */
4859 }
4860
4861 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4862 &sandybridge_display_wm_info,
4863 latency, &sprite_wm);
4864 if (!ret) {
4865 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4866 pipe);
4867 return;
4868 }
4869
4870 val = I915_READ(reg);
4871 val &= ~WM0_PIPE_SPRITE_MASK;
4872 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4873 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4874
4875
4876 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4877 pixel_size,
4878 &sandybridge_display_srwm_info,
4879 SNB_READ_WM1_LATENCY() * 500,
4880 &sprite_wm);
4881 if (!ret) {
4882 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4883 pipe);
4884 return;
4885 }
4886 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4887
4888 /* Only IVB has two more LP watermarks for sprite */
4889 if (!IS_IVYBRIDGE(dev))
4890 return;
4891
4892 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4893 pixel_size,
4894 &sandybridge_display_srwm_info,
4895 SNB_READ_WM2_LATENCY() * 500,
4896 &sprite_wm);
4897 if (!ret) {
4898 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4899 pipe);
4900 return;
4901 }
4902 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4903
4904 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4905 pixel_size,
4906 &sandybridge_display_srwm_info,
4907 SNB_READ_WM3_LATENCY() * 500,
4908 &sprite_wm);
4909 if (!ret) {
4910 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4911 pipe);
4912 return;
4913 }
4914 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4915}
4916
4917/**
4918 * intel_update_watermarks - update FIFO watermark values based on current modes
4919 *
4920 * Calculate watermark values for the various WM regs based on current mode
4921 * and plane configuration.
4922 *
4923 * There are several cases to deal with here:
4924 * - normal (i.e. non-self-refresh)
4925 * - self-refresh (SR) mode
4926 * - lines are large relative to FIFO size (buffer can hold up to 2)
4927 * - lines are small relative to FIFO size (buffer can hold more than 2
4928 * lines), so need to account for TLB latency
4929 *
4930 * The normal calculation is:
4931 * watermark = dotclock * bytes per pixel * latency
4932 * where latency is platform & configuration dependent (we assume pessimal
4933 * values here).
4934 *
4935 * The SR calculation is:
4936 * watermark = (trunc(latency/line time)+1) * surface width *
4937 * bytes per pixel
4938 * where
4939 * line time = htotal / dotclock
4940 * surface width = hdisplay for normal plane and 64 for cursor
4941 * and latency is assumed to be high, as above.
4942 *
4943 * The final value programmed to the register should always be rounded up,
4944 * and include an extra 2 entries to account for clock crossings.
4945 *
4946 * We don't use the sprite, so we can ignore that. And on Crestline we have
4947 * to set the non-SR watermarks to 8.
4948 */
4949static void intel_update_watermarks(struct drm_device *dev)
4950{
4951 struct drm_i915_private *dev_priv = dev->dev_private;
4952
4953 if (dev_priv->display.update_wm)
4954 dev_priv->display.update_wm(dev);
4955}
4956
4957void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4958 uint32_t sprite_width, int pixel_size)
4959{
4960 struct drm_i915_private *dev_priv = dev->dev_private;
4961
4962 if (dev_priv->display.update_sprite_wm)
4963 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4964 pixel_size);
4965}
4966
4967static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4968{
4969 if (i915_panel_use_ssc >= 0)
4970 return i915_panel_use_ssc != 0;
4971 return dev_priv->lvds_use_ssc
4972 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4973}
4974
4975/**
4976 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4977 * @crtc: CRTC structure
4978 * @mode: requested mode
4979 *
4980 * A pipe may be connected to one or more outputs. Based on the depth of the
4981 * attached framebuffer, choose a good color depth to use on the pipe.
4982 *
4983 * If possible, match the pipe depth to the fb depth. In some cases, this
4984 * isn't ideal, because the connected output supports a lesser or restricted
4985 * set of depths. Resolve that here:
4986 * LVDS typically supports only 6bpc, so clamp down in that case
4987 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4988 * Displays may support a restricted set as well, check EDID and clamp as
4989 * appropriate.
4990 * DP may want to dither down to 6bpc to fit larger modes
4991 *
4992 * RETURNS:
4993 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4994 * true if they don't match).
4995 */
4996static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4997 unsigned int *pipe_bpp,
4998 struct drm_display_mode *mode)
4999{
5000 struct drm_device *dev = crtc->dev;
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002 struct drm_encoder *encoder;
5003 struct drm_connector *connector;
5004 unsigned int display_bpc = UINT_MAX, bpc;
5005
5006 /* Walk the encoders & connectors on this crtc, get min bpc */
5007 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5008 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5009
5010 if (encoder->crtc != crtc)
5011 continue;
5012
5013 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
5014 unsigned int lvds_bpc;
5015
5016 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
5017 LVDS_A3_POWER_UP)
5018 lvds_bpc = 8;
5019 else
5020 lvds_bpc = 6;
5021
5022 if (lvds_bpc < display_bpc) {
5023 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5024 display_bpc = lvds_bpc;
5025 }
5026 continue;
5027 }
5028
5029 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
5030 /* Use VBT settings if we have an eDP panel */
5031 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
5032
5033 if (edp_bpc < display_bpc) {
5034 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5035 display_bpc = edp_bpc;
5036 }
5037 continue;
5038 }
5039
5040 /* Not one of the known troublemakers, check the EDID */
5041 list_for_each_entry(connector, &dev->mode_config.connector_list,
5042 head) {
5043 if (connector->encoder != encoder)
5044 continue;
5045
5046 /* Don't use an invalid EDID bpc value */
5047 if (connector->display_info.bpc &&
5048 connector->display_info.bpc < display_bpc) {
5049 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5050 display_bpc = connector->display_info.bpc;
5051 }
5052 }
5053
5054 /*
5055 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5056 * through, clamp it down. (Note: >12bpc will be caught below.)
5057 */
5058 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5059 if (display_bpc > 8 && display_bpc < 12) {
5060 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5061 display_bpc = 12;
5062 } else {
5063 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5064 display_bpc = 8;
5065 }
5066 }
5067 }
5068
5069 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5070 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5071 display_bpc = 6;
5072 }
5073
5074 /*
5075 * We could just drive the pipe at the highest bpc all the time and
5076 * enable dithering as needed, but that costs bandwidth. So choose
5077 * the minimum value that expresses the full color range of the fb but
5078 * also stays within the max display bpc discovered above.
5079 */
5080
5081 switch (crtc->fb->depth) {
5082 case 8:
5083 bpc = 8; /* since we go through a colormap */
5084 break;
5085 case 15:
5086 case 16:
5087 bpc = 6; /* min is 18bpp */
5088 break;
5089 case 24:
5090 bpc = 8;
5091 break;
5092 case 30:
5093 bpc = 10;
5094 break;
5095 case 48:
5096 bpc = 12;
5097 break;
5098 default:
5099 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5100 bpc = min((unsigned int)8, display_bpc);
5101 break;
5102 }
5103
5104 display_bpc = min(display_bpc, bpc);
5105
5106 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5107 bpc, display_bpc);
5108
5109 *pipe_bpp = display_bpc * 3;
5110
5111 return display_bpc != bpc;
5112}
5113
5114static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5115{
5116 struct drm_device *dev = crtc->dev;
5117 struct drm_i915_private *dev_priv = dev->dev_private;
5118 int refclk;
5119
5120 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5121 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5122 refclk = dev_priv->lvds_ssc_freq * 1000;
5123 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5124 refclk / 1000);
5125 } else if (!IS_GEN2(dev)) {
5126 refclk = 96000;
5127 } else {
5128 refclk = 48000;
5129 }
5130
5131 return refclk;
5132}
5133
5134static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5135 intel_clock_t *clock)
5136{
5137 /* SDVO TV has fixed PLL values depend on its clock range,
5138 this mirrors vbios setting. */
5139 if (adjusted_mode->clock >= 100000
5140 && adjusted_mode->clock < 140500) {
5141 clock->p1 = 2;
5142 clock->p2 = 10;
5143 clock->n = 3;
5144 clock->m1 = 16;
5145 clock->m2 = 8;
5146 } else if (adjusted_mode->clock >= 140500
5147 && adjusted_mode->clock <= 200000) {
5148 clock->p1 = 1;
5149 clock->p2 = 10;
5150 clock->n = 6;
5151 clock->m1 = 12;
5152 clock->m2 = 8;
5153 }
5154}
5155
5156static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5157 intel_clock_t *clock,
5158 intel_clock_t *reduced_clock)
5159{
5160 struct drm_device *dev = crtc->dev;
5161 struct drm_i915_private *dev_priv = dev->dev_private;
5162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5163 int pipe = intel_crtc->pipe;
5164 u32 fp, fp2 = 0;
5165
5166 if (IS_PINEVIEW(dev)) {
5167 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5168 if (reduced_clock)
5169 fp2 = (1 << reduced_clock->n) << 16 |
5170 reduced_clock->m1 << 8 | reduced_clock->m2;
5171 } else {
5172 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5173 if (reduced_clock)
5174 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5175 reduced_clock->m2;
5176 }
5177
5178 I915_WRITE(FP0(pipe), fp);
5179
5180 intel_crtc->lowfreq_avail = false;
5181 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5182 reduced_clock && i915_powersave) {
5183 I915_WRITE(FP1(pipe), fp2);
5184 intel_crtc->lowfreq_avail = true;
5185 } else {
5186 I915_WRITE(FP1(pipe), fp);
5187 }
5188}
5189
5190static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5191 struct drm_display_mode *mode,
5192 struct drm_display_mode *adjusted_mode,
5193 int x, int y,
5194 struct drm_framebuffer *old_fb)
5195{
5196 struct drm_device *dev = crtc->dev;
5197 struct drm_i915_private *dev_priv = dev->dev_private;
5198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5199 int pipe = intel_crtc->pipe;
5200 int plane = intel_crtc->plane;
5201 int refclk, num_connectors = 0;
5202 intel_clock_t clock, reduced_clock;
5203 u32 dpll, dspcntr, pipeconf, vsyncshift;
5204 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5205 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5206 struct drm_mode_config *mode_config = &dev->mode_config;
5207 struct intel_encoder *encoder;
5208 const intel_limit_t *limit;
5209 int ret;
5210 u32 temp;
5211 u32 lvds_sync = 0;
5212
5213 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5214 if (encoder->base.crtc != crtc)
5215 continue;
5216
5217 switch (encoder->type) {
5218 case INTEL_OUTPUT_LVDS:
5219 is_lvds = true;
5220 break;
5221 case INTEL_OUTPUT_SDVO:
5222 case INTEL_OUTPUT_HDMI:
5223 is_sdvo = true;
5224 if (encoder->needs_tv_clock)
5225 is_tv = true;
5226 break;
5227 case INTEL_OUTPUT_DVO:
5228 is_dvo = true;
5229 break;
5230 case INTEL_OUTPUT_TVOUT:
5231 is_tv = true;
5232 break;
5233 case INTEL_OUTPUT_ANALOG:
5234 is_crt = true;
5235 break;
5236 case INTEL_OUTPUT_DISPLAYPORT:
5237 is_dp = true;
5238 break;
5239 }
5240
5241 num_connectors++;
5242 }
5243
5244 refclk = i9xx_get_refclk(crtc, num_connectors);
5245
5246 /*
5247 * Returns a set of divisors for the desired target clock with the given
5248 * refclk, or false. The returned values represent the clock equation:
5249 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5250 */
5251 limit = intel_limit(crtc, refclk);
5252 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5253 &clock);
5254 if (!ok) {
5255 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5256 return -EINVAL;
5257 }
5258
5259 /* Ensure that the cursor is valid for the new mode before changing... */
5260 intel_crtc_update_cursor(crtc, true);
5261
5262 if (is_lvds && dev_priv->lvds_downclock_avail) {
5263 /*
5264 * Ensure we match the reduced clock's P to the target clock.
5265 * If the clocks don't match, we can't switch the display clock
5266 * by using the FP0/FP1. In such case we will disable the LVDS
5267 * downclock feature.
5268 */
5269 has_reduced_clock = limit->find_pll(limit, crtc,
5270 dev_priv->lvds_downclock,
5271 refclk,
5272 &clock,
5273 &reduced_clock);
5274 }
5275
5276 if (is_sdvo && is_tv)
5277 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5278
5279 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5280 &reduced_clock : NULL);
5281
5282 dpll = DPLL_VGA_MODE_DIS;
5283
5284 if (!IS_GEN2(dev)) {
5285 if (is_lvds)
5286 dpll |= DPLLB_MODE_LVDS;
5287 else
5288 dpll |= DPLLB_MODE_DAC_SERIAL;
5289 if (is_sdvo) {
5290 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5291 if (pixel_multiplier > 1) {
5292 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5293 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5294 }
5295 dpll |= DPLL_DVO_HIGH_SPEED;
5296 }
5297 if (is_dp)
5298 dpll |= DPLL_DVO_HIGH_SPEED;
5299
5300 /* compute bitmask from p1 value */
5301 if (IS_PINEVIEW(dev))
5302 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5303 else {
5304 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5305 if (IS_G4X(dev) && has_reduced_clock)
5306 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5307 }
5308 switch (clock.p2) {
5309 case 5:
5310 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5311 break;
5312 case 7:
5313 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5314 break;
5315 case 10:
5316 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5317 break;
5318 case 14:
5319 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5320 break;
5321 }
5322 if (INTEL_INFO(dev)->gen >= 4)
5323 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5324 } else {
5325 if (is_lvds) {
5326 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5327 } else {
5328 if (clock.p1 == 2)
5329 dpll |= PLL_P1_DIVIDE_BY_TWO;
5330 else
5331 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5332 if (clock.p2 == 4)
5333 dpll |= PLL_P2_DIVIDE_BY_4;
5334 }
5335 }
5336
5337 if (is_sdvo && is_tv)
5338 dpll |= PLL_REF_INPUT_TVCLKINBC;
5339 else if (is_tv)
5340 /* XXX: just matching BIOS for now */
5341 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5342 dpll |= 3;
5343 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5344 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5345 else
5346 dpll |= PLL_REF_INPUT_DREFCLK;
5347
5348 /* setup pipeconf */
5349 pipeconf = I915_READ(PIPECONF(pipe));
5350
5351 /* Set up the display plane register */
5352 dspcntr = DISPPLANE_GAMMA_ENABLE;
5353
5354 if (pipe == 0)
5355 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5356 else
5357 dspcntr |= DISPPLANE_SEL_PIPE_B;
5358
5359 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5360 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5361 * core speed.
5362 *
5363 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5364 * pipe == 0 check?
5365 */
5366 if (mode->clock >
5367 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5368 pipeconf |= PIPECONF_DOUBLE_WIDE;
5369 else
5370 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5371 }
5372
5373 /* default to 8bpc */
5374 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5375 if (is_dp) {
5376 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5377 pipeconf |= PIPECONF_BPP_6 |
5378 PIPECONF_DITHER_EN |
5379 PIPECONF_DITHER_TYPE_SP;
5380 }
5381 }
5382
5383 dpll |= DPLL_VCO_ENABLE;
5384
5385 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5386 drm_mode_debug_printmodeline(mode);
5387
5388 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5389
5390 POSTING_READ(DPLL(pipe));
5391 DELAY(150);
5392
5393 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5394 * This is an exception to the general rule that mode_set doesn't turn
5395 * things on.
5396 */
5397 if (is_lvds) {
5398 temp = I915_READ(LVDS);
5399 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5400 if (pipe == 1) {
5401 temp |= LVDS_PIPEB_SELECT;
5402 } else {
5403 temp &= ~LVDS_PIPEB_SELECT;
5404 }
5405 /* set the corresponsding LVDS_BORDER bit */
5406 temp |= dev_priv->lvds_border_bits;
5407 /* Set the B0-B3 data pairs corresponding to whether we're going to
5408 * set the DPLLs for dual-channel mode or not.
5409 */
5410 if (clock.p2 == 7)
5411 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5412 else
5413 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5414
5415 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5416 * appropriately here, but we need to look more thoroughly into how
5417 * panels behave in the two modes.
5418 */
5419 /* set the dithering flag on LVDS as needed */
5420 if (INTEL_INFO(dev)->gen >= 4) {
5421 if (dev_priv->lvds_dither)
5422 temp |= LVDS_ENABLE_DITHER;
5423 else
5424 temp &= ~LVDS_ENABLE_DITHER;
5425 }
5426 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5427 lvds_sync |= LVDS_HSYNC_POLARITY;
5428 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5429 lvds_sync |= LVDS_VSYNC_POLARITY;
5430 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5431 != lvds_sync) {
5432 char flags[2] = "-+";
5433 DRM_INFO("Changing LVDS panel from "
5434 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5435 flags[!(temp & LVDS_HSYNC_POLARITY)],
5436 flags[!(temp & LVDS_VSYNC_POLARITY)],
5437 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5438 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5439 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5440 temp |= lvds_sync;
5441 }
5442 I915_WRITE(LVDS, temp);
5443 }
5444
5445 if (is_dp) {
5446 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5447 }
5448
5449 I915_WRITE(DPLL(pipe), dpll);
5450
5451 /* Wait for the clocks to stabilize. */
5452 POSTING_READ(DPLL(pipe));
5453 DELAY(150);
5454
5455 if (INTEL_INFO(dev)->gen >= 4) {
5456 temp = 0;
5457 if (is_sdvo) {
5458 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5459 if (temp > 1)
5460 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5461 else
5462 temp = 0;
5463 }
5464 I915_WRITE(DPLL_MD(pipe), temp);
5465 } else {
5466 /* The pixel multiplier can only be updated once the
5467 * DPLL is enabled and the clocks are stable.
5468 *
5469 * So write it again.
5470 */
5471 I915_WRITE(DPLL(pipe), dpll);
5472 }
5473
5474 if (HAS_PIPE_CXSR(dev)) {
5475 if (intel_crtc->lowfreq_avail) {
5476 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5477 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5478 } else {
5479 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5480 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5481 }
5482 }
5483
5484 pipeconf &= ~PIPECONF_INTERLACE_MASK;
5485 if (!IS_GEN2(dev) &&
5486 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5487 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5488 /* the chip adds 2 halflines automatically */
5489 adjusted_mode->crtc_vtotal -= 1;
5490 adjusted_mode->crtc_vblank_end -= 1;
5491 vsyncshift = adjusted_mode->crtc_hsync_start
5492 - adjusted_mode->crtc_htotal/2;
5493 } else {
5494 pipeconf |= PIPECONF_PROGRESSIVE;
5495 vsyncshift = 0;
5496 }
5497
5498 if (!IS_GEN3(dev))
5499 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5500
5501 I915_WRITE(HTOTAL(pipe),
5502 (adjusted_mode->crtc_hdisplay - 1) |
5503 ((adjusted_mode->crtc_htotal - 1) << 16));
5504 I915_WRITE(HBLANK(pipe),
5505 (adjusted_mode->crtc_hblank_start - 1) |
5506 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5507 I915_WRITE(HSYNC(pipe),
5508 (adjusted_mode->crtc_hsync_start - 1) |
5509 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5510
5511 I915_WRITE(VTOTAL(pipe),
5512 (adjusted_mode->crtc_vdisplay - 1) |
5513 ((adjusted_mode->crtc_vtotal - 1) << 16));
5514 I915_WRITE(VBLANK(pipe),
5515 (adjusted_mode->crtc_vblank_start - 1) |
5516 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5517 I915_WRITE(VSYNC(pipe),
5518 (adjusted_mode->crtc_vsync_start - 1) |
5519 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5520
5521 /* pipesrc and dspsize control the size that is scaled from,
5522 * which should always be the user's requested size.
5523 */
5524 I915_WRITE(DSPSIZE(plane),
5525 ((mode->vdisplay - 1) << 16) |
5526 (mode->hdisplay - 1));
5527 I915_WRITE(DSPPOS(plane), 0);
5528 I915_WRITE(PIPESRC(pipe),
5529 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5530
5531 I915_WRITE(PIPECONF(pipe), pipeconf);
5532 POSTING_READ(PIPECONF(pipe));
5533 intel_enable_pipe(dev_priv, pipe, false);
5534
5535 intel_wait_for_vblank(dev, pipe);
5536
5537 I915_WRITE(DSPCNTR(plane), dspcntr);
5538 POSTING_READ(DSPCNTR(plane));
5539 intel_enable_plane(dev_priv, plane, pipe);
5540
5541 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5542
5543 intel_update_watermarks(dev);
5544
5545 return ret;
5546}
5547
5548/*
5549 * Initialize reference clocks when the driver loads
5550 */
5551void ironlake_init_pch_refclk(struct drm_device *dev)
5552{
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 struct drm_mode_config *mode_config = &dev->mode_config;
5555 struct intel_encoder *encoder;
5556 u32 temp;
5557 bool has_lvds = false;
5558 bool has_cpu_edp = false;
5559 bool has_pch_edp = false;
5560 bool has_panel = false;
5561 bool has_ck505 = false;
5562 bool can_ssc = false;
5563
5564 /* We need to take the global config into account */
5565 list_for_each_entry(encoder, &mode_config->encoder_list,
5566 base.head) {
5567 switch (encoder->type) {
5568 case INTEL_OUTPUT_LVDS:
5569 has_panel = true;
5570 has_lvds = true;
5571 break;
5572 case INTEL_OUTPUT_EDP:
5573 has_panel = true;
5574 if (intel_encoder_is_pch_edp(&encoder->base))
5575 has_pch_edp = true;
5576 else
5577 has_cpu_edp = true;
5578 break;
5579 }
5580 }
5581
5582 if (HAS_PCH_IBX(dev)) {
5583 has_ck505 = dev_priv->display_clock_mode;
5584 can_ssc = has_ck505;
5585 } else {
5586 has_ck505 = false;
5587 can_ssc = true;
5588 }
5589
5590 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5591 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5592 has_ck505);
5593
5594 /* Ironlake: try to setup display ref clock before DPLL
5595 * enabling. This is only under driver's control after
5596 * PCH B stepping, previous chipset stepping should be
5597 * ignoring this setting.
5598 */
5599 temp = I915_READ(PCH_DREF_CONTROL);
5600 /* Always enable nonspread source */
5601 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5602
5603 if (has_ck505)
5604 temp |= DREF_NONSPREAD_CK505_ENABLE;
5605 else
5606 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5607
5608 if (has_panel) {
5609 temp &= ~DREF_SSC_SOURCE_MASK;
5610 temp |= DREF_SSC_SOURCE_ENABLE;
5611
5612 /* SSC must be turned on before enabling the CPU output */
5613 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5614 DRM_DEBUG_KMS("Using SSC on panel\n");
5615 temp |= DREF_SSC1_ENABLE;
5616 } else
5617 temp &= ~DREF_SSC1_ENABLE;
5618
5619 /* Get SSC going before enabling the outputs */
5620 I915_WRITE(PCH_DREF_CONTROL, temp);
5621 POSTING_READ(PCH_DREF_CONTROL);
5622 DELAY(200);
5623
5624 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5625
5626 /* Enable CPU source on CPU attached eDP */
5627 if (has_cpu_edp) {
5628 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5629 DRM_DEBUG_KMS("Using SSC on eDP\n");
5630 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5631 }
5632 else
5633 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5634 } else
5635 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5636
5637 I915_WRITE(PCH_DREF_CONTROL, temp);
5638 POSTING_READ(PCH_DREF_CONTROL);
5639 DELAY(200);
5640 } else {
5641 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5642
5643 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5644
5645 /* Turn off CPU output */
5646 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5647
5648 I915_WRITE(PCH_DREF_CONTROL, temp);
5649 POSTING_READ(PCH_DREF_CONTROL);
5650 DELAY(200);
5651
5652 /* Turn off the SSC source */
5653 temp &= ~DREF_SSC_SOURCE_MASK;
5654 temp |= DREF_SSC_SOURCE_DISABLE;
5655
5656 /* Turn off SSC1 */
5657 temp &= ~ DREF_SSC1_ENABLE;
5658
5659 I915_WRITE(PCH_DREF_CONTROL, temp);
5660 POSTING_READ(PCH_DREF_CONTROL);
5661 DELAY(200);
5662 }
5663}
5664
5665static int ironlake_get_refclk(struct drm_crtc *crtc)
5666{
5667 struct drm_device *dev = crtc->dev;
5668 struct drm_i915_private *dev_priv = dev->dev_private;
5669 struct intel_encoder *encoder;
5670 struct drm_mode_config *mode_config = &dev->mode_config;
5671 struct intel_encoder *edp_encoder = NULL;
5672 int num_connectors = 0;
5673 bool is_lvds = false;
5674
5675 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5676 if (encoder->base.crtc != crtc)
5677 continue;
5678
5679 switch (encoder->type) {
5680 case INTEL_OUTPUT_LVDS:
5681 is_lvds = true;
5682 break;
5683 case INTEL_OUTPUT_EDP:
5684 edp_encoder = encoder;
5685 break;
5686 }
5687 num_connectors++;
5688 }
5689
5690 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5691 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5692 dev_priv->lvds_ssc_freq);
5693 return dev_priv->lvds_ssc_freq * 1000;
5694 }
5695
5696 return 120000;
5697}
5698
5699static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5700 struct drm_display_mode *mode,
5701 struct drm_display_mode *adjusted_mode,
5702 int x, int y,
5703 struct drm_framebuffer *old_fb)
5704{
5705 struct drm_device *dev = crtc->dev;
5706 struct drm_i915_private *dev_priv = dev->dev_private;
5707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5708 int pipe = intel_crtc->pipe;
5709 int plane = intel_crtc->plane;
5710 int refclk, num_connectors = 0;
5711 intel_clock_t clock, reduced_clock;
5712 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5713 bool ok, has_reduced_clock = false, is_sdvo = false;
5714 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5715 struct intel_encoder *has_edp_encoder = NULL;
5716 struct drm_mode_config *mode_config = &dev->mode_config;
5717 struct intel_encoder *encoder;
5718 const intel_limit_t *limit;
5719 int ret;
5720 struct fdi_m_n m_n = {0};
5721 u32 temp;
5722 u32 lvds_sync = 0;
5723 int target_clock, pixel_multiplier, lane, link_bw, factor;
5724 unsigned int pipe_bpp;
5725 bool dither;
5726
5727 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5728 if (encoder->base.crtc != crtc)
5729 continue;
5730
5731 switch (encoder->type) {
5732 case INTEL_OUTPUT_LVDS:
5733 is_lvds = true;
5734 break;
5735 case INTEL_OUTPUT_SDVO:
5736 case INTEL_OUTPUT_HDMI:
5737 is_sdvo = true;
5738 if (encoder->needs_tv_clock)
5739 is_tv = true;
5740 break;
5741 case INTEL_OUTPUT_TVOUT:
5742 is_tv = true;
5743 break;
5744 case INTEL_OUTPUT_ANALOG:
5745 is_crt = true;
5746 break;
5747 case INTEL_OUTPUT_DISPLAYPORT:
5748 is_dp = true;
5749 break;
5750 case INTEL_OUTPUT_EDP:
5751 has_edp_encoder = encoder;
5752 break;
5753 }
5754
5755 num_connectors++;
5756 }
5757
5758 refclk = ironlake_get_refclk(crtc);
5759
5760 /*
5761 * Returns a set of divisors for the desired target clock with the given
5762 * refclk, or false. The returned values represent the clock equation:
5763 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5764 */
5765 limit = intel_limit(crtc, refclk);
5766 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5767 &clock);
5768 if (!ok) {
5769 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5770 return -EINVAL;
5771 }
5772
5773 /* Ensure that the cursor is valid for the new mode before changing... */
5774 intel_crtc_update_cursor(crtc, true);
5775
5776 if (is_lvds && dev_priv->lvds_downclock_avail) {
5777 /*
5778 * Ensure we match the reduced clock's P to the target clock.
5779 * If the clocks don't match, we can't switch the display clock
5780 * by using the FP0/FP1. In such case we will disable the LVDS
5781 * downclock feature.
5782 */
5783 has_reduced_clock = limit->find_pll(limit, crtc,
5784 dev_priv->lvds_downclock,
5785 refclk,
5786 &clock,
5787 &reduced_clock);
5788 }
5789 /* SDVO TV has fixed PLL values depend on its clock range,
5790 this mirrors vbios setting. */
5791 if (is_sdvo && is_tv) {
5792 if (adjusted_mode->clock >= 100000
5793 && adjusted_mode->clock < 140500) {
5794 clock.p1 = 2;
5795 clock.p2 = 10;
5796 clock.n = 3;
5797 clock.m1 = 16;
5798 clock.m2 = 8;
5799 } else if (adjusted_mode->clock >= 140500
5800 && adjusted_mode->clock <= 200000) {
5801 clock.p1 = 1;
5802 clock.p2 = 10;
5803 clock.n = 6;
5804 clock.m1 = 12;
5805 clock.m2 = 8;
5806 }
5807 }
5808
5809 /* FDI link */
5810 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5811 lane = 0;
5812 /* CPU eDP doesn't require FDI link, so just set DP M/N
5813 according to current link config */
5814 if (has_edp_encoder &&
5815 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5816 target_clock = mode->clock;
5817 intel_edp_link_config(has_edp_encoder,
5818 &lane, &link_bw);
5819 } else {
5820 /* [e]DP over FDI requires target mode clock
5821 instead of link clock */
5822 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5823 target_clock = mode->clock;
5824 else
5825 target_clock = adjusted_mode->clock;
5826
5827 /* FDI is a binary signal running at ~2.7GHz, encoding
5828 * each output octet as 10 bits. The actual frequency
5829 * is stored as a divider into a 100MHz clock, and the
5830 * mode pixel clock is stored in units of 1KHz.
5831 * Hence the bw of each lane in terms of the mode signal
5832 * is:
5833 */
5834 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5835 }
5836
5837 /* determine panel color depth */
5838 temp = I915_READ(PIPECONF(pipe));
5839 temp &= ~PIPE_BPC_MASK;
5840 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5841 switch (pipe_bpp) {
5842 case 18:
5843 temp |= PIPE_6BPC;
5844 break;
5845 case 24:
5846 temp |= PIPE_8BPC;
5847 break;
5848 case 30:
5849 temp |= PIPE_10BPC;
5850 break;
5851 case 36:
5852 temp |= PIPE_12BPC;
5853 break;
5854 default:
5855 printf("intel_choose_pipe_bpp returned invalid value %d\n",
5856 pipe_bpp);
5857 temp |= PIPE_8BPC;
5858 pipe_bpp = 24;
5859 break;
5860 }
5861
5862 intel_crtc->bpp = pipe_bpp;
5863 I915_WRITE(PIPECONF(pipe), temp);
5864
5865 if (!lane) {
5866 /*
5867 * Account for spread spectrum to avoid
5868 * oversubscribing the link. Max center spread
5869 * is 2.5%; use 5% for safety's sake.
5870 */
5871 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5872 lane = bps / (link_bw * 8) + 1;
5873 }
5874
5875 intel_crtc->fdi_lanes = lane;
5876
5877 if (pixel_multiplier > 1)
5878 link_bw *= pixel_multiplier;
5879 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5880 &m_n);
5881
5882 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5883 if (has_reduced_clock)
5884 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5885 reduced_clock.m2;
5886
5887 /* Enable autotuning of the PLL clock (if permissible) */
5888 factor = 21;
5889 if (is_lvds) {
5890 if ((intel_panel_use_ssc(dev_priv) &&
5891 dev_priv->lvds_ssc_freq == 100) ||
5892 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5893 factor = 25;
5894 } else if (is_sdvo && is_tv)
5895 factor = 20;
5896
5897 if (clock.m < factor * clock.n)
5898 fp |= FP_CB_TUNE;
5899
5900 dpll = 0;
5901
5902 if (is_lvds)
5903 dpll |= DPLLB_MODE_LVDS;
5904 else
5905 dpll |= DPLLB_MODE_DAC_SERIAL;
5906 if (is_sdvo) {
5907 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5908 if (pixel_multiplier > 1) {
5909 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5910 }
5911 dpll |= DPLL_DVO_HIGH_SPEED;
5912 }
5913 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5914 dpll |= DPLL_DVO_HIGH_SPEED;
5915
5916 /* compute bitmask from p1 value */
5917 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5918 /* also FPA1 */
5919 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5920
5921 switch (clock.p2) {
5922 case 5:
5923 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5924 break;
5925 case 7:
5926 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5927 break;
5928 case 10:
5929 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5930 break;
5931 case 14:
5932 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5933 break;
5934 }
5935
5936 if (is_sdvo && is_tv)
5937 dpll |= PLL_REF_INPUT_TVCLKINBC;
5938 else if (is_tv)
5939 /* XXX: just matching BIOS for now */
5940 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5941 dpll |= 3;
5942 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5943 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5944 else
5945 dpll |= PLL_REF_INPUT_DREFCLK;
5946
5947 /* setup pipeconf */
5948 pipeconf = I915_READ(PIPECONF(pipe));
5949
5950 /* Set up the display plane register */
5951 dspcntr = DISPPLANE_GAMMA_ENABLE;
5952
5953 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5954 drm_mode_debug_printmodeline(mode);
5955
5956 /* PCH eDP needs FDI, but CPU eDP does not */
5957 if (!intel_crtc->no_pll) {
5958 if (!has_edp_encoder ||
5959 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5960 I915_WRITE(PCH_FP0(pipe), fp);
5961 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5962
5963 POSTING_READ(PCH_DPLL(pipe));
5964 DELAY(150);
5965 }
5966 } else {
5967 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5968 fp == I915_READ(PCH_FP0(0))) {
5969 intel_crtc->use_pll_a = true;
5970 DRM_DEBUG_KMS("using pipe a dpll\n");
5971 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5972 fp == I915_READ(PCH_FP0(1))) {
5973 intel_crtc->use_pll_a = false;
5974 DRM_DEBUG_KMS("using pipe b dpll\n");
5975 } else {
5976 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5977 return -EINVAL;
5978 }
5979 }
5980
5981 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5982 * This is an exception to the general rule that mode_set doesn't turn
5983 * things on.
5984 */
5985 if (is_lvds) {
5986 temp = I915_READ(PCH_LVDS);
5987 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5988 if (HAS_PCH_CPT(dev)) {
5989 temp &= ~PORT_TRANS_SEL_MASK;
5990 temp |= PORT_TRANS_SEL_CPT(pipe);
5991 } else {
5992 if (pipe == 1)
5993 temp |= LVDS_PIPEB_SELECT;
5994 else
5995 temp &= ~LVDS_PIPEB_SELECT;
5996 }
5997
5998 /* set the corresponsding LVDS_BORDER bit */
5999 temp |= dev_priv->lvds_border_bits;
6000 /* Set the B0-B3 data pairs corresponding to whether we're going to
6001 * set the DPLLs for dual-channel mode or not.
6002 */
6003 if (clock.p2 == 7)
6004 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
6005 else
6006 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
6007
6008 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
6009 * appropriately here, but we need to look more thoroughly into how
6010 * panels behave in the two modes.
6011 */
6012 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
6013 lvds_sync |= LVDS_HSYNC_POLARITY;
6014 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
6015 lvds_sync |= LVDS_VSYNC_POLARITY;
6016 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
6017 != lvds_sync) {
6018 char flags[2] = "-+";
6019 DRM_INFO("Changing LVDS panel from "
6020 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
6021 flags[!(temp & LVDS_HSYNC_POLARITY)],
6022 flags[!(temp & LVDS_VSYNC_POLARITY)],
6023 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
6024 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
6025 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
6026 temp |= lvds_sync;
6027 }
6028 I915_WRITE(PCH_LVDS, temp);
6029 }
6030
6031 pipeconf &= ~PIPECONF_DITHER_EN;
6032 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
6033 if ((is_lvds && dev_priv->lvds_dither) || dither) {
6034 pipeconf |= PIPECONF_DITHER_EN;
6035 pipeconf |= PIPECONF_DITHER_TYPE_SP;
6036 }
6037 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6038 intel_dp_set_m_n(crtc, mode, adjusted_mode);
6039 } else {
6040 /* For non-DP output, clear any trans DP clock recovery setting.*/
6041 I915_WRITE(TRANSDATA_M1(pipe), 0);
6042 I915_WRITE(TRANSDATA_N1(pipe), 0);
6043 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6044 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
6045 }
6046
6047 if (!intel_crtc->no_pll &&
6048 (!has_edp_encoder ||
6049 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6050 I915_WRITE(PCH_DPLL(pipe), dpll);
6051
6052 /* Wait for the clocks to stabilize. */
6053 POSTING_READ(PCH_DPLL(pipe));
6054 DELAY(150);
6055
6056 /* The pixel multiplier can only be updated once the
6057 * DPLL is enabled and the clocks are stable.
6058 *
6059 * So write it again.
6060 */
6061 I915_WRITE(PCH_DPLL(pipe), dpll);
6062 }
6063
6064 intel_crtc->lowfreq_avail = false;
6065 if (!intel_crtc->no_pll) {
6066 if (is_lvds && has_reduced_clock && i915_powersave) {
6067 I915_WRITE(PCH_FP1(pipe), fp2);
6068 intel_crtc->lowfreq_avail = true;
6069 if (HAS_PIPE_CXSR(dev)) {
6070 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6071 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6072 }
6073 } else {
6074 I915_WRITE(PCH_FP1(pipe), fp);
6075 if (HAS_PIPE_CXSR(dev)) {
6076 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6077 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6078 }
6079 }
6080 }
6081
6082 pipeconf &= ~PIPECONF_INTERLACE_MASK;
6083 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6084 pipeconf |= PIPECONF_INTERLACED_ILK;
6085 /* the chip adds 2 halflines automatically */
6086 adjusted_mode->crtc_vtotal -= 1;
6087 adjusted_mode->crtc_vblank_end -= 1;
6088 I915_WRITE(VSYNCSHIFT(pipe),
6089 adjusted_mode->crtc_hsync_start
6090 - adjusted_mode->crtc_htotal/2);
6091 } else {
6092 pipeconf |= PIPECONF_PROGRESSIVE;
6093 I915_WRITE(VSYNCSHIFT(pipe), 0);
6094 }
6095
6096 I915_WRITE(HTOTAL(pipe),
6097 (adjusted_mode->crtc_hdisplay - 1) |
6098 ((adjusted_mode->crtc_htotal - 1) << 16));
6099 I915_WRITE(HBLANK(pipe),
6100 (adjusted_mode->crtc_hblank_start - 1) |
6101 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6102 I915_WRITE(HSYNC(pipe),
6103 (adjusted_mode->crtc_hsync_start - 1) |
6104 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6105
6106 I915_WRITE(VTOTAL(pipe),
6107 (adjusted_mode->crtc_vdisplay - 1) |
6108 ((adjusted_mode->crtc_vtotal - 1) << 16));
6109 I915_WRITE(VBLANK(pipe),
6110 (adjusted_mode->crtc_vblank_start - 1) |
6111 ((adjusted_mode->crtc_vblank_end - 1) << 16));
6112 I915_WRITE(VSYNC(pipe),
6113 (adjusted_mode->crtc_vsync_start - 1) |
6114 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6115
6116 /* pipesrc controls the size that is scaled from, which should
6117 * always be the user's requested size.
6118 */
6119 I915_WRITE(PIPESRC(pipe),
6120 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6121
6122 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6123 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6124 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6125 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6126
6127 if (has_edp_encoder &&
6128 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6129 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6130 }
6131
6132 I915_WRITE(PIPECONF(pipe), pipeconf);
6133 POSTING_READ(PIPECONF(pipe));
6134
6135 intel_wait_for_vblank(dev, pipe);
6136
6137 I915_WRITE(DSPCNTR(plane), dspcntr);
6138 POSTING_READ(DSPCNTR(plane));
6139
6140 ret = intel_pipe_set_base(crtc, x, y, old_fb);
6141
6142 intel_update_watermarks(dev);
6143
6144 return ret;
6145}
6146
6147static int intel_crtc_mode_set(struct drm_crtc *crtc,
6148 struct drm_display_mode *mode,
6149 struct drm_display_mode *adjusted_mode,
6150 int x, int y,
6151 struct drm_framebuffer *old_fb)
6152{
6153 struct drm_device *dev = crtc->dev;
6154 struct drm_i915_private *dev_priv = dev->dev_private;
6155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6156 int pipe = intel_crtc->pipe;
6157 int ret;
6158
6159 drm_vblank_pre_modeset(dev, pipe);
6160
6161 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6162 x, y, old_fb);
6163 drm_vblank_post_modeset(dev, pipe);
6164
6165 if (ret)
6166 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6167 else
6168 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6169
6170 return ret;
6171}
6172
6173static bool intel_eld_uptodate(struct drm_connector *connector,
6174 int reg_eldv, uint32_t bits_eldv,
6175 int reg_elda, uint32_t bits_elda,
6176 int reg_edid)
6177{
6178 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6179 uint8_t *eld = connector->eld;
6180 uint32_t i;
6181
6182 i = I915_READ(reg_eldv);
6183 i &= bits_eldv;
6184
6185 if (!eld[0])
6186 return !i;
6187
6188 if (!i)
6189 return false;
6190
6191 i = I915_READ(reg_elda);
6192 i &= ~bits_elda;
6193 I915_WRITE(reg_elda, i);
6194
6195 for (i = 0; i < eld[2]; i++)
6196 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6197 return false;
6198
6199 return true;
6200}
6201
6202static void g4x_write_eld(struct drm_connector *connector,
6203 struct drm_crtc *crtc)
6204{
6205 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6206 uint8_t *eld = connector->eld;
6207 uint32_t eldv;
6208 uint32_t len;
6209 uint32_t i;
6210
6211 i = I915_READ(G4X_AUD_VID_DID);
6212
6213 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6214 eldv = G4X_ELDV_DEVCL_DEVBLC;
6215 else
6216 eldv = G4X_ELDV_DEVCTG;
6217
6218 if (intel_eld_uptodate(connector,
6219 G4X_AUD_CNTL_ST, eldv,
6220 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6221 G4X_HDMIW_HDMIEDID))
6222 return;
6223
6224 i = I915_READ(G4X_AUD_CNTL_ST);
6225 i &= ~(eldv | G4X_ELD_ADDR);
6226 len = (i >> 9) & 0x1f; /* ELD buffer size */
6227 I915_WRITE(G4X_AUD_CNTL_ST, i);
6228
6229 if (!eld[0])
6230 return;
6231
6232 if (eld[2] < (uint8_t)len)
6233 len = eld[2];
6234 DRM_DEBUG_KMS("ELD size %d\n", len);
6235 for (i = 0; i < len; i++)
6236 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6237
6238 i = I915_READ(G4X_AUD_CNTL_ST);
6239 i |= eldv;
6240 I915_WRITE(G4X_AUD_CNTL_ST, i);
6241}
6242
6243static void ironlake_write_eld(struct drm_connector *connector,
6244 struct drm_crtc *crtc)
6245{
6246 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6247 uint8_t *eld = connector->eld;
6248 uint32_t eldv;
6249 uint32_t i;
6250 int len;
6251 int hdmiw_hdmiedid;
6252 int aud_config;
6253 int aud_cntl_st;
6254 int aud_cntrl_st2;
6255
6256 if (HAS_PCH_IBX(connector->dev)) {
6257 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6258 aud_config = IBX_AUD_CONFIG_A;
6259 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6260 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6261 } else {
6262 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6263 aud_config = CPT_AUD_CONFIG_A;
6264 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6265 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6266 }
6267
6268 i = to_intel_crtc(crtc)->pipe;
6269 hdmiw_hdmiedid += i * 0x100;
6270 aud_cntl_st += i * 0x100;
6271 aud_config += i * 0x100;
6272
6273 DRM_DEBUG_KMS("ELD on pipe %c\n", pipe_name(i));
6274
6275 i = I915_READ(aud_cntl_st);
6276 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6277 if (!i) {
6278 DRM_DEBUG_KMS("Audio directed to unknown port\n");
6279 /* operate blindly on all ports */
6280 eldv = IBX_ELD_VALIDB;
6281 eldv |= IBX_ELD_VALIDB << 4;
6282 eldv |= IBX_ELD_VALIDB << 8;
6283 } else {
6284 DRM_DEBUG_KMS("ELD on port %c\n", 'A' + i);
6285 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6286 }
6287
6288 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6289 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6290 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6291 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6292 } else
6293 I915_WRITE(aud_config, 0);
6294
6295 if (intel_eld_uptodate(connector,
6296 aud_cntrl_st2, eldv,
6297 aud_cntl_st, IBX_ELD_ADDRESS,
6298 hdmiw_hdmiedid))
6299 return;
6300
6301 i = I915_READ(aud_cntrl_st2);
6302 i &= ~eldv;
6303 I915_WRITE(aud_cntrl_st2, i);
6304
6305 if (!eld[0])
6306 return;
6307
6308 i = I915_READ(aud_cntl_st);
6309 i &= ~IBX_ELD_ADDRESS;
6310 I915_WRITE(aud_cntl_st, i);
6311
6312 /* 84 bytes of hw ELD buffer */
6313 len = 21;
6314 if (eld[2] < (uint8_t)len)
6315 len = eld[2];
6316 DRM_DEBUG_KMS("ELD size %d\n", len);
6317 for (i = 0; i < len; i++)
6318 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6319
6320 i = I915_READ(aud_cntrl_st2);
6321 i |= eldv;
6322 I915_WRITE(aud_cntrl_st2, i);
6323}
6324
6325void intel_write_eld(struct drm_encoder *encoder,
6326 struct drm_display_mode *mode)
6327{
6328 struct drm_crtc *crtc = encoder->crtc;
6329 struct drm_connector *connector;
6330 struct drm_device *dev = encoder->dev;
6331 struct drm_i915_private *dev_priv = dev->dev_private;
6332
6333 connector = drm_select_eld(encoder, mode);
6334 if (!connector)
6335 return;
6336
6337 DRM_DEBUG_KMS("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6338 connector->base.id,
6339 drm_get_connector_name(connector),
6340 connector->encoder->base.id,
6341 drm_get_encoder_name(connector->encoder));
6342
6343 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6344
6345 if (dev_priv->display.write_eld)
6346 dev_priv->display.write_eld(connector, crtc);
6347}
6348
6349/** Loads the palette/gamma unit for the CRTC with the prepared values */
6350void intel_crtc_load_lut(struct drm_crtc *crtc)
6351{
6352 struct drm_device *dev = crtc->dev;
6353 struct drm_i915_private *dev_priv = dev->dev_private;
6354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6355 int palreg = PALETTE(intel_crtc->pipe);
6356 int i;
6357
6358 /* The clocks have to be on to load the palette. */
6359 if (!crtc->enabled || !intel_crtc->active)
6360 return;
6361
6362 /* use legacy palette for Ironlake */
6363 if (HAS_PCH_SPLIT(dev))
6364 palreg = LGC_PALETTE(intel_crtc->pipe);
6365
6366 for (i = 0; i < 256; i++) {
6367 I915_WRITE(palreg + 4 * i,
6368 (intel_crtc->lut_r[i] << 16) |
6369 (intel_crtc->lut_g[i] << 8) |
6370 intel_crtc->lut_b[i]);
6371 }
6372}
6373
6374static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6375{
6376 struct drm_device *dev = crtc->dev;
6377 struct drm_i915_private *dev_priv = dev->dev_private;
6378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379 bool visible = base != 0;
6380 u32 cntl;
6381
6382 if (intel_crtc->cursor_visible == visible)
6383 return;
6384
6385 cntl = I915_READ(_CURACNTR);
6386 if (visible) {
6387 /* On these chipsets we can only modify the base whilst
6388 * the cursor is disabled.
6389 */
6390 I915_WRITE(_CURABASE, base);
6391
6392 cntl &= ~(CURSOR_FORMAT_MASK);
6393 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6394 cntl |= CURSOR_ENABLE |
6395 CURSOR_GAMMA_ENABLE |
6396 CURSOR_FORMAT_ARGB;
6397 } else
6398 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6399 I915_WRITE(_CURACNTR, cntl);
6400
6401 intel_crtc->cursor_visible = visible;
6402}
6403
6404static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6405{
6406 struct drm_device *dev = crtc->dev;
6407 struct drm_i915_private *dev_priv = dev->dev_private;
6408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6409 int pipe = intel_crtc->pipe;
6410 bool visible = base != 0;
6411
6412 if (intel_crtc->cursor_visible != visible) {
6413 uint32_t cntl = I915_READ(CURCNTR(pipe));
6414 if (base) {
6415 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6416 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6417 cntl |= pipe << 28; /* Connect to correct pipe */
6418 } else {
6419 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6420 cntl |= CURSOR_MODE_DISABLE;
6421 }
6422 I915_WRITE(CURCNTR(pipe), cntl);
6423
6424 intel_crtc->cursor_visible = visible;
6425 }
6426 /* and commit changes on next vblank */
6427 I915_WRITE(CURBASE(pipe), base);
6428}
6429
6430static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6431{
6432 struct drm_device *dev = crtc->dev;
6433 struct drm_i915_private *dev_priv = dev->dev_private;
6434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6435 int pipe = intel_crtc->pipe;
6436 bool visible = base != 0;
6437
6438 if (intel_crtc->cursor_visible != visible) {
6439 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6440 if (base) {
6441 cntl &= ~CURSOR_MODE;
6442 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6443 } else {
6444 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6445 cntl |= CURSOR_MODE_DISABLE;
6446 }
6447 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6448
6449 intel_crtc->cursor_visible = visible;
6450 }
6451 /* and commit changes on next vblank */
6452 I915_WRITE(CURBASE_IVB(pipe), base);
6453}
6454
6455/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6456static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6457 bool on)
6458{
6459 struct drm_device *dev = crtc->dev;
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6462 int pipe = intel_crtc->pipe;
6463 int x = intel_crtc->cursor_x;
6464 int y = intel_crtc->cursor_y;
6465 u32 base, pos;
6466 bool visible;
6467
6468 pos = 0;
6469
6470 if (on && crtc->enabled && crtc->fb) {
6471 base = intel_crtc->cursor_addr;
6472 if (x > (int) crtc->fb->width)
6473 base = 0;
6474
6475 if (y > (int) crtc->fb->height)
6476 base = 0;
6477 } else
6478 base = 0;
6479
6480 if (x < 0) {
6481 if (x + intel_crtc->cursor_width < 0)
6482 base = 0;
6483
6484 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6485 x = -x;
6486 }
6487 pos |= x << CURSOR_X_SHIFT;
6488
6489 if (y < 0) {
6490 if (y + intel_crtc->cursor_height < 0)
6491 base = 0;
6492
6493 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6494 y = -y;
6495 }
6496 pos |= y << CURSOR_Y_SHIFT;
6497
6498 visible = base != 0;
6499 if (!visible && !intel_crtc->cursor_visible)
6500 return;
6501
6502 if (IS_IVYBRIDGE(dev)) {
6503 I915_WRITE(CURPOS_IVB(pipe), pos);
6504 ivb_update_cursor(crtc, base);
6505 } else {
6506 I915_WRITE(CURPOS(pipe), pos);
6507 if (IS_845G(dev) || IS_I865G(dev))
6508 i845_update_cursor(crtc, base);
6509 else
6510 i9xx_update_cursor(crtc, base);
6511 }
6512
6513 if (visible)
6514 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6515}
6516
6517static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6518 struct drm_file *file,
6519 uint32_t handle,
6520 uint32_t width, uint32_t height)
6521{
6522 struct drm_device *dev = crtc->dev;
6523 struct drm_i915_private *dev_priv = dev->dev_private;
6524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6525 struct drm_i915_gem_object *obj;
6526 uint32_t addr;
6527 int ret;
6528
6529 DRM_DEBUG_KMS("\n");
6530
6531 /* if we want to turn off the cursor ignore width and height */
6532 if (!handle) {
6533 DRM_DEBUG_KMS("cursor off\n");
6534 addr = 0;
6535 obj = NULL;
6536 DRM_LOCK(dev);
6537 goto finish;
6538 }
6539
6540 /* Currently we only support 64x64 cursors */
6541 if (width != 64 || height != 64) {
6542 DRM_ERROR("we currently only support 64x64 cursors\n");
6543 return -EINVAL;
6544 }
6545
6546 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6547 if (&obj->base == NULL)
6548 return -ENOENT;
6549
6550 if (obj->base.size < width * height * 4) {
6551 DRM_ERROR("buffer is to small\n");
6552 ret = -ENOMEM;
6553 goto fail;
6554 }
6555
6556 /* we only need to pin inside GTT if cursor is non-phy */
6557 DRM_LOCK(dev);
6558 if (!dev_priv->info->cursor_needs_physical) {
6559 if (obj->tiling_mode) {
6560 DRM_ERROR("cursor cannot be tiled\n");
6561 ret = -EINVAL;
6562 goto fail_locked;
6563 }
6564
6565 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6566 if (ret) {
6567 DRM_ERROR("failed to move cursor bo into the GTT\n");
6568 goto fail_locked;
6569 }
6570
6571 ret = i915_gem_object_put_fence(obj);
6572 if (ret) {
6573 DRM_ERROR("failed to release fence for cursor\n");
6574 goto fail_unpin;
6575 }
6576
6577 addr = obj->gtt_offset;
6578 } else {
6579 int align = IS_I830(dev) ? 16 * 1024 : 256;
6580 ret = i915_gem_attach_phys_object(dev, obj,
6581 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6582 align);
6583 if (ret) {
6584 DRM_ERROR("failed to attach phys object\n");
6585 goto fail_locked;
6586 }
6587 addr = obj->phys_obj->handle->busaddr;
6588 }
6589
6590 if (IS_GEN2(dev))
6591 I915_WRITE(CURSIZE, (height << 12) | width);
6592
6593 finish:
6594 if (intel_crtc->cursor_bo) {
6595 if (dev_priv->info->cursor_needs_physical) {
6596 if (intel_crtc->cursor_bo != obj)
6597 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6598 } else
6599 i915_gem_object_unpin(intel_crtc->cursor_bo);
6600 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6601 }
6602
6603 DRM_UNLOCK(dev);
6604
6605 intel_crtc->cursor_addr = addr;
6606 intel_crtc->cursor_bo = obj;
6607 intel_crtc->cursor_width = width;
6608 intel_crtc->cursor_height = height;
6609
6610 intel_crtc_update_cursor(crtc, true);
6611
6612 return 0;
6613fail_unpin:
6614 i915_gem_object_unpin(obj);
6615fail_locked:
6616 DRM_UNLOCK(dev);
6617fail:
6618 drm_gem_object_unreference_unlocked(&obj->base);
6619 return ret;
6620}
6621
6622static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6623{
6624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6625
6626 intel_crtc->cursor_x = x;
6627 intel_crtc->cursor_y = y;
6628
6629 intel_crtc_update_cursor(crtc, true);
6630
6631 return 0;
6632}
6633
6634/** Sets the color ramps on behalf of RandR */
6635void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6636 u16 blue, int regno)
6637{
6638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6639
6640 intel_crtc->lut_r[regno] = red >> 8;
6641 intel_crtc->lut_g[regno] = green >> 8;
6642 intel_crtc->lut_b[regno] = blue >> 8;
6643}
6644
6645void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6646 u16 *blue, int regno)
6647{
6648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649
6650 *red = intel_crtc->lut_r[regno] << 8;
6651 *green = intel_crtc->lut_g[regno] << 8;
6652 *blue = intel_crtc->lut_b[regno] << 8;
6653}
6654
6655static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6656 u16 *blue, uint32_t start, uint32_t size)
6657{
6658 int end = (start + size > 256) ? 256 : start + size, i;
6659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6660
6661 for (i = start; i < end; i++) {
6662 intel_crtc->lut_r[i] = red[i] >> 8;
6663 intel_crtc->lut_g[i] = green[i] >> 8;
6664 intel_crtc->lut_b[i] = blue[i] >> 8;
6665 }
6666
6667 intel_crtc_load_lut(crtc);
6668}
6669
6670/**
6671 * Get a pipe with a simple mode set on it for doing load-based monitor
6672 * detection.
6673 *
6674 * It will be up to the load-detect code to adjust the pipe as appropriate for
6675 * its requirements. The pipe will be connected to no other encoders.
6676 *
6677 * Currently this code will only succeed if there is a pipe with no encoders
6678 * configured for it. In the future, it could choose to temporarily disable
6679 * some outputs to free up a pipe for its use.
6680 *
6681 * \return crtc, or NULL if no pipes are available.
6682 */
6683
6684/* VESA 640x480x72Hz mode to set on the pipe */
6685static struct drm_display_mode load_detect_mode = {
6686 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6687 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6688};
6689
6690static int
6691intel_framebuffer_create(struct drm_device *dev,
6692 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_i915_gem_object *obj,
6693 struct drm_framebuffer **res)
6694{
6695 struct intel_framebuffer *intel_fb;
6696 int ret;
6697
6698 intel_fb = malloc(sizeof(*intel_fb), DRM_MEM_KMS, M_WAITOK | M_ZERO);
6699 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6700 if (ret) {
6701 drm_gem_object_unreference_unlocked(&obj->base);
6702 free(intel_fb, DRM_MEM_KMS);
6703 return (ret);
6704 }
6705
6706 *res = &intel_fb->base;
6707 return (0);
6708}
6709
6710static u32
6711intel_framebuffer_pitch_for_width(int width, int bpp)
6712{
6713 u32 pitch = howmany(width * bpp, 8);
6714 return roundup2(pitch, 64);
6715}
6716
6717static u32
6718intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6719{
6720 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6721 return roundup2(pitch * mode->vdisplay, PAGE_SIZE);
6722}
6723
6724static int
6725intel_framebuffer_create_for_mode(struct drm_device *dev,
6726 struct drm_display_mode *mode, int depth, int bpp,
6727 struct drm_framebuffer **res)
6728{
6729 struct drm_i915_gem_object *obj;
6730 struct drm_mode_fb_cmd2 mode_cmd;
6731
6732 obj = i915_gem_alloc_object(dev,
6733 intel_framebuffer_size_for_mode(mode, bpp));
6734 if (obj == NULL)
6735 return (-ENOMEM);
6736
6737 mode_cmd.width = mode->hdisplay;
6738 mode_cmd.height = mode->vdisplay;
6739 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6740 bpp);
6741 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6742
6743 return (intel_framebuffer_create(dev, &mode_cmd, obj, res));
6744}
6745
6746static int
6747mode_fits_in_fbdev(struct drm_device *dev,
6748 struct drm_display_mode *mode, struct drm_framebuffer **res)
6749{
6750 struct drm_i915_private *dev_priv = dev->dev_private;
6751 struct drm_i915_gem_object *obj;
6752 struct drm_framebuffer *fb;
6753
6754 if (dev_priv->fbdev == NULL) {
6755 *res = NULL;
6756 return (0);
6757 }
6758
6759 obj = dev_priv->fbdev->ifb.obj;
6760 if (obj == NULL) {
6761 *res = NULL;
6762 return (0);
6763 }
6764
6765 fb = &dev_priv->fbdev->ifb.base;
6766 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6767 fb->bits_per_pixel)) {
6768 *res = NULL;
6769 return (0);
6770 }
6771
6772 if (obj->base.size < mode->vdisplay * fb->pitches[0]) {
6773 *res = NULL;
6774 return (0);
6775 }
6776
6777 *res = fb;
6778 return (0);
6779}
6780
6781bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6782 struct drm_connector *connector,
6783 struct drm_display_mode *mode,
6784 struct intel_load_detect_pipe *old)
6785{
6786 struct intel_crtc *intel_crtc;
6787 struct drm_crtc *possible_crtc;
6788 struct drm_encoder *encoder = &intel_encoder->base;
6789 struct drm_crtc *crtc = NULL;
6790 struct drm_device *dev = encoder->dev;
6791 struct drm_framebuffer *old_fb;
6792 int i = -1, r;
6793
6794 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6795 connector->base.id, drm_get_connector_name(connector),
6796 encoder->base.id, drm_get_encoder_name(encoder));
6797
6798 /*
6799 * Algorithm gets a little messy:
6800 *
6801 * - if the connector already has an assigned crtc, use it (but make
6802 * sure it's on first)
6803 *
6804 * - try to find the first unused crtc that can drive this connector,
6805 * and use that if we find one
6806 */
6807
6808 /* See if we already have a CRTC for this connector */
6809 if (encoder->crtc) {
6810 crtc = encoder->crtc;
6811
6812 intel_crtc = to_intel_crtc(crtc);
6813 old->dpms_mode = intel_crtc->dpms_mode;
6814 old->load_detect_temp = false;
6815
6816 /* Make sure the crtc and connector are running */
6817 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6818 struct drm_encoder_helper_funcs *encoder_funcs;
6819 struct drm_crtc_helper_funcs *crtc_funcs;
6820
6821 crtc_funcs = crtc->helper_private;
6822 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6823
6824 encoder_funcs = encoder->helper_private;
6825 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6826 }
6827
6828 return true;
6829 }
6830
6831 /* Find an unused one (if possible) */
6832 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6833 i++;
6834 if (!(encoder->possible_crtcs & (1 << i)))
6835 continue;
6836 if (!possible_crtc->enabled) {
6837 crtc = possible_crtc;
6838 break;
6839 }
6840 }
6841
6842 /*
6843 * If we didn't find an unused CRTC, don't use any.
6844 */
6845 if (!crtc) {
6846 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6847 return false;
6848 }
6849
6850 encoder->crtc = crtc;
6851 connector->encoder = encoder;
6852
6853 intel_crtc = to_intel_crtc(crtc);
6854 old->dpms_mode = intel_crtc->dpms_mode;
6855 old->load_detect_temp = true;
6856 old->release_fb = NULL;
6857
6858 if (!mode)
6859 mode = &load_detect_mode;
6860
6861 old_fb = crtc->fb;
6862
6863 /* We need a framebuffer large enough to accommodate all accesses
6864 * that the plane may generate whilst we perform load detection.
6865 * We can not rely on the fbcon either being present (we get called
6866 * during its initialisation to detect all boot displays, or it may
6867 * not even exist) or that it is large enough to satisfy the
6868 * requested mode.
6869 */
6870 r = mode_fits_in_fbdev(dev, mode, &crtc->fb);
6871 if (crtc->fb == NULL) {
6872 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6873 r = intel_framebuffer_create_for_mode(dev, mode, 24, 32,
6874 &crtc->fb);
6875 old->release_fb = crtc->fb;
6876 } else
6877 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6878 if (r != 0) {
6879 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6880 crtc->fb = old_fb;
6881 return false;
6882 }
6883
6884 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6885 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6886 if (old->release_fb)
6887 old->release_fb->funcs->destroy(old->release_fb);
6888 crtc->fb = old_fb;
6889 return false;
6890 }
6891
6892 /* let the connector get through one full cycle before testing */
6893 intel_wait_for_vblank(dev, intel_crtc->pipe);
6894
6895 return true;
6896}
6897
6898void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6899 struct drm_connector *connector,
6900 struct intel_load_detect_pipe *old)
6901{
6902 struct drm_encoder *encoder = &intel_encoder->base;
6903 struct drm_device *dev = encoder->dev;
6904 struct drm_crtc *crtc = encoder->crtc;
6905 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6906 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6907
6908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6909 connector->base.id, drm_get_connector_name(connector),
6910 encoder->base.id, drm_get_encoder_name(encoder));
6911
6912 if (old->load_detect_temp) {
6913 connector->encoder = NULL;
6914 drm_helper_disable_unused_functions(dev);
6915
6916 if (old->release_fb)
6917 old->release_fb->funcs->destroy(old->release_fb);
6918
6919 return;
6920 }
6921
6922 /* Switch crtc and encoder back off if necessary */
6923 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6924 encoder_funcs->dpms(encoder, old->dpms_mode);
6925 crtc_funcs->dpms(crtc, old->dpms_mode);
6926 }
6927}
6928
6929/* Returns the clock of the currently programmed mode of the given pipe. */
6930static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6931{
6932 struct drm_i915_private *dev_priv = dev->dev_private;
6933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6934 int pipe = intel_crtc->pipe;
6935 u32 dpll = I915_READ(DPLL(pipe));
6936 u32 fp;
6937 intel_clock_t clock;
6938
6939 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6940 fp = I915_READ(FP0(pipe));
6941 else
6942 fp = I915_READ(FP1(pipe));
6943
6944 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6945 if (IS_PINEVIEW(dev)) {
6946 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6947 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6948 } else {
6949 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6950 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6951 }
6952
6953 if (!IS_GEN2(dev)) {
6954 if (IS_PINEVIEW(dev))
6955 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6956 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6957 else
6958 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6959 DPLL_FPA01_P1_POST_DIV_SHIFT);
6960
6961 switch (dpll & DPLL_MODE_MASK) {
6962 case DPLLB_MODE_DAC_SERIAL:
6963 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6964 5 : 10;
6965 break;
6966 case DPLLB_MODE_LVDS:
6967 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6968 7 : 14;
6969 break;
6970 default:
6971 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6972 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6973 return 0;
6974 }
6975
6976 /* XXX: Handle the 100Mhz refclk */
6977 intel_clock(dev, 96000, &clock);
6978 } else {
6979 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6980
6981 if (is_lvds) {
6982 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6983 DPLL_FPA01_P1_POST_DIV_SHIFT);
6984 clock.p2 = 14;
6985
6986 if ((dpll & PLL_REF_INPUT_MASK) ==
6987 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6988 /* XXX: might not be 66MHz */
6989 intel_clock(dev, 66000, &clock);
6990 } else
6991 intel_clock(dev, 48000, &clock);
6992 } else {
6993 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6994 clock.p1 = 2;
6995 else {
6996 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6997 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6998 }
6999 if (dpll & PLL_P2_DIVIDE_BY_4)
7000 clock.p2 = 4;
7001 else
7002 clock.p2 = 2;
7003
7004 intel_clock(dev, 48000, &clock);
7005 }
7006 }
7007
7008 /* XXX: It would be nice to validate the clocks, but we can't reuse
7009 * i830PllIsValid() because it relies on the xf86_config connector
7010 * configuration being accurate, which it isn't necessarily.
7011 */
7012
7013 return clock.dot;
7014}
7015
7016/** Returns the currently programmed mode of the given pipe. */
7017struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7018 struct drm_crtc *crtc)
7019{
7020 struct drm_i915_private *dev_priv = dev->dev_private;
7021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7022 int pipe = intel_crtc->pipe;
7023 struct drm_display_mode *mode;
7024 int htot = I915_READ(HTOTAL(pipe));
7025 int hsync = I915_READ(HSYNC(pipe));
7026 int vtot = I915_READ(VTOTAL(pipe));
7027 int vsync = I915_READ(VSYNC(pipe));
7028
7029 mode = malloc(sizeof(*mode), DRM_MEM_KMS, M_WAITOK | M_ZERO);
7030
7031 mode->clock = intel_crtc_clock_get(dev, crtc);
7032 mode->hdisplay = (htot & 0xffff) + 1;
7033 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7034 mode->hsync_start = (hsync & 0xffff) + 1;
7035 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7036 mode->vdisplay = (vtot & 0xffff) + 1;
7037 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7038 mode->vsync_start = (vsync & 0xffff) + 1;
7039 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7040
7041 drm_mode_set_name(mode);
7042 drm_mode_set_crtcinfo(mode, 0);
7043
7044 return mode;
7045}
7046
7047#define GPU_IDLE_TIMEOUT (500 /* ms */ * 1000 / hz)
7048
7049/* When this timer fires, we've been idle for awhile */
7050static void intel_gpu_idle_timer(void *arg)
7051{
7052 struct drm_device *dev = arg;
7053 drm_i915_private_t *dev_priv = dev->dev_private;
7054
7055 if (!list_empty(&dev_priv->mm.active_list)) {
7056 /* Still processing requests, so just re-arm the timer. */
7057 callout_schedule(&dev_priv->idle_callout, GPU_IDLE_TIMEOUT);
7058 return;
7059 }
7060
7061 dev_priv->busy = false;
7062 taskqueue_enqueue(dev_priv->tq, &dev_priv->idle_task);
7063}
7064
7065#define CRTC_IDLE_TIMEOUT (1000 /* ms */ * 1000 / hz)
7066
7067static void intel_crtc_idle_timer(void *arg)
7068{
7069 struct intel_crtc *intel_crtc = arg;
7070 struct drm_crtc *crtc = &intel_crtc->base;
7071 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
7072 struct intel_framebuffer *intel_fb;
7073
7074 intel_fb = to_intel_framebuffer(crtc->fb);
7075 if (intel_fb && intel_fb->obj->active) {
7076 /* The framebuffer is still being accessed by the GPU. */
7077 callout_schedule(&intel_crtc->idle_callout, CRTC_IDLE_TIMEOUT);
7078 return;
7079 }
7080
7081 intel_crtc->busy = false;
7082 taskqueue_enqueue(dev_priv->tq, &dev_priv->idle_task);
7083}
7084
7085static void intel_increase_pllclock(struct drm_crtc *crtc)
7086{
7087 struct drm_device *dev = crtc->dev;
7088 drm_i915_private_t *dev_priv = dev->dev_private;
7089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7090 int pipe = intel_crtc->pipe;
7091 int dpll_reg = DPLL(pipe);
7092 int dpll;
7093
7094 if (HAS_PCH_SPLIT(dev))
7095 return;
7096
7097 if (!dev_priv->lvds_downclock_avail)
7098 return;
7099
7100 dpll = I915_READ(dpll_reg);
7101 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7102 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7103
7104 assert_panel_unlocked(dev_priv, pipe);
7105
7106 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7107 I915_WRITE(dpll_reg, dpll);
7108 intel_wait_for_vblank(dev, pipe);
7109
7110 dpll = I915_READ(dpll_reg);
7111 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7112 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7113 }
7114
7115 /* Schedule downclock */
7116 callout_reset(&intel_crtc->idle_callout, CRTC_IDLE_TIMEOUT,
7117 intel_crtc_idle_timer, intel_crtc);
7118}
7119
7120static void intel_decrease_pllclock(struct drm_crtc *crtc)
7121{
7122 struct drm_device *dev = crtc->dev;
7123 drm_i915_private_t *dev_priv = dev->dev_private;
7124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7125
7126 if (HAS_PCH_SPLIT(dev))
7127 return;
7128
7129 if (!dev_priv->lvds_downclock_avail)
7130 return;
7131
7132 /*
7133 * Since this is called by a timer, we should never get here in
7134 * the manual case.
7135 */
7136 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7137 int pipe = intel_crtc->pipe;
7138 int dpll_reg = DPLL(pipe);
7139 u32 dpll;
7140
7141 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7142
7143 assert_panel_unlocked(dev_priv, pipe);
7144
7145 dpll = I915_READ(dpll_reg);
7146 dpll |= DISPLAY_RATE_SELECT_FPA1;
7147 I915_WRITE(dpll_reg, dpll);
7148 intel_wait_for_vblank(dev, pipe);
7149 dpll = I915_READ(dpll_reg);
7150 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7151 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7152 }
7153}
7154
7155/**
7156 * intel_idle_update - adjust clocks for idleness
7157 * @work: work struct
7158 *
7159 * Either the GPU or display (or both) went idle. Check the busy status
7160 * here and adjust the CRTC and GPU clocks as necessary.
7161 */
7162static void intel_idle_update(void *arg, int pending)
7163{
7164 drm_i915_private_t *dev_priv = arg;
7165 struct drm_device *dev = dev_priv->dev;
7166 struct drm_crtc *crtc;
7167 struct intel_crtc *intel_crtc;
7168
7169 if (!i915_powersave)
7170 return;
7171
7172 DRM_LOCK(dev);
7173
7174 i915_update_gfx_val(dev_priv);
7175
7176 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7177 /* Skip inactive CRTCs */
7178 if (!crtc->fb)
7179 continue;
7180
7181 intel_crtc = to_intel_crtc(crtc);
7182 if (!intel_crtc->busy)
7183 intel_decrease_pllclock(crtc);
7184 }
7185
7186 DRM_UNLOCK(dev);
7187}
7188
7189/**
7190 * intel_mark_busy - mark the GPU and possibly the display busy
7191 * @dev: drm device
7192 * @obj: object we're operating on
7193 *
7194 * Callers can use this function to indicate that the GPU is busy processing
7195 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7196 * buffer), we'll also mark the display as busy, so we know to increase its
7197 * clock frequency.
7198 */
7199void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7200{
7201 drm_i915_private_t *dev_priv = dev->dev_private;
7202 struct drm_crtc *crtc = NULL;
7203 struct intel_framebuffer *intel_fb;
7204 struct intel_crtc *intel_crtc;
7205
7206 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7207 return;
7208
7209 if (!dev_priv->busy)
7210 dev_priv->busy = true;
7211 else
7212 callout_reset(&dev_priv->idle_callout, GPU_IDLE_TIMEOUT,
7213 intel_gpu_idle_timer, dev);
7214
7215 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7216 if (!crtc->fb)
7217 continue;
7218
7219 intel_crtc = to_intel_crtc(crtc);
7220 intel_fb = to_intel_framebuffer(crtc->fb);
7221 if (intel_fb->obj == obj) {
7222 if (!intel_crtc->busy) {
7223 /* Non-busy -> busy, upclock */
7224 intel_increase_pllclock(crtc);
7225 intel_crtc->busy = true;
7226 } else {
7227 /* Busy -> busy, put off timer */
7228 callout_reset(&intel_crtc->idle_callout,
7229 CRTC_IDLE_TIMEOUT, intel_crtc_idle_timer,
7230 intel_crtc);
7231 }
7232 }
7233 }
7234}
7235
7236static void intel_crtc_destroy(struct drm_crtc *crtc)
7237{
7238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7239 struct drm_device *dev = crtc->dev;
7240 struct drm_i915_private *dev_priv = dev->dev_private;
7241 struct intel_unpin_work *work;
7242
7243 mtx_lock(&dev->event_lock);
7244 work = intel_crtc->unpin_work;
7245 intel_crtc->unpin_work = NULL;
7246 mtx_unlock(&dev->event_lock);
7247
7248 if (work) {
7249 taskqueue_cancel(dev_priv->tq, &work->task, NULL);
7250 taskqueue_drain(dev_priv->tq, &work->task);
7251 free(work, DRM_MEM_KMS);
7252 }
7253
7254 drm_crtc_cleanup(crtc);
7255
7256 free(intel_crtc, DRM_MEM_KMS);
7257}
7258
7259static void intel_unpin_work_fn(void *arg, int pending)
7260{
7261 struct intel_unpin_work *work = arg;
7262 struct drm_device *dev;
7263
7264 dev = work->dev;
7265 DRM_LOCK(dev);
7266 intel_unpin_fb_obj(work->old_fb_obj);
7267 drm_gem_object_unreference(&work->pending_flip_obj->base);
7268 drm_gem_object_unreference(&work->old_fb_obj->base);
7269
7270 intel_update_fbc(work->dev);
7271 DRM_UNLOCK(dev);
7272 free(work, DRM_MEM_KMS);
7273}
7274
7275static void do_intel_finish_page_flip(struct drm_device *dev,
7276 struct drm_crtc *crtc)
7277{
7278 drm_i915_private_t *dev_priv = dev->dev_private;
7279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7280 struct intel_unpin_work *work;
7281 struct drm_i915_gem_object *obj;
7282 struct drm_pending_vblank_event *e;
7283 struct timeval tnow, tvbl;
7284
7285 /* Ignore early vblank irqs */
7286 if (intel_crtc == NULL)
7287 return;
7288
7289 microtime(&tnow);
7290
7291 mtx_lock(&dev->event_lock);
7292 work = intel_crtc->unpin_work;
7293 if (work == NULL || !work->pending) {
7294 mtx_unlock(&dev->event_lock);
7295 return;
7296 }
7297
7298 intel_crtc->unpin_work = NULL;
7299
7300 if (work->event) {
7301 e = work->event;
7302 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7303
7304 /* Called before vblank count and timestamps have
7305 * been updated for the vblank interval of flip
7306 * completion? Need to increment vblank count and
7307 * add one videorefresh duration to returned timestamp
7308 * to account for this. We assume this happened if we
7309 * get called over 0.9 frame durations after the last
7310 * timestamped vblank.
7311 *
7312 * This calculation can not be used with vrefresh rates
7313 * below 5Hz (10Hz to be on the safe side) without
7314 * promoting to 64 integers.
7315 */
7316 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7317 9 * crtc->framedur_ns) {
7318 e->event.sequence++;
7319 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7320 crtc->framedur_ns);
7321 }
7322
7323 e->event.tv_sec = tvbl.tv_sec;
7324 e->event.tv_usec = tvbl.tv_usec;
7325
7326 list_add_tail(&e->base.link,
7327 &e->base.file_priv->event_list);
7328 drm_event_wakeup(&e->base);
7329 }
7330
7331 drm_vblank_put(dev, intel_crtc->pipe);
7332
7333 obj = work->old_fb_obj;
7334
7335 atomic_clear_int(&obj->pending_flip, 1 << intel_crtc->plane);
7336 if (atomic_read(&obj->pending_flip) == 0)
7337 wakeup(&obj->pending_flip);
7338 mtx_unlock(&dev->event_lock);
7339
7340 taskqueue_enqueue(dev_priv->tq, &work->task);
7341
7342 CTR2(KTR_DRM, "i915_flip_complete %d %p", intel_crtc->plane,
7343 work->pending_flip_obj);
7344}
7345
7346void intel_finish_page_flip(struct drm_device *dev, int pipe)
7347{
7348 drm_i915_private_t *dev_priv = dev->dev_private;
7349 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7350
7351 do_intel_finish_page_flip(dev, crtc);
7352}
7353
7354void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7355{
7356 drm_i915_private_t *dev_priv = dev->dev_private;
7357 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7358
7359 do_intel_finish_page_flip(dev, crtc);
7360}
7361
7362void intel_prepare_page_flip(struct drm_device *dev, int plane)
7363{
7364 drm_i915_private_t *dev_priv = dev->dev_private;
7365 struct intel_crtc *intel_crtc =
7366 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7367
7368 mtx_lock(&dev->event_lock);
7369 if (intel_crtc->unpin_work) {
7370 if ((++intel_crtc->unpin_work->pending) > 1)
7371 DRM_ERROR("Prepared flip multiple times\n");
7372 } else {
7373 DRM_DEBUG("preparing flip with no unpin work?\n");
7374 }
7375 mtx_unlock(&dev->event_lock);
7376}
7377
7378static int intel_gen2_queue_flip(struct drm_device *dev,
7379 struct drm_crtc *crtc,
7380 struct drm_framebuffer *fb,
7381 struct drm_i915_gem_object *obj)
7382{
7383 struct drm_i915_private *dev_priv = dev->dev_private;
7384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7385 unsigned long offset;
7386 u32 flip_mask;
7387 int ret;
7388
7389 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7390 if (ret)
7391 goto out;
7392
7393 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7394 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7395
7396 ret = BEGIN_LP_RING(6);
7397 if (ret)
7398 goto out;
7399
7400 /* Can't queue multiple flips, so wait for the previous
7401 * one to finish before executing the next.
7402 */
7403 if (intel_crtc->plane)
7404 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7405 else
7406 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7407 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7408 OUT_RING(MI_NOOP);
7409 OUT_RING(MI_DISPLAY_FLIP |
7410 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7411 OUT_RING(fb->pitches[0]);
7412 OUT_RING(obj->gtt_offset + offset);
7413 OUT_RING(0); /* aux display base address, unused */
7414 ADVANCE_LP_RING();
7415out:
7416 return ret;
7417}
7418
7419static int intel_gen3_queue_flip(struct drm_device *dev,
7420 struct drm_crtc *crtc,
7421 struct drm_framebuffer *fb,
7422 struct drm_i915_gem_object *obj)
7423{
7424 struct drm_i915_private *dev_priv = dev->dev_private;
7425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7426 unsigned long offset;
7427 u32 flip_mask;
7428 int ret;
7429
7430 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7431 if (ret)
7432 goto out;
7433
7434 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7435 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7436
7437 ret = BEGIN_LP_RING(6);
7438 if (ret)
7439 goto out;
7440
7441 if (intel_crtc->plane)
7442 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7443 else
7444 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7445 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7446 OUT_RING(MI_NOOP);
7447 OUT_RING(MI_DISPLAY_FLIP_I915 |
7448 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7449 OUT_RING(fb->pitches[0]);
7450 OUT_RING(obj->gtt_offset + offset);
7451 OUT_RING(MI_NOOP);
7452
7453 ADVANCE_LP_RING();
7454out:
7455 return ret;
7456}
7457
7458static int intel_gen4_queue_flip(struct drm_device *dev,
7459 struct drm_crtc *crtc,
7460 struct drm_framebuffer *fb,
7461 struct drm_i915_gem_object *obj)
7462{
7463 struct drm_i915_private *dev_priv = dev->dev_private;
7464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7465 uint32_t pf, pipesrc;
7466 int ret;
7467
7468 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7469 if (ret)
7470 goto out;
7471
7472 ret = BEGIN_LP_RING(4);
7473 if (ret)
7474 goto out;
7475
7476 /* i965+ uses the linear or tiled offsets from the
7477 * Display Registers (which do not change across a page-flip)
7478 * so we need only reprogram the base address.
7479 */
7480 OUT_RING(MI_DISPLAY_FLIP |
7481 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7482 OUT_RING(fb->pitches[0]);
7483 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7484
7485 /* XXX Enabling the panel-fitter across page-flip is so far
7486 * untested on non-native modes, so ignore it for now.
7487 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7488 */
7489 pf = 0;
7490 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7491 OUT_RING(pf | pipesrc);
7492 ADVANCE_LP_RING();
7493out:
7494 return ret;
7495}
7496
7497static int intel_gen6_queue_flip(struct drm_device *dev,
7498 struct drm_crtc *crtc,
7499 struct drm_framebuffer *fb,
7500 struct drm_i915_gem_object *obj)
7501{
7502 struct drm_i915_private *dev_priv = dev->dev_private;
7503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7504 uint32_t pf, pipesrc;
7505 int ret;
7506
7507 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7508 if (ret)
7509 goto out;
7510
7511 ret = BEGIN_LP_RING(4);
7512 if (ret)
7513 goto out;
7514
7515 OUT_RING(MI_DISPLAY_FLIP |
7516 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7517 OUT_RING(fb->pitches[0] | obj->tiling_mode);
7518 OUT_RING(obj->gtt_offset);
7519
7520 /* Contrary to the suggestions in the documentation,
7521 * "Enable Panel Fitter" does not seem to be required when page
7522 * flipping with a non-native mode, and worse causes a normal
7523 * modeset to fail.
7524 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7525 */
7526 pf = 0;
7527 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7528 OUT_RING(pf | pipesrc);
7529 ADVANCE_LP_RING();
7530out:
7531 return ret;
7532}
7533
7534/*
7535 * On gen7 we currently use the blit ring because (in early silicon at least)
7536 * the render ring doesn't give us interrpts for page flip completion, which
7537 * means clients will hang after the first flip is queued. Fortunately the
7538 * blit ring generates interrupts properly, so use it instead.
7539 */
7540static int intel_gen7_queue_flip(struct drm_device *dev,
7541 struct drm_crtc *crtc,
7542 struct drm_framebuffer *fb,
7543 struct drm_i915_gem_object *obj)
7544{
7545 struct drm_i915_private *dev_priv = dev->dev_private;
7546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7547 struct intel_ring_buffer *ring = &dev_priv->rings[BCS];
7548 int ret;
7549
7550 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7551 if (ret)
7552 goto out;
7553
7554 ret = intel_ring_begin(ring, 4);
7555 if (ret)
7556 goto out;
7557
7558 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7559 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7560 intel_ring_emit(ring, (obj->gtt_offset));
7561 intel_ring_emit(ring, (MI_NOOP));
7562 intel_ring_advance(ring);
7563out:
7564 return ret;
7565}
7566
7567static int intel_default_queue_flip(struct drm_device *dev,
7568 struct drm_crtc *crtc,
7569 struct drm_framebuffer *fb,
7570 struct drm_i915_gem_object *obj)
7571{
7572 return -ENODEV;
7573}
7574
7575static int intel_crtc_page_flip(struct drm_crtc *crtc,
7576 struct drm_framebuffer *fb,
7577 struct drm_pending_vblank_event *event)
7578{
7579 struct drm_device *dev = crtc->dev;
7580 struct drm_i915_private *dev_priv = dev->dev_private;
7581 struct intel_framebuffer *intel_fb;
7582 struct drm_i915_gem_object *obj;
7583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7584 struct intel_unpin_work *work;
7585 int ret;
7586
7587 work = malloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO);
7588
7589 work->event = event;
7590 work->dev = crtc->dev;
7591 intel_fb = to_intel_framebuffer(crtc->fb);
7592 work->old_fb_obj = intel_fb->obj;
7593 TASK_INIT(&work->task, 0, intel_unpin_work_fn, work);
7594
7595 ret = drm_vblank_get(dev, intel_crtc->pipe);
7596 if (ret)
7597 goto free_work;
7598
7599 /* We borrow the event spin lock for protecting unpin_work */
7600 mtx_lock(&dev->event_lock);
7601 if (intel_crtc->unpin_work) {
7602 mtx_unlock(&dev->event_lock);
7603 free(work, DRM_MEM_KMS);
7604 drm_vblank_put(dev, intel_crtc->pipe);
7605
7606 DRM_DEBUG("flip queue: crtc already busy\n");
7607 return -EBUSY;
7608 }
7609 intel_crtc->unpin_work = work;
7610 mtx_unlock(&dev->event_lock);
7611
7612 intel_fb = to_intel_framebuffer(fb);
7613 obj = intel_fb->obj;
7614
7615 DRM_LOCK(dev);
7616
7617 /* Reference the objects for the scheduled work. */
7618 drm_gem_object_reference(&work->old_fb_obj->base);
7619 drm_gem_object_reference(&obj->base);
7620
7621 crtc->fb = fb;
7622
7623 work->pending_flip_obj = obj;
7624
7625 work->enable_stall_check = true;
7626
7627 /* Block clients from rendering to the new back buffer until
7628 * the flip occurs and the object is no longer visible.
7629 */
7630 atomic_set_int(&work->old_fb_obj->pending_flip, 1 << intel_crtc->plane);
7631
7632 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7633 if (ret)
7634 goto cleanup_pending;
7635 intel_disable_fbc(dev);
7636 DRM_UNLOCK(dev);
7637
7638 CTR2(KTR_DRM, "i915_flip_request %d %p", intel_crtc->plane, obj);
7639
7640 return 0;
7641
7642cleanup_pending:
7643 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7644 drm_gem_object_unreference(&work->old_fb_obj->base);
7645 drm_gem_object_unreference(&obj->base);
7646 DRM_UNLOCK(dev);
7647
7648 mtx_lock(&dev->event_lock);
7649 intel_crtc->unpin_work = NULL;
7650 mtx_unlock(&dev->event_lock);
7651
7652 drm_vblank_put(dev, intel_crtc->pipe);
7653free_work:
7654 free(work, DRM_MEM_KMS);
7655
7656 return ret;
7657}
7658
7659static void intel_sanitize_modesetting(struct drm_device *dev,
7660 int pipe, int plane)
7661{
7662 struct drm_i915_private *dev_priv = dev->dev_private;
7663 u32 reg, val;
7664
7665 /* Clear any frame start delays used for debugging left by the BIOS */
7666 for_each_pipe(pipe) {
7667 reg = PIPECONF(pipe);
7668 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7669 }
7670
7671 if (HAS_PCH_SPLIT(dev))
7672 return;
7673
7674 /* Who knows what state these registers were left in by the BIOS or
7675 * grub?
7676 *
7677 * If we leave the registers in a conflicting state (e.g. with the
7678 * display plane reading from the other pipe than the one we intend
7679 * to use) then when we attempt to teardown the active mode, we will
7680 * not disable the pipes and planes in the correct order -- leaving
7681 * a plane reading from a disabled pipe and possibly leading to
7682 * undefined behaviour.
7683 */
7684
7685 reg = DSPCNTR(plane);
7686 val = I915_READ(reg);
7687
7688 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7689 return;
7690 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7691 return;
7692
7693 /* This display plane is active and attached to the other CPU pipe. */
7694 pipe = !pipe;
7695
7696 /* Disable the plane and wait for it to stop reading from the pipe. */
7697 intel_disable_plane(dev_priv, plane, pipe);
7698 intel_disable_pipe(dev_priv, pipe);
7699}
7700
7701static void intel_crtc_reset(struct drm_crtc *crtc)
7702{
7703 struct drm_device *dev = crtc->dev;
7704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7705
7706 /* Reset flags back to the 'unknown' status so that they
7707 * will be correctly set on the initial modeset.
7708 */
7709 intel_crtc->dpms_mode = -1;
7710
7711 /* We need to fix up any BIOS configuration that conflicts with
7712 * our expectations.
7713 */
7714 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7715}
7716
7717static struct drm_crtc_helper_funcs intel_helper_funcs = {
7718 .dpms = intel_crtc_dpms,
7719 .mode_fixup = intel_crtc_mode_fixup,
7720 .mode_set = intel_crtc_mode_set,
7721 .mode_set_base = intel_pipe_set_base,
7722 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7723 .load_lut = intel_crtc_load_lut,
7724 .disable = intel_crtc_disable,
7725};
7726
7727static const struct drm_crtc_funcs intel_crtc_funcs = {
7728 .reset = intel_crtc_reset,
7729 .cursor_set = intel_crtc_cursor_set,
7730 .cursor_move = intel_crtc_cursor_move,
7731 .gamma_set = intel_crtc_gamma_set,
7732 .set_config = drm_crtc_helper_set_config,
7733 .destroy = intel_crtc_destroy,
7734 .page_flip = intel_crtc_page_flip,
7735};
7736
7737static void intel_crtc_init(struct drm_device *dev, int pipe)
7738{
7739 drm_i915_private_t *dev_priv = dev->dev_private;
7740 struct intel_crtc *intel_crtc;
7741 int i;
7742
7743 intel_crtc = malloc(sizeof(struct intel_crtc) +
7744 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
7745 DRM_MEM_KMS, M_WAITOK | M_ZERO);
7746
7747 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7748
7749 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7750 for (i = 0; i < 256; i++) {
7751 intel_crtc->lut_r[i] = i;
7752 intel_crtc->lut_g[i] = i;
7753 intel_crtc->lut_b[i] = i;
7754 }
7755
7756 /* Swap pipes & planes for FBC on pre-965 */
7757 intel_crtc->pipe = pipe;
7758 intel_crtc->plane = pipe;
7759 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7760 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7761 intel_crtc->plane = !pipe;
7762 }
7763
7764 KASSERT(pipe < DRM_ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) &&
7765 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] == NULL,
7766 ("plane_to_crtc is already initialized"));
7767 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7768 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7769
7770 intel_crtc_reset(&intel_crtc->base);
7771 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7772 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7773
7774 if (HAS_PCH_SPLIT(dev)) {
7775 if (pipe == 2 && IS_IVYBRIDGE(dev))
7776 intel_crtc->no_pll = true;
7777 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7778 intel_helper_funcs.commit = ironlake_crtc_commit;
7779 } else {
7780 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7781 intel_helper_funcs.commit = i9xx_crtc_commit;
7782 }
7783
7784 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7785
7786 intel_crtc->busy = false;
7787
7788 callout_init(&intel_crtc->idle_callout, CALLOUT_MPSAFE);
7789}
7790
7791int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7792 struct drm_file *file)
7793{
7794 drm_i915_private_t *dev_priv = dev->dev_private;
7795 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7796 struct drm_mode_object *drmmode_obj;
7797 struct intel_crtc *crtc;
7798
7799 if (!dev_priv) {
7800 DRM_ERROR("called with no initialization\n");
7801 return -EINVAL;
7802 }
7803
7804 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7805 DRM_MODE_OBJECT_CRTC);
7806
7807 if (!drmmode_obj) {
7808 DRM_ERROR("no such CRTC id\n");
7809 return -EINVAL;
7810 }
7811
7812 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7813 pipe_from_crtc_id->pipe = crtc->pipe;
7814
7815 return 0;
7816}
7817
7818static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7819{
7820 struct intel_encoder *encoder;
7821 int index_mask = 0;
7822 int entry = 0;
7823
7824 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7825 if (type_mask & encoder->clone_mask)
7826 index_mask |= (1 << entry);
7827 entry++;
7828 }
7829
7830 return index_mask;
7831}
7832
7833static bool has_edp_a(struct drm_device *dev)
7834{
7835 struct drm_i915_private *dev_priv = dev->dev_private;
7836
7837 if (!IS_MOBILE(dev))
7838 return false;
7839
7840 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7841 return false;
7842
7843 if (IS_GEN5(dev) &&
7844 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7845 return false;
7846
7847 return true;
7848}
7849
7850static void intel_setup_outputs(struct drm_device *dev)
7851{
7852 struct drm_i915_private *dev_priv = dev->dev_private;
7853 struct intel_encoder *encoder;
7854 bool dpd_is_edp = false;
7855 bool has_lvds;
7856
7857 has_lvds = intel_lvds_init(dev);
7858 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7859 /* disable the panel fitter on everything but LVDS */
7860 I915_WRITE(PFIT_CONTROL, 0);
7861 }
7862
7863 if (HAS_PCH_SPLIT(dev)) {
7864 dpd_is_edp = intel_dpd_is_edp(dev);
7865
7866 if (has_edp_a(dev))
7867 intel_dp_init(dev, DP_A);
7868
7869 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7870 intel_dp_init(dev, PCH_DP_D);
7871 }
7872
7873 intel_crt_init(dev);
7874
7875 if (HAS_PCH_SPLIT(dev)) {
7876 int found;
7877
7878 DRM_DEBUG_KMS(
7879"HDMIB %d PCH_DP_B %d HDMIC %d HDMID %d PCH_DP_C %d PCH_DP_D %d LVDS %d\n",
7880 (I915_READ(HDMIB) & PORT_DETECTED) != 0,
7881 (I915_READ(PCH_DP_B) & DP_DETECTED) != 0,
7882 (I915_READ(HDMIC) & PORT_DETECTED) != 0,
7883 (I915_READ(HDMID) & PORT_DETECTED) != 0,
7884 (I915_READ(PCH_DP_C) & DP_DETECTED) != 0,
7885 (I915_READ(PCH_DP_D) & DP_DETECTED) != 0,
7886 (I915_READ(PCH_LVDS) & LVDS_DETECTED) != 0);
7887
7888 if (I915_READ(HDMIB) & PORT_DETECTED) {
7889 /* PCH SDVOB multiplex with HDMIB */
7890 found = intel_sdvo_init(dev, PCH_SDVOB);
7891 if (!found)
7892 intel_hdmi_init(dev, HDMIB);
7893 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7894 intel_dp_init(dev, PCH_DP_B);
7895 }
7896
7897 if (I915_READ(HDMIC) & PORT_DETECTED)
7898 intel_hdmi_init(dev, HDMIC);
7899
7900 if (I915_READ(HDMID) & PORT_DETECTED)
7901 intel_hdmi_init(dev, HDMID);
7902
7903 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7904 intel_dp_init(dev, PCH_DP_C);
7905
7906 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7907 intel_dp_init(dev, PCH_DP_D);
7908
7909 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7910 bool found = false;
7911
7912 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7913 DRM_DEBUG_KMS("probing SDVOB\n");
7914 found = intel_sdvo_init(dev, SDVOB);
7915 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7916 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7917 intel_hdmi_init(dev, SDVOB);
7918 }
7919
7920 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7921 DRM_DEBUG_KMS("probing DP_B\n");
7922 intel_dp_init(dev, DP_B);
7923 }
7924 }
7925
7926 /* Before G4X SDVOC doesn't have its own detect register */
7927
7928 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7929 DRM_DEBUG_KMS("probing SDVOC\n");
7930 found = intel_sdvo_init(dev, SDVOC);
7931 }
7932
7933 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7934
7935 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7936 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7937 intel_hdmi_init(dev, SDVOC);
7938 }
7939 if (SUPPORTS_INTEGRATED_DP(dev)) {
7940 DRM_DEBUG_KMS("probing DP_C\n");
7941 intel_dp_init(dev, DP_C);
7942 }
7943 }
7944
7945 if (SUPPORTS_INTEGRATED_DP(dev) &&
7946 (I915_READ(DP_D) & DP_DETECTED)) {
7947 DRM_DEBUG_KMS("probing DP_D\n");
7948 intel_dp_init(dev, DP_D);
7949 }
7950 } else if (IS_GEN2(dev)) {
7951#if 1
7952 KIB_NOTYET();
7953#else
7954 intel_dvo_init(dev);
7955#endif
7956 }
7957
7958 if (SUPPORTS_TV(dev))
7959 intel_tv_init(dev);
7960
7961 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7962 encoder->base.possible_crtcs = encoder->crtc_mask;
7963 encoder->base.possible_clones =
7964 intel_encoder_clones(dev, encoder->clone_mask);
7965 }
7966
7967 /* disable all the possible outputs/crtcs before entering KMS mode */
7968 drm_helper_disable_unused_functions(dev);
7969
7970 if (HAS_PCH_SPLIT(dev))
7971 ironlake_init_pch_refclk(dev);
7972}
7973
7974static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7975{
7976 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7977
7978 drm_framebuffer_cleanup(fb);
7979 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7980
7981 free(intel_fb, DRM_MEM_KMS);
7982}
7983
7984static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7985 struct drm_file *file,
7986 unsigned int *handle)
7987{
7988 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7989 struct drm_i915_gem_object *obj = intel_fb->obj;
7990
7991 return drm_gem_handle_create(file, &obj->base, handle);
7992}
7993
7994static const struct drm_framebuffer_funcs intel_fb_funcs = {
7995 .destroy = intel_user_framebuffer_destroy,
7996 .create_handle = intel_user_framebuffer_create_handle,
7997};
7998
7999int intel_framebuffer_init(struct drm_device *dev,
8000 struct intel_framebuffer *intel_fb,
8001 struct drm_mode_fb_cmd2 *mode_cmd,
8002 struct drm_i915_gem_object *obj)
8003{
8004 int ret;
8005
8006 if (obj->tiling_mode == I915_TILING_Y)
8007 return -EINVAL;
8008
8009 if (mode_cmd->pitches[0] & 63)
8010 return -EINVAL;
8011
8012 switch (mode_cmd->pixel_format) {
8013 case DRM_FORMAT_RGB332:
8014 case DRM_FORMAT_RGB565:
8015 case DRM_FORMAT_XRGB8888:
8016 case DRM_FORMAT_XBGR8888:
8017 case DRM_FORMAT_ARGB8888:
8018 case DRM_FORMAT_XRGB2101010:
8019 case DRM_FORMAT_ARGB2101010:
8020 /* RGB formats are common across chipsets */
8021 break;
8022 case DRM_FORMAT_YUYV:
8023 case DRM_FORMAT_UYVY:
8024 case DRM_FORMAT_YVYU:
8025 case DRM_FORMAT_VYUY:
8026 break;
8027 default:
8028 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8029 mode_cmd->pixel_format);
8030 return -EINVAL;
8031 }
8032
8033 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8034 if (ret) {
8035 DRM_ERROR("framebuffer init failed %d\n", ret);
8036 return ret;
8037 }
8038
8039 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8040 intel_fb->obj = obj;
8041 return 0;
8042}
8043
8044static int
8045intel_user_framebuffer_create(struct drm_device *dev,
8046 struct drm_file *filp, struct drm_mode_fb_cmd2 *mode_cmd,
8047 struct drm_framebuffer **res)
8048{
8049 struct drm_i915_gem_object *obj;
8050
8051 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8052 mode_cmd->handles[0]));
8053 if (&obj->base == NULL)
8054 return (-ENOENT);
8055
8056 return (intel_framebuffer_create(dev, mode_cmd, obj, res));
8057}
8058
8059static const struct drm_mode_config_funcs intel_mode_funcs = {
8060 .fb_create = intel_user_framebuffer_create,
8061 .output_poll_changed = intel_fb_output_poll_changed,
8062};
8063
8064static struct drm_i915_gem_object *
8065intel_alloc_context_page(struct drm_device *dev)
8066{
8067 struct drm_i915_gem_object *ctx;
8068 int ret;
8069
8070 DRM_LOCK_ASSERT(dev);
8071
8072 ctx = i915_gem_alloc_object(dev, 4096);
8073 if (!ctx) {
8074 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8075 return NULL;
8076 }
8077
8078 ret = i915_gem_object_pin(ctx, 4096, true);
8079 if (ret) {
8080 DRM_ERROR("failed to pin power context: %d\n", ret);
8081 goto err_unref;
8082 }
8083
8084 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8085 if (ret) {
8086 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8087 goto err_unpin;
8088 }
8089
8090 return ctx;
8091
8092err_unpin:
8093 i915_gem_object_unpin(ctx);
8094err_unref:
8095 drm_gem_object_unreference(&ctx->base);
8096 DRM_UNLOCK(dev);
8097 return NULL;
8098}
8099
8100bool ironlake_set_drps(struct drm_device *dev, u8 val)
8101{
8102 struct drm_i915_private *dev_priv = dev->dev_private;
8103 u16 rgvswctl;
8104
8105 rgvswctl = I915_READ16(MEMSWCTL);
8106 if (rgvswctl & MEMCTL_CMD_STS) {
8107 DRM_DEBUG("gpu busy, RCS change rejected\n");
8108 return false; /* still busy with another command */
8109 }
8110
8111 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8112 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8113 I915_WRITE16(MEMSWCTL, rgvswctl);
8114 POSTING_READ16(MEMSWCTL);
8115
8116 rgvswctl |= MEMCTL_CMD_STS;
8117 I915_WRITE16(MEMSWCTL, rgvswctl);
8118
8119 return true;
8120}
8121
8122void ironlake_enable_drps(struct drm_device *dev)
8123{
8124 struct drm_i915_private *dev_priv = dev->dev_private;
8125 u32 rgvmodectl = I915_READ(MEMMODECTL);
8126 u8 fmax, fmin, fstart, vstart;
8127
8128 /* Enable temp reporting */
8129 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8130 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8131
8132 /* 100ms RC evaluation intervals */
8133 I915_WRITE(RCUPEI, 100000);
8134 I915_WRITE(RCDNEI, 100000);
8135
8136 /* Set max/min thresholds to 90ms and 80ms respectively */
8137 I915_WRITE(RCBMAXAVG, 90000);
8138 I915_WRITE(RCBMINAVG, 80000);
8139
8140 I915_WRITE(MEMIHYST, 1);
8141
8142 /* Set up min, max, and cur for interrupt handling */
8143 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8144 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8145 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8146 MEMMODE_FSTART_SHIFT;
8147
8148 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8149 PXVFREQ_PX_SHIFT;
8150
8151 dev_priv->fmax = fmax; /* IPS callback will increase this */
8152 dev_priv->fstart = fstart;
8153
8154 dev_priv->max_delay = fstart;
8155 dev_priv->min_delay = fmin;
8156 dev_priv->cur_delay = fstart;
8157
8158 DRM_DEBUG("fmax: %d, fmin: %d, fstart: %d\n",
8159 fmax, fmin, fstart);
8160
8161 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8162
8163 /*
8164 * Interrupts will be enabled in ironlake_irq_postinstall
8165 */
8166
8167 I915_WRITE(VIDSTART, vstart);
8168 POSTING_READ(VIDSTART);
8169
8170 rgvmodectl |= MEMMODE_SWMODE_EN;
8171 I915_WRITE(MEMMODECTL, rgvmodectl);
8172
8173 if (_intel_wait_for(dev,
8174 (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10,
8175 1, "915per"))
8176 DRM_ERROR("stuck trying to change perf mode\n");
8177 pause("915dsp", 1);
8178
8179 ironlake_set_drps(dev, fstart);
8180
8181 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8182 I915_READ(0x112e0);
8183 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8184 dev_priv->last_count2 = I915_READ(0x112f4);
8185 nanotime(&dev_priv->last_time2);
8186}
8187
8188void ironlake_disable_drps(struct drm_device *dev)
8189{
8190 struct drm_i915_private *dev_priv = dev->dev_private;
8191 u16 rgvswctl = I915_READ16(MEMSWCTL);
8192
8193 /* Ack interrupts, disable EFC interrupt */
8194 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8195 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8196 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8197 I915_WRITE(DEIIR, DE_PCU_EVENT);
8198 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8199
8200 /* Go back to the starting frequency */
8201 ironlake_set_drps(dev, dev_priv->fstart);
8202 pause("915dsp", 1);
8203 rgvswctl |= MEMCTL_CMD_STS;
8204 I915_WRITE(MEMSWCTL, rgvswctl);
8205 pause("915dsp", 1);
8206
8207}
8208
8209void gen6_set_rps(struct drm_device *dev, u8 val)
8210{
8211 struct drm_i915_private *dev_priv = dev->dev_private;
8212 u32 swreq;
8213
8214 swreq = (val & 0x3ff) << 25;
8215 I915_WRITE(GEN6_RPNSWREQ, swreq);
8216}
8217
8218void gen6_disable_rps(struct drm_device *dev)
8219{
8220 struct drm_i915_private *dev_priv = dev->dev_private;
8221
8222 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8223 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8224 I915_WRITE(GEN6_PMIER, 0);
8225 /* Complete PM interrupt masking here doesn't race with the rps work
8226 * item again unmasking PM interrupts because that is using a different
8227 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8228 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8229
8230 mtx_lock(&dev_priv->rps_lock);
8231 dev_priv->pm_iir = 0;
8232 mtx_unlock(&dev_priv->rps_lock);
8233
8234 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8235}
8236
8237static unsigned long intel_pxfreq(u32 vidfreq)
8238{
8239 unsigned long freq;
8240 int div = (vidfreq & 0x3f0000) >> 16;
8241 int post = (vidfreq & 0x3000) >> 12;
8242 int pre = (vidfreq & 0x7);
8243
8244 if (!pre)
8245 return 0;
8246
8247 freq = ((div * 133333) / ((1<<post) * pre));
8248
8249 return freq;
8250}
8251
8252void intel_init_emon(struct drm_device *dev)
8253{
8254 struct drm_i915_private *dev_priv = dev->dev_private;
8255 u32 lcfuse;
8256 u8 pxw[16];
8257 int i;
8258
8259 /* Disable to program */
8260 I915_WRITE(ECR, 0);
8261 POSTING_READ(ECR);
8262
8263 /* Program energy weights for various events */
8264 I915_WRITE(SDEW, 0x15040d00);
8265 I915_WRITE(CSIEW0, 0x007f0000);
8266 I915_WRITE(CSIEW1, 0x1e220004);
8267 I915_WRITE(CSIEW2, 0x04000004);
8268
8269 for (i = 0; i < 5; i++)
8270 I915_WRITE(PEW + (i * 4), 0);
8271 for (i = 0; i < 3; i++)
8272 I915_WRITE(DEW + (i * 4), 0);
8273
8274 /* Program P-state weights to account for frequency power adjustment */
8275 for (i = 0; i < 16; i++) {
8276 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8277 unsigned long freq = intel_pxfreq(pxvidfreq);
8278 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8279 PXVFREQ_PX_SHIFT;
8280 unsigned long val;
8281
8282 val = vid * vid;
8283 val *= (freq / 1000);
8284 val *= 255;
8285 val /= (127*127*900);
8286 if (val > 0xff)
8287 DRM_ERROR("bad pxval: %ld\n", val);
8288 pxw[i] = val;
8289 }
8290 /* Render standby states get 0 weight */
8291 pxw[14] = 0;
8292 pxw[15] = 0;
8293
8294 for (i = 0; i < 4; i++) {
8295 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8296 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8297 I915_WRITE(PXW + (i * 4), val);
8298 }
8299
8300 /* Adjust magic regs to magic values (more experimental results) */
8301 I915_WRITE(OGW0, 0);
8302 I915_WRITE(OGW1, 0);
8303 I915_WRITE(EG0, 0x00007f00);
8304 I915_WRITE(EG1, 0x0000000e);
8305 I915_WRITE(EG2, 0x000e0000);
8306 I915_WRITE(EG3, 0x68000300);
8307 I915_WRITE(EG4, 0x42000000);
8308 I915_WRITE(EG5, 0x00140031);
8309 I915_WRITE(EG6, 0);
8310 I915_WRITE(EG7, 0);
8311
8312 for (i = 0; i < 8; i++)
8313 I915_WRITE(PXWL + (i * 4), 0);
8314
8315 /* Enable PMON + select events */
8316 I915_WRITE(ECR, 0x80000019);
8317
8318 lcfuse = I915_READ(LCFUSE02);
8319
8320 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8321}
8322
8323static int intel_enable_rc6(struct drm_device *dev)
8324{
8325 /*
8326 * Respect the kernel parameter if it is set
8327 */
8328 if (i915_enable_rc6 >= 0)
8329 return i915_enable_rc6;
8330
8331 /*
8332 * Disable RC6 on Ironlake
8333 */
8334 if (INTEL_INFO(dev)->gen == 5)
8335 return 0;
8336
8337 /*
8338 * Enable rc6 on Sandybridge if DMA remapping is disabled
8339 */
8340 if (INTEL_INFO(dev)->gen == 6) {
8341 DRM_DEBUG_DRIVER(
8342 "Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",
8343 intel_iommu_enabled ? "true" : "false",
8344 !intel_iommu_enabled ? "en" : "dis");
8345 return (intel_iommu_enabled ? 0 : INTEL_RC6_ENABLE);
8346 }
8347 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
8348 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8349}
8350
8351void gen6_enable_rps(struct drm_i915_private *dev_priv)
8352{
8353 struct drm_device *dev = dev_priv->dev;
8354 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8355 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8356 u32 pcu_mbox, rc6_mask = 0;
8357 u32 gtfifodbg;
8358 int cur_freq, min_freq, max_freq;
8359 int rc6_mode;
8360 int i;
8361
8362 /* Here begins a magic sequence of register writes to enable
8363 * auto-downclocking.
8364 *
8365 * Perhaps there might be some value in exposing these to
8366 * userspace...
8367 */
8368 I915_WRITE(GEN6_RC_STATE, 0);
8369 DRM_LOCK(dev);
8370
8371 /* Clear the DBG now so we don't confuse earlier errors */
8372 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8373 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8374 I915_WRITE(GTFIFODBG, gtfifodbg);
8375 }
8376
8377 gen6_gt_force_wake_get(dev_priv);
8378
8379 /* disable the counters and set deterministic thresholds */
8380 I915_WRITE(GEN6_RC_CONTROL, 0);
8381
8382 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8383 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8384 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8385 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8386 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8387
8388 for (i = 0; i < I915_NUM_RINGS; i++)
8389 I915_WRITE(RING_MAX_IDLE(dev_priv->rings[i].mmio_base), 10);
8390
8391 I915_WRITE(GEN6_RC_SLEEP, 0);
8392 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8393 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8394 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8395 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8396
8397 rc6_mode = intel_enable_rc6(dev_priv->dev);
8398 if (rc6_mode & INTEL_RC6_ENABLE)
8399 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
8400
8401 if (rc6_mode & INTEL_RC6p_ENABLE)
8402 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
8403
8404 if (rc6_mode & INTEL_RC6pp_ENABLE)
8405 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
8406
8407 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
8408 (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
8409 (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
8410 (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
8411
8412 I915_WRITE(GEN6_RC_CONTROL,
8413 rc6_mask |
8414 GEN6_RC_CTL_EI_MODE(1) |
8415 GEN6_RC_CTL_HW_ENABLE);
8416
8417 I915_WRITE(GEN6_RPNSWREQ,
8418 GEN6_FREQUENCY(10) |
8419 GEN6_OFFSET(0) |
8420 GEN6_AGGRESSIVE_TURBO);
8421 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8422 GEN6_FREQUENCY(12));
8423
8424 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8425 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8426 18 << 24 |
8427 6 << 16);
8428 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8429 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8430 I915_WRITE(GEN6_RP_UP_EI, 100000);
8431 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8432 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8433 I915_WRITE(GEN6_RP_CONTROL,
8434 GEN6_RP_MEDIA_TURBO |
8435 GEN6_RP_MEDIA_HW_MODE |
8436 GEN6_RP_MEDIA_IS_GFX |
8437 GEN6_RP_ENABLE |
8438 GEN6_RP_UP_BUSY_AVG |
8439 GEN6_RP_DOWN_IDLE_CONT);
8440
8441 if (_intel_wait_for(dev,
8442 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500,
8443 1, "915pr1"))
8444 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8445
8446 I915_WRITE(GEN6_PCODE_DATA, 0);
8447 I915_WRITE(GEN6_PCODE_MAILBOX,
8448 GEN6_PCODE_READY |
8449 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8450 if (_intel_wait_for(dev,
8451 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500,
8452 1, "915pr2"))
8453 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8454
8455 min_freq = (rp_state_cap & 0xff0000) >> 16;
8456 max_freq = rp_state_cap & 0xff;
8457 cur_freq = (gt_perf_status & 0xff00) >> 8;
8458
8459 /* Check for overclock support */
8460 if (_intel_wait_for(dev,
8461 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500,
8462 1, "915pr3"))
8463 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8464 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8465 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8466 if (_intel_wait_for(dev,
8467 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500,
8468 1, "915pr4"))
8469 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8470 if (pcu_mbox & (1<<31)) { /* OC supported */
8471 max_freq = pcu_mbox & 0xff;
8472 DRM_DEBUG("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8473 }
8474
8475 /* In units of 100MHz */
8476 dev_priv->max_delay = max_freq;
8477 dev_priv->min_delay = min_freq;
8478 dev_priv->cur_delay = cur_freq;
8479
8480 /* requires MSI enabled */
8481 I915_WRITE(GEN6_PMIER,
8482 GEN6_PM_MBOX_EVENT |
8483 GEN6_PM_THERMAL_EVENT |
8484 GEN6_PM_RP_DOWN_TIMEOUT |
8485 GEN6_PM_RP_UP_THRESHOLD |
8486 GEN6_PM_RP_DOWN_THRESHOLD |
8487 GEN6_PM_RP_UP_EI_EXPIRED |
8488 GEN6_PM_RP_DOWN_EI_EXPIRED);
8489 mtx_lock(&dev_priv->rps_lock);
8490 if (dev_priv->pm_iir != 0)
8491 printf("pm_iir %x\n", dev_priv->pm_iir);
8492 I915_WRITE(GEN6_PMIMR, 0);
8493 mtx_unlock(&dev_priv->rps_lock);
8494 /* enable all PM interrupts */
8495 I915_WRITE(GEN6_PMINTRMSK, 0);
8496
8497 gen6_gt_force_wake_put(dev_priv);
8498 DRM_UNLOCK(dev);
8499}
8500
8501void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8502{
8503 struct drm_device *dev;
8504 int min_freq = 15;
8505 int gpu_freq, ia_freq, max_ia_freq;
8506 int scaling_factor = 180;
8507 uint64_t tsc_freq;
8508
8509 dev = dev_priv->dev;
8510#if 0
8511 max_ia_freq = cpufreq_quick_get_max(0);
8512 /*
8513 * Default to measured freq if none found, PCU will ensure we don't go
8514 * over
8515 */
8516 if (!max_ia_freq)
8517 max_ia_freq = tsc_freq;
8518
8519 /* Convert from Hz to MHz */
8520 max_ia_freq /= 1000;
8521#else
8522 tsc_freq = atomic_load_acq_64(&tsc_freq);
8523 max_ia_freq = tsc_freq / 1000 / 1000;
8524#endif
8525
8526 DRM_LOCK(dev);
8527
8528 /*
8529 * For each potential GPU frequency, load a ring frequency we'd like
8530 * to use for memory access. We do this by specifying the IA frequency
8531 * the PCU should use as a reference to determine the ring frequency.
8532 */
8533 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8534 gpu_freq--) {
8535 int diff = dev_priv->max_delay - gpu_freq;
8536 int d;
8537
8538 /*
8539 * For GPU frequencies less than 750MHz, just use the lowest
8540 * ring freq.
8541 */
8542 if (gpu_freq < min_freq)
8543 ia_freq = 800;
8544 else
8545 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8546 d = 100;
8547 ia_freq = (ia_freq + d / 2) / d;
8548
8549 I915_WRITE(GEN6_PCODE_DATA,
8550 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8551 gpu_freq);
8552 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8553 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8554 if (_intel_wait_for(dev,
8555 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8556 10, 1, "915frq")) {
8557 DRM_ERROR("pcode write of freq table timed out\n");
8558 continue;
8559 }
8560 }
8561
8562 DRM_UNLOCK(dev);
8563}
8564
8565static void ironlake_init_clock_gating(struct drm_device *dev)
8566{
8567 struct drm_i915_private *dev_priv = dev->dev_private;
8568 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8569
8570 /* Required for FBC */
8571 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8572 DPFCRUNIT_CLOCK_GATE_DISABLE |
8573 DPFDUNIT_CLOCK_GATE_DISABLE;
8574 /* Required for CxSR */
8575 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8576
8577 I915_WRITE(PCH_3DCGDIS0,
8578 MARIUNIT_CLOCK_GATE_DISABLE |
8579 SVSMUNIT_CLOCK_GATE_DISABLE);
8580 I915_WRITE(PCH_3DCGDIS1,
8581 VFMUNIT_CLOCK_GATE_DISABLE);
8582
8583 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8584
8585 /*
8586 * According to the spec the following bits should be set in
8587 * order to enable memory self-refresh
8588 * The bit 22/21 of 0x42004
8589 * The bit 5 of 0x42020
8590 * The bit 15 of 0x45000
8591 */
8592 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8593 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8594 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8595 I915_WRITE(ILK_DSPCLK_GATE,
8596 (I915_READ(ILK_DSPCLK_GATE) |
8597 ILK_DPARB_CLK_GATE));
8598 I915_WRITE(DISP_ARB_CTL,
8599 (I915_READ(DISP_ARB_CTL) |
8600 DISP_FBC_WM_DIS));
8601 I915_WRITE(WM3_LP_ILK, 0);
8602 I915_WRITE(WM2_LP_ILK, 0);
8603 I915_WRITE(WM1_LP_ILK, 0);
8604
8605 /*
8606 * Based on the document from hardware guys the following bits
8607 * should be set unconditionally in order to enable FBC.
8608 * The bit 22 of 0x42000
8609 * The bit 22 of 0x42004
8610 * The bit 7,8,9 of 0x42020.
8611 */
8612 if (IS_IRONLAKE_M(dev)) {
8613 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8614 I915_READ(ILK_DISPLAY_CHICKEN1) |
8615 ILK_FBCQ_DIS);
8616 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8617 I915_READ(ILK_DISPLAY_CHICKEN2) |
8618 ILK_DPARB_GATE);
8619 I915_WRITE(ILK_DSPCLK_GATE,
8620 I915_READ(ILK_DSPCLK_GATE) |
8621 ILK_DPFC_DIS1 |
8622 ILK_DPFC_DIS2 |
8623 ILK_CLK_FBC);
8624 }
8625
8626 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8627 I915_READ(ILK_DISPLAY_CHICKEN2) |
8628 ILK_ELPIN_409_SELECT);
8629 I915_WRITE(_3D_CHICKEN2,
8630 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8631 _3D_CHICKEN2_WM_READ_PIPELINED);
8632}
8633
8634static void gen6_init_clock_gating(struct drm_device *dev)
8635{
8636 struct drm_i915_private *dev_priv = dev->dev_private;
8637 int pipe;
8638 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8639
8640 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8641
8642 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8643 I915_READ(ILK_DISPLAY_CHICKEN2) |
8644 ILK_ELPIN_409_SELECT);
8645
8646 I915_WRITE(WM3_LP_ILK, 0);
8647 I915_WRITE(WM2_LP_ILK, 0);
8648 I915_WRITE(WM1_LP_ILK, 0);
8649
8650 I915_WRITE(GEN6_UCGCTL1,
8651 I915_READ(GEN6_UCGCTL1) |
8652 GEN6_BLBUNIT_CLOCK_GATE_DISABLE);
8653
8654 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8655 * gating disable must be set. Failure to set it results in
8656 * flickering pixels due to Z write ordering failures after
8657 * some amount of runtime in the Mesa "fire" demo, and Unigine
8658 * Sanctuary and Tropics, and apparently anything else with
8659 * alpha test or pixel discard.
8660 *
8661 * According to the spec, bit 11 (RCCUNIT) must also be set,
8662 * but we didn't debug actual testcases to find it out.
8663 */
8664 I915_WRITE(GEN6_UCGCTL2,
8665 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8666 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8667
8668 /*
8669 * According to the spec the following bits should be
8670 * set in order to enable memory self-refresh and fbc:
8671 * The bit21 and bit22 of 0x42000
8672 * The bit21 and bit22 of 0x42004
8673 * The bit5 and bit7 of 0x42020
8674 * The bit14 of 0x70180
8675 * The bit14 of 0x71180
8676 */
8677 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8678 I915_READ(ILK_DISPLAY_CHICKEN1) |
8679 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8680 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8681 I915_READ(ILK_DISPLAY_CHICKEN2) |
8682 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8683 I915_WRITE(ILK_DSPCLK_GATE,
8684 I915_READ(ILK_DSPCLK_GATE) |
8685 ILK_DPARB_CLK_GATE |
8686 ILK_DPFD_CLK_GATE);
8687
8688 for_each_pipe(pipe) {
8689 I915_WRITE(DSPCNTR(pipe),
8690 I915_READ(DSPCNTR(pipe)) |
8691 DISPPLANE_TRICKLE_FEED_DISABLE);
8692 intel_flush_display_plane(dev_priv, pipe);
8693 }
8694}
8695
8696static void ivybridge_init_clock_gating(struct drm_device *dev)
8697{
8698 struct drm_i915_private *dev_priv = dev->dev_private;
8699 int pipe;
8700 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8701
8702 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8703
8704 I915_WRITE(WM3_LP_ILK, 0);
8705 I915_WRITE(WM2_LP_ILK, 0);
8706 I915_WRITE(WM1_LP_ILK, 0);
8707
8708 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8709 * This implements the WaDisableRCZUnitClockGating workaround.
8710 */
8711 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8712
8713 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8714
8715 I915_WRITE(IVB_CHICKEN3,
8716 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8717 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8718
8719 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8720 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8721 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8722
8723 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8724 I915_WRITE(GEN7_L3CNTLREG1,
8725 GEN7_WA_FOR_GEN7_L3_CONTROL);
8726 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8727 GEN7_WA_L3_CHICKEN_MODE);
8728
8729 /* This is required by WaCatErrorRejectionIssue */
8730 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8731 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8732 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8733
8734 for_each_pipe(pipe) {
8735 I915_WRITE(DSPCNTR(pipe),
8736 I915_READ(DSPCNTR(pipe)) |
8737 DISPPLANE_TRICKLE_FEED_DISABLE);
8738 intel_flush_display_plane(dev_priv, pipe);
8739 }
8740}
8741
8742static void g4x_init_clock_gating(struct drm_device *dev)
8743{
8744 struct drm_i915_private *dev_priv = dev->dev_private;
8745 uint32_t dspclk_gate;
8746
8747 I915_WRITE(RENCLK_GATE_D1, 0);
8748 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8749 GS_UNIT_CLOCK_GATE_DISABLE |
8750 CL_UNIT_CLOCK_GATE_DISABLE);
8751 I915_WRITE(RAMCLK_GATE_D, 0);
8752 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8753 OVRUNIT_CLOCK_GATE_DISABLE |
8754 OVCUNIT_CLOCK_GATE_DISABLE;
8755 if (IS_GM45(dev))
8756 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8757 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8758}
8759
8760static void crestline_init_clock_gating(struct drm_device *dev)
8761{
8762 struct drm_i915_private *dev_priv = dev->dev_private;
8763
8764 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8765 I915_WRITE(RENCLK_GATE_D2, 0);
8766 I915_WRITE(DSPCLK_GATE_D, 0);
8767 I915_WRITE(RAMCLK_GATE_D, 0);
8768 I915_WRITE16(DEUC, 0);
8769}
8770
8771static void broadwater_init_clock_gating(struct drm_device *dev)
8772{
8773 struct drm_i915_private *dev_priv = dev->dev_private;
8774
8775 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8776 I965_RCC_CLOCK_GATE_DISABLE |
8777 I965_RCPB_CLOCK_GATE_DISABLE |
8778 I965_ISC_CLOCK_GATE_DISABLE |
8779 I965_FBC_CLOCK_GATE_DISABLE);
8780 I915_WRITE(RENCLK_GATE_D2, 0);
8781}
8782
8783static void gen3_init_clock_gating(struct drm_device *dev)
8784{
8785 struct drm_i915_private *dev_priv = dev->dev_private;
8786 u32 dstate = I915_READ(D_STATE);
8787
8788 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8789 DSTATE_DOT_CLOCK_GATING;
8790 I915_WRITE(D_STATE, dstate);
8791}
8792
8793static void i85x_init_clock_gating(struct drm_device *dev)
8794{
8795 struct drm_i915_private *dev_priv = dev->dev_private;
8796
8797 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8798}
8799
8800static void i830_init_clock_gating(struct drm_device *dev)
8801{
8802 struct drm_i915_private *dev_priv = dev->dev_private;
8803
8804 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8805}
8806
8807static void ibx_init_clock_gating(struct drm_device *dev)
8808{
8809 struct drm_i915_private *dev_priv = dev->dev_private;
8810
8811 /*
8812 * On Ibex Peak and Cougar Point, we need to disable clock
8813 * gating for the panel power sequencer or it will fail to
8814 * start up when no ports are active.
8815 */
8816 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8817}
8818
8819static void cpt_init_clock_gating(struct drm_device *dev)
8820{
8821 struct drm_i915_private *dev_priv = dev->dev_private;
8822 int pipe;
8823
8824 /*
8825 * On Ibex Peak and Cougar Point, we need to disable clock
8826 * gating for the panel power sequencer or it will fail to
8827 * start up when no ports are active.
8828 */
8829 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8830 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8831 DPLS_EDP_PPS_FIX_DIS);
8832 /* Without this, mode sets may fail silently on FDI */
8833 for_each_pipe(pipe)
8834 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8835}
8836
8837static void ironlake_teardown_rc6(struct drm_device *dev)
8838{
8839 struct drm_i915_private *dev_priv = dev->dev_private;
8840
8841 if (dev_priv->renderctx) {
8842 i915_gem_object_unpin(dev_priv->renderctx);
8843 drm_gem_object_unreference(&dev_priv->renderctx->base);
8844 dev_priv->renderctx = NULL;
8845 }
8846
8847 if (dev_priv->pwrctx) {
8848 i915_gem_object_unpin(dev_priv->pwrctx);
8849 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8850 dev_priv->pwrctx = NULL;
8851 }
8852}
8853
8854static void ironlake_disable_rc6(struct drm_device *dev)
8855{
8856 struct drm_i915_private *dev_priv = dev->dev_private;
8857
8858 if (I915_READ(PWRCTXA)) {
8859 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8860 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8861 (void)_intel_wait_for(dev,
8862 ((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8863 50, 1, "915pro");
8864
8865 I915_WRITE(PWRCTXA, 0);
8866 POSTING_READ(PWRCTXA);
8867
8868 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8869 POSTING_READ(RSTDBYCTL);
8870 }
8871
8872 ironlake_teardown_rc6(dev);
8873}
8874
8875static int ironlake_setup_rc6(struct drm_device *dev)
8876{
8877 struct drm_i915_private *dev_priv = dev->dev_private;
8878
8879 if (dev_priv->renderctx == NULL)
8880 dev_priv->renderctx = intel_alloc_context_page(dev);
8881 if (!dev_priv->renderctx)
8882 return -ENOMEM;
8883
8884 if (dev_priv->pwrctx == NULL)
8885 dev_priv->pwrctx = intel_alloc_context_page(dev);
8886 if (!dev_priv->pwrctx) {
8887 ironlake_teardown_rc6(dev);
8888 return -ENOMEM;
8889 }
8890
8891 return 0;
8892}
8893
8894void ironlake_enable_rc6(struct drm_device *dev)
8895{
8896 struct drm_i915_private *dev_priv = dev->dev_private;
8897 int ret;
8898
8899 /* rc6 disabled by default due to repeated reports of hanging during
8900 * boot and resume.
8901 */
8902 if (!intel_enable_rc6(dev))
8903 return;
8904
8905 DRM_LOCK(dev);
8906 ret = ironlake_setup_rc6(dev);
8907 if (ret) {
8908 DRM_UNLOCK(dev);
8909 return;
8910 }
8911
8912 /*
8913 * GPU can automatically power down the render unit if given a page
8914 * to save state.
8915 */
8916 ret = BEGIN_LP_RING(6);
8917 if (ret) {
8918 ironlake_teardown_rc6(dev);
8919 DRM_UNLOCK(dev);
8920 return;
8921 }
8922
8923 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8924 OUT_RING(MI_SET_CONTEXT);
8925 OUT_RING(dev_priv->renderctx->gtt_offset |
8926 MI_MM_SPACE_GTT |
8927 MI_SAVE_EXT_STATE_EN |
8928 MI_RESTORE_EXT_STATE_EN |
8929 MI_RESTORE_INHIBIT);
8930 OUT_RING(MI_SUSPEND_FLUSH);
8931 OUT_RING(MI_NOOP);
8932 OUT_RING(MI_FLUSH);
8933 ADVANCE_LP_RING();
8934
8935 /*
8936 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8937 * does an implicit flush, combined with MI_FLUSH above, it should be
8938 * safe to assume that renderctx is valid
8939 */
8940 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8941 if (ret) {
8942 DRM_ERROR("failed to enable ironlake power power savings\n");
8943 ironlake_teardown_rc6(dev);
8944 DRM_UNLOCK(dev);
8945 return;
8946 }
8947
8948 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8949 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8950 DRM_UNLOCK(dev);
8951}
8952
8953void intel_init_clock_gating(struct drm_device *dev)
8954{
8955 struct drm_i915_private *dev_priv = dev->dev_private;
8956
8957 dev_priv->display.init_clock_gating(dev);
8958
8959 if (dev_priv->display.init_pch_clock_gating)
8960 dev_priv->display.init_pch_clock_gating(dev);
8961}
8962
8963/* Set up chip specific display functions */
8964static void intel_init_display(struct drm_device *dev)
8965{
8966 struct drm_i915_private *dev_priv = dev->dev_private;
8967
8968 /* We always want a DPMS function */
8969 if (HAS_PCH_SPLIT(dev)) {
8970 dev_priv->display.dpms = ironlake_crtc_dpms;
8971 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8972 dev_priv->display.update_plane = ironlake_update_plane;
8973 } else {
8974 dev_priv->display.dpms = i9xx_crtc_dpms;
8975 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8976 dev_priv->display.update_plane = i9xx_update_plane;
8977 }
8978
8979 if (I915_HAS_FBC(dev)) {
8980 if (HAS_PCH_SPLIT(dev)) {
8981 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8982 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8983 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8984 } else if (IS_GM45(dev)) {
8985 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8986 dev_priv->display.enable_fbc = g4x_enable_fbc;
8987 dev_priv->display.disable_fbc = g4x_disable_fbc;
8988 } else if (IS_CRESTLINE(dev)) {
8989 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8990 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8991 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8992 }
8993 /* 855GM needs testing */
8994 }
8995
8996 /* Returns the core display clock speed */
8997 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8998 dev_priv->display.get_display_clock_speed =
8999 i945_get_display_clock_speed;
9000 else if (IS_I915G(dev))
9001 dev_priv->display.get_display_clock_speed =
9002 i915_get_display_clock_speed;
9003 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9004 dev_priv->display.get_display_clock_speed =
9005 i9xx_misc_get_display_clock_speed;
9006 else if (IS_I915GM(dev))
9007 dev_priv->display.get_display_clock_speed =
9008 i915gm_get_display_clock_speed;
9009 else if (IS_I865G(dev))
9010 dev_priv->display.get_display_clock_speed =
9011 i865_get_display_clock_speed;
9012 else if (IS_I85X(dev))
9013 dev_priv->display.get_display_clock_speed =
9014 i855_get_display_clock_speed;
9015 else /* 852, 830 */
9016 dev_priv->display.get_display_clock_speed =
9017 i830_get_display_clock_speed;
9018
9019 /* For FIFO watermark updates */
9020 if (HAS_PCH_SPLIT(dev)) {
9021 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
9022 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
9023
9024 /* IVB configs may use multi-threaded forcewake */
9025 if (IS_IVYBRIDGE(dev)) {
9026 u32 ecobus;
9027
9028 /* A small trick here - if the bios hasn't configured MT forcewake,
9029 * and if the device is in RC6, then force_wake_mt_get will not wake
9030 * the device and the ECOBUS read will return zero. Which will be
9031 * (correctly) interpreted by the test below as MT forcewake being
9032 * disabled.
9033 */
9034 DRM_LOCK(dev);
9035 __gen6_gt_force_wake_mt_get(dev_priv);
9036 ecobus = I915_READ_NOTRACE(ECOBUS);
9037 __gen6_gt_force_wake_mt_put(dev_priv);
9038 DRM_UNLOCK(dev);
9039
9040 if (ecobus & FORCEWAKE_MT_ENABLE) {
9041 DRM_DEBUG_KMS("Using MT version of forcewake\n");
9042 dev_priv->display.force_wake_get =
9043 __gen6_gt_force_wake_mt_get;
9044 dev_priv->display.force_wake_put =
9045 __gen6_gt_force_wake_mt_put;
9046 }
9047 }
9048
9049 if (HAS_PCH_IBX(dev))
9050 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
9051 else if (HAS_PCH_CPT(dev))
9052 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
9053
9054 if (IS_GEN5(dev)) {
9055 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
9056 dev_priv->display.update_wm = ironlake_update_wm;
9057 else {
9058 DRM_DEBUG_KMS("Failed to get proper latency. "
9059 "Disable CxSR\n");
9060 dev_priv->display.update_wm = NULL;
9061 }
9062 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9063 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
9064 dev_priv->display.write_eld = ironlake_write_eld;
9065 } else if (IS_GEN6(dev)) {
9066 if (SNB_READ_WM0_LATENCY()) {
9067 dev_priv->display.update_wm = sandybridge_update_wm;
9068 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9069 } else {
9070 DRM_DEBUG_KMS("Failed to read display plane latency. "
9071 "Disable CxSR\n");
9072 dev_priv->display.update_wm = NULL;
9073 }
9074 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9075 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9076 dev_priv->display.write_eld = ironlake_write_eld;
9077 } else if (IS_IVYBRIDGE(dev)) {
9078 /* FIXME: detect B0+ stepping and use auto training */
9079 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9080 if (SNB_READ_WM0_LATENCY()) {
9081 dev_priv->display.update_wm = sandybridge_update_wm;
9082 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9083 } else {
9084 DRM_DEBUG_KMS("Failed to read display plane latency. "
9085 "Disable CxSR\n");
9086 dev_priv->display.update_wm = NULL;
9087 }
9088 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
9089 dev_priv->display.write_eld = ironlake_write_eld;
9090 } else
9091 dev_priv->display.update_wm = NULL;
9092 } else if (IS_PINEVIEW(dev)) {
9093 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
9094 dev_priv->is_ddr3,
9095 dev_priv->fsb_freq,
9096 dev_priv->mem_freq)) {
9097 DRM_INFO("failed to find known CxSR latency "
9098 "(found ddr%s fsb freq %d, mem freq %d), "
9099 "disabling CxSR\n",
9100 (dev_priv->is_ddr3 == 1) ? "3" : "2",
9101 dev_priv->fsb_freq, dev_priv->mem_freq);
9102 /* Disable CxSR and never update its watermark again */
9103 pineview_disable_cxsr(dev);
9104 dev_priv->display.update_wm = NULL;
9105 } else
9106 dev_priv->display.update_wm = pineview_update_wm;
9107 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9108 } else if (IS_G4X(dev)) {
9109 dev_priv->display.write_eld = g4x_write_eld;
9110 dev_priv->display.update_wm = g4x_update_wm;
9111 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9112 } else if (IS_GEN4(dev)) {
9113 dev_priv->display.update_wm = i965_update_wm;
9114 if (IS_CRESTLINE(dev))
9115 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9116 else if (IS_BROADWATER(dev))
9117 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9118 } else if (IS_GEN3(dev)) {
9119 dev_priv->display.update_wm = i9xx_update_wm;
9120 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9121 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9122 } else if (IS_I865G(dev)) {
9123 dev_priv->display.update_wm = i830_update_wm;
9124 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9125 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9126 } else if (IS_I85X(dev)) {
9127 dev_priv->display.update_wm = i9xx_update_wm;
9128 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
9129 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9130 } else {
9131 dev_priv->display.update_wm = i830_update_wm;
9132 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9133 if (IS_845G(dev))
9134 dev_priv->display.get_fifo_size = i845_get_fifo_size;
9135 else
9136 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9137 }
9138
9139 /* Default just returns -ENODEV to indicate unsupported */
9140 dev_priv->display.queue_flip = intel_default_queue_flip;
9141
9142 switch (INTEL_INFO(dev)->gen) {
9143 case 2:
9144 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9145 break;
9146
9147 case 3:
9148 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9149 break;
9150
9151 case 4:
9152 case 5:
9153 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9154 break;
9155
9156 case 6:
9157 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9158 break;
9159 case 7:
9160 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9161 break;
9162 }
9163}
9164
9165/*
9166 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9167 * resume, or other times. This quirk makes sure that's the case for
9168 * affected systems.
9169 */
9170static void quirk_pipea_force(struct drm_device *dev)
9171{
9172 struct drm_i915_private *dev_priv = dev->dev_private;
9173
9174 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9175 DRM_DEBUG("applying pipe a force quirk\n");
9176}
9177
9178/*
9179 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9180 */
9181static void quirk_ssc_force_disable(struct drm_device *dev)
9182{
9183 struct drm_i915_private *dev_priv = dev->dev_private;
9184 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9185}
9186
9187struct intel_quirk {
9188 int device;
9189 int subsystem_vendor;
9190 int subsystem_device;
9191 void (*hook)(struct drm_device *dev);
9192};
9193
9194#define PCI_ANY_ID (~0u)
9195
9196struct intel_quirk intel_quirks[] = {
9197 /* HP Mini needs pipe A force quirk (LP: #322104) */
9198 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9199
9200 /* Thinkpad R31 needs pipe A force quirk */
9201 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9202 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9203 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9204
9205 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9206 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9207 /* ThinkPad X40 needs pipe A force quirk */
9208
9209 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9210 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9211
9212 /* 855 & before need to leave pipe A & dpll A up */
9213 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9214 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9215
9216 /* Lenovo U160 cannot use SSC on LVDS */
9217 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9218
9219 /* Sony Vaio Y cannot use SSC on LVDS */
9220 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9221};
9222
9223static void intel_init_quirks(struct drm_device *dev)
9224{
9225 struct intel_quirk *q;
9226 device_t d;
9227 int i;
9228
9229 d = dev->device;
9230 for (i = 0; i < DRM_ARRAY_SIZE(intel_quirks); i++) {
9231 q = &intel_quirks[i];
9232 if (pci_get_device(d) == q->device &&
9233 (pci_get_subvendor(d) == q->subsystem_vendor ||
9234 q->subsystem_vendor == PCI_ANY_ID) &&
9235 (pci_get_subdevice(d) == q->subsystem_device ||
9236 q->subsystem_device == PCI_ANY_ID))
9237 q->hook(dev);
9238 }
9239}
9240
9241/* Disable the VGA plane that we never use */
9242static void i915_disable_vga(struct drm_device *dev)
9243{
9244 struct drm_i915_private *dev_priv = dev->dev_private;
9245 u8 sr1;
9246 u32 vga_reg;
9247
9248 if (HAS_PCH_SPLIT(dev))
9249 vga_reg = CPU_VGACNTRL;
9250 else
9251 vga_reg = VGACNTRL;
9252
9253#if 0
9254 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9255#endif
9256 outb(VGA_SR_INDEX, 1);
9257 sr1 = inb(VGA_SR_DATA);
9258 outb(VGA_SR_DATA, sr1 | 1 << 5);
9259#if 0
9260 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9261#endif
9262 DELAY(300);
9263
9264 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9265 POSTING_READ(vga_reg);
9266}
9267
9268void intel_modeset_init(struct drm_device *dev)
9269{
9270 struct drm_i915_private *dev_priv = dev->dev_private;
9271 int i, ret;
9272
9273 drm_mode_config_init(dev);
9274
9275 dev->mode_config.min_width = 0;
9276 dev->mode_config.min_height = 0;
9277
9278 dev->mode_config.preferred_depth = 24;
9279 dev->mode_config.prefer_shadow = 1;
9280
9281 dev->mode_config.funcs = __DECONST(struct drm_mode_config_funcs *,
9282 &intel_mode_funcs);
9283
9284 intel_init_quirks(dev);
9285
9286 intel_init_display(dev);
9287
9288 if (IS_GEN2(dev)) {
9289 dev->mode_config.max_width = 2048;
9290 dev->mode_config.max_height = 2048;
9291 } else if (IS_GEN3(dev)) {
9292 dev->mode_config.max_width = 4096;
9293 dev->mode_config.max_height = 4096;
9294 } else {
9295 dev->mode_config.max_width = 8192;
9296 dev->mode_config.max_height = 8192;
9297 }
9298 dev->mode_config.fb_base = dev->agp->base;
9299
9300 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9301 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9302
9303 for (i = 0; i < dev_priv->num_pipe; i++) {
9304 intel_crtc_init(dev, i);
9305 ret = intel_plane_init(dev, i);
9306 if (ret)
9307 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9308 }
9309
9310 /* Just disable it once at startup */
9311 i915_disable_vga(dev);
9312 intel_setup_outputs(dev);
9313
9314 intel_init_clock_gating(dev);
9315
9316 if (IS_IRONLAKE_M(dev)) {
9317 ironlake_enable_drps(dev);
9318 intel_init_emon(dev);
9319 }
9320
9321 if (IS_GEN6(dev)) {
9322 gen6_enable_rps(dev_priv);
9323 gen6_update_ring_freq(dev_priv);
9324 }
9325
9326 TASK_INIT(&dev_priv->idle_task, 0, intel_idle_update, dev_priv);
9327 callout_init(&dev_priv->idle_callout, CALLOUT_MPSAFE);
9328}
9329
9330void intel_modeset_gem_init(struct drm_device *dev)
9331{
9332 if (IS_IRONLAKE_M(dev))
9333 ironlake_enable_rc6(dev);
9334
9335 intel_setup_overlay(dev);
9336}
9337
9338void intel_modeset_cleanup(struct drm_device *dev)
9339{
9340 struct drm_i915_private *dev_priv = dev->dev_private;
9341 struct drm_crtc *crtc;
9342 struct intel_crtc *intel_crtc;
9343
9344 drm_kms_helper_poll_fini(dev);
9345 DRM_LOCK(dev);
9346
9347#if 0
9348 intel_unregister_dsm_handler();
9349#endif
9350
9351 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9352 /* Skip inactive CRTCs */
9353 if (!crtc->fb)
9354 continue;
9355
9356 intel_crtc = to_intel_crtc(crtc);
9357 intel_increase_pllclock(crtc);
9358 }
9359
9360 intel_disable_fbc(dev);
9361
9362 if (IS_IRONLAKE_M(dev))
9363 ironlake_disable_drps(dev);
9364 if (IS_GEN6(dev))
9365 gen6_disable_rps(dev);
9366
9367 if (IS_IRONLAKE_M(dev))
9368 ironlake_disable_rc6(dev);
9369
9370 /* Disable the irq before mode object teardown, for the irq might
9371 * enqueue unpin/hotplug work. */
9372 drm_irq_uninstall(dev);
9373 DRM_UNLOCK(dev);
9374
9375 if (taskqueue_cancel(dev_priv->tq, &dev_priv->hotplug_task, NULL))
9376 taskqueue_drain(dev_priv->tq, &dev_priv->hotplug_task);
9377 if (taskqueue_cancel(dev_priv->tq, &dev_priv->rps_task, NULL))
9378 taskqueue_drain(dev_priv->tq, &dev_priv->rps_task);
9379
9380 /* Shut off idle work before the crtcs get freed. */
9381 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9382 intel_crtc = to_intel_crtc(crtc);
9383 callout_drain(&intel_crtc->idle_callout);
9384 }
9385 callout_drain(&dev_priv->idle_callout);
9386 if (taskqueue_cancel(dev_priv->tq, &dev_priv->idle_task, NULL))
9387 taskqueue_drain(dev_priv->tq, &dev_priv->idle_task);
9388
9389 drm_mode_config_cleanup(dev);
9390}
9391
9392/*
9393 * Return which encoder is currently attached for connector.
9394 */
9395struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9396{
9397 return &intel_attached_encoder(connector)->base;
9398}
9399
9400void intel_connector_attach_encoder(struct intel_connector *connector,
9401 struct intel_encoder *encoder)
9402{
9403 connector->encoder = encoder;
9404 drm_mode_connector_attach_encoder(&connector->base,
9405 &encoder->base);
9406}
9407
9408/*
9409 * set vga decode state - true == enable VGA decode
9410 */
9411int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9412{
9413 struct drm_i915_private *dev_priv;
9414 device_t bridge_dev;
9415 u16 gmch_ctrl;
9416
9417 dev_priv = dev->dev_private;
9418 bridge_dev = intel_gtt_get_bridge_device();
9419 gmch_ctrl = pci_read_config(bridge_dev, INTEL_GMCH_CTRL, 2);
9420 if (state)
9421 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9422 else
9423 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9424 pci_write_config(bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl, 2);
9425 return (0);
9426}
9427
9428struct intel_display_error_state {
9429 struct intel_cursor_error_state {
9430 u32 control;
9431 u32 position;
9432 u32 base;
9433 u32 size;
9434 } cursor[2];
9435
9436 struct intel_pipe_error_state {
9437 u32 conf;
9438 u32 source;
9439
9440 u32 htotal;
9441 u32 hblank;
9442 u32 hsync;
9443 u32 vtotal;
9444 u32 vblank;
9445 u32 vsync;
9446 } pipe[2];
9447
9448 struct intel_plane_error_state {
9449 u32 control;
9450 u32 stride;
9451 u32 size;
9452 u32 pos;
9453 u32 addr;
9454 u32 surface;
9455 u32 tile_offset;
9456 } plane[2];
9457};
9458
9459struct intel_display_error_state *
9460intel_display_capture_error_state(struct drm_device *dev)
9461{
9462 drm_i915_private_t *dev_priv = dev->dev_private;
9463 struct intel_display_error_state *error;
9464 int i;
9465
9466 error = malloc(sizeof(*error), DRM_MEM_KMS, M_NOWAIT);
9467 if (error == NULL)
9468 return NULL;
9469
9470 for (i = 0; i < 2; i++) {
9471 error->cursor[i].control = I915_READ(CURCNTR(i));
9472 error->cursor[i].position = I915_READ(CURPOS(i));
9473 error->cursor[i].base = I915_READ(CURBASE(i));
9474
9475 error->plane[i].control = I915_READ(DSPCNTR(i));
9476 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9477 error->plane[i].size = I915_READ(DSPSIZE(i));
9478 error->plane[i].pos = I915_READ(DSPPOS(i));
9479 error->plane[i].addr = I915_READ(DSPADDR(i));
9480 if (INTEL_INFO(dev)->gen >= 4) {
9481 error->plane[i].surface = I915_READ(DSPSURF(i));
9482 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9483 }
9484
9485 error->pipe[i].conf = I915_READ(PIPECONF(i));
9486 error->pipe[i].source = I915_READ(PIPESRC(i));
9487 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9488 error->pipe[i].hblank = I915_READ(HBLANK(i));
9489 error->pipe[i].hsync = I915_READ(HSYNC(i));
9490 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9491 error->pipe[i].vblank = I915_READ(VBLANK(i));
9492 error->pipe[i].vsync = I915_READ(VSYNC(i));
9493 }
9494
9495 return error;
9496}
9497
9498void
9499intel_display_print_error_state(struct sbuf *m,
9500 struct drm_device *dev,
9501 struct intel_display_error_state *error)
9502{
9503 int i;
9504
9505 for (i = 0; i < 2; i++) {
9506 sbuf_printf(m, "Pipe [%d]:\n", i);
9507 sbuf_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9508 sbuf_printf(m, " SRC: %08x\n", error->pipe[i].source);
9509 sbuf_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9510 sbuf_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9511 sbuf_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9512 sbuf_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9513 sbuf_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9514 sbuf_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9515
9516 sbuf_printf(m, "Plane [%d]:\n", i);
9517 sbuf_printf(m, " CNTR: %08x\n", error->plane[i].control);
9518 sbuf_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9519 sbuf_printf(m, " SIZE: %08x\n", error->plane[i].size);
9520 sbuf_printf(m, " POS: %08x\n", error->plane[i].pos);
9521 sbuf_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9522 if (INTEL_INFO(dev)->gen >= 4) {
9523 sbuf_printf(m, " SURF: %08x\n", error->plane[i].surface);
9524 sbuf_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9525 }
9526
9527 sbuf_printf(m, "Cursor [%d]:\n", i);
9528 sbuf_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9529 sbuf_printf(m, " POS: %08x\n", error->cursor[i].position);
9530 sbuf_printf(m, " BASE: %08x\n", error->cursor[i].base);
9531 }
9532}
| 3516 struct drm_display_mode *adjusted_mode)
3517{
3518 struct drm_device *dev = crtc->dev;
3519
3520 if (HAS_PCH_SPLIT(dev)) {
3521 /* FDI link clock is fixed at 2.7G */
3522 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3523 return false;
3524 }
3525
3526 /* All interlaced capable intel hw wants timings in frames. Note though
3527 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3528 * timings, so we need to be careful not to clobber these.*/
3529 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3530 drm_mode_set_crtcinfo(adjusted_mode, 0);
3531
3532 return true;
3533}
3534
3535static int i945_get_display_clock_speed(struct drm_device *dev)
3536{
3537 return 400000;
3538}
3539
3540static int i915_get_display_clock_speed(struct drm_device *dev)
3541{
3542 return 333000;
3543}
3544
3545static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3546{
3547 return 200000;
3548}
3549
3550static int i915gm_get_display_clock_speed(struct drm_device *dev)
3551{
3552 u16 gcfgc = 0;
3553
3554 gcfgc = pci_read_config(dev->device, GCFGC, 2);
3555
3556 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3557 return 133000;
3558 else {
3559 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3560 case GC_DISPLAY_CLOCK_333_MHZ:
3561 return 333000;
3562 default:
3563 case GC_DISPLAY_CLOCK_190_200_MHZ:
3564 return 190000;
3565 }
3566 }
3567}
3568
3569static int i865_get_display_clock_speed(struct drm_device *dev)
3570{
3571 return 266000;
3572}
3573
3574static int i855_get_display_clock_speed(struct drm_device *dev)
3575{
3576 u16 hpllcc = 0;
3577 /* Assume that the hardware is in the high speed state. This
3578 * should be the default.
3579 */
3580 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3581 case GC_CLOCK_133_200:
3582 case GC_CLOCK_100_200:
3583 return 200000;
3584 case GC_CLOCK_166_250:
3585 return 250000;
3586 case GC_CLOCK_100_133:
3587 return 133000;
3588 }
3589
3590 /* Shouldn't happen */
3591 return 0;
3592}
3593
3594static int i830_get_display_clock_speed(struct drm_device *dev)
3595{
3596 return 133000;
3597}
3598
3599struct fdi_m_n {
3600 u32 tu;
3601 u32 gmch_m;
3602 u32 gmch_n;
3603 u32 link_m;
3604 u32 link_n;
3605};
3606
3607static void
3608fdi_reduce_ratio(u32 *num, u32 *den)
3609{
3610 while (*num > 0xffffff || *den > 0xffffff) {
3611 *num >>= 1;
3612 *den >>= 1;
3613 }
3614}
3615
3616static void
3617ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3618 int link_clock, struct fdi_m_n *m_n)
3619{
3620 m_n->tu = 64; /* default size */
3621
3622 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3623 m_n->gmch_m = bits_per_pixel * pixel_clock;
3624 m_n->gmch_n = link_clock * nlanes * 8;
3625 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3626
3627 m_n->link_m = pixel_clock;
3628 m_n->link_n = link_clock;
3629 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3630}
3631
3632
3633struct intel_watermark_params {
3634 unsigned long fifo_size;
3635 unsigned long max_wm;
3636 unsigned long default_wm;
3637 unsigned long guard_size;
3638 unsigned long cacheline_size;
3639};
3640
3641/* Pineview has different values for various configs */
3642static const struct intel_watermark_params pineview_display_wm = {
3643 PINEVIEW_DISPLAY_FIFO,
3644 PINEVIEW_MAX_WM,
3645 PINEVIEW_DFT_WM,
3646 PINEVIEW_GUARD_WM,
3647 PINEVIEW_FIFO_LINE_SIZE
3648};
3649static const struct intel_watermark_params pineview_display_hplloff_wm = {
3650 PINEVIEW_DISPLAY_FIFO,
3651 PINEVIEW_MAX_WM,
3652 PINEVIEW_DFT_HPLLOFF_WM,
3653 PINEVIEW_GUARD_WM,
3654 PINEVIEW_FIFO_LINE_SIZE
3655};
3656static const struct intel_watermark_params pineview_cursor_wm = {
3657 PINEVIEW_CURSOR_FIFO,
3658 PINEVIEW_CURSOR_MAX_WM,
3659 PINEVIEW_CURSOR_DFT_WM,
3660 PINEVIEW_CURSOR_GUARD_WM,
3661 PINEVIEW_FIFO_LINE_SIZE,
3662};
3663static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3664 PINEVIEW_CURSOR_FIFO,
3665 PINEVIEW_CURSOR_MAX_WM,
3666 PINEVIEW_CURSOR_DFT_WM,
3667 PINEVIEW_CURSOR_GUARD_WM,
3668 PINEVIEW_FIFO_LINE_SIZE
3669};
3670static const struct intel_watermark_params g4x_wm_info = {
3671 G4X_FIFO_SIZE,
3672 G4X_MAX_WM,
3673 G4X_MAX_WM,
3674 2,
3675 G4X_FIFO_LINE_SIZE,
3676};
3677static const struct intel_watermark_params g4x_cursor_wm_info = {
3678 I965_CURSOR_FIFO,
3679 I965_CURSOR_MAX_WM,
3680 I965_CURSOR_DFT_WM,
3681 2,
3682 G4X_FIFO_LINE_SIZE,
3683};
3684static const struct intel_watermark_params i965_cursor_wm_info = {
3685 I965_CURSOR_FIFO,
3686 I965_CURSOR_MAX_WM,
3687 I965_CURSOR_DFT_WM,
3688 2,
3689 I915_FIFO_LINE_SIZE,
3690};
3691static const struct intel_watermark_params i945_wm_info = {
3692 I945_FIFO_SIZE,
3693 I915_MAX_WM,
3694 1,
3695 2,
3696 I915_FIFO_LINE_SIZE
3697};
3698static const struct intel_watermark_params i915_wm_info = {
3699 I915_FIFO_SIZE,
3700 I915_MAX_WM,
3701 1,
3702 2,
3703 I915_FIFO_LINE_SIZE
3704};
3705static const struct intel_watermark_params i855_wm_info = {
3706 I855GM_FIFO_SIZE,
3707 I915_MAX_WM,
3708 1,
3709 2,
3710 I830_FIFO_LINE_SIZE
3711};
3712static const struct intel_watermark_params i830_wm_info = {
3713 I830_FIFO_SIZE,
3714 I915_MAX_WM,
3715 1,
3716 2,
3717 I830_FIFO_LINE_SIZE
3718};
3719
3720static const struct intel_watermark_params ironlake_display_wm_info = {
3721 ILK_DISPLAY_FIFO,
3722 ILK_DISPLAY_MAXWM,
3723 ILK_DISPLAY_DFTWM,
3724 2,
3725 ILK_FIFO_LINE_SIZE
3726};
3727static const struct intel_watermark_params ironlake_cursor_wm_info = {
3728 ILK_CURSOR_FIFO,
3729 ILK_CURSOR_MAXWM,
3730 ILK_CURSOR_DFTWM,
3731 2,
3732 ILK_FIFO_LINE_SIZE
3733};
3734static const struct intel_watermark_params ironlake_display_srwm_info = {
3735 ILK_DISPLAY_SR_FIFO,
3736 ILK_DISPLAY_MAX_SRWM,
3737 ILK_DISPLAY_DFT_SRWM,
3738 2,
3739 ILK_FIFO_LINE_SIZE
3740};
3741static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3742 ILK_CURSOR_SR_FIFO,
3743 ILK_CURSOR_MAX_SRWM,
3744 ILK_CURSOR_DFT_SRWM,
3745 2,
3746 ILK_FIFO_LINE_SIZE
3747};
3748
3749static const struct intel_watermark_params sandybridge_display_wm_info = {
3750 SNB_DISPLAY_FIFO,
3751 SNB_DISPLAY_MAXWM,
3752 SNB_DISPLAY_DFTWM,
3753 2,
3754 SNB_FIFO_LINE_SIZE
3755};
3756static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3757 SNB_CURSOR_FIFO,
3758 SNB_CURSOR_MAXWM,
3759 SNB_CURSOR_DFTWM,
3760 2,
3761 SNB_FIFO_LINE_SIZE
3762};
3763static const struct intel_watermark_params sandybridge_display_srwm_info = {
3764 SNB_DISPLAY_SR_FIFO,
3765 SNB_DISPLAY_MAX_SRWM,
3766 SNB_DISPLAY_DFT_SRWM,
3767 2,
3768 SNB_FIFO_LINE_SIZE
3769};
3770static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3771 SNB_CURSOR_SR_FIFO,
3772 SNB_CURSOR_MAX_SRWM,
3773 SNB_CURSOR_DFT_SRWM,
3774 2,
3775 SNB_FIFO_LINE_SIZE
3776};
3777
3778
3779/**
3780 * intel_calculate_wm - calculate watermark level
3781 * @clock_in_khz: pixel clock
3782 * @wm: chip FIFO params
3783 * @pixel_size: display pixel size
3784 * @latency_ns: memory latency for the platform
3785 *
3786 * Calculate the watermark level (the level at which the display plane will
3787 * start fetching from memory again). Each chip has a different display
3788 * FIFO size and allocation, so the caller needs to figure that out and pass
3789 * in the correct intel_watermark_params structure.
3790 *
3791 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3792 * on the pixel size. When it reaches the watermark level, it'll start
3793 * fetching FIFO line sized based chunks from memory until the FIFO fills
3794 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3795 * will occur, and a display engine hang could result.
3796 */
3797static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3798 const struct intel_watermark_params *wm,
3799 int fifo_size,
3800 int pixel_size,
3801 unsigned long latency_ns)
3802{
3803 long entries_required, wm_size;
3804
3805 /*
3806 * Note: we need to make sure we don't overflow for various clock &
3807 * latency values.
3808 * clocks go from a few thousand to several hundred thousand.
3809 * latency is usually a few thousand
3810 */
3811 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3812 1000;
3813 entries_required = howmany(entries_required, wm->cacheline_size);
3814
3815 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3816
3817 wm_size = fifo_size - (entries_required + wm->guard_size);
3818
3819 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3820
3821 /* Don't promote wm_size to unsigned... */
3822 if (wm_size > (long)wm->max_wm)
3823 wm_size = wm->max_wm;
3824 if (wm_size <= 0)
3825 wm_size = wm->default_wm;
3826 return wm_size;
3827}
3828
3829struct cxsr_latency {
3830 int is_desktop;
3831 int is_ddr3;
3832 unsigned long fsb_freq;
3833 unsigned long mem_freq;
3834 unsigned long display_sr;
3835 unsigned long display_hpll_disable;
3836 unsigned long cursor_sr;
3837 unsigned long cursor_hpll_disable;
3838};
3839
3840static const struct cxsr_latency cxsr_latency_table[] = {
3841 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3842 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3843 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3844 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3845 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3846
3847 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3848 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3849 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3850 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3851 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3852
3853 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3854 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3855 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3856 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3857 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3858
3859 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3860 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3861 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3862 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3863 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3864
3865 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3866 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3867 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3868 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3869 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3870
3871 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3872 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3873 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3874 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3875 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3876};
3877
3878static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3879 int is_ddr3,
3880 int fsb,
3881 int mem)
3882{
3883 const struct cxsr_latency *latency;
3884 int i;
3885
3886 if (fsb == 0 || mem == 0)
3887 return NULL;
3888
3889 for (i = 0; i < DRM_ARRAY_SIZE(cxsr_latency_table); i++) {
3890 latency = &cxsr_latency_table[i];
3891 if (is_desktop == latency->is_desktop &&
3892 is_ddr3 == latency->is_ddr3 &&
3893 fsb == latency->fsb_freq && mem == latency->mem_freq)
3894 return latency;
3895 }
3896
3897 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3898
3899 return NULL;
3900}
3901
3902static void pineview_disable_cxsr(struct drm_device *dev)
3903{
3904 struct drm_i915_private *dev_priv = dev->dev_private;
3905
3906 /* deactivate cxsr */
3907 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3908}
3909
3910/*
3911 * Latency for FIFO fetches is dependent on several factors:
3912 * - memory configuration (speed, channels)
3913 * - chipset
3914 * - current MCH state
3915 * It can be fairly high in some situations, so here we assume a fairly
3916 * pessimal value. It's a tradeoff between extra memory fetches (if we
3917 * set this value too high, the FIFO will fetch frequently to stay full)
3918 * and power consumption (set it too low to save power and we might see
3919 * FIFO underruns and display "flicker").
3920 *
3921 * A value of 5us seems to be a good balance; safe for very low end
3922 * platforms but not overly aggressive on lower latency configs.
3923 */
3924static const int latency_ns = 5000;
3925
3926static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3927{
3928 struct drm_i915_private *dev_priv = dev->dev_private;
3929 uint32_t dsparb = I915_READ(DSPARB);
3930 int size;
3931
3932 size = dsparb & 0x7f;
3933 if (plane)
3934 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3935
3936 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3937 plane ? "B" : "A", size);
3938
3939 return size;
3940}
3941
3942static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3943{
3944 struct drm_i915_private *dev_priv = dev->dev_private;
3945 uint32_t dsparb = I915_READ(DSPARB);
3946 int size;
3947
3948 size = dsparb & 0x1ff;
3949 if (plane)
3950 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3951 size >>= 1; /* Convert to cachelines */
3952
3953 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3954 plane ? "B" : "A", size);
3955
3956 return size;
3957}
3958
3959static int i845_get_fifo_size(struct drm_device *dev, int plane)
3960{
3961 struct drm_i915_private *dev_priv = dev->dev_private;
3962 uint32_t dsparb = I915_READ(DSPARB);
3963 int size;
3964
3965 size = dsparb & 0x7f;
3966 size >>= 2; /* Convert to cachelines */
3967
3968 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3969 plane ? "B" : "A",
3970 size);
3971
3972 return size;
3973}
3974
3975static int i830_get_fifo_size(struct drm_device *dev, int plane)
3976{
3977 struct drm_i915_private *dev_priv = dev->dev_private;
3978 uint32_t dsparb = I915_READ(DSPARB);
3979 int size;
3980
3981 size = dsparb & 0x7f;
3982 size >>= 1; /* Convert to cachelines */
3983
3984 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3985 plane ? "B" : "A", size);
3986
3987 return size;
3988}
3989
3990static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3991{
3992 struct drm_crtc *crtc, *enabled = NULL;
3993
3994 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3995 if (crtc->enabled && crtc->fb) {
3996 if (enabled)
3997 return NULL;
3998 enabled = crtc;
3999 }
4000 }
4001
4002 return enabled;
4003}
4004
4005static void pineview_update_wm(struct drm_device *dev)
4006{
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 struct drm_crtc *crtc;
4009 const struct cxsr_latency *latency;
4010 u32 reg;
4011 unsigned long wm;
4012
4013 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
4014 dev_priv->fsb_freq, dev_priv->mem_freq);
4015 if (!latency) {
4016 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
4017 pineview_disable_cxsr(dev);
4018 return;
4019 }
4020
4021 crtc = single_enabled_crtc(dev);
4022 if (crtc) {
4023 int clock = crtc->mode.clock;
4024 int pixel_size = crtc->fb->bits_per_pixel / 8;
4025
4026 /* Display SR */
4027 wm = intel_calculate_wm(clock, &pineview_display_wm,
4028 pineview_display_wm.fifo_size,
4029 pixel_size, latency->display_sr);
4030 reg = I915_READ(DSPFW1);
4031 reg &= ~DSPFW_SR_MASK;
4032 reg |= wm << DSPFW_SR_SHIFT;
4033 I915_WRITE(DSPFW1, reg);
4034 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
4035
4036 /* cursor SR */
4037 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
4038 pineview_display_wm.fifo_size,
4039 pixel_size, latency->cursor_sr);
4040 reg = I915_READ(DSPFW3);
4041 reg &= ~DSPFW_CURSOR_SR_MASK;
4042 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
4043 I915_WRITE(DSPFW3, reg);
4044
4045 /* Display HPLL off SR */
4046 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4047 pineview_display_hplloff_wm.fifo_size,
4048 pixel_size, latency->display_hpll_disable);
4049 reg = I915_READ(DSPFW3);
4050 reg &= ~DSPFW_HPLL_SR_MASK;
4051 reg |= wm & DSPFW_HPLL_SR_MASK;
4052 I915_WRITE(DSPFW3, reg);
4053
4054 /* cursor HPLL off SR */
4055 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4056 pineview_display_hplloff_wm.fifo_size,
4057 pixel_size, latency->cursor_hpll_disable);
4058 reg = I915_READ(DSPFW3);
4059 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4060 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4061 I915_WRITE(DSPFW3, reg);
4062 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4063
4064 /* activate cxsr */
4065 I915_WRITE(DSPFW3,
4066 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4067 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4068 } else {
4069 pineview_disable_cxsr(dev);
4070 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4071 }
4072}
4073
4074static bool g4x_compute_wm0(struct drm_device *dev,
4075 int plane,
4076 const struct intel_watermark_params *display,
4077 int display_latency_ns,
4078 const struct intel_watermark_params *cursor,
4079 int cursor_latency_ns,
4080 int *plane_wm,
4081 int *cursor_wm)
4082{
4083 struct drm_crtc *crtc;
4084 int htotal, hdisplay, clock, pixel_size;
4085 int line_time_us, line_count;
4086 int entries, tlb_miss;
4087
4088 crtc = intel_get_crtc_for_plane(dev, plane);
4089 if (crtc->fb == NULL || !crtc->enabled) {
4090 *cursor_wm = cursor->guard_size;
4091 *plane_wm = display->guard_size;
4092 return false;
4093 }
4094
4095 htotal = crtc->mode.htotal;
4096 hdisplay = crtc->mode.hdisplay;
4097 clock = crtc->mode.clock;
4098 pixel_size = crtc->fb->bits_per_pixel / 8;
4099
4100 /* Use the small buffer method to calculate plane watermark */
4101 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4102 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4103 if (tlb_miss > 0)
4104 entries += tlb_miss;
4105 entries = howmany(entries, display->cacheline_size);
4106 *plane_wm = entries + display->guard_size;
4107 if (*plane_wm > (int)display->max_wm)
4108 *plane_wm = display->max_wm;
4109
4110 /* Use the large buffer method to calculate cursor watermark */
4111 line_time_us = ((htotal * 1000) / clock);
4112 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4113 entries = line_count * 64 * pixel_size;
4114 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4115 if (tlb_miss > 0)
4116 entries += tlb_miss;
4117 entries = howmany(entries, cursor->cacheline_size);
4118 *cursor_wm = entries + cursor->guard_size;
4119 if (*cursor_wm > (int)cursor->max_wm)
4120 *cursor_wm = (int)cursor->max_wm;
4121
4122 return true;
4123}
4124
4125/*
4126 * Check the wm result.
4127 *
4128 * If any calculated watermark values is larger than the maximum value that
4129 * can be programmed into the associated watermark register, that watermark
4130 * must be disabled.
4131 */
4132static bool g4x_check_srwm(struct drm_device *dev,
4133 int display_wm, int cursor_wm,
4134 const struct intel_watermark_params *display,
4135 const struct intel_watermark_params *cursor)
4136{
4137 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4138 display_wm, cursor_wm);
4139
4140 if (display_wm > display->max_wm) {
4141 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4142 display_wm, display->max_wm);
4143 return false;
4144 }
4145
4146 if (cursor_wm > cursor->max_wm) {
4147 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4148 cursor_wm, cursor->max_wm);
4149 return false;
4150 }
4151
4152 if (!(display_wm || cursor_wm)) {
4153 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4154 return false;
4155 }
4156
4157 return true;
4158}
4159
4160static bool g4x_compute_srwm(struct drm_device *dev,
4161 int plane,
4162 int latency_ns,
4163 const struct intel_watermark_params *display,
4164 const struct intel_watermark_params *cursor,
4165 int *display_wm, int *cursor_wm)
4166{
4167 struct drm_crtc *crtc;
4168 int hdisplay, htotal, pixel_size, clock;
4169 unsigned long line_time_us;
4170 int line_count, line_size;
4171 int small, large;
4172 int entries;
4173
4174 if (!latency_ns) {
4175 *display_wm = *cursor_wm = 0;
4176 return false;
4177 }
4178
4179 crtc = intel_get_crtc_for_plane(dev, plane);
4180 hdisplay = crtc->mode.hdisplay;
4181 htotal = crtc->mode.htotal;
4182 clock = crtc->mode.clock;
4183 pixel_size = crtc->fb->bits_per_pixel / 8;
4184
4185 line_time_us = (htotal * 1000) / clock;
4186 line_count = (latency_ns / line_time_us + 1000) / 1000;
4187 line_size = hdisplay * pixel_size;
4188
4189 /* Use the minimum of the small and large buffer method for primary */
4190 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4191 large = line_count * line_size;
4192
4193 entries = howmany(min(small, large), display->cacheline_size);
4194 *display_wm = entries + display->guard_size;
4195
4196 /* calculate the self-refresh watermark for display cursor */
4197 entries = line_count * pixel_size * 64;
4198 entries = howmany(entries, cursor->cacheline_size);
4199 *cursor_wm = entries + cursor->guard_size;
4200
4201 return g4x_check_srwm(dev,
4202 *display_wm, *cursor_wm,
4203 display, cursor);
4204}
4205
4206#define single_plane_enabled(mask) ((mask) != 0 && powerof2(mask))
4207
4208static void g4x_update_wm(struct drm_device *dev)
4209{
4210 static const int sr_latency_ns = 12000;
4211 struct drm_i915_private *dev_priv = dev->dev_private;
4212 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4213 int plane_sr, cursor_sr;
4214 unsigned int enabled = 0;
4215
4216 if (g4x_compute_wm0(dev, 0,
4217 &g4x_wm_info, latency_ns,
4218 &g4x_cursor_wm_info, latency_ns,
4219 &planea_wm, &cursora_wm))
4220 enabled |= 1;
4221
4222 if (g4x_compute_wm0(dev, 1,
4223 &g4x_wm_info, latency_ns,
4224 &g4x_cursor_wm_info, latency_ns,
4225 &planeb_wm, &cursorb_wm))
4226 enabled |= 2;
4227
4228 plane_sr = cursor_sr = 0;
4229 if (single_plane_enabled(enabled) &&
4230 g4x_compute_srwm(dev, ffs(enabled) - 1,
4231 sr_latency_ns,
4232 &g4x_wm_info,
4233 &g4x_cursor_wm_info,
4234 &plane_sr, &cursor_sr))
4235 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4236 else
4237 I915_WRITE(FW_BLC_SELF,
4238 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4239
4240 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4241 planea_wm, cursora_wm,
4242 planeb_wm, cursorb_wm,
4243 plane_sr, cursor_sr);
4244
4245 I915_WRITE(DSPFW1,
4246 (plane_sr << DSPFW_SR_SHIFT) |
4247 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4248 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4249 planea_wm);
4250 I915_WRITE(DSPFW2,
4251 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4252 (cursora_wm << DSPFW_CURSORA_SHIFT));
4253 /* HPLL off in SR has some issues on G4x... disable it */
4254 I915_WRITE(DSPFW3,
4255 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4256 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4257}
4258
4259static void i965_update_wm(struct drm_device *dev)
4260{
4261 struct drm_i915_private *dev_priv = dev->dev_private;
4262 struct drm_crtc *crtc;
4263 int srwm = 1;
4264 int cursor_sr = 16;
4265
4266 /* Calc sr entries for one plane configs */
4267 crtc = single_enabled_crtc(dev);
4268 if (crtc) {
4269 /* self-refresh has much higher latency */
4270 static const int sr_latency_ns = 12000;
4271 int clock = crtc->mode.clock;
4272 int htotal = crtc->mode.htotal;
4273 int hdisplay = crtc->mode.hdisplay;
4274 int pixel_size = crtc->fb->bits_per_pixel / 8;
4275 unsigned long line_time_us;
4276 int entries;
4277
4278 line_time_us = ((htotal * 1000) / clock);
4279
4280 /* Use ns/us then divide to preserve precision */
4281 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4282 pixel_size * hdisplay;
4283 entries = howmany(entries, I915_FIFO_LINE_SIZE);
4284 srwm = I965_FIFO_SIZE - entries;
4285 if (srwm < 0)
4286 srwm = 1;
4287 srwm &= 0x1ff;
4288 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4289 entries, srwm);
4290
4291 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4292 pixel_size * 64;
4293 entries = howmany(entries, i965_cursor_wm_info.cacheline_size);
4294 cursor_sr = i965_cursor_wm_info.fifo_size -
4295 (entries + i965_cursor_wm_info.guard_size);
4296
4297 if (cursor_sr > i965_cursor_wm_info.max_wm)
4298 cursor_sr = i965_cursor_wm_info.max_wm;
4299
4300 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4301 "cursor %d\n", srwm, cursor_sr);
4302
4303 if (IS_CRESTLINE(dev))
4304 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4305 } else {
4306 /* Turn off self refresh if both pipes are enabled */
4307 if (IS_CRESTLINE(dev))
4308 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4309 & ~FW_BLC_SELF_EN);
4310 }
4311
4312 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4313 srwm);
4314
4315 /* 965 has limitations... */
4316 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4317 (8 << 16) | (8 << 8) | (8 << 0));
4318 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4319 /* update cursor SR watermark */
4320 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4321}
4322
4323static void i9xx_update_wm(struct drm_device *dev)
4324{
4325 struct drm_i915_private *dev_priv = dev->dev_private;
4326 const struct intel_watermark_params *wm_info;
4327 uint32_t fwater_lo;
4328 uint32_t fwater_hi;
4329 int cwm, srwm = 1;
4330 int fifo_size;
4331 int planea_wm, planeb_wm;
4332 struct drm_crtc *crtc, *enabled = NULL;
4333
4334 if (IS_I945GM(dev))
4335 wm_info = &i945_wm_info;
4336 else if (!IS_GEN2(dev))
4337 wm_info = &i915_wm_info;
4338 else
4339 wm_info = &i855_wm_info;
4340
4341 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4342 crtc = intel_get_crtc_for_plane(dev, 0);
4343 if (crtc->enabled && crtc->fb) {
4344 planea_wm = intel_calculate_wm(crtc->mode.clock,
4345 wm_info, fifo_size,
4346 crtc->fb->bits_per_pixel / 8,
4347 latency_ns);
4348 enabled = crtc;
4349 } else
4350 planea_wm = fifo_size - wm_info->guard_size;
4351
4352 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4353 crtc = intel_get_crtc_for_plane(dev, 1);
4354 if (crtc->enabled && crtc->fb) {
4355 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4356 wm_info, fifo_size,
4357 crtc->fb->bits_per_pixel / 8,
4358 latency_ns);
4359 if (enabled == NULL)
4360 enabled = crtc;
4361 else
4362 enabled = NULL;
4363 } else
4364 planeb_wm = fifo_size - wm_info->guard_size;
4365
4366 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4367
4368 /*
4369 * Overlay gets an aggressive default since video jitter is bad.
4370 */
4371 cwm = 2;
4372
4373 /* Play safe and disable self-refresh before adjusting watermarks. */
4374 if (IS_I945G(dev) || IS_I945GM(dev))
4375 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4376 else if (IS_I915GM(dev))
4377 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4378
4379 /* Calc sr entries for one plane configs */
4380 if (HAS_FW_BLC(dev) && enabled) {
4381 /* self-refresh has much higher latency */
4382 static const int sr_latency_ns = 6000;
4383 int clock = enabled->mode.clock;
4384 int htotal = enabled->mode.htotal;
4385 int hdisplay = enabled->mode.hdisplay;
4386 int pixel_size = enabled->fb->bits_per_pixel / 8;
4387 unsigned long line_time_us;
4388 int entries;
4389
4390 line_time_us = (htotal * 1000) / clock;
4391
4392 /* Use ns/us then divide to preserve precision */
4393 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4394 pixel_size * hdisplay;
4395 entries = howmany(entries, wm_info->cacheline_size);
4396 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4397 srwm = wm_info->fifo_size - entries;
4398 if (srwm < 0)
4399 srwm = 1;
4400
4401 if (IS_I945G(dev) || IS_I945GM(dev))
4402 I915_WRITE(FW_BLC_SELF,
4403 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4404 else if (IS_I915GM(dev))
4405 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4406 }
4407
4408 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4409 planea_wm, planeb_wm, cwm, srwm);
4410
4411 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4412 fwater_hi = (cwm & 0x1f);
4413
4414 /* Set request length to 8 cachelines per fetch */
4415 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4416 fwater_hi = fwater_hi | (1 << 8);
4417
4418 I915_WRITE(FW_BLC, fwater_lo);
4419 I915_WRITE(FW_BLC2, fwater_hi);
4420
4421 if (HAS_FW_BLC(dev)) {
4422 if (enabled) {
4423 if (IS_I945G(dev) || IS_I945GM(dev))
4424 I915_WRITE(FW_BLC_SELF,
4425 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4426 else if (IS_I915GM(dev))
4427 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4428 DRM_DEBUG_KMS("memory self refresh enabled\n");
4429 } else
4430 DRM_DEBUG_KMS("memory self refresh disabled\n");
4431 }
4432}
4433
4434static void i830_update_wm(struct drm_device *dev)
4435{
4436 struct drm_i915_private *dev_priv = dev->dev_private;
4437 struct drm_crtc *crtc;
4438 uint32_t fwater_lo;
4439 int planea_wm;
4440
4441 crtc = single_enabled_crtc(dev);
4442 if (crtc == NULL)
4443 return;
4444
4445 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4446 dev_priv->display.get_fifo_size(dev, 0),
4447 crtc->fb->bits_per_pixel / 8,
4448 latency_ns);
4449 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4450 fwater_lo |= (3<<8) | planea_wm;
4451
4452 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4453
4454 I915_WRITE(FW_BLC, fwater_lo);
4455}
4456
4457#define ILK_LP0_PLANE_LATENCY 700
4458#define ILK_LP0_CURSOR_LATENCY 1300
4459
4460/*
4461 * Check the wm result.
4462 *
4463 * If any calculated watermark values is larger than the maximum value that
4464 * can be programmed into the associated watermark register, that watermark
4465 * must be disabled.
4466 */
4467static bool ironlake_check_srwm(struct drm_device *dev, int level,
4468 int fbc_wm, int display_wm, int cursor_wm,
4469 const struct intel_watermark_params *display,
4470 const struct intel_watermark_params *cursor)
4471{
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473
4474 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4475 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4476
4477 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4478 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4479 fbc_wm, SNB_FBC_MAX_SRWM, level);
4480
4481 /* fbc has it's own way to disable FBC WM */
4482 I915_WRITE(DISP_ARB_CTL,
4483 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4484 return false;
4485 }
4486
4487 if (display_wm > display->max_wm) {
4488 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4489 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4490 return false;
4491 }
4492
4493 if (cursor_wm > cursor->max_wm) {
4494 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4495 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4496 return false;
4497 }
4498
4499 if (!(fbc_wm || display_wm || cursor_wm)) {
4500 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4501 return false;
4502 }
4503
4504 return true;
4505}
4506
4507/*
4508 * Compute watermark values of WM[1-3],
4509 */
4510static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4511 int latency_ns,
4512 const struct intel_watermark_params *display,
4513 const struct intel_watermark_params *cursor,
4514 int *fbc_wm, int *display_wm, int *cursor_wm)
4515{
4516 struct drm_crtc *crtc;
4517 unsigned long line_time_us;
4518 int hdisplay, htotal, pixel_size, clock;
4519 int line_count, line_size;
4520 int small, large;
4521 int entries;
4522
4523 if (!latency_ns) {
4524 *fbc_wm = *display_wm = *cursor_wm = 0;
4525 return false;
4526 }
4527
4528 crtc = intel_get_crtc_for_plane(dev, plane);
4529 hdisplay = crtc->mode.hdisplay;
4530 htotal = crtc->mode.htotal;
4531 clock = crtc->mode.clock;
4532 pixel_size = crtc->fb->bits_per_pixel / 8;
4533
4534 line_time_us = (htotal * 1000) / clock;
4535 line_count = (latency_ns / line_time_us + 1000) / 1000;
4536 line_size = hdisplay * pixel_size;
4537
4538 /* Use the minimum of the small and large buffer method for primary */
4539 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4540 large = line_count * line_size;
4541
4542 entries = howmany(min(small, large), display->cacheline_size);
4543 *display_wm = entries + display->guard_size;
4544
4545 /*
4546 * Spec says:
4547 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4548 */
4549 *fbc_wm = howmany(*display_wm * 64, line_size) + 2;
4550
4551 /* calculate the self-refresh watermark for display cursor */
4552 entries = line_count * pixel_size * 64;
4553 entries = howmany(entries, cursor->cacheline_size);
4554 *cursor_wm = entries + cursor->guard_size;
4555
4556 return ironlake_check_srwm(dev, level,
4557 *fbc_wm, *display_wm, *cursor_wm,
4558 display, cursor);
4559}
4560
4561static void ironlake_update_wm(struct drm_device *dev)
4562{
4563 struct drm_i915_private *dev_priv = dev->dev_private;
4564 int fbc_wm, plane_wm, cursor_wm;
4565 unsigned int enabled;
4566
4567 enabled = 0;
4568 if (g4x_compute_wm0(dev, 0,
4569 &ironlake_display_wm_info,
4570 ILK_LP0_PLANE_LATENCY,
4571 &ironlake_cursor_wm_info,
4572 ILK_LP0_CURSOR_LATENCY,
4573 &plane_wm, &cursor_wm)) {
4574 I915_WRITE(WM0_PIPEA_ILK,
4575 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4576 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4577 " plane %d, " "cursor: %d\n",
4578 plane_wm, cursor_wm);
4579 enabled |= 1;
4580 }
4581
4582 if (g4x_compute_wm0(dev, 1,
4583 &ironlake_display_wm_info,
4584 ILK_LP0_PLANE_LATENCY,
4585 &ironlake_cursor_wm_info,
4586 ILK_LP0_CURSOR_LATENCY,
4587 &plane_wm, &cursor_wm)) {
4588 I915_WRITE(WM0_PIPEB_ILK,
4589 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4590 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4591 " plane %d, cursor: %d\n",
4592 plane_wm, cursor_wm);
4593 enabled |= 2;
4594 }
4595
4596 /*
4597 * Calculate and update the self-refresh watermark only when one
4598 * display plane is used.
4599 */
4600 I915_WRITE(WM3_LP_ILK, 0);
4601 I915_WRITE(WM2_LP_ILK, 0);
4602 I915_WRITE(WM1_LP_ILK, 0);
4603
4604 if (!single_plane_enabled(enabled))
4605 return;
4606 enabled = ffs(enabled) - 1;
4607
4608 /* WM1 */
4609 if (!ironlake_compute_srwm(dev, 1, enabled,
4610 ILK_READ_WM1_LATENCY() * 500,
4611 &ironlake_display_srwm_info,
4612 &ironlake_cursor_srwm_info,
4613 &fbc_wm, &plane_wm, &cursor_wm))
4614 return;
4615
4616 I915_WRITE(WM1_LP_ILK,
4617 WM1_LP_SR_EN |
4618 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4619 (fbc_wm << WM1_LP_FBC_SHIFT) |
4620 (plane_wm << WM1_LP_SR_SHIFT) |
4621 cursor_wm);
4622
4623 /* WM2 */
4624 if (!ironlake_compute_srwm(dev, 2, enabled,
4625 ILK_READ_WM2_LATENCY() * 500,
4626 &ironlake_display_srwm_info,
4627 &ironlake_cursor_srwm_info,
4628 &fbc_wm, &plane_wm, &cursor_wm))
4629 return;
4630
4631 I915_WRITE(WM2_LP_ILK,
4632 WM2_LP_EN |
4633 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4634 (fbc_wm << WM1_LP_FBC_SHIFT) |
4635 (plane_wm << WM1_LP_SR_SHIFT) |
4636 cursor_wm);
4637
4638 /*
4639 * WM3 is unsupported on ILK, probably because we don't have latency
4640 * data for that power state
4641 */
4642}
4643
4644void sandybridge_update_wm(struct drm_device *dev)
4645{
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4647 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4648 u32 val;
4649 int fbc_wm, plane_wm, cursor_wm;
4650 unsigned int enabled;
4651
4652 enabled = 0;
4653 if (g4x_compute_wm0(dev, 0,
4654 &sandybridge_display_wm_info, latency,
4655 &sandybridge_cursor_wm_info, latency,
4656 &plane_wm, &cursor_wm)) {
4657 val = I915_READ(WM0_PIPEA_ILK);
4658 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4659 I915_WRITE(WM0_PIPEA_ILK, val |
4660 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4661 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4662 " plane %d, " "cursor: %d\n",
4663 plane_wm, cursor_wm);
4664 enabled |= 1;
4665 }
4666
4667 if (g4x_compute_wm0(dev, 1,
4668 &sandybridge_display_wm_info, latency,
4669 &sandybridge_cursor_wm_info, latency,
4670 &plane_wm, &cursor_wm)) {
4671 val = I915_READ(WM0_PIPEB_ILK);
4672 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4673 I915_WRITE(WM0_PIPEB_ILK, val |
4674 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4675 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4676 " plane %d, cursor: %d\n",
4677 plane_wm, cursor_wm);
4678 enabled |= 2;
4679 }
4680
4681 /* IVB has 3 pipes */
4682 if (IS_IVYBRIDGE(dev) &&
4683 g4x_compute_wm0(dev, 2,
4684 &sandybridge_display_wm_info, latency,
4685 &sandybridge_cursor_wm_info, latency,
4686 &plane_wm, &cursor_wm)) {
4687 val = I915_READ(WM0_PIPEC_IVB);
4688 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4689 I915_WRITE(WM0_PIPEC_IVB, val |
4690 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4691 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4692 " plane %d, cursor: %d\n",
4693 plane_wm, cursor_wm);
4694 enabled |= 3;
4695 }
4696
4697 /*
4698 * Calculate and update the self-refresh watermark only when one
4699 * display plane is used.
4700 *
4701 * SNB support 3 levels of watermark.
4702 *
4703 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4704 * and disabled in the descending order
4705 *
4706 */
4707 I915_WRITE(WM3_LP_ILK, 0);
4708 I915_WRITE(WM2_LP_ILK, 0);
4709 I915_WRITE(WM1_LP_ILK, 0);
4710
4711 if (!single_plane_enabled(enabled) ||
4712 dev_priv->sprite_scaling_enabled)
4713 return;
4714 enabled = ffs(enabled) - 1;
4715
4716 /* WM1 */
4717 if (!ironlake_compute_srwm(dev, 1, enabled,
4718 SNB_READ_WM1_LATENCY() * 500,
4719 &sandybridge_display_srwm_info,
4720 &sandybridge_cursor_srwm_info,
4721 &fbc_wm, &plane_wm, &cursor_wm))
4722 return;
4723
4724 I915_WRITE(WM1_LP_ILK,
4725 WM1_LP_SR_EN |
4726 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4727 (fbc_wm << WM1_LP_FBC_SHIFT) |
4728 (plane_wm << WM1_LP_SR_SHIFT) |
4729 cursor_wm);
4730
4731 /* WM2 */
4732 if (!ironlake_compute_srwm(dev, 2, enabled,
4733 SNB_READ_WM2_LATENCY() * 500,
4734 &sandybridge_display_srwm_info,
4735 &sandybridge_cursor_srwm_info,
4736 &fbc_wm, &plane_wm, &cursor_wm))
4737 return;
4738
4739 I915_WRITE(WM2_LP_ILK,
4740 WM2_LP_EN |
4741 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4742 (fbc_wm << WM1_LP_FBC_SHIFT) |
4743 (plane_wm << WM1_LP_SR_SHIFT) |
4744 cursor_wm);
4745
4746 /* WM3 */
4747 if (!ironlake_compute_srwm(dev, 3, enabled,
4748 SNB_READ_WM3_LATENCY() * 500,
4749 &sandybridge_display_srwm_info,
4750 &sandybridge_cursor_srwm_info,
4751 &fbc_wm, &plane_wm, &cursor_wm))
4752 return;
4753
4754 I915_WRITE(WM3_LP_ILK,
4755 WM3_LP_EN |
4756 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4757 (fbc_wm << WM1_LP_FBC_SHIFT) |
4758 (plane_wm << WM1_LP_SR_SHIFT) |
4759 cursor_wm);
4760}
4761
4762static bool
4763sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4764 uint32_t sprite_width, int pixel_size,
4765 const struct intel_watermark_params *display,
4766 int display_latency_ns, int *sprite_wm)
4767{
4768 struct drm_crtc *crtc;
4769 int clock;
4770 int entries, tlb_miss;
4771
4772 crtc = intel_get_crtc_for_plane(dev, plane);
4773 if (crtc->fb == NULL || !crtc->enabled) {
4774 *sprite_wm = display->guard_size;
4775 return false;
4776 }
4777
4778 clock = crtc->mode.clock;
4779
4780 /* Use the small buffer method to calculate the sprite watermark */
4781 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4782 tlb_miss = display->fifo_size*display->cacheline_size -
4783 sprite_width * 8;
4784 if (tlb_miss > 0)
4785 entries += tlb_miss;
4786 entries = howmany(entries, display->cacheline_size);
4787 *sprite_wm = entries + display->guard_size;
4788 if (*sprite_wm > (int)display->max_wm)
4789 *sprite_wm = display->max_wm;
4790
4791 return true;
4792}
4793
4794static bool
4795sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4796 uint32_t sprite_width, int pixel_size,
4797 const struct intel_watermark_params *display,
4798 int latency_ns, int *sprite_wm)
4799{
4800 struct drm_crtc *crtc;
4801 unsigned long line_time_us;
4802 int clock;
4803 int line_count, line_size;
4804 int small, large;
4805 int entries;
4806
4807 if (!latency_ns) {
4808 *sprite_wm = 0;
4809 return false;
4810 }
4811
4812 crtc = intel_get_crtc_for_plane(dev, plane);
4813 clock = crtc->mode.clock;
4814 if (!clock) {
4815 *sprite_wm = 0;
4816 return false;
4817 }
4818
4819 line_time_us = (sprite_width * 1000) / clock;
4820 if (!line_time_us) {
4821 *sprite_wm = 0;
4822 return false;
4823 }
4824
4825 line_count = (latency_ns / line_time_us + 1000) / 1000;
4826 line_size = sprite_width * pixel_size;
4827
4828 /* Use the minimum of the small and large buffer method for primary */
4829 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4830 large = line_count * line_size;
4831
4832 entries = howmany(min(small, large), display->cacheline_size);
4833 *sprite_wm = entries + display->guard_size;
4834
4835 return *sprite_wm > 0x3ff ? false : true;
4836}
4837
4838static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4839 uint32_t sprite_width, int pixel_size)
4840{
4841 struct drm_i915_private *dev_priv = dev->dev_private;
4842 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4843 u32 val;
4844 int sprite_wm, reg;
4845 int ret;
4846
4847 switch (pipe) {
4848 case 0:
4849 reg = WM0_PIPEA_ILK;
4850 break;
4851 case 1:
4852 reg = WM0_PIPEB_ILK;
4853 break;
4854 case 2:
4855 reg = WM0_PIPEC_IVB;
4856 break;
4857 default:
4858 return; /* bad pipe */
4859 }
4860
4861 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4862 &sandybridge_display_wm_info,
4863 latency, &sprite_wm);
4864 if (!ret) {
4865 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4866 pipe);
4867 return;
4868 }
4869
4870 val = I915_READ(reg);
4871 val &= ~WM0_PIPE_SPRITE_MASK;
4872 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4873 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4874
4875
4876 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4877 pixel_size,
4878 &sandybridge_display_srwm_info,
4879 SNB_READ_WM1_LATENCY() * 500,
4880 &sprite_wm);
4881 if (!ret) {
4882 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4883 pipe);
4884 return;
4885 }
4886 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4887
4888 /* Only IVB has two more LP watermarks for sprite */
4889 if (!IS_IVYBRIDGE(dev))
4890 return;
4891
4892 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4893 pixel_size,
4894 &sandybridge_display_srwm_info,
4895 SNB_READ_WM2_LATENCY() * 500,
4896 &sprite_wm);
4897 if (!ret) {
4898 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4899 pipe);
4900 return;
4901 }
4902 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4903
4904 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4905 pixel_size,
4906 &sandybridge_display_srwm_info,
4907 SNB_READ_WM3_LATENCY() * 500,
4908 &sprite_wm);
4909 if (!ret) {
4910 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4911 pipe);
4912 return;
4913 }
4914 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4915}
4916
4917/**
4918 * intel_update_watermarks - update FIFO watermark values based on current modes
4919 *
4920 * Calculate watermark values for the various WM regs based on current mode
4921 * and plane configuration.
4922 *
4923 * There are several cases to deal with here:
4924 * - normal (i.e. non-self-refresh)
4925 * - self-refresh (SR) mode
4926 * - lines are large relative to FIFO size (buffer can hold up to 2)
4927 * - lines are small relative to FIFO size (buffer can hold more than 2
4928 * lines), so need to account for TLB latency
4929 *
4930 * The normal calculation is:
4931 * watermark = dotclock * bytes per pixel * latency
4932 * where latency is platform & configuration dependent (we assume pessimal
4933 * values here).
4934 *
4935 * The SR calculation is:
4936 * watermark = (trunc(latency/line time)+1) * surface width *
4937 * bytes per pixel
4938 * where
4939 * line time = htotal / dotclock
4940 * surface width = hdisplay for normal plane and 64 for cursor
4941 * and latency is assumed to be high, as above.
4942 *
4943 * The final value programmed to the register should always be rounded up,
4944 * and include an extra 2 entries to account for clock crossings.
4945 *
4946 * We don't use the sprite, so we can ignore that. And on Crestline we have
4947 * to set the non-SR watermarks to 8.
4948 */
4949static void intel_update_watermarks(struct drm_device *dev)
4950{
4951 struct drm_i915_private *dev_priv = dev->dev_private;
4952
4953 if (dev_priv->display.update_wm)
4954 dev_priv->display.update_wm(dev);
4955}
4956
4957void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4958 uint32_t sprite_width, int pixel_size)
4959{
4960 struct drm_i915_private *dev_priv = dev->dev_private;
4961
4962 if (dev_priv->display.update_sprite_wm)
4963 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4964 pixel_size);
4965}
4966
4967static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4968{
4969 if (i915_panel_use_ssc >= 0)
4970 return i915_panel_use_ssc != 0;
4971 return dev_priv->lvds_use_ssc
4972 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4973}
4974
4975/**
4976 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4977 * @crtc: CRTC structure
4978 * @mode: requested mode
4979 *
4980 * A pipe may be connected to one or more outputs. Based on the depth of the
4981 * attached framebuffer, choose a good color depth to use on the pipe.
4982 *
4983 * If possible, match the pipe depth to the fb depth. In some cases, this
4984 * isn't ideal, because the connected output supports a lesser or restricted
4985 * set of depths. Resolve that here:
4986 * LVDS typically supports only 6bpc, so clamp down in that case
4987 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4988 * Displays may support a restricted set as well, check EDID and clamp as
4989 * appropriate.
4990 * DP may want to dither down to 6bpc to fit larger modes
4991 *
4992 * RETURNS:
4993 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4994 * true if they don't match).
4995 */
4996static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4997 unsigned int *pipe_bpp,
4998 struct drm_display_mode *mode)
4999{
5000 struct drm_device *dev = crtc->dev;
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002 struct drm_encoder *encoder;
5003 struct drm_connector *connector;
5004 unsigned int display_bpc = UINT_MAX, bpc;
5005
5006 /* Walk the encoders & connectors on this crtc, get min bpc */
5007 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5008 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5009
5010 if (encoder->crtc != crtc)
5011 continue;
5012
5013 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
5014 unsigned int lvds_bpc;
5015
5016 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
5017 LVDS_A3_POWER_UP)
5018 lvds_bpc = 8;
5019 else
5020 lvds_bpc = 6;
5021
5022 if (lvds_bpc < display_bpc) {
5023 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5024 display_bpc = lvds_bpc;
5025 }
5026 continue;
5027 }
5028
5029 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
5030 /* Use VBT settings if we have an eDP panel */
5031 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
5032
5033 if (edp_bpc < display_bpc) {
5034 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5035 display_bpc = edp_bpc;
5036 }
5037 continue;
5038 }
5039
5040 /* Not one of the known troublemakers, check the EDID */
5041 list_for_each_entry(connector, &dev->mode_config.connector_list,
5042 head) {
5043 if (connector->encoder != encoder)
5044 continue;
5045
5046 /* Don't use an invalid EDID bpc value */
5047 if (connector->display_info.bpc &&
5048 connector->display_info.bpc < display_bpc) {
5049 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5050 display_bpc = connector->display_info.bpc;
5051 }
5052 }
5053
5054 /*
5055 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5056 * through, clamp it down. (Note: >12bpc will be caught below.)
5057 */
5058 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5059 if (display_bpc > 8 && display_bpc < 12) {
5060 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5061 display_bpc = 12;
5062 } else {
5063 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5064 display_bpc = 8;
5065 }
5066 }
5067 }
5068
5069 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5070 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5071 display_bpc = 6;
5072 }
5073
5074 /*
5075 * We could just drive the pipe at the highest bpc all the time and
5076 * enable dithering as needed, but that costs bandwidth. So choose
5077 * the minimum value that expresses the full color range of the fb but
5078 * also stays within the max display bpc discovered above.
5079 */
5080
5081 switch (crtc->fb->depth) {
5082 case 8:
5083 bpc = 8; /* since we go through a colormap */
5084 break;
5085 case 15:
5086 case 16:
5087 bpc = 6; /* min is 18bpp */
5088 break;
5089 case 24:
5090 bpc = 8;
5091 break;
5092 case 30:
5093 bpc = 10;
5094 break;
5095 case 48:
5096 bpc = 12;
5097 break;
5098 default:
5099 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5100 bpc = min((unsigned int)8, display_bpc);
5101 break;
5102 }
5103
5104 display_bpc = min(display_bpc, bpc);
5105
5106 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5107 bpc, display_bpc);
5108
5109 *pipe_bpp = display_bpc * 3;
5110
5111 return display_bpc != bpc;
5112}
5113
5114static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5115{
5116 struct drm_device *dev = crtc->dev;
5117 struct drm_i915_private *dev_priv = dev->dev_private;
5118 int refclk;
5119
5120 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5121 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5122 refclk = dev_priv->lvds_ssc_freq * 1000;
5123 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5124 refclk / 1000);
5125 } else if (!IS_GEN2(dev)) {
5126 refclk = 96000;
5127 } else {
5128 refclk = 48000;
5129 }
5130
5131 return refclk;
5132}
5133
5134static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5135 intel_clock_t *clock)
5136{
5137 /* SDVO TV has fixed PLL values depend on its clock range,
5138 this mirrors vbios setting. */
5139 if (adjusted_mode->clock >= 100000
5140 && adjusted_mode->clock < 140500) {
5141 clock->p1 = 2;
5142 clock->p2 = 10;
5143 clock->n = 3;
5144 clock->m1 = 16;
5145 clock->m2 = 8;
5146 } else if (adjusted_mode->clock >= 140500
5147 && adjusted_mode->clock <= 200000) {
5148 clock->p1 = 1;
5149 clock->p2 = 10;
5150 clock->n = 6;
5151 clock->m1 = 12;
5152 clock->m2 = 8;
5153 }
5154}
5155
5156static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5157 intel_clock_t *clock,
5158 intel_clock_t *reduced_clock)
5159{
5160 struct drm_device *dev = crtc->dev;
5161 struct drm_i915_private *dev_priv = dev->dev_private;
5162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5163 int pipe = intel_crtc->pipe;
5164 u32 fp, fp2 = 0;
5165
5166 if (IS_PINEVIEW(dev)) {
5167 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5168 if (reduced_clock)
5169 fp2 = (1 << reduced_clock->n) << 16 |
5170 reduced_clock->m1 << 8 | reduced_clock->m2;
5171 } else {
5172 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5173 if (reduced_clock)
5174 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5175 reduced_clock->m2;
5176 }
5177
5178 I915_WRITE(FP0(pipe), fp);
5179
5180 intel_crtc->lowfreq_avail = false;
5181 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5182 reduced_clock && i915_powersave) {
5183 I915_WRITE(FP1(pipe), fp2);
5184 intel_crtc->lowfreq_avail = true;
5185 } else {
5186 I915_WRITE(FP1(pipe), fp);
5187 }
5188}
5189
5190static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5191 struct drm_display_mode *mode,
5192 struct drm_display_mode *adjusted_mode,
5193 int x, int y,
5194 struct drm_framebuffer *old_fb)
5195{
5196 struct drm_device *dev = crtc->dev;
5197 struct drm_i915_private *dev_priv = dev->dev_private;
5198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5199 int pipe = intel_crtc->pipe;
5200 int plane = intel_crtc->plane;
5201 int refclk, num_connectors = 0;
5202 intel_clock_t clock, reduced_clock;
5203 u32 dpll, dspcntr, pipeconf, vsyncshift;
5204 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5205 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5206 struct drm_mode_config *mode_config = &dev->mode_config;
5207 struct intel_encoder *encoder;
5208 const intel_limit_t *limit;
5209 int ret;
5210 u32 temp;
5211 u32 lvds_sync = 0;
5212
5213 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5214 if (encoder->base.crtc != crtc)
5215 continue;
5216
5217 switch (encoder->type) {
5218 case INTEL_OUTPUT_LVDS:
5219 is_lvds = true;
5220 break;
5221 case INTEL_OUTPUT_SDVO:
5222 case INTEL_OUTPUT_HDMI:
5223 is_sdvo = true;
5224 if (encoder->needs_tv_clock)
5225 is_tv = true;
5226 break;
5227 case INTEL_OUTPUT_DVO:
5228 is_dvo = true;
5229 break;
5230 case INTEL_OUTPUT_TVOUT:
5231 is_tv = true;
5232 break;
5233 case INTEL_OUTPUT_ANALOG:
5234 is_crt = true;
5235 break;
5236 case INTEL_OUTPUT_DISPLAYPORT:
5237 is_dp = true;
5238 break;
5239 }
5240
5241 num_connectors++;
5242 }
5243
5244 refclk = i9xx_get_refclk(crtc, num_connectors);
5245
5246 /*
5247 * Returns a set of divisors for the desired target clock with the given
5248 * refclk, or false. The returned values represent the clock equation:
5249 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5250 */
5251 limit = intel_limit(crtc, refclk);
5252 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5253 &clock);
5254 if (!ok) {
5255 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5256 return -EINVAL;
5257 }
5258
5259 /* Ensure that the cursor is valid for the new mode before changing... */
5260 intel_crtc_update_cursor(crtc, true);
5261
5262 if (is_lvds && dev_priv->lvds_downclock_avail) {
5263 /*
5264 * Ensure we match the reduced clock's P to the target clock.
5265 * If the clocks don't match, we can't switch the display clock
5266 * by using the FP0/FP1. In such case we will disable the LVDS
5267 * downclock feature.
5268 */
5269 has_reduced_clock = limit->find_pll(limit, crtc,
5270 dev_priv->lvds_downclock,
5271 refclk,
5272 &clock,
5273 &reduced_clock);
5274 }
5275
5276 if (is_sdvo && is_tv)
5277 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5278
5279 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5280 &reduced_clock : NULL);
5281
5282 dpll = DPLL_VGA_MODE_DIS;
5283
5284 if (!IS_GEN2(dev)) {
5285 if (is_lvds)
5286 dpll |= DPLLB_MODE_LVDS;
5287 else
5288 dpll |= DPLLB_MODE_DAC_SERIAL;
5289 if (is_sdvo) {
5290 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5291 if (pixel_multiplier > 1) {
5292 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5293 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5294 }
5295 dpll |= DPLL_DVO_HIGH_SPEED;
5296 }
5297 if (is_dp)
5298 dpll |= DPLL_DVO_HIGH_SPEED;
5299
5300 /* compute bitmask from p1 value */
5301 if (IS_PINEVIEW(dev))
5302 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5303 else {
5304 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5305 if (IS_G4X(dev) && has_reduced_clock)
5306 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5307 }
5308 switch (clock.p2) {
5309 case 5:
5310 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5311 break;
5312 case 7:
5313 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5314 break;
5315 case 10:
5316 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5317 break;
5318 case 14:
5319 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5320 break;
5321 }
5322 if (INTEL_INFO(dev)->gen >= 4)
5323 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5324 } else {
5325 if (is_lvds) {
5326 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5327 } else {
5328 if (clock.p1 == 2)
5329 dpll |= PLL_P1_DIVIDE_BY_TWO;
5330 else
5331 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5332 if (clock.p2 == 4)
5333 dpll |= PLL_P2_DIVIDE_BY_4;
5334 }
5335 }
5336
5337 if (is_sdvo && is_tv)
5338 dpll |= PLL_REF_INPUT_TVCLKINBC;
5339 else if (is_tv)
5340 /* XXX: just matching BIOS for now */
5341 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5342 dpll |= 3;
5343 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5344 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5345 else
5346 dpll |= PLL_REF_INPUT_DREFCLK;
5347
5348 /* setup pipeconf */
5349 pipeconf = I915_READ(PIPECONF(pipe));
5350
5351 /* Set up the display plane register */
5352 dspcntr = DISPPLANE_GAMMA_ENABLE;
5353
5354 if (pipe == 0)
5355 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5356 else
5357 dspcntr |= DISPPLANE_SEL_PIPE_B;
5358
5359 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5360 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5361 * core speed.
5362 *
5363 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5364 * pipe == 0 check?
5365 */
5366 if (mode->clock >
5367 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5368 pipeconf |= PIPECONF_DOUBLE_WIDE;
5369 else
5370 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5371 }
5372
5373 /* default to 8bpc */
5374 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5375 if (is_dp) {
5376 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5377 pipeconf |= PIPECONF_BPP_6 |
5378 PIPECONF_DITHER_EN |
5379 PIPECONF_DITHER_TYPE_SP;
5380 }
5381 }
5382
5383 dpll |= DPLL_VCO_ENABLE;
5384
5385 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5386 drm_mode_debug_printmodeline(mode);
5387
5388 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5389
5390 POSTING_READ(DPLL(pipe));
5391 DELAY(150);
5392
5393 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5394 * This is an exception to the general rule that mode_set doesn't turn
5395 * things on.
5396 */
5397 if (is_lvds) {
5398 temp = I915_READ(LVDS);
5399 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5400 if (pipe == 1) {
5401 temp |= LVDS_PIPEB_SELECT;
5402 } else {
5403 temp &= ~LVDS_PIPEB_SELECT;
5404 }
5405 /* set the corresponsding LVDS_BORDER bit */
5406 temp |= dev_priv->lvds_border_bits;
5407 /* Set the B0-B3 data pairs corresponding to whether we're going to
5408 * set the DPLLs for dual-channel mode or not.
5409 */
5410 if (clock.p2 == 7)
5411 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5412 else
5413 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5414
5415 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5416 * appropriately here, but we need to look more thoroughly into how
5417 * panels behave in the two modes.
5418 */
5419 /* set the dithering flag on LVDS as needed */
5420 if (INTEL_INFO(dev)->gen >= 4) {
5421 if (dev_priv->lvds_dither)
5422 temp |= LVDS_ENABLE_DITHER;
5423 else
5424 temp &= ~LVDS_ENABLE_DITHER;
5425 }
5426 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5427 lvds_sync |= LVDS_HSYNC_POLARITY;
5428 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5429 lvds_sync |= LVDS_VSYNC_POLARITY;
5430 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5431 != lvds_sync) {
5432 char flags[2] = "-+";
5433 DRM_INFO("Changing LVDS panel from "
5434 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5435 flags[!(temp & LVDS_HSYNC_POLARITY)],
5436 flags[!(temp & LVDS_VSYNC_POLARITY)],
5437 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5438 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5439 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5440 temp |= lvds_sync;
5441 }
5442 I915_WRITE(LVDS, temp);
5443 }
5444
5445 if (is_dp) {
5446 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5447 }
5448
5449 I915_WRITE(DPLL(pipe), dpll);
5450
5451 /* Wait for the clocks to stabilize. */
5452 POSTING_READ(DPLL(pipe));
5453 DELAY(150);
5454
5455 if (INTEL_INFO(dev)->gen >= 4) {
5456 temp = 0;
5457 if (is_sdvo) {
5458 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5459 if (temp > 1)
5460 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5461 else
5462 temp = 0;
5463 }
5464 I915_WRITE(DPLL_MD(pipe), temp);
5465 } else {
5466 /* The pixel multiplier can only be updated once the
5467 * DPLL is enabled and the clocks are stable.
5468 *
5469 * So write it again.
5470 */
5471 I915_WRITE(DPLL(pipe), dpll);
5472 }
5473
5474 if (HAS_PIPE_CXSR(dev)) {
5475 if (intel_crtc->lowfreq_avail) {
5476 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5477 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5478 } else {
5479 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5480 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5481 }
5482 }
5483
5484 pipeconf &= ~PIPECONF_INTERLACE_MASK;
5485 if (!IS_GEN2(dev) &&
5486 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5487 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5488 /* the chip adds 2 halflines automatically */
5489 adjusted_mode->crtc_vtotal -= 1;
5490 adjusted_mode->crtc_vblank_end -= 1;
5491 vsyncshift = adjusted_mode->crtc_hsync_start
5492 - adjusted_mode->crtc_htotal/2;
5493 } else {
5494 pipeconf |= PIPECONF_PROGRESSIVE;
5495 vsyncshift = 0;
5496 }
5497
5498 if (!IS_GEN3(dev))
5499 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5500
5501 I915_WRITE(HTOTAL(pipe),
5502 (adjusted_mode->crtc_hdisplay - 1) |
5503 ((adjusted_mode->crtc_htotal - 1) << 16));
5504 I915_WRITE(HBLANK(pipe),
5505 (adjusted_mode->crtc_hblank_start - 1) |
5506 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5507 I915_WRITE(HSYNC(pipe),
5508 (adjusted_mode->crtc_hsync_start - 1) |
5509 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5510
5511 I915_WRITE(VTOTAL(pipe),
5512 (adjusted_mode->crtc_vdisplay - 1) |
5513 ((adjusted_mode->crtc_vtotal - 1) << 16));
5514 I915_WRITE(VBLANK(pipe),
5515 (adjusted_mode->crtc_vblank_start - 1) |
5516 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5517 I915_WRITE(VSYNC(pipe),
5518 (adjusted_mode->crtc_vsync_start - 1) |
5519 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5520
5521 /* pipesrc and dspsize control the size that is scaled from,
5522 * which should always be the user's requested size.
5523 */
5524 I915_WRITE(DSPSIZE(plane),
5525 ((mode->vdisplay - 1) << 16) |
5526 (mode->hdisplay - 1));
5527 I915_WRITE(DSPPOS(plane), 0);
5528 I915_WRITE(PIPESRC(pipe),
5529 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5530
5531 I915_WRITE(PIPECONF(pipe), pipeconf);
5532 POSTING_READ(PIPECONF(pipe));
5533 intel_enable_pipe(dev_priv, pipe, false);
5534
5535 intel_wait_for_vblank(dev, pipe);
5536
5537 I915_WRITE(DSPCNTR(plane), dspcntr);
5538 POSTING_READ(DSPCNTR(plane));
5539 intel_enable_plane(dev_priv, plane, pipe);
5540
5541 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5542
5543 intel_update_watermarks(dev);
5544
5545 return ret;
5546}
5547
5548/*
5549 * Initialize reference clocks when the driver loads
5550 */
5551void ironlake_init_pch_refclk(struct drm_device *dev)
5552{
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 struct drm_mode_config *mode_config = &dev->mode_config;
5555 struct intel_encoder *encoder;
5556 u32 temp;
5557 bool has_lvds = false;
5558 bool has_cpu_edp = false;
5559 bool has_pch_edp = false;
5560 bool has_panel = false;
5561 bool has_ck505 = false;
5562 bool can_ssc = false;
5563
5564 /* We need to take the global config into account */
5565 list_for_each_entry(encoder, &mode_config->encoder_list,
5566 base.head) {
5567 switch (encoder->type) {
5568 case INTEL_OUTPUT_LVDS:
5569 has_panel = true;
5570 has_lvds = true;
5571 break;
5572 case INTEL_OUTPUT_EDP:
5573 has_panel = true;
5574 if (intel_encoder_is_pch_edp(&encoder->base))
5575 has_pch_edp = true;
5576 else
5577 has_cpu_edp = true;
5578 break;
5579 }
5580 }
5581
5582 if (HAS_PCH_IBX(dev)) {
5583 has_ck505 = dev_priv->display_clock_mode;
5584 can_ssc = has_ck505;
5585 } else {
5586 has_ck505 = false;
5587 can_ssc = true;
5588 }
5589
5590 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5591 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5592 has_ck505);
5593
5594 /* Ironlake: try to setup display ref clock before DPLL
5595 * enabling. This is only under driver's control after
5596 * PCH B stepping, previous chipset stepping should be
5597 * ignoring this setting.
5598 */
5599 temp = I915_READ(PCH_DREF_CONTROL);
5600 /* Always enable nonspread source */
5601 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5602
5603 if (has_ck505)
5604 temp |= DREF_NONSPREAD_CK505_ENABLE;
5605 else
5606 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5607
5608 if (has_panel) {
5609 temp &= ~DREF_SSC_SOURCE_MASK;
5610 temp |= DREF_SSC_SOURCE_ENABLE;
5611
5612 /* SSC must be turned on before enabling the CPU output */
5613 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5614 DRM_DEBUG_KMS("Using SSC on panel\n");
5615 temp |= DREF_SSC1_ENABLE;
5616 } else
5617 temp &= ~DREF_SSC1_ENABLE;
5618
5619 /* Get SSC going before enabling the outputs */
5620 I915_WRITE(PCH_DREF_CONTROL, temp);
5621 POSTING_READ(PCH_DREF_CONTROL);
5622 DELAY(200);
5623
5624 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5625
5626 /* Enable CPU source on CPU attached eDP */
5627 if (has_cpu_edp) {
5628 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5629 DRM_DEBUG_KMS("Using SSC on eDP\n");
5630 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5631 }
5632 else
5633 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5634 } else
5635 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5636
5637 I915_WRITE(PCH_DREF_CONTROL, temp);
5638 POSTING_READ(PCH_DREF_CONTROL);
5639 DELAY(200);
5640 } else {
5641 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5642
5643 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5644
5645 /* Turn off CPU output */
5646 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5647
5648 I915_WRITE(PCH_DREF_CONTROL, temp);
5649 POSTING_READ(PCH_DREF_CONTROL);
5650 DELAY(200);
5651
5652 /* Turn off the SSC source */
5653 temp &= ~DREF_SSC_SOURCE_MASK;
5654 temp |= DREF_SSC_SOURCE_DISABLE;
5655
5656 /* Turn off SSC1 */
5657 temp &= ~ DREF_SSC1_ENABLE;
5658
5659 I915_WRITE(PCH_DREF_CONTROL, temp);
5660 POSTING_READ(PCH_DREF_CONTROL);
5661 DELAY(200);
5662 }
5663}
5664
5665static int ironlake_get_refclk(struct drm_crtc *crtc)
5666{
5667 struct drm_device *dev = crtc->dev;
5668 struct drm_i915_private *dev_priv = dev->dev_private;
5669 struct intel_encoder *encoder;
5670 struct drm_mode_config *mode_config = &dev->mode_config;
5671 struct intel_encoder *edp_encoder = NULL;
5672 int num_connectors = 0;
5673 bool is_lvds = false;
5674
5675 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5676 if (encoder->base.crtc != crtc)
5677 continue;
5678
5679 switch (encoder->type) {
5680 case INTEL_OUTPUT_LVDS:
5681 is_lvds = true;
5682 break;
5683 case INTEL_OUTPUT_EDP:
5684 edp_encoder = encoder;
5685 break;
5686 }
5687 num_connectors++;
5688 }
5689
5690 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5691 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5692 dev_priv->lvds_ssc_freq);
5693 return dev_priv->lvds_ssc_freq * 1000;
5694 }
5695
5696 return 120000;
5697}
5698
5699static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5700 struct drm_display_mode *mode,
5701 struct drm_display_mode *adjusted_mode,
5702 int x, int y,
5703 struct drm_framebuffer *old_fb)
5704{
5705 struct drm_device *dev = crtc->dev;
5706 struct drm_i915_private *dev_priv = dev->dev_private;
5707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5708 int pipe = intel_crtc->pipe;
5709 int plane = intel_crtc->plane;
5710 int refclk, num_connectors = 0;
5711 intel_clock_t clock, reduced_clock;
5712 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5713 bool ok, has_reduced_clock = false, is_sdvo = false;
5714 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5715 struct intel_encoder *has_edp_encoder = NULL;
5716 struct drm_mode_config *mode_config = &dev->mode_config;
5717 struct intel_encoder *encoder;
5718 const intel_limit_t *limit;
5719 int ret;
5720 struct fdi_m_n m_n = {0};
5721 u32 temp;
5722 u32 lvds_sync = 0;
5723 int target_clock, pixel_multiplier, lane, link_bw, factor;
5724 unsigned int pipe_bpp;
5725 bool dither;
5726
5727 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5728 if (encoder->base.crtc != crtc)
5729 continue;
5730
5731 switch (encoder->type) {
5732 case INTEL_OUTPUT_LVDS:
5733 is_lvds = true;
5734 break;
5735 case INTEL_OUTPUT_SDVO:
5736 case INTEL_OUTPUT_HDMI:
5737 is_sdvo = true;
5738 if (encoder->needs_tv_clock)
5739 is_tv = true;
5740 break;
5741 case INTEL_OUTPUT_TVOUT:
5742 is_tv = true;
5743 break;
5744 case INTEL_OUTPUT_ANALOG:
5745 is_crt = true;
5746 break;
5747 case INTEL_OUTPUT_DISPLAYPORT:
5748 is_dp = true;
5749 break;
5750 case INTEL_OUTPUT_EDP:
5751 has_edp_encoder = encoder;
5752 break;
5753 }
5754
5755 num_connectors++;
5756 }
5757
5758 refclk = ironlake_get_refclk(crtc);
5759
5760 /*
5761 * Returns a set of divisors for the desired target clock with the given
5762 * refclk, or false. The returned values represent the clock equation:
5763 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5764 */
5765 limit = intel_limit(crtc, refclk);
5766 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5767 &clock);
5768 if (!ok) {
5769 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5770 return -EINVAL;
5771 }
5772
5773 /* Ensure that the cursor is valid for the new mode before changing... */
5774 intel_crtc_update_cursor(crtc, true);
5775
5776 if (is_lvds && dev_priv->lvds_downclock_avail) {
5777 /*
5778 * Ensure we match the reduced clock's P to the target clock.
5779 * If the clocks don't match, we can't switch the display clock
5780 * by using the FP0/FP1. In such case we will disable the LVDS
5781 * downclock feature.
5782 */
5783 has_reduced_clock = limit->find_pll(limit, crtc,
5784 dev_priv->lvds_downclock,
5785 refclk,
5786 &clock,
5787 &reduced_clock);
5788 }
5789 /* SDVO TV has fixed PLL values depend on its clock range,
5790 this mirrors vbios setting. */
5791 if (is_sdvo && is_tv) {
5792 if (adjusted_mode->clock >= 100000
5793 && adjusted_mode->clock < 140500) {
5794 clock.p1 = 2;
5795 clock.p2 = 10;
5796 clock.n = 3;
5797 clock.m1 = 16;
5798 clock.m2 = 8;
5799 } else if (adjusted_mode->clock >= 140500
5800 && adjusted_mode->clock <= 200000) {
5801 clock.p1 = 1;
5802 clock.p2 = 10;
5803 clock.n = 6;
5804 clock.m1 = 12;
5805 clock.m2 = 8;
5806 }
5807 }
5808
5809 /* FDI link */
5810 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5811 lane = 0;
5812 /* CPU eDP doesn't require FDI link, so just set DP M/N
5813 according to current link config */
5814 if (has_edp_encoder &&
5815 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5816 target_clock = mode->clock;
5817 intel_edp_link_config(has_edp_encoder,
5818 &lane, &link_bw);
5819 } else {
5820 /* [e]DP over FDI requires target mode clock
5821 instead of link clock */
5822 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5823 target_clock = mode->clock;
5824 else
5825 target_clock = adjusted_mode->clock;
5826
5827 /* FDI is a binary signal running at ~2.7GHz, encoding
5828 * each output octet as 10 bits. The actual frequency
5829 * is stored as a divider into a 100MHz clock, and the
5830 * mode pixel clock is stored in units of 1KHz.
5831 * Hence the bw of each lane in terms of the mode signal
5832 * is:
5833 */
5834 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5835 }
5836
5837 /* determine panel color depth */
5838 temp = I915_READ(PIPECONF(pipe));
5839 temp &= ~PIPE_BPC_MASK;
5840 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5841 switch (pipe_bpp) {
5842 case 18:
5843 temp |= PIPE_6BPC;
5844 break;
5845 case 24:
5846 temp |= PIPE_8BPC;
5847 break;
5848 case 30:
5849 temp |= PIPE_10BPC;
5850 break;
5851 case 36:
5852 temp |= PIPE_12BPC;
5853 break;
5854 default:
5855 printf("intel_choose_pipe_bpp returned invalid value %d\n",
5856 pipe_bpp);
5857 temp |= PIPE_8BPC;
5858 pipe_bpp = 24;
5859 break;
5860 }
5861
5862 intel_crtc->bpp = pipe_bpp;
5863 I915_WRITE(PIPECONF(pipe), temp);
5864
5865 if (!lane) {
5866 /*
5867 * Account for spread spectrum to avoid
5868 * oversubscribing the link. Max center spread
5869 * is 2.5%; use 5% for safety's sake.
5870 */
5871 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5872 lane = bps / (link_bw * 8) + 1;
5873 }
5874
5875 intel_crtc->fdi_lanes = lane;
5876
5877 if (pixel_multiplier > 1)
5878 link_bw *= pixel_multiplier;
5879 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5880 &m_n);
5881
5882 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5883 if (has_reduced_clock)
5884 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5885 reduced_clock.m2;
5886
5887 /* Enable autotuning of the PLL clock (if permissible) */
5888 factor = 21;
5889 if (is_lvds) {
5890 if ((intel_panel_use_ssc(dev_priv) &&
5891 dev_priv->lvds_ssc_freq == 100) ||
5892 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5893 factor = 25;
5894 } else if (is_sdvo && is_tv)
5895 factor = 20;
5896
5897 if (clock.m < factor * clock.n)
5898 fp |= FP_CB_TUNE;
5899
5900 dpll = 0;
5901
5902 if (is_lvds)
5903 dpll |= DPLLB_MODE_LVDS;
5904 else
5905 dpll |= DPLLB_MODE_DAC_SERIAL;
5906 if (is_sdvo) {
5907 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5908 if (pixel_multiplier > 1) {
5909 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5910 }
5911 dpll |= DPLL_DVO_HIGH_SPEED;
5912 }
5913 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5914 dpll |= DPLL_DVO_HIGH_SPEED;
5915
5916 /* compute bitmask from p1 value */
5917 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5918 /* also FPA1 */
5919 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5920
5921 switch (clock.p2) {
5922 case 5:
5923 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5924 break;
5925 case 7:
5926 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5927 break;
5928 case 10:
5929 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5930 break;
5931 case 14:
5932 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5933 break;
5934 }
5935
5936 if (is_sdvo && is_tv)
5937 dpll |= PLL_REF_INPUT_TVCLKINBC;
5938 else if (is_tv)
5939 /* XXX: just matching BIOS for now */
5940 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5941 dpll |= 3;
5942 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5943 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5944 else
5945 dpll |= PLL_REF_INPUT_DREFCLK;
5946
5947 /* setup pipeconf */
5948 pipeconf = I915_READ(PIPECONF(pipe));
5949
5950 /* Set up the display plane register */
5951 dspcntr = DISPPLANE_GAMMA_ENABLE;
5952
5953 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5954 drm_mode_debug_printmodeline(mode);
5955
5956 /* PCH eDP needs FDI, but CPU eDP does not */
5957 if (!intel_crtc->no_pll) {
5958 if (!has_edp_encoder ||
5959 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5960 I915_WRITE(PCH_FP0(pipe), fp);
5961 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5962
5963 POSTING_READ(PCH_DPLL(pipe));
5964 DELAY(150);
5965 }
5966 } else {
5967 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5968 fp == I915_READ(PCH_FP0(0))) {
5969 intel_crtc->use_pll_a = true;
5970 DRM_DEBUG_KMS("using pipe a dpll\n");
5971 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5972 fp == I915_READ(PCH_FP0(1))) {
5973 intel_crtc->use_pll_a = false;
5974 DRM_DEBUG_KMS("using pipe b dpll\n");
5975 } else {
5976 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5977 return -EINVAL;
5978 }
5979 }
5980
5981 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5982 * This is an exception to the general rule that mode_set doesn't turn
5983 * things on.
5984 */
5985 if (is_lvds) {
5986 temp = I915_READ(PCH_LVDS);
5987 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5988 if (HAS_PCH_CPT(dev)) {
5989 temp &= ~PORT_TRANS_SEL_MASK;
5990 temp |= PORT_TRANS_SEL_CPT(pipe);
5991 } else {
5992 if (pipe == 1)
5993 temp |= LVDS_PIPEB_SELECT;
5994 else
5995 temp &= ~LVDS_PIPEB_SELECT;
5996 }
5997
5998 /* set the corresponsding LVDS_BORDER bit */
5999 temp |= dev_priv->lvds_border_bits;
6000 /* Set the B0-B3 data pairs corresponding to whether we're going to
6001 * set the DPLLs for dual-channel mode or not.
6002 */
6003 if (clock.p2 == 7)
6004 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
6005 else
6006 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
6007
6008 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
6009 * appropriately here, but we need to look more thoroughly into how
6010 * panels behave in the two modes.
6011 */
6012 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
6013 lvds_sync |= LVDS_HSYNC_POLARITY;
6014 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
6015 lvds_sync |= LVDS_VSYNC_POLARITY;
6016 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
6017 != lvds_sync) {
6018 char flags[2] = "-+";
6019 DRM_INFO("Changing LVDS panel from "
6020 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
6021 flags[!(temp & LVDS_HSYNC_POLARITY)],
6022 flags[!(temp & LVDS_VSYNC_POLARITY)],
6023 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
6024 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
6025 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
6026 temp |= lvds_sync;
6027 }
6028 I915_WRITE(PCH_LVDS, temp);
6029 }
6030
6031 pipeconf &= ~PIPECONF_DITHER_EN;
6032 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
6033 if ((is_lvds && dev_priv->lvds_dither) || dither) {
6034 pipeconf |= PIPECONF_DITHER_EN;
6035 pipeconf |= PIPECONF_DITHER_TYPE_SP;
6036 }
6037 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6038 intel_dp_set_m_n(crtc, mode, adjusted_mode);
6039 } else {
6040 /* For non-DP output, clear any trans DP clock recovery setting.*/
6041 I915_WRITE(TRANSDATA_M1(pipe), 0);
6042 I915_WRITE(TRANSDATA_N1(pipe), 0);
6043 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6044 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
6045 }
6046
6047 if (!intel_crtc->no_pll &&
6048 (!has_edp_encoder ||
6049 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6050 I915_WRITE(PCH_DPLL(pipe), dpll);
6051
6052 /* Wait for the clocks to stabilize. */
6053 POSTING_READ(PCH_DPLL(pipe));
6054 DELAY(150);
6055
6056 /* The pixel multiplier can only be updated once the
6057 * DPLL is enabled and the clocks are stable.
6058 *
6059 * So write it again.
6060 */
6061 I915_WRITE(PCH_DPLL(pipe), dpll);
6062 }
6063
6064 intel_crtc->lowfreq_avail = false;
6065 if (!intel_crtc->no_pll) {
6066 if (is_lvds && has_reduced_clock && i915_powersave) {
6067 I915_WRITE(PCH_FP1(pipe), fp2);
6068 intel_crtc->lowfreq_avail = true;
6069 if (HAS_PIPE_CXSR(dev)) {
6070 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6071 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6072 }
6073 } else {
6074 I915_WRITE(PCH_FP1(pipe), fp);
6075 if (HAS_PIPE_CXSR(dev)) {
6076 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6077 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6078 }
6079 }
6080 }
6081
6082 pipeconf &= ~PIPECONF_INTERLACE_MASK;
6083 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6084 pipeconf |= PIPECONF_INTERLACED_ILK;
6085 /* the chip adds 2 halflines automatically */
6086 adjusted_mode->crtc_vtotal -= 1;
6087 adjusted_mode->crtc_vblank_end -= 1;
6088 I915_WRITE(VSYNCSHIFT(pipe),
6089 adjusted_mode->crtc_hsync_start
6090 - adjusted_mode->crtc_htotal/2);
6091 } else {
6092 pipeconf |= PIPECONF_PROGRESSIVE;
6093 I915_WRITE(VSYNCSHIFT(pipe), 0);
6094 }
6095
6096 I915_WRITE(HTOTAL(pipe),
6097 (adjusted_mode->crtc_hdisplay - 1) |
6098 ((adjusted_mode->crtc_htotal - 1) << 16));
6099 I915_WRITE(HBLANK(pipe),
6100 (adjusted_mode->crtc_hblank_start - 1) |
6101 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6102 I915_WRITE(HSYNC(pipe),
6103 (adjusted_mode->crtc_hsync_start - 1) |
6104 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6105
6106 I915_WRITE(VTOTAL(pipe),
6107 (adjusted_mode->crtc_vdisplay - 1) |
6108 ((adjusted_mode->crtc_vtotal - 1) << 16));
6109 I915_WRITE(VBLANK(pipe),
6110 (adjusted_mode->crtc_vblank_start - 1) |
6111 ((adjusted_mode->crtc_vblank_end - 1) << 16));
6112 I915_WRITE(VSYNC(pipe),
6113 (adjusted_mode->crtc_vsync_start - 1) |
6114 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6115
6116 /* pipesrc controls the size that is scaled from, which should
6117 * always be the user's requested size.
6118 */
6119 I915_WRITE(PIPESRC(pipe),
6120 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6121
6122 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6123 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6124 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6125 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6126
6127 if (has_edp_encoder &&
6128 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6129 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6130 }
6131
6132 I915_WRITE(PIPECONF(pipe), pipeconf);
6133 POSTING_READ(PIPECONF(pipe));
6134
6135 intel_wait_for_vblank(dev, pipe);
6136
6137 I915_WRITE(DSPCNTR(plane), dspcntr);
6138 POSTING_READ(DSPCNTR(plane));
6139
6140 ret = intel_pipe_set_base(crtc, x, y, old_fb);
6141
6142 intel_update_watermarks(dev);
6143
6144 return ret;
6145}
6146
6147static int intel_crtc_mode_set(struct drm_crtc *crtc,
6148 struct drm_display_mode *mode,
6149 struct drm_display_mode *adjusted_mode,
6150 int x, int y,
6151 struct drm_framebuffer *old_fb)
6152{
6153 struct drm_device *dev = crtc->dev;
6154 struct drm_i915_private *dev_priv = dev->dev_private;
6155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6156 int pipe = intel_crtc->pipe;
6157 int ret;
6158
6159 drm_vblank_pre_modeset(dev, pipe);
6160
6161 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6162 x, y, old_fb);
6163 drm_vblank_post_modeset(dev, pipe);
6164
6165 if (ret)
6166 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6167 else
6168 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6169
6170 return ret;
6171}
6172
6173static bool intel_eld_uptodate(struct drm_connector *connector,
6174 int reg_eldv, uint32_t bits_eldv,
6175 int reg_elda, uint32_t bits_elda,
6176 int reg_edid)
6177{
6178 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6179 uint8_t *eld = connector->eld;
6180 uint32_t i;
6181
6182 i = I915_READ(reg_eldv);
6183 i &= bits_eldv;
6184
6185 if (!eld[0])
6186 return !i;
6187
6188 if (!i)
6189 return false;
6190
6191 i = I915_READ(reg_elda);
6192 i &= ~bits_elda;
6193 I915_WRITE(reg_elda, i);
6194
6195 for (i = 0; i < eld[2]; i++)
6196 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6197 return false;
6198
6199 return true;
6200}
6201
6202static void g4x_write_eld(struct drm_connector *connector,
6203 struct drm_crtc *crtc)
6204{
6205 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6206 uint8_t *eld = connector->eld;
6207 uint32_t eldv;
6208 uint32_t len;
6209 uint32_t i;
6210
6211 i = I915_READ(G4X_AUD_VID_DID);
6212
6213 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6214 eldv = G4X_ELDV_DEVCL_DEVBLC;
6215 else
6216 eldv = G4X_ELDV_DEVCTG;
6217
6218 if (intel_eld_uptodate(connector,
6219 G4X_AUD_CNTL_ST, eldv,
6220 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6221 G4X_HDMIW_HDMIEDID))
6222 return;
6223
6224 i = I915_READ(G4X_AUD_CNTL_ST);
6225 i &= ~(eldv | G4X_ELD_ADDR);
6226 len = (i >> 9) & 0x1f; /* ELD buffer size */
6227 I915_WRITE(G4X_AUD_CNTL_ST, i);
6228
6229 if (!eld[0])
6230 return;
6231
6232 if (eld[2] < (uint8_t)len)
6233 len = eld[2];
6234 DRM_DEBUG_KMS("ELD size %d\n", len);
6235 for (i = 0; i < len; i++)
6236 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6237
6238 i = I915_READ(G4X_AUD_CNTL_ST);
6239 i |= eldv;
6240 I915_WRITE(G4X_AUD_CNTL_ST, i);
6241}
6242
6243static void ironlake_write_eld(struct drm_connector *connector,
6244 struct drm_crtc *crtc)
6245{
6246 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6247 uint8_t *eld = connector->eld;
6248 uint32_t eldv;
6249 uint32_t i;
6250 int len;
6251 int hdmiw_hdmiedid;
6252 int aud_config;
6253 int aud_cntl_st;
6254 int aud_cntrl_st2;
6255
6256 if (HAS_PCH_IBX(connector->dev)) {
6257 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6258 aud_config = IBX_AUD_CONFIG_A;
6259 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6260 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6261 } else {
6262 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6263 aud_config = CPT_AUD_CONFIG_A;
6264 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6265 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6266 }
6267
6268 i = to_intel_crtc(crtc)->pipe;
6269 hdmiw_hdmiedid += i * 0x100;
6270 aud_cntl_st += i * 0x100;
6271 aud_config += i * 0x100;
6272
6273 DRM_DEBUG_KMS("ELD on pipe %c\n", pipe_name(i));
6274
6275 i = I915_READ(aud_cntl_st);
6276 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6277 if (!i) {
6278 DRM_DEBUG_KMS("Audio directed to unknown port\n");
6279 /* operate blindly on all ports */
6280 eldv = IBX_ELD_VALIDB;
6281 eldv |= IBX_ELD_VALIDB << 4;
6282 eldv |= IBX_ELD_VALIDB << 8;
6283 } else {
6284 DRM_DEBUG_KMS("ELD on port %c\n", 'A' + i);
6285 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6286 }
6287
6288 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6289 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6290 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6291 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6292 } else
6293 I915_WRITE(aud_config, 0);
6294
6295 if (intel_eld_uptodate(connector,
6296 aud_cntrl_st2, eldv,
6297 aud_cntl_st, IBX_ELD_ADDRESS,
6298 hdmiw_hdmiedid))
6299 return;
6300
6301 i = I915_READ(aud_cntrl_st2);
6302 i &= ~eldv;
6303 I915_WRITE(aud_cntrl_st2, i);
6304
6305 if (!eld[0])
6306 return;
6307
6308 i = I915_READ(aud_cntl_st);
6309 i &= ~IBX_ELD_ADDRESS;
6310 I915_WRITE(aud_cntl_st, i);
6311
6312 /* 84 bytes of hw ELD buffer */
6313 len = 21;
6314 if (eld[2] < (uint8_t)len)
6315 len = eld[2];
6316 DRM_DEBUG_KMS("ELD size %d\n", len);
6317 for (i = 0; i < len; i++)
6318 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6319
6320 i = I915_READ(aud_cntrl_st2);
6321 i |= eldv;
6322 I915_WRITE(aud_cntrl_st2, i);
6323}
6324
6325void intel_write_eld(struct drm_encoder *encoder,
6326 struct drm_display_mode *mode)
6327{
6328 struct drm_crtc *crtc = encoder->crtc;
6329 struct drm_connector *connector;
6330 struct drm_device *dev = encoder->dev;
6331 struct drm_i915_private *dev_priv = dev->dev_private;
6332
6333 connector = drm_select_eld(encoder, mode);
6334 if (!connector)
6335 return;
6336
6337 DRM_DEBUG_KMS("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6338 connector->base.id,
6339 drm_get_connector_name(connector),
6340 connector->encoder->base.id,
6341 drm_get_encoder_name(connector->encoder));
6342
6343 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6344
6345 if (dev_priv->display.write_eld)
6346 dev_priv->display.write_eld(connector, crtc);
6347}
6348
6349/** Loads the palette/gamma unit for the CRTC with the prepared values */
6350void intel_crtc_load_lut(struct drm_crtc *crtc)
6351{
6352 struct drm_device *dev = crtc->dev;
6353 struct drm_i915_private *dev_priv = dev->dev_private;
6354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6355 int palreg = PALETTE(intel_crtc->pipe);
6356 int i;
6357
6358 /* The clocks have to be on to load the palette. */
6359 if (!crtc->enabled || !intel_crtc->active)
6360 return;
6361
6362 /* use legacy palette for Ironlake */
6363 if (HAS_PCH_SPLIT(dev))
6364 palreg = LGC_PALETTE(intel_crtc->pipe);
6365
6366 for (i = 0; i < 256; i++) {
6367 I915_WRITE(palreg + 4 * i,
6368 (intel_crtc->lut_r[i] << 16) |
6369 (intel_crtc->lut_g[i] << 8) |
6370 intel_crtc->lut_b[i]);
6371 }
6372}
6373
6374static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6375{
6376 struct drm_device *dev = crtc->dev;
6377 struct drm_i915_private *dev_priv = dev->dev_private;
6378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379 bool visible = base != 0;
6380 u32 cntl;
6381
6382 if (intel_crtc->cursor_visible == visible)
6383 return;
6384
6385 cntl = I915_READ(_CURACNTR);
6386 if (visible) {
6387 /* On these chipsets we can only modify the base whilst
6388 * the cursor is disabled.
6389 */
6390 I915_WRITE(_CURABASE, base);
6391
6392 cntl &= ~(CURSOR_FORMAT_MASK);
6393 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6394 cntl |= CURSOR_ENABLE |
6395 CURSOR_GAMMA_ENABLE |
6396 CURSOR_FORMAT_ARGB;
6397 } else
6398 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6399 I915_WRITE(_CURACNTR, cntl);
6400
6401 intel_crtc->cursor_visible = visible;
6402}
6403
6404static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6405{
6406 struct drm_device *dev = crtc->dev;
6407 struct drm_i915_private *dev_priv = dev->dev_private;
6408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6409 int pipe = intel_crtc->pipe;
6410 bool visible = base != 0;
6411
6412 if (intel_crtc->cursor_visible != visible) {
6413 uint32_t cntl = I915_READ(CURCNTR(pipe));
6414 if (base) {
6415 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6416 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6417 cntl |= pipe << 28; /* Connect to correct pipe */
6418 } else {
6419 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6420 cntl |= CURSOR_MODE_DISABLE;
6421 }
6422 I915_WRITE(CURCNTR(pipe), cntl);
6423
6424 intel_crtc->cursor_visible = visible;
6425 }
6426 /* and commit changes on next vblank */
6427 I915_WRITE(CURBASE(pipe), base);
6428}
6429
6430static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6431{
6432 struct drm_device *dev = crtc->dev;
6433 struct drm_i915_private *dev_priv = dev->dev_private;
6434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6435 int pipe = intel_crtc->pipe;
6436 bool visible = base != 0;
6437
6438 if (intel_crtc->cursor_visible != visible) {
6439 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6440 if (base) {
6441 cntl &= ~CURSOR_MODE;
6442 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6443 } else {
6444 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6445 cntl |= CURSOR_MODE_DISABLE;
6446 }
6447 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6448
6449 intel_crtc->cursor_visible = visible;
6450 }
6451 /* and commit changes on next vblank */
6452 I915_WRITE(CURBASE_IVB(pipe), base);
6453}
6454
6455/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6456static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6457 bool on)
6458{
6459 struct drm_device *dev = crtc->dev;
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6462 int pipe = intel_crtc->pipe;
6463 int x = intel_crtc->cursor_x;
6464 int y = intel_crtc->cursor_y;
6465 u32 base, pos;
6466 bool visible;
6467
6468 pos = 0;
6469
6470 if (on && crtc->enabled && crtc->fb) {
6471 base = intel_crtc->cursor_addr;
6472 if (x > (int) crtc->fb->width)
6473 base = 0;
6474
6475 if (y > (int) crtc->fb->height)
6476 base = 0;
6477 } else
6478 base = 0;
6479
6480 if (x < 0) {
6481 if (x + intel_crtc->cursor_width < 0)
6482 base = 0;
6483
6484 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6485 x = -x;
6486 }
6487 pos |= x << CURSOR_X_SHIFT;
6488
6489 if (y < 0) {
6490 if (y + intel_crtc->cursor_height < 0)
6491 base = 0;
6492
6493 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6494 y = -y;
6495 }
6496 pos |= y << CURSOR_Y_SHIFT;
6497
6498 visible = base != 0;
6499 if (!visible && !intel_crtc->cursor_visible)
6500 return;
6501
6502 if (IS_IVYBRIDGE(dev)) {
6503 I915_WRITE(CURPOS_IVB(pipe), pos);
6504 ivb_update_cursor(crtc, base);
6505 } else {
6506 I915_WRITE(CURPOS(pipe), pos);
6507 if (IS_845G(dev) || IS_I865G(dev))
6508 i845_update_cursor(crtc, base);
6509 else
6510 i9xx_update_cursor(crtc, base);
6511 }
6512
6513 if (visible)
6514 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6515}
6516
6517static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6518 struct drm_file *file,
6519 uint32_t handle,
6520 uint32_t width, uint32_t height)
6521{
6522 struct drm_device *dev = crtc->dev;
6523 struct drm_i915_private *dev_priv = dev->dev_private;
6524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6525 struct drm_i915_gem_object *obj;
6526 uint32_t addr;
6527 int ret;
6528
6529 DRM_DEBUG_KMS("\n");
6530
6531 /* if we want to turn off the cursor ignore width and height */
6532 if (!handle) {
6533 DRM_DEBUG_KMS("cursor off\n");
6534 addr = 0;
6535 obj = NULL;
6536 DRM_LOCK(dev);
6537 goto finish;
6538 }
6539
6540 /* Currently we only support 64x64 cursors */
6541 if (width != 64 || height != 64) {
6542 DRM_ERROR("we currently only support 64x64 cursors\n");
6543 return -EINVAL;
6544 }
6545
6546 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6547 if (&obj->base == NULL)
6548 return -ENOENT;
6549
6550 if (obj->base.size < width * height * 4) {
6551 DRM_ERROR("buffer is to small\n");
6552 ret = -ENOMEM;
6553 goto fail;
6554 }
6555
6556 /* we only need to pin inside GTT if cursor is non-phy */
6557 DRM_LOCK(dev);
6558 if (!dev_priv->info->cursor_needs_physical) {
6559 if (obj->tiling_mode) {
6560 DRM_ERROR("cursor cannot be tiled\n");
6561 ret = -EINVAL;
6562 goto fail_locked;
6563 }
6564
6565 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6566 if (ret) {
6567 DRM_ERROR("failed to move cursor bo into the GTT\n");
6568 goto fail_locked;
6569 }
6570
6571 ret = i915_gem_object_put_fence(obj);
6572 if (ret) {
6573 DRM_ERROR("failed to release fence for cursor\n");
6574 goto fail_unpin;
6575 }
6576
6577 addr = obj->gtt_offset;
6578 } else {
6579 int align = IS_I830(dev) ? 16 * 1024 : 256;
6580 ret = i915_gem_attach_phys_object(dev, obj,
6581 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6582 align);
6583 if (ret) {
6584 DRM_ERROR("failed to attach phys object\n");
6585 goto fail_locked;
6586 }
6587 addr = obj->phys_obj->handle->busaddr;
6588 }
6589
6590 if (IS_GEN2(dev))
6591 I915_WRITE(CURSIZE, (height << 12) | width);
6592
6593 finish:
6594 if (intel_crtc->cursor_bo) {
6595 if (dev_priv->info->cursor_needs_physical) {
6596 if (intel_crtc->cursor_bo != obj)
6597 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6598 } else
6599 i915_gem_object_unpin(intel_crtc->cursor_bo);
6600 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6601 }
6602
6603 DRM_UNLOCK(dev);
6604
6605 intel_crtc->cursor_addr = addr;
6606 intel_crtc->cursor_bo = obj;
6607 intel_crtc->cursor_width = width;
6608 intel_crtc->cursor_height = height;
6609
6610 intel_crtc_update_cursor(crtc, true);
6611
6612 return 0;
6613fail_unpin:
6614 i915_gem_object_unpin(obj);
6615fail_locked:
6616 DRM_UNLOCK(dev);
6617fail:
6618 drm_gem_object_unreference_unlocked(&obj->base);
6619 return ret;
6620}
6621
6622static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6623{
6624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6625
6626 intel_crtc->cursor_x = x;
6627 intel_crtc->cursor_y = y;
6628
6629 intel_crtc_update_cursor(crtc, true);
6630
6631 return 0;
6632}
6633
6634/** Sets the color ramps on behalf of RandR */
6635void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6636 u16 blue, int regno)
6637{
6638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6639
6640 intel_crtc->lut_r[regno] = red >> 8;
6641 intel_crtc->lut_g[regno] = green >> 8;
6642 intel_crtc->lut_b[regno] = blue >> 8;
6643}
6644
6645void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6646 u16 *blue, int regno)
6647{
6648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649
6650 *red = intel_crtc->lut_r[regno] << 8;
6651 *green = intel_crtc->lut_g[regno] << 8;
6652 *blue = intel_crtc->lut_b[regno] << 8;
6653}
6654
6655static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6656 u16 *blue, uint32_t start, uint32_t size)
6657{
6658 int end = (start + size > 256) ? 256 : start + size, i;
6659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6660
6661 for (i = start; i < end; i++) {
6662 intel_crtc->lut_r[i] = red[i] >> 8;
6663 intel_crtc->lut_g[i] = green[i] >> 8;
6664 intel_crtc->lut_b[i] = blue[i] >> 8;
6665 }
6666
6667 intel_crtc_load_lut(crtc);
6668}
6669
6670/**
6671 * Get a pipe with a simple mode set on it for doing load-based monitor
6672 * detection.
6673 *
6674 * It will be up to the load-detect code to adjust the pipe as appropriate for
6675 * its requirements. The pipe will be connected to no other encoders.
6676 *
6677 * Currently this code will only succeed if there is a pipe with no encoders
6678 * configured for it. In the future, it could choose to temporarily disable
6679 * some outputs to free up a pipe for its use.
6680 *
6681 * \return crtc, or NULL if no pipes are available.
6682 */
6683
6684/* VESA 640x480x72Hz mode to set on the pipe */
6685static struct drm_display_mode load_detect_mode = {
6686 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6687 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6688};
6689
6690static int
6691intel_framebuffer_create(struct drm_device *dev,
6692 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_i915_gem_object *obj,
6693 struct drm_framebuffer **res)
6694{
6695 struct intel_framebuffer *intel_fb;
6696 int ret;
6697
6698 intel_fb = malloc(sizeof(*intel_fb), DRM_MEM_KMS, M_WAITOK | M_ZERO);
6699 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6700 if (ret) {
6701 drm_gem_object_unreference_unlocked(&obj->base);
6702 free(intel_fb, DRM_MEM_KMS);
6703 return (ret);
6704 }
6705
6706 *res = &intel_fb->base;
6707 return (0);
6708}
6709
6710static u32
6711intel_framebuffer_pitch_for_width(int width, int bpp)
6712{
6713 u32 pitch = howmany(width * bpp, 8);
6714 return roundup2(pitch, 64);
6715}
6716
6717static u32
6718intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6719{
6720 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6721 return roundup2(pitch * mode->vdisplay, PAGE_SIZE);
6722}
6723
6724static int
6725intel_framebuffer_create_for_mode(struct drm_device *dev,
6726 struct drm_display_mode *mode, int depth, int bpp,
6727 struct drm_framebuffer **res)
6728{
6729 struct drm_i915_gem_object *obj;
6730 struct drm_mode_fb_cmd2 mode_cmd;
6731
6732 obj = i915_gem_alloc_object(dev,
6733 intel_framebuffer_size_for_mode(mode, bpp));
6734 if (obj == NULL)
6735 return (-ENOMEM);
6736
6737 mode_cmd.width = mode->hdisplay;
6738 mode_cmd.height = mode->vdisplay;
6739 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6740 bpp);
6741 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6742
6743 return (intel_framebuffer_create(dev, &mode_cmd, obj, res));
6744}
6745
6746static int
6747mode_fits_in_fbdev(struct drm_device *dev,
6748 struct drm_display_mode *mode, struct drm_framebuffer **res)
6749{
6750 struct drm_i915_private *dev_priv = dev->dev_private;
6751 struct drm_i915_gem_object *obj;
6752 struct drm_framebuffer *fb;
6753
6754 if (dev_priv->fbdev == NULL) {
6755 *res = NULL;
6756 return (0);
6757 }
6758
6759 obj = dev_priv->fbdev->ifb.obj;
6760 if (obj == NULL) {
6761 *res = NULL;
6762 return (0);
6763 }
6764
6765 fb = &dev_priv->fbdev->ifb.base;
6766 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6767 fb->bits_per_pixel)) {
6768 *res = NULL;
6769 return (0);
6770 }
6771
6772 if (obj->base.size < mode->vdisplay * fb->pitches[0]) {
6773 *res = NULL;
6774 return (0);
6775 }
6776
6777 *res = fb;
6778 return (0);
6779}
6780
6781bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6782 struct drm_connector *connector,
6783 struct drm_display_mode *mode,
6784 struct intel_load_detect_pipe *old)
6785{
6786 struct intel_crtc *intel_crtc;
6787 struct drm_crtc *possible_crtc;
6788 struct drm_encoder *encoder = &intel_encoder->base;
6789 struct drm_crtc *crtc = NULL;
6790 struct drm_device *dev = encoder->dev;
6791 struct drm_framebuffer *old_fb;
6792 int i = -1, r;
6793
6794 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6795 connector->base.id, drm_get_connector_name(connector),
6796 encoder->base.id, drm_get_encoder_name(encoder));
6797
6798 /*
6799 * Algorithm gets a little messy:
6800 *
6801 * - if the connector already has an assigned crtc, use it (but make
6802 * sure it's on first)
6803 *
6804 * - try to find the first unused crtc that can drive this connector,
6805 * and use that if we find one
6806 */
6807
6808 /* See if we already have a CRTC for this connector */
6809 if (encoder->crtc) {
6810 crtc = encoder->crtc;
6811
6812 intel_crtc = to_intel_crtc(crtc);
6813 old->dpms_mode = intel_crtc->dpms_mode;
6814 old->load_detect_temp = false;
6815
6816 /* Make sure the crtc and connector are running */
6817 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6818 struct drm_encoder_helper_funcs *encoder_funcs;
6819 struct drm_crtc_helper_funcs *crtc_funcs;
6820
6821 crtc_funcs = crtc->helper_private;
6822 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6823
6824 encoder_funcs = encoder->helper_private;
6825 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6826 }
6827
6828 return true;
6829 }
6830
6831 /* Find an unused one (if possible) */
6832 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6833 i++;
6834 if (!(encoder->possible_crtcs & (1 << i)))
6835 continue;
6836 if (!possible_crtc->enabled) {
6837 crtc = possible_crtc;
6838 break;
6839 }
6840 }
6841
6842 /*
6843 * If we didn't find an unused CRTC, don't use any.
6844 */
6845 if (!crtc) {
6846 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6847 return false;
6848 }
6849
6850 encoder->crtc = crtc;
6851 connector->encoder = encoder;
6852
6853 intel_crtc = to_intel_crtc(crtc);
6854 old->dpms_mode = intel_crtc->dpms_mode;
6855 old->load_detect_temp = true;
6856 old->release_fb = NULL;
6857
6858 if (!mode)
6859 mode = &load_detect_mode;
6860
6861 old_fb = crtc->fb;
6862
6863 /* We need a framebuffer large enough to accommodate all accesses
6864 * that the plane may generate whilst we perform load detection.
6865 * We can not rely on the fbcon either being present (we get called
6866 * during its initialisation to detect all boot displays, or it may
6867 * not even exist) or that it is large enough to satisfy the
6868 * requested mode.
6869 */
6870 r = mode_fits_in_fbdev(dev, mode, &crtc->fb);
6871 if (crtc->fb == NULL) {
6872 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6873 r = intel_framebuffer_create_for_mode(dev, mode, 24, 32,
6874 &crtc->fb);
6875 old->release_fb = crtc->fb;
6876 } else
6877 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6878 if (r != 0) {
6879 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6880 crtc->fb = old_fb;
6881 return false;
6882 }
6883
6884 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6885 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6886 if (old->release_fb)
6887 old->release_fb->funcs->destroy(old->release_fb);
6888 crtc->fb = old_fb;
6889 return false;
6890 }
6891
6892 /* let the connector get through one full cycle before testing */
6893 intel_wait_for_vblank(dev, intel_crtc->pipe);
6894
6895 return true;
6896}
6897
6898void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6899 struct drm_connector *connector,
6900 struct intel_load_detect_pipe *old)
6901{
6902 struct drm_encoder *encoder = &intel_encoder->base;
6903 struct drm_device *dev = encoder->dev;
6904 struct drm_crtc *crtc = encoder->crtc;
6905 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6906 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6907
6908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6909 connector->base.id, drm_get_connector_name(connector),
6910 encoder->base.id, drm_get_encoder_name(encoder));
6911
6912 if (old->load_detect_temp) {
6913 connector->encoder = NULL;
6914 drm_helper_disable_unused_functions(dev);
6915
6916 if (old->release_fb)
6917 old->release_fb->funcs->destroy(old->release_fb);
6918
6919 return;
6920 }
6921
6922 /* Switch crtc and encoder back off if necessary */
6923 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6924 encoder_funcs->dpms(encoder, old->dpms_mode);
6925 crtc_funcs->dpms(crtc, old->dpms_mode);
6926 }
6927}
6928
6929/* Returns the clock of the currently programmed mode of the given pipe. */
6930static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6931{
6932 struct drm_i915_private *dev_priv = dev->dev_private;
6933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6934 int pipe = intel_crtc->pipe;
6935 u32 dpll = I915_READ(DPLL(pipe));
6936 u32 fp;
6937 intel_clock_t clock;
6938
6939 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6940 fp = I915_READ(FP0(pipe));
6941 else
6942 fp = I915_READ(FP1(pipe));
6943
6944 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6945 if (IS_PINEVIEW(dev)) {
6946 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6947 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6948 } else {
6949 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6950 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6951 }
6952
6953 if (!IS_GEN2(dev)) {
6954 if (IS_PINEVIEW(dev))
6955 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6956 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6957 else
6958 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6959 DPLL_FPA01_P1_POST_DIV_SHIFT);
6960
6961 switch (dpll & DPLL_MODE_MASK) {
6962 case DPLLB_MODE_DAC_SERIAL:
6963 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6964 5 : 10;
6965 break;
6966 case DPLLB_MODE_LVDS:
6967 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6968 7 : 14;
6969 break;
6970 default:
6971 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6972 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6973 return 0;
6974 }
6975
6976 /* XXX: Handle the 100Mhz refclk */
6977 intel_clock(dev, 96000, &clock);
6978 } else {
6979 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6980
6981 if (is_lvds) {
6982 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6983 DPLL_FPA01_P1_POST_DIV_SHIFT);
6984 clock.p2 = 14;
6985
6986 if ((dpll & PLL_REF_INPUT_MASK) ==
6987 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6988 /* XXX: might not be 66MHz */
6989 intel_clock(dev, 66000, &clock);
6990 } else
6991 intel_clock(dev, 48000, &clock);
6992 } else {
6993 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6994 clock.p1 = 2;
6995 else {
6996 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6997 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6998 }
6999 if (dpll & PLL_P2_DIVIDE_BY_4)
7000 clock.p2 = 4;
7001 else
7002 clock.p2 = 2;
7003
7004 intel_clock(dev, 48000, &clock);
7005 }
7006 }
7007
7008 /* XXX: It would be nice to validate the clocks, but we can't reuse
7009 * i830PllIsValid() because it relies on the xf86_config connector
7010 * configuration being accurate, which it isn't necessarily.
7011 */
7012
7013 return clock.dot;
7014}
7015
7016/** Returns the currently programmed mode of the given pipe. */
7017struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7018 struct drm_crtc *crtc)
7019{
7020 struct drm_i915_private *dev_priv = dev->dev_private;
7021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7022 int pipe = intel_crtc->pipe;
7023 struct drm_display_mode *mode;
7024 int htot = I915_READ(HTOTAL(pipe));
7025 int hsync = I915_READ(HSYNC(pipe));
7026 int vtot = I915_READ(VTOTAL(pipe));
7027 int vsync = I915_READ(VSYNC(pipe));
7028
7029 mode = malloc(sizeof(*mode), DRM_MEM_KMS, M_WAITOK | M_ZERO);
7030
7031 mode->clock = intel_crtc_clock_get(dev, crtc);
7032 mode->hdisplay = (htot & 0xffff) + 1;
7033 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7034 mode->hsync_start = (hsync & 0xffff) + 1;
7035 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7036 mode->vdisplay = (vtot & 0xffff) + 1;
7037 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7038 mode->vsync_start = (vsync & 0xffff) + 1;
7039 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7040
7041 drm_mode_set_name(mode);
7042 drm_mode_set_crtcinfo(mode, 0);
7043
7044 return mode;
7045}
7046
7047#define GPU_IDLE_TIMEOUT (500 /* ms */ * 1000 / hz)
7048
7049/* When this timer fires, we've been idle for awhile */
7050static void intel_gpu_idle_timer(void *arg)
7051{
7052 struct drm_device *dev = arg;
7053 drm_i915_private_t *dev_priv = dev->dev_private;
7054
7055 if (!list_empty(&dev_priv->mm.active_list)) {
7056 /* Still processing requests, so just re-arm the timer. */
7057 callout_schedule(&dev_priv->idle_callout, GPU_IDLE_TIMEOUT);
7058 return;
7059 }
7060
7061 dev_priv->busy = false;
7062 taskqueue_enqueue(dev_priv->tq, &dev_priv->idle_task);
7063}
7064
7065#define CRTC_IDLE_TIMEOUT (1000 /* ms */ * 1000 / hz)
7066
7067static void intel_crtc_idle_timer(void *arg)
7068{
7069 struct intel_crtc *intel_crtc = arg;
7070 struct drm_crtc *crtc = &intel_crtc->base;
7071 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
7072 struct intel_framebuffer *intel_fb;
7073
7074 intel_fb = to_intel_framebuffer(crtc->fb);
7075 if (intel_fb && intel_fb->obj->active) {
7076 /* The framebuffer is still being accessed by the GPU. */
7077 callout_schedule(&intel_crtc->idle_callout, CRTC_IDLE_TIMEOUT);
7078 return;
7079 }
7080
7081 intel_crtc->busy = false;
7082 taskqueue_enqueue(dev_priv->tq, &dev_priv->idle_task);
7083}
7084
7085static void intel_increase_pllclock(struct drm_crtc *crtc)
7086{
7087 struct drm_device *dev = crtc->dev;
7088 drm_i915_private_t *dev_priv = dev->dev_private;
7089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7090 int pipe = intel_crtc->pipe;
7091 int dpll_reg = DPLL(pipe);
7092 int dpll;
7093
7094 if (HAS_PCH_SPLIT(dev))
7095 return;
7096
7097 if (!dev_priv->lvds_downclock_avail)
7098 return;
7099
7100 dpll = I915_READ(dpll_reg);
7101 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7102 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7103
7104 assert_panel_unlocked(dev_priv, pipe);
7105
7106 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7107 I915_WRITE(dpll_reg, dpll);
7108 intel_wait_for_vblank(dev, pipe);
7109
7110 dpll = I915_READ(dpll_reg);
7111 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7112 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7113 }
7114
7115 /* Schedule downclock */
7116 callout_reset(&intel_crtc->idle_callout, CRTC_IDLE_TIMEOUT,
7117 intel_crtc_idle_timer, intel_crtc);
7118}
7119
7120static void intel_decrease_pllclock(struct drm_crtc *crtc)
7121{
7122 struct drm_device *dev = crtc->dev;
7123 drm_i915_private_t *dev_priv = dev->dev_private;
7124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7125
7126 if (HAS_PCH_SPLIT(dev))
7127 return;
7128
7129 if (!dev_priv->lvds_downclock_avail)
7130 return;
7131
7132 /*
7133 * Since this is called by a timer, we should never get here in
7134 * the manual case.
7135 */
7136 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7137 int pipe = intel_crtc->pipe;
7138 int dpll_reg = DPLL(pipe);
7139 u32 dpll;
7140
7141 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7142
7143 assert_panel_unlocked(dev_priv, pipe);
7144
7145 dpll = I915_READ(dpll_reg);
7146 dpll |= DISPLAY_RATE_SELECT_FPA1;
7147 I915_WRITE(dpll_reg, dpll);
7148 intel_wait_for_vblank(dev, pipe);
7149 dpll = I915_READ(dpll_reg);
7150 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7151 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7152 }
7153}
7154
7155/**
7156 * intel_idle_update - adjust clocks for idleness
7157 * @work: work struct
7158 *
7159 * Either the GPU or display (or both) went idle. Check the busy status
7160 * here and adjust the CRTC and GPU clocks as necessary.
7161 */
7162static void intel_idle_update(void *arg, int pending)
7163{
7164 drm_i915_private_t *dev_priv = arg;
7165 struct drm_device *dev = dev_priv->dev;
7166 struct drm_crtc *crtc;
7167 struct intel_crtc *intel_crtc;
7168
7169 if (!i915_powersave)
7170 return;
7171
7172 DRM_LOCK(dev);
7173
7174 i915_update_gfx_val(dev_priv);
7175
7176 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7177 /* Skip inactive CRTCs */
7178 if (!crtc->fb)
7179 continue;
7180
7181 intel_crtc = to_intel_crtc(crtc);
7182 if (!intel_crtc->busy)
7183 intel_decrease_pllclock(crtc);
7184 }
7185
7186 DRM_UNLOCK(dev);
7187}
7188
7189/**
7190 * intel_mark_busy - mark the GPU and possibly the display busy
7191 * @dev: drm device
7192 * @obj: object we're operating on
7193 *
7194 * Callers can use this function to indicate that the GPU is busy processing
7195 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7196 * buffer), we'll also mark the display as busy, so we know to increase its
7197 * clock frequency.
7198 */
7199void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7200{
7201 drm_i915_private_t *dev_priv = dev->dev_private;
7202 struct drm_crtc *crtc = NULL;
7203 struct intel_framebuffer *intel_fb;
7204 struct intel_crtc *intel_crtc;
7205
7206 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7207 return;
7208
7209 if (!dev_priv->busy)
7210 dev_priv->busy = true;
7211 else
7212 callout_reset(&dev_priv->idle_callout, GPU_IDLE_TIMEOUT,
7213 intel_gpu_idle_timer, dev);
7214
7215 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7216 if (!crtc->fb)
7217 continue;
7218
7219 intel_crtc = to_intel_crtc(crtc);
7220 intel_fb = to_intel_framebuffer(crtc->fb);
7221 if (intel_fb->obj == obj) {
7222 if (!intel_crtc->busy) {
7223 /* Non-busy -> busy, upclock */
7224 intel_increase_pllclock(crtc);
7225 intel_crtc->busy = true;
7226 } else {
7227 /* Busy -> busy, put off timer */
7228 callout_reset(&intel_crtc->idle_callout,
7229 CRTC_IDLE_TIMEOUT, intel_crtc_idle_timer,
7230 intel_crtc);
7231 }
7232 }
7233 }
7234}
7235
7236static void intel_crtc_destroy(struct drm_crtc *crtc)
7237{
7238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7239 struct drm_device *dev = crtc->dev;
7240 struct drm_i915_private *dev_priv = dev->dev_private;
7241 struct intel_unpin_work *work;
7242
7243 mtx_lock(&dev->event_lock);
7244 work = intel_crtc->unpin_work;
7245 intel_crtc->unpin_work = NULL;
7246 mtx_unlock(&dev->event_lock);
7247
7248 if (work) {
7249 taskqueue_cancel(dev_priv->tq, &work->task, NULL);
7250 taskqueue_drain(dev_priv->tq, &work->task);
7251 free(work, DRM_MEM_KMS);
7252 }
7253
7254 drm_crtc_cleanup(crtc);
7255
7256 free(intel_crtc, DRM_MEM_KMS);
7257}
7258
7259static void intel_unpin_work_fn(void *arg, int pending)
7260{
7261 struct intel_unpin_work *work = arg;
7262 struct drm_device *dev;
7263
7264 dev = work->dev;
7265 DRM_LOCK(dev);
7266 intel_unpin_fb_obj(work->old_fb_obj);
7267 drm_gem_object_unreference(&work->pending_flip_obj->base);
7268 drm_gem_object_unreference(&work->old_fb_obj->base);
7269
7270 intel_update_fbc(work->dev);
7271 DRM_UNLOCK(dev);
7272 free(work, DRM_MEM_KMS);
7273}
7274
7275static void do_intel_finish_page_flip(struct drm_device *dev,
7276 struct drm_crtc *crtc)
7277{
7278 drm_i915_private_t *dev_priv = dev->dev_private;
7279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7280 struct intel_unpin_work *work;
7281 struct drm_i915_gem_object *obj;
7282 struct drm_pending_vblank_event *e;
7283 struct timeval tnow, tvbl;
7284
7285 /* Ignore early vblank irqs */
7286 if (intel_crtc == NULL)
7287 return;
7288
7289 microtime(&tnow);
7290
7291 mtx_lock(&dev->event_lock);
7292 work = intel_crtc->unpin_work;
7293 if (work == NULL || !work->pending) {
7294 mtx_unlock(&dev->event_lock);
7295 return;
7296 }
7297
7298 intel_crtc->unpin_work = NULL;
7299
7300 if (work->event) {
7301 e = work->event;
7302 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7303
7304 /* Called before vblank count and timestamps have
7305 * been updated for the vblank interval of flip
7306 * completion? Need to increment vblank count and
7307 * add one videorefresh duration to returned timestamp
7308 * to account for this. We assume this happened if we
7309 * get called over 0.9 frame durations after the last
7310 * timestamped vblank.
7311 *
7312 * This calculation can not be used with vrefresh rates
7313 * below 5Hz (10Hz to be on the safe side) without
7314 * promoting to 64 integers.
7315 */
7316 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7317 9 * crtc->framedur_ns) {
7318 e->event.sequence++;
7319 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7320 crtc->framedur_ns);
7321 }
7322
7323 e->event.tv_sec = tvbl.tv_sec;
7324 e->event.tv_usec = tvbl.tv_usec;
7325
7326 list_add_tail(&e->base.link,
7327 &e->base.file_priv->event_list);
7328 drm_event_wakeup(&e->base);
7329 }
7330
7331 drm_vblank_put(dev, intel_crtc->pipe);
7332
7333 obj = work->old_fb_obj;
7334
7335 atomic_clear_int(&obj->pending_flip, 1 << intel_crtc->plane);
7336 if (atomic_read(&obj->pending_flip) == 0)
7337 wakeup(&obj->pending_flip);
7338 mtx_unlock(&dev->event_lock);
7339
7340 taskqueue_enqueue(dev_priv->tq, &work->task);
7341
7342 CTR2(KTR_DRM, "i915_flip_complete %d %p", intel_crtc->plane,
7343 work->pending_flip_obj);
7344}
7345
7346void intel_finish_page_flip(struct drm_device *dev, int pipe)
7347{
7348 drm_i915_private_t *dev_priv = dev->dev_private;
7349 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7350
7351 do_intel_finish_page_flip(dev, crtc);
7352}
7353
7354void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7355{
7356 drm_i915_private_t *dev_priv = dev->dev_private;
7357 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7358
7359 do_intel_finish_page_flip(dev, crtc);
7360}
7361
7362void intel_prepare_page_flip(struct drm_device *dev, int plane)
7363{
7364 drm_i915_private_t *dev_priv = dev->dev_private;
7365 struct intel_crtc *intel_crtc =
7366 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7367
7368 mtx_lock(&dev->event_lock);
7369 if (intel_crtc->unpin_work) {
7370 if ((++intel_crtc->unpin_work->pending) > 1)
7371 DRM_ERROR("Prepared flip multiple times\n");
7372 } else {
7373 DRM_DEBUG("preparing flip with no unpin work?\n");
7374 }
7375 mtx_unlock(&dev->event_lock);
7376}
7377
7378static int intel_gen2_queue_flip(struct drm_device *dev,
7379 struct drm_crtc *crtc,
7380 struct drm_framebuffer *fb,
7381 struct drm_i915_gem_object *obj)
7382{
7383 struct drm_i915_private *dev_priv = dev->dev_private;
7384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7385 unsigned long offset;
7386 u32 flip_mask;
7387 int ret;
7388
7389 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7390 if (ret)
7391 goto out;
7392
7393 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7394 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7395
7396 ret = BEGIN_LP_RING(6);
7397 if (ret)
7398 goto out;
7399
7400 /* Can't queue multiple flips, so wait for the previous
7401 * one to finish before executing the next.
7402 */
7403 if (intel_crtc->plane)
7404 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7405 else
7406 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7407 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7408 OUT_RING(MI_NOOP);
7409 OUT_RING(MI_DISPLAY_FLIP |
7410 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7411 OUT_RING(fb->pitches[0]);
7412 OUT_RING(obj->gtt_offset + offset);
7413 OUT_RING(0); /* aux display base address, unused */
7414 ADVANCE_LP_RING();
7415out:
7416 return ret;
7417}
7418
7419static int intel_gen3_queue_flip(struct drm_device *dev,
7420 struct drm_crtc *crtc,
7421 struct drm_framebuffer *fb,
7422 struct drm_i915_gem_object *obj)
7423{
7424 struct drm_i915_private *dev_priv = dev->dev_private;
7425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7426 unsigned long offset;
7427 u32 flip_mask;
7428 int ret;
7429
7430 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7431 if (ret)
7432 goto out;
7433
7434 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7435 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7436
7437 ret = BEGIN_LP_RING(6);
7438 if (ret)
7439 goto out;
7440
7441 if (intel_crtc->plane)
7442 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7443 else
7444 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7445 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7446 OUT_RING(MI_NOOP);
7447 OUT_RING(MI_DISPLAY_FLIP_I915 |
7448 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7449 OUT_RING(fb->pitches[0]);
7450 OUT_RING(obj->gtt_offset + offset);
7451 OUT_RING(MI_NOOP);
7452
7453 ADVANCE_LP_RING();
7454out:
7455 return ret;
7456}
7457
7458static int intel_gen4_queue_flip(struct drm_device *dev,
7459 struct drm_crtc *crtc,
7460 struct drm_framebuffer *fb,
7461 struct drm_i915_gem_object *obj)
7462{
7463 struct drm_i915_private *dev_priv = dev->dev_private;
7464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7465 uint32_t pf, pipesrc;
7466 int ret;
7467
7468 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7469 if (ret)
7470 goto out;
7471
7472 ret = BEGIN_LP_RING(4);
7473 if (ret)
7474 goto out;
7475
7476 /* i965+ uses the linear or tiled offsets from the
7477 * Display Registers (which do not change across a page-flip)
7478 * so we need only reprogram the base address.
7479 */
7480 OUT_RING(MI_DISPLAY_FLIP |
7481 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7482 OUT_RING(fb->pitches[0]);
7483 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7484
7485 /* XXX Enabling the panel-fitter across page-flip is so far
7486 * untested on non-native modes, so ignore it for now.
7487 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7488 */
7489 pf = 0;
7490 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7491 OUT_RING(pf | pipesrc);
7492 ADVANCE_LP_RING();
7493out:
7494 return ret;
7495}
7496
7497static int intel_gen6_queue_flip(struct drm_device *dev,
7498 struct drm_crtc *crtc,
7499 struct drm_framebuffer *fb,
7500 struct drm_i915_gem_object *obj)
7501{
7502 struct drm_i915_private *dev_priv = dev->dev_private;
7503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7504 uint32_t pf, pipesrc;
7505 int ret;
7506
7507 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7508 if (ret)
7509 goto out;
7510
7511 ret = BEGIN_LP_RING(4);
7512 if (ret)
7513 goto out;
7514
7515 OUT_RING(MI_DISPLAY_FLIP |
7516 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7517 OUT_RING(fb->pitches[0] | obj->tiling_mode);
7518 OUT_RING(obj->gtt_offset);
7519
7520 /* Contrary to the suggestions in the documentation,
7521 * "Enable Panel Fitter" does not seem to be required when page
7522 * flipping with a non-native mode, and worse causes a normal
7523 * modeset to fail.
7524 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7525 */
7526 pf = 0;
7527 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7528 OUT_RING(pf | pipesrc);
7529 ADVANCE_LP_RING();
7530out:
7531 return ret;
7532}
7533
7534/*
7535 * On gen7 we currently use the blit ring because (in early silicon at least)
7536 * the render ring doesn't give us interrpts for page flip completion, which
7537 * means clients will hang after the first flip is queued. Fortunately the
7538 * blit ring generates interrupts properly, so use it instead.
7539 */
7540static int intel_gen7_queue_flip(struct drm_device *dev,
7541 struct drm_crtc *crtc,
7542 struct drm_framebuffer *fb,
7543 struct drm_i915_gem_object *obj)
7544{
7545 struct drm_i915_private *dev_priv = dev->dev_private;
7546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7547 struct intel_ring_buffer *ring = &dev_priv->rings[BCS];
7548 int ret;
7549
7550 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7551 if (ret)
7552 goto out;
7553
7554 ret = intel_ring_begin(ring, 4);
7555 if (ret)
7556 goto out;
7557
7558 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7559 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7560 intel_ring_emit(ring, (obj->gtt_offset));
7561 intel_ring_emit(ring, (MI_NOOP));
7562 intel_ring_advance(ring);
7563out:
7564 return ret;
7565}
7566
7567static int intel_default_queue_flip(struct drm_device *dev,
7568 struct drm_crtc *crtc,
7569 struct drm_framebuffer *fb,
7570 struct drm_i915_gem_object *obj)
7571{
7572 return -ENODEV;
7573}
7574
7575static int intel_crtc_page_flip(struct drm_crtc *crtc,
7576 struct drm_framebuffer *fb,
7577 struct drm_pending_vblank_event *event)
7578{
7579 struct drm_device *dev = crtc->dev;
7580 struct drm_i915_private *dev_priv = dev->dev_private;
7581 struct intel_framebuffer *intel_fb;
7582 struct drm_i915_gem_object *obj;
7583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7584 struct intel_unpin_work *work;
7585 int ret;
7586
7587 work = malloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO);
7588
7589 work->event = event;
7590 work->dev = crtc->dev;
7591 intel_fb = to_intel_framebuffer(crtc->fb);
7592 work->old_fb_obj = intel_fb->obj;
7593 TASK_INIT(&work->task, 0, intel_unpin_work_fn, work);
7594
7595 ret = drm_vblank_get(dev, intel_crtc->pipe);
7596 if (ret)
7597 goto free_work;
7598
7599 /* We borrow the event spin lock for protecting unpin_work */
7600 mtx_lock(&dev->event_lock);
7601 if (intel_crtc->unpin_work) {
7602 mtx_unlock(&dev->event_lock);
7603 free(work, DRM_MEM_KMS);
7604 drm_vblank_put(dev, intel_crtc->pipe);
7605
7606 DRM_DEBUG("flip queue: crtc already busy\n");
7607 return -EBUSY;
7608 }
7609 intel_crtc->unpin_work = work;
7610 mtx_unlock(&dev->event_lock);
7611
7612 intel_fb = to_intel_framebuffer(fb);
7613 obj = intel_fb->obj;
7614
7615 DRM_LOCK(dev);
7616
7617 /* Reference the objects for the scheduled work. */
7618 drm_gem_object_reference(&work->old_fb_obj->base);
7619 drm_gem_object_reference(&obj->base);
7620
7621 crtc->fb = fb;
7622
7623 work->pending_flip_obj = obj;
7624
7625 work->enable_stall_check = true;
7626
7627 /* Block clients from rendering to the new back buffer until
7628 * the flip occurs and the object is no longer visible.
7629 */
7630 atomic_set_int(&work->old_fb_obj->pending_flip, 1 << intel_crtc->plane);
7631
7632 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7633 if (ret)
7634 goto cleanup_pending;
7635 intel_disable_fbc(dev);
7636 DRM_UNLOCK(dev);
7637
7638 CTR2(KTR_DRM, "i915_flip_request %d %p", intel_crtc->plane, obj);
7639
7640 return 0;
7641
7642cleanup_pending:
7643 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7644 drm_gem_object_unreference(&work->old_fb_obj->base);
7645 drm_gem_object_unreference(&obj->base);
7646 DRM_UNLOCK(dev);
7647
7648 mtx_lock(&dev->event_lock);
7649 intel_crtc->unpin_work = NULL;
7650 mtx_unlock(&dev->event_lock);
7651
7652 drm_vblank_put(dev, intel_crtc->pipe);
7653free_work:
7654 free(work, DRM_MEM_KMS);
7655
7656 return ret;
7657}
7658
7659static void intel_sanitize_modesetting(struct drm_device *dev,
7660 int pipe, int plane)
7661{
7662 struct drm_i915_private *dev_priv = dev->dev_private;
7663 u32 reg, val;
7664
7665 /* Clear any frame start delays used for debugging left by the BIOS */
7666 for_each_pipe(pipe) {
7667 reg = PIPECONF(pipe);
7668 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7669 }
7670
7671 if (HAS_PCH_SPLIT(dev))
7672 return;
7673
7674 /* Who knows what state these registers were left in by the BIOS or
7675 * grub?
7676 *
7677 * If we leave the registers in a conflicting state (e.g. with the
7678 * display plane reading from the other pipe than the one we intend
7679 * to use) then when we attempt to teardown the active mode, we will
7680 * not disable the pipes and planes in the correct order -- leaving
7681 * a plane reading from a disabled pipe and possibly leading to
7682 * undefined behaviour.
7683 */
7684
7685 reg = DSPCNTR(plane);
7686 val = I915_READ(reg);
7687
7688 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7689 return;
7690 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7691 return;
7692
7693 /* This display plane is active and attached to the other CPU pipe. */
7694 pipe = !pipe;
7695
7696 /* Disable the plane and wait for it to stop reading from the pipe. */
7697 intel_disable_plane(dev_priv, plane, pipe);
7698 intel_disable_pipe(dev_priv, pipe);
7699}
7700
7701static void intel_crtc_reset(struct drm_crtc *crtc)
7702{
7703 struct drm_device *dev = crtc->dev;
7704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7705
7706 /* Reset flags back to the 'unknown' status so that they
7707 * will be correctly set on the initial modeset.
7708 */
7709 intel_crtc->dpms_mode = -1;
7710
7711 /* We need to fix up any BIOS configuration that conflicts with
7712 * our expectations.
7713 */
7714 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7715}
7716
7717static struct drm_crtc_helper_funcs intel_helper_funcs = {
7718 .dpms = intel_crtc_dpms,
7719 .mode_fixup = intel_crtc_mode_fixup,
7720 .mode_set = intel_crtc_mode_set,
7721 .mode_set_base = intel_pipe_set_base,
7722 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7723 .load_lut = intel_crtc_load_lut,
7724 .disable = intel_crtc_disable,
7725};
7726
7727static const struct drm_crtc_funcs intel_crtc_funcs = {
7728 .reset = intel_crtc_reset,
7729 .cursor_set = intel_crtc_cursor_set,
7730 .cursor_move = intel_crtc_cursor_move,
7731 .gamma_set = intel_crtc_gamma_set,
7732 .set_config = drm_crtc_helper_set_config,
7733 .destroy = intel_crtc_destroy,
7734 .page_flip = intel_crtc_page_flip,
7735};
7736
7737static void intel_crtc_init(struct drm_device *dev, int pipe)
7738{
7739 drm_i915_private_t *dev_priv = dev->dev_private;
7740 struct intel_crtc *intel_crtc;
7741 int i;
7742
7743 intel_crtc = malloc(sizeof(struct intel_crtc) +
7744 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
7745 DRM_MEM_KMS, M_WAITOK | M_ZERO);
7746
7747 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7748
7749 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7750 for (i = 0; i < 256; i++) {
7751 intel_crtc->lut_r[i] = i;
7752 intel_crtc->lut_g[i] = i;
7753 intel_crtc->lut_b[i] = i;
7754 }
7755
7756 /* Swap pipes & planes for FBC on pre-965 */
7757 intel_crtc->pipe = pipe;
7758 intel_crtc->plane = pipe;
7759 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7760 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7761 intel_crtc->plane = !pipe;
7762 }
7763
7764 KASSERT(pipe < DRM_ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) &&
7765 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] == NULL,
7766 ("plane_to_crtc is already initialized"));
7767 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7768 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7769
7770 intel_crtc_reset(&intel_crtc->base);
7771 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7772 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7773
7774 if (HAS_PCH_SPLIT(dev)) {
7775 if (pipe == 2 && IS_IVYBRIDGE(dev))
7776 intel_crtc->no_pll = true;
7777 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7778 intel_helper_funcs.commit = ironlake_crtc_commit;
7779 } else {
7780 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7781 intel_helper_funcs.commit = i9xx_crtc_commit;
7782 }
7783
7784 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7785
7786 intel_crtc->busy = false;
7787
7788 callout_init(&intel_crtc->idle_callout, CALLOUT_MPSAFE);
7789}
7790
7791int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7792 struct drm_file *file)
7793{
7794 drm_i915_private_t *dev_priv = dev->dev_private;
7795 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7796 struct drm_mode_object *drmmode_obj;
7797 struct intel_crtc *crtc;
7798
7799 if (!dev_priv) {
7800 DRM_ERROR("called with no initialization\n");
7801 return -EINVAL;
7802 }
7803
7804 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7805 DRM_MODE_OBJECT_CRTC);
7806
7807 if (!drmmode_obj) {
7808 DRM_ERROR("no such CRTC id\n");
7809 return -EINVAL;
7810 }
7811
7812 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7813 pipe_from_crtc_id->pipe = crtc->pipe;
7814
7815 return 0;
7816}
7817
7818static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7819{
7820 struct intel_encoder *encoder;
7821 int index_mask = 0;
7822 int entry = 0;
7823
7824 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7825 if (type_mask & encoder->clone_mask)
7826 index_mask |= (1 << entry);
7827 entry++;
7828 }
7829
7830 return index_mask;
7831}
7832
7833static bool has_edp_a(struct drm_device *dev)
7834{
7835 struct drm_i915_private *dev_priv = dev->dev_private;
7836
7837 if (!IS_MOBILE(dev))
7838 return false;
7839
7840 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7841 return false;
7842
7843 if (IS_GEN5(dev) &&
7844 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7845 return false;
7846
7847 return true;
7848}
7849
7850static void intel_setup_outputs(struct drm_device *dev)
7851{
7852 struct drm_i915_private *dev_priv = dev->dev_private;
7853 struct intel_encoder *encoder;
7854 bool dpd_is_edp = false;
7855 bool has_lvds;
7856
7857 has_lvds = intel_lvds_init(dev);
7858 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7859 /* disable the panel fitter on everything but LVDS */
7860 I915_WRITE(PFIT_CONTROL, 0);
7861 }
7862
7863 if (HAS_PCH_SPLIT(dev)) {
7864 dpd_is_edp = intel_dpd_is_edp(dev);
7865
7866 if (has_edp_a(dev))
7867 intel_dp_init(dev, DP_A);
7868
7869 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7870 intel_dp_init(dev, PCH_DP_D);
7871 }
7872
7873 intel_crt_init(dev);
7874
7875 if (HAS_PCH_SPLIT(dev)) {
7876 int found;
7877
7878 DRM_DEBUG_KMS(
7879"HDMIB %d PCH_DP_B %d HDMIC %d HDMID %d PCH_DP_C %d PCH_DP_D %d LVDS %d\n",
7880 (I915_READ(HDMIB) & PORT_DETECTED) != 0,
7881 (I915_READ(PCH_DP_B) & DP_DETECTED) != 0,
7882 (I915_READ(HDMIC) & PORT_DETECTED) != 0,
7883 (I915_READ(HDMID) & PORT_DETECTED) != 0,
7884 (I915_READ(PCH_DP_C) & DP_DETECTED) != 0,
7885 (I915_READ(PCH_DP_D) & DP_DETECTED) != 0,
7886 (I915_READ(PCH_LVDS) & LVDS_DETECTED) != 0);
7887
7888 if (I915_READ(HDMIB) & PORT_DETECTED) {
7889 /* PCH SDVOB multiplex with HDMIB */
7890 found = intel_sdvo_init(dev, PCH_SDVOB);
7891 if (!found)
7892 intel_hdmi_init(dev, HDMIB);
7893 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7894 intel_dp_init(dev, PCH_DP_B);
7895 }
7896
7897 if (I915_READ(HDMIC) & PORT_DETECTED)
7898 intel_hdmi_init(dev, HDMIC);
7899
7900 if (I915_READ(HDMID) & PORT_DETECTED)
7901 intel_hdmi_init(dev, HDMID);
7902
7903 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7904 intel_dp_init(dev, PCH_DP_C);
7905
7906 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7907 intel_dp_init(dev, PCH_DP_D);
7908
7909 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7910 bool found = false;
7911
7912 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7913 DRM_DEBUG_KMS("probing SDVOB\n");
7914 found = intel_sdvo_init(dev, SDVOB);
7915 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7916 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7917 intel_hdmi_init(dev, SDVOB);
7918 }
7919
7920 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7921 DRM_DEBUG_KMS("probing DP_B\n");
7922 intel_dp_init(dev, DP_B);
7923 }
7924 }
7925
7926 /* Before G4X SDVOC doesn't have its own detect register */
7927
7928 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7929 DRM_DEBUG_KMS("probing SDVOC\n");
7930 found = intel_sdvo_init(dev, SDVOC);
7931 }
7932
7933 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7934
7935 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7936 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7937 intel_hdmi_init(dev, SDVOC);
7938 }
7939 if (SUPPORTS_INTEGRATED_DP(dev)) {
7940 DRM_DEBUG_KMS("probing DP_C\n");
7941 intel_dp_init(dev, DP_C);
7942 }
7943 }
7944
7945 if (SUPPORTS_INTEGRATED_DP(dev) &&
7946 (I915_READ(DP_D) & DP_DETECTED)) {
7947 DRM_DEBUG_KMS("probing DP_D\n");
7948 intel_dp_init(dev, DP_D);
7949 }
7950 } else if (IS_GEN2(dev)) {
7951#if 1
7952 KIB_NOTYET();
7953#else
7954 intel_dvo_init(dev);
7955#endif
7956 }
7957
7958 if (SUPPORTS_TV(dev))
7959 intel_tv_init(dev);
7960
7961 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7962 encoder->base.possible_crtcs = encoder->crtc_mask;
7963 encoder->base.possible_clones =
7964 intel_encoder_clones(dev, encoder->clone_mask);
7965 }
7966
7967 /* disable all the possible outputs/crtcs before entering KMS mode */
7968 drm_helper_disable_unused_functions(dev);
7969
7970 if (HAS_PCH_SPLIT(dev))
7971 ironlake_init_pch_refclk(dev);
7972}
7973
7974static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7975{
7976 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7977
7978 drm_framebuffer_cleanup(fb);
7979 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7980
7981 free(intel_fb, DRM_MEM_KMS);
7982}
7983
7984static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7985 struct drm_file *file,
7986 unsigned int *handle)
7987{
7988 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7989 struct drm_i915_gem_object *obj = intel_fb->obj;
7990
7991 return drm_gem_handle_create(file, &obj->base, handle);
7992}
7993
7994static const struct drm_framebuffer_funcs intel_fb_funcs = {
7995 .destroy = intel_user_framebuffer_destroy,
7996 .create_handle = intel_user_framebuffer_create_handle,
7997};
7998
7999int intel_framebuffer_init(struct drm_device *dev,
8000 struct intel_framebuffer *intel_fb,
8001 struct drm_mode_fb_cmd2 *mode_cmd,
8002 struct drm_i915_gem_object *obj)
8003{
8004 int ret;
8005
8006 if (obj->tiling_mode == I915_TILING_Y)
8007 return -EINVAL;
8008
8009 if (mode_cmd->pitches[0] & 63)
8010 return -EINVAL;
8011
8012 switch (mode_cmd->pixel_format) {
8013 case DRM_FORMAT_RGB332:
8014 case DRM_FORMAT_RGB565:
8015 case DRM_FORMAT_XRGB8888:
8016 case DRM_FORMAT_XBGR8888:
8017 case DRM_FORMAT_ARGB8888:
8018 case DRM_FORMAT_XRGB2101010:
8019 case DRM_FORMAT_ARGB2101010:
8020 /* RGB formats are common across chipsets */
8021 break;
8022 case DRM_FORMAT_YUYV:
8023 case DRM_FORMAT_UYVY:
8024 case DRM_FORMAT_YVYU:
8025 case DRM_FORMAT_VYUY:
8026 break;
8027 default:
8028 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8029 mode_cmd->pixel_format);
8030 return -EINVAL;
8031 }
8032
8033 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8034 if (ret) {
8035 DRM_ERROR("framebuffer init failed %d\n", ret);
8036 return ret;
8037 }
8038
8039 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8040 intel_fb->obj = obj;
8041 return 0;
8042}
8043
8044static int
8045intel_user_framebuffer_create(struct drm_device *dev,
8046 struct drm_file *filp, struct drm_mode_fb_cmd2 *mode_cmd,
8047 struct drm_framebuffer **res)
8048{
8049 struct drm_i915_gem_object *obj;
8050
8051 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8052 mode_cmd->handles[0]));
8053 if (&obj->base == NULL)
8054 return (-ENOENT);
8055
8056 return (intel_framebuffer_create(dev, mode_cmd, obj, res));
8057}
8058
8059static const struct drm_mode_config_funcs intel_mode_funcs = {
8060 .fb_create = intel_user_framebuffer_create,
8061 .output_poll_changed = intel_fb_output_poll_changed,
8062};
8063
8064static struct drm_i915_gem_object *
8065intel_alloc_context_page(struct drm_device *dev)
8066{
8067 struct drm_i915_gem_object *ctx;
8068 int ret;
8069
8070 DRM_LOCK_ASSERT(dev);
8071
8072 ctx = i915_gem_alloc_object(dev, 4096);
8073 if (!ctx) {
8074 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8075 return NULL;
8076 }
8077
8078 ret = i915_gem_object_pin(ctx, 4096, true);
8079 if (ret) {
8080 DRM_ERROR("failed to pin power context: %d\n", ret);
8081 goto err_unref;
8082 }
8083
8084 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8085 if (ret) {
8086 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8087 goto err_unpin;
8088 }
8089
8090 return ctx;
8091
8092err_unpin:
8093 i915_gem_object_unpin(ctx);
8094err_unref:
8095 drm_gem_object_unreference(&ctx->base);
8096 DRM_UNLOCK(dev);
8097 return NULL;
8098}
8099
8100bool ironlake_set_drps(struct drm_device *dev, u8 val)
8101{
8102 struct drm_i915_private *dev_priv = dev->dev_private;
8103 u16 rgvswctl;
8104
8105 rgvswctl = I915_READ16(MEMSWCTL);
8106 if (rgvswctl & MEMCTL_CMD_STS) {
8107 DRM_DEBUG("gpu busy, RCS change rejected\n");
8108 return false; /* still busy with another command */
8109 }
8110
8111 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8112 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8113 I915_WRITE16(MEMSWCTL, rgvswctl);
8114 POSTING_READ16(MEMSWCTL);
8115
8116 rgvswctl |= MEMCTL_CMD_STS;
8117 I915_WRITE16(MEMSWCTL, rgvswctl);
8118
8119 return true;
8120}
8121
8122void ironlake_enable_drps(struct drm_device *dev)
8123{
8124 struct drm_i915_private *dev_priv = dev->dev_private;
8125 u32 rgvmodectl = I915_READ(MEMMODECTL);
8126 u8 fmax, fmin, fstart, vstart;
8127
8128 /* Enable temp reporting */
8129 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8130 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8131
8132 /* 100ms RC evaluation intervals */
8133 I915_WRITE(RCUPEI, 100000);
8134 I915_WRITE(RCDNEI, 100000);
8135
8136 /* Set max/min thresholds to 90ms and 80ms respectively */
8137 I915_WRITE(RCBMAXAVG, 90000);
8138 I915_WRITE(RCBMINAVG, 80000);
8139
8140 I915_WRITE(MEMIHYST, 1);
8141
8142 /* Set up min, max, and cur for interrupt handling */
8143 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8144 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8145 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8146 MEMMODE_FSTART_SHIFT;
8147
8148 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8149 PXVFREQ_PX_SHIFT;
8150
8151 dev_priv->fmax = fmax; /* IPS callback will increase this */
8152 dev_priv->fstart = fstart;
8153
8154 dev_priv->max_delay = fstart;
8155 dev_priv->min_delay = fmin;
8156 dev_priv->cur_delay = fstart;
8157
8158 DRM_DEBUG("fmax: %d, fmin: %d, fstart: %d\n",
8159 fmax, fmin, fstart);
8160
8161 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8162
8163 /*
8164 * Interrupts will be enabled in ironlake_irq_postinstall
8165 */
8166
8167 I915_WRITE(VIDSTART, vstart);
8168 POSTING_READ(VIDSTART);
8169
8170 rgvmodectl |= MEMMODE_SWMODE_EN;
8171 I915_WRITE(MEMMODECTL, rgvmodectl);
8172
8173 if (_intel_wait_for(dev,
8174 (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10,
8175 1, "915per"))
8176 DRM_ERROR("stuck trying to change perf mode\n");
8177 pause("915dsp", 1);
8178
8179 ironlake_set_drps(dev, fstart);
8180
8181 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8182 I915_READ(0x112e0);
8183 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8184 dev_priv->last_count2 = I915_READ(0x112f4);
8185 nanotime(&dev_priv->last_time2);
8186}
8187
8188void ironlake_disable_drps(struct drm_device *dev)
8189{
8190 struct drm_i915_private *dev_priv = dev->dev_private;
8191 u16 rgvswctl = I915_READ16(MEMSWCTL);
8192
8193 /* Ack interrupts, disable EFC interrupt */
8194 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8195 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8196 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8197 I915_WRITE(DEIIR, DE_PCU_EVENT);
8198 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8199
8200 /* Go back to the starting frequency */
8201 ironlake_set_drps(dev, dev_priv->fstart);
8202 pause("915dsp", 1);
8203 rgvswctl |= MEMCTL_CMD_STS;
8204 I915_WRITE(MEMSWCTL, rgvswctl);
8205 pause("915dsp", 1);
8206
8207}
8208
8209void gen6_set_rps(struct drm_device *dev, u8 val)
8210{
8211 struct drm_i915_private *dev_priv = dev->dev_private;
8212 u32 swreq;
8213
8214 swreq = (val & 0x3ff) << 25;
8215 I915_WRITE(GEN6_RPNSWREQ, swreq);
8216}
8217
8218void gen6_disable_rps(struct drm_device *dev)
8219{
8220 struct drm_i915_private *dev_priv = dev->dev_private;
8221
8222 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8223 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8224 I915_WRITE(GEN6_PMIER, 0);
8225 /* Complete PM interrupt masking here doesn't race with the rps work
8226 * item again unmasking PM interrupts because that is using a different
8227 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8228 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8229
8230 mtx_lock(&dev_priv->rps_lock);
8231 dev_priv->pm_iir = 0;
8232 mtx_unlock(&dev_priv->rps_lock);
8233
8234 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8235}
8236
8237static unsigned long intel_pxfreq(u32 vidfreq)
8238{
8239 unsigned long freq;
8240 int div = (vidfreq & 0x3f0000) >> 16;
8241 int post = (vidfreq & 0x3000) >> 12;
8242 int pre = (vidfreq & 0x7);
8243
8244 if (!pre)
8245 return 0;
8246
8247 freq = ((div * 133333) / ((1<<post) * pre));
8248
8249 return freq;
8250}
8251
8252void intel_init_emon(struct drm_device *dev)
8253{
8254 struct drm_i915_private *dev_priv = dev->dev_private;
8255 u32 lcfuse;
8256 u8 pxw[16];
8257 int i;
8258
8259 /* Disable to program */
8260 I915_WRITE(ECR, 0);
8261 POSTING_READ(ECR);
8262
8263 /* Program energy weights for various events */
8264 I915_WRITE(SDEW, 0x15040d00);
8265 I915_WRITE(CSIEW0, 0x007f0000);
8266 I915_WRITE(CSIEW1, 0x1e220004);
8267 I915_WRITE(CSIEW2, 0x04000004);
8268
8269 for (i = 0; i < 5; i++)
8270 I915_WRITE(PEW + (i * 4), 0);
8271 for (i = 0; i < 3; i++)
8272 I915_WRITE(DEW + (i * 4), 0);
8273
8274 /* Program P-state weights to account for frequency power adjustment */
8275 for (i = 0; i < 16; i++) {
8276 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8277 unsigned long freq = intel_pxfreq(pxvidfreq);
8278 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8279 PXVFREQ_PX_SHIFT;
8280 unsigned long val;
8281
8282 val = vid * vid;
8283 val *= (freq / 1000);
8284 val *= 255;
8285 val /= (127*127*900);
8286 if (val > 0xff)
8287 DRM_ERROR("bad pxval: %ld\n", val);
8288 pxw[i] = val;
8289 }
8290 /* Render standby states get 0 weight */
8291 pxw[14] = 0;
8292 pxw[15] = 0;
8293
8294 for (i = 0; i < 4; i++) {
8295 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8296 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8297 I915_WRITE(PXW + (i * 4), val);
8298 }
8299
8300 /* Adjust magic regs to magic values (more experimental results) */
8301 I915_WRITE(OGW0, 0);
8302 I915_WRITE(OGW1, 0);
8303 I915_WRITE(EG0, 0x00007f00);
8304 I915_WRITE(EG1, 0x0000000e);
8305 I915_WRITE(EG2, 0x000e0000);
8306 I915_WRITE(EG3, 0x68000300);
8307 I915_WRITE(EG4, 0x42000000);
8308 I915_WRITE(EG5, 0x00140031);
8309 I915_WRITE(EG6, 0);
8310 I915_WRITE(EG7, 0);
8311
8312 for (i = 0; i < 8; i++)
8313 I915_WRITE(PXWL + (i * 4), 0);
8314
8315 /* Enable PMON + select events */
8316 I915_WRITE(ECR, 0x80000019);
8317
8318 lcfuse = I915_READ(LCFUSE02);
8319
8320 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8321}
8322
8323static int intel_enable_rc6(struct drm_device *dev)
8324{
8325 /*
8326 * Respect the kernel parameter if it is set
8327 */
8328 if (i915_enable_rc6 >= 0)
8329 return i915_enable_rc6;
8330
8331 /*
8332 * Disable RC6 on Ironlake
8333 */
8334 if (INTEL_INFO(dev)->gen == 5)
8335 return 0;
8336
8337 /*
8338 * Enable rc6 on Sandybridge if DMA remapping is disabled
8339 */
8340 if (INTEL_INFO(dev)->gen == 6) {
8341 DRM_DEBUG_DRIVER(
8342 "Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",
8343 intel_iommu_enabled ? "true" : "false",
8344 !intel_iommu_enabled ? "en" : "dis");
8345 return (intel_iommu_enabled ? 0 : INTEL_RC6_ENABLE);
8346 }
8347 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
8348 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8349}
8350
8351void gen6_enable_rps(struct drm_i915_private *dev_priv)
8352{
8353 struct drm_device *dev = dev_priv->dev;
8354 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8355 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8356 u32 pcu_mbox, rc6_mask = 0;
8357 u32 gtfifodbg;
8358 int cur_freq, min_freq, max_freq;
8359 int rc6_mode;
8360 int i;
8361
8362 /* Here begins a magic sequence of register writes to enable
8363 * auto-downclocking.
8364 *
8365 * Perhaps there might be some value in exposing these to
8366 * userspace...
8367 */
8368 I915_WRITE(GEN6_RC_STATE, 0);
8369 DRM_LOCK(dev);
8370
8371 /* Clear the DBG now so we don't confuse earlier errors */
8372 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8373 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8374 I915_WRITE(GTFIFODBG, gtfifodbg);
8375 }
8376
8377 gen6_gt_force_wake_get(dev_priv);
8378
8379 /* disable the counters and set deterministic thresholds */
8380 I915_WRITE(GEN6_RC_CONTROL, 0);
8381
8382 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8383 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8384 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8385 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8386 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8387
8388 for (i = 0; i < I915_NUM_RINGS; i++)
8389 I915_WRITE(RING_MAX_IDLE(dev_priv->rings[i].mmio_base), 10);
8390
8391 I915_WRITE(GEN6_RC_SLEEP, 0);
8392 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8393 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8394 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8395 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8396
8397 rc6_mode = intel_enable_rc6(dev_priv->dev);
8398 if (rc6_mode & INTEL_RC6_ENABLE)
8399 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
8400
8401 if (rc6_mode & INTEL_RC6p_ENABLE)
8402 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
8403
8404 if (rc6_mode & INTEL_RC6pp_ENABLE)
8405 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
8406
8407 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
8408 (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
8409 (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
8410 (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
8411
8412 I915_WRITE(GEN6_RC_CONTROL,
8413 rc6_mask |
8414 GEN6_RC_CTL_EI_MODE(1) |
8415 GEN6_RC_CTL_HW_ENABLE);
8416
8417 I915_WRITE(GEN6_RPNSWREQ,
8418 GEN6_FREQUENCY(10) |
8419 GEN6_OFFSET(0) |
8420 GEN6_AGGRESSIVE_TURBO);
8421 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8422 GEN6_FREQUENCY(12));
8423
8424 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8425 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8426 18 << 24 |
8427 6 << 16);
8428 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8429 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8430 I915_WRITE(GEN6_RP_UP_EI, 100000);
8431 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8432 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8433 I915_WRITE(GEN6_RP_CONTROL,
8434 GEN6_RP_MEDIA_TURBO |
8435 GEN6_RP_MEDIA_HW_MODE |
8436 GEN6_RP_MEDIA_IS_GFX |
8437 GEN6_RP_ENABLE |
8438 GEN6_RP_UP_BUSY_AVG |
8439 GEN6_RP_DOWN_IDLE_CONT);
8440
8441 if (_intel_wait_for(dev,
8442 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500,
8443 1, "915pr1"))
8444 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8445
8446 I915_WRITE(GEN6_PCODE_DATA, 0);
8447 I915_WRITE(GEN6_PCODE_MAILBOX,
8448 GEN6_PCODE_READY |
8449 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8450 if (_intel_wait_for(dev,
8451 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500,
8452 1, "915pr2"))
8453 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8454
8455 min_freq = (rp_state_cap & 0xff0000) >> 16;
8456 max_freq = rp_state_cap & 0xff;
8457 cur_freq = (gt_perf_status & 0xff00) >> 8;
8458
8459 /* Check for overclock support */
8460 if (_intel_wait_for(dev,
8461 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500,
8462 1, "915pr3"))
8463 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8464 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8465 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8466 if (_intel_wait_for(dev,
8467 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500,
8468 1, "915pr4"))
8469 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8470 if (pcu_mbox & (1<<31)) { /* OC supported */
8471 max_freq = pcu_mbox & 0xff;
8472 DRM_DEBUG("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8473 }
8474
8475 /* In units of 100MHz */
8476 dev_priv->max_delay = max_freq;
8477 dev_priv->min_delay = min_freq;
8478 dev_priv->cur_delay = cur_freq;
8479
8480 /* requires MSI enabled */
8481 I915_WRITE(GEN6_PMIER,
8482 GEN6_PM_MBOX_EVENT |
8483 GEN6_PM_THERMAL_EVENT |
8484 GEN6_PM_RP_DOWN_TIMEOUT |
8485 GEN6_PM_RP_UP_THRESHOLD |
8486 GEN6_PM_RP_DOWN_THRESHOLD |
8487 GEN6_PM_RP_UP_EI_EXPIRED |
8488 GEN6_PM_RP_DOWN_EI_EXPIRED);
8489 mtx_lock(&dev_priv->rps_lock);
8490 if (dev_priv->pm_iir != 0)
8491 printf("pm_iir %x\n", dev_priv->pm_iir);
8492 I915_WRITE(GEN6_PMIMR, 0);
8493 mtx_unlock(&dev_priv->rps_lock);
8494 /* enable all PM interrupts */
8495 I915_WRITE(GEN6_PMINTRMSK, 0);
8496
8497 gen6_gt_force_wake_put(dev_priv);
8498 DRM_UNLOCK(dev);
8499}
8500
8501void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8502{
8503 struct drm_device *dev;
8504 int min_freq = 15;
8505 int gpu_freq, ia_freq, max_ia_freq;
8506 int scaling_factor = 180;
8507 uint64_t tsc_freq;
8508
8509 dev = dev_priv->dev;
8510#if 0
8511 max_ia_freq = cpufreq_quick_get_max(0);
8512 /*
8513 * Default to measured freq if none found, PCU will ensure we don't go
8514 * over
8515 */
8516 if (!max_ia_freq)
8517 max_ia_freq = tsc_freq;
8518
8519 /* Convert from Hz to MHz */
8520 max_ia_freq /= 1000;
8521#else
8522 tsc_freq = atomic_load_acq_64(&tsc_freq);
8523 max_ia_freq = tsc_freq / 1000 / 1000;
8524#endif
8525
8526 DRM_LOCK(dev);
8527
8528 /*
8529 * For each potential GPU frequency, load a ring frequency we'd like
8530 * to use for memory access. We do this by specifying the IA frequency
8531 * the PCU should use as a reference to determine the ring frequency.
8532 */
8533 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8534 gpu_freq--) {
8535 int diff = dev_priv->max_delay - gpu_freq;
8536 int d;
8537
8538 /*
8539 * For GPU frequencies less than 750MHz, just use the lowest
8540 * ring freq.
8541 */
8542 if (gpu_freq < min_freq)
8543 ia_freq = 800;
8544 else
8545 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8546 d = 100;
8547 ia_freq = (ia_freq + d / 2) / d;
8548
8549 I915_WRITE(GEN6_PCODE_DATA,
8550 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8551 gpu_freq);
8552 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8553 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8554 if (_intel_wait_for(dev,
8555 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8556 10, 1, "915frq")) {
8557 DRM_ERROR("pcode write of freq table timed out\n");
8558 continue;
8559 }
8560 }
8561
8562 DRM_UNLOCK(dev);
8563}
8564
8565static void ironlake_init_clock_gating(struct drm_device *dev)
8566{
8567 struct drm_i915_private *dev_priv = dev->dev_private;
8568 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8569
8570 /* Required for FBC */
8571 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8572 DPFCRUNIT_CLOCK_GATE_DISABLE |
8573 DPFDUNIT_CLOCK_GATE_DISABLE;
8574 /* Required for CxSR */
8575 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8576
8577 I915_WRITE(PCH_3DCGDIS0,
8578 MARIUNIT_CLOCK_GATE_DISABLE |
8579 SVSMUNIT_CLOCK_GATE_DISABLE);
8580 I915_WRITE(PCH_3DCGDIS1,
8581 VFMUNIT_CLOCK_GATE_DISABLE);
8582
8583 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8584
8585 /*
8586 * According to the spec the following bits should be set in
8587 * order to enable memory self-refresh
8588 * The bit 22/21 of 0x42004
8589 * The bit 5 of 0x42020
8590 * The bit 15 of 0x45000
8591 */
8592 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8593 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8594 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8595 I915_WRITE(ILK_DSPCLK_GATE,
8596 (I915_READ(ILK_DSPCLK_GATE) |
8597 ILK_DPARB_CLK_GATE));
8598 I915_WRITE(DISP_ARB_CTL,
8599 (I915_READ(DISP_ARB_CTL) |
8600 DISP_FBC_WM_DIS));
8601 I915_WRITE(WM3_LP_ILK, 0);
8602 I915_WRITE(WM2_LP_ILK, 0);
8603 I915_WRITE(WM1_LP_ILK, 0);
8604
8605 /*
8606 * Based on the document from hardware guys the following bits
8607 * should be set unconditionally in order to enable FBC.
8608 * The bit 22 of 0x42000
8609 * The bit 22 of 0x42004
8610 * The bit 7,8,9 of 0x42020.
8611 */
8612 if (IS_IRONLAKE_M(dev)) {
8613 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8614 I915_READ(ILK_DISPLAY_CHICKEN1) |
8615 ILK_FBCQ_DIS);
8616 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8617 I915_READ(ILK_DISPLAY_CHICKEN2) |
8618 ILK_DPARB_GATE);
8619 I915_WRITE(ILK_DSPCLK_GATE,
8620 I915_READ(ILK_DSPCLK_GATE) |
8621 ILK_DPFC_DIS1 |
8622 ILK_DPFC_DIS2 |
8623 ILK_CLK_FBC);
8624 }
8625
8626 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8627 I915_READ(ILK_DISPLAY_CHICKEN2) |
8628 ILK_ELPIN_409_SELECT);
8629 I915_WRITE(_3D_CHICKEN2,
8630 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8631 _3D_CHICKEN2_WM_READ_PIPELINED);
8632}
8633
8634static void gen6_init_clock_gating(struct drm_device *dev)
8635{
8636 struct drm_i915_private *dev_priv = dev->dev_private;
8637 int pipe;
8638 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8639
8640 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8641
8642 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8643 I915_READ(ILK_DISPLAY_CHICKEN2) |
8644 ILK_ELPIN_409_SELECT);
8645
8646 I915_WRITE(WM3_LP_ILK, 0);
8647 I915_WRITE(WM2_LP_ILK, 0);
8648 I915_WRITE(WM1_LP_ILK, 0);
8649
8650 I915_WRITE(GEN6_UCGCTL1,
8651 I915_READ(GEN6_UCGCTL1) |
8652 GEN6_BLBUNIT_CLOCK_GATE_DISABLE);
8653
8654 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8655 * gating disable must be set. Failure to set it results in
8656 * flickering pixels due to Z write ordering failures after
8657 * some amount of runtime in the Mesa "fire" demo, and Unigine
8658 * Sanctuary and Tropics, and apparently anything else with
8659 * alpha test or pixel discard.
8660 *
8661 * According to the spec, bit 11 (RCCUNIT) must also be set,
8662 * but we didn't debug actual testcases to find it out.
8663 */
8664 I915_WRITE(GEN6_UCGCTL2,
8665 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8666 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8667
8668 /*
8669 * According to the spec the following bits should be
8670 * set in order to enable memory self-refresh and fbc:
8671 * The bit21 and bit22 of 0x42000
8672 * The bit21 and bit22 of 0x42004
8673 * The bit5 and bit7 of 0x42020
8674 * The bit14 of 0x70180
8675 * The bit14 of 0x71180
8676 */
8677 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8678 I915_READ(ILK_DISPLAY_CHICKEN1) |
8679 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8680 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8681 I915_READ(ILK_DISPLAY_CHICKEN2) |
8682 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8683 I915_WRITE(ILK_DSPCLK_GATE,
8684 I915_READ(ILK_DSPCLK_GATE) |
8685 ILK_DPARB_CLK_GATE |
8686 ILK_DPFD_CLK_GATE);
8687
8688 for_each_pipe(pipe) {
8689 I915_WRITE(DSPCNTR(pipe),
8690 I915_READ(DSPCNTR(pipe)) |
8691 DISPPLANE_TRICKLE_FEED_DISABLE);
8692 intel_flush_display_plane(dev_priv, pipe);
8693 }
8694}
8695
8696static void ivybridge_init_clock_gating(struct drm_device *dev)
8697{
8698 struct drm_i915_private *dev_priv = dev->dev_private;
8699 int pipe;
8700 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8701
8702 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8703
8704 I915_WRITE(WM3_LP_ILK, 0);
8705 I915_WRITE(WM2_LP_ILK, 0);
8706 I915_WRITE(WM1_LP_ILK, 0);
8707
8708 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8709 * This implements the WaDisableRCZUnitClockGating workaround.
8710 */
8711 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8712
8713 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8714
8715 I915_WRITE(IVB_CHICKEN3,
8716 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8717 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8718
8719 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8720 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8721 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8722
8723 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8724 I915_WRITE(GEN7_L3CNTLREG1,
8725 GEN7_WA_FOR_GEN7_L3_CONTROL);
8726 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8727 GEN7_WA_L3_CHICKEN_MODE);
8728
8729 /* This is required by WaCatErrorRejectionIssue */
8730 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8731 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8732 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8733
8734 for_each_pipe(pipe) {
8735 I915_WRITE(DSPCNTR(pipe),
8736 I915_READ(DSPCNTR(pipe)) |
8737 DISPPLANE_TRICKLE_FEED_DISABLE);
8738 intel_flush_display_plane(dev_priv, pipe);
8739 }
8740}
8741
8742static void g4x_init_clock_gating(struct drm_device *dev)
8743{
8744 struct drm_i915_private *dev_priv = dev->dev_private;
8745 uint32_t dspclk_gate;
8746
8747 I915_WRITE(RENCLK_GATE_D1, 0);
8748 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8749 GS_UNIT_CLOCK_GATE_DISABLE |
8750 CL_UNIT_CLOCK_GATE_DISABLE);
8751 I915_WRITE(RAMCLK_GATE_D, 0);
8752 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8753 OVRUNIT_CLOCK_GATE_DISABLE |
8754 OVCUNIT_CLOCK_GATE_DISABLE;
8755 if (IS_GM45(dev))
8756 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8757 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8758}
8759
8760static void crestline_init_clock_gating(struct drm_device *dev)
8761{
8762 struct drm_i915_private *dev_priv = dev->dev_private;
8763
8764 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8765 I915_WRITE(RENCLK_GATE_D2, 0);
8766 I915_WRITE(DSPCLK_GATE_D, 0);
8767 I915_WRITE(RAMCLK_GATE_D, 0);
8768 I915_WRITE16(DEUC, 0);
8769}
8770
8771static void broadwater_init_clock_gating(struct drm_device *dev)
8772{
8773 struct drm_i915_private *dev_priv = dev->dev_private;
8774
8775 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8776 I965_RCC_CLOCK_GATE_DISABLE |
8777 I965_RCPB_CLOCK_GATE_DISABLE |
8778 I965_ISC_CLOCK_GATE_DISABLE |
8779 I965_FBC_CLOCK_GATE_DISABLE);
8780 I915_WRITE(RENCLK_GATE_D2, 0);
8781}
8782
8783static void gen3_init_clock_gating(struct drm_device *dev)
8784{
8785 struct drm_i915_private *dev_priv = dev->dev_private;
8786 u32 dstate = I915_READ(D_STATE);
8787
8788 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8789 DSTATE_DOT_CLOCK_GATING;
8790 I915_WRITE(D_STATE, dstate);
8791}
8792
8793static void i85x_init_clock_gating(struct drm_device *dev)
8794{
8795 struct drm_i915_private *dev_priv = dev->dev_private;
8796
8797 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8798}
8799
8800static void i830_init_clock_gating(struct drm_device *dev)
8801{
8802 struct drm_i915_private *dev_priv = dev->dev_private;
8803
8804 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8805}
8806
8807static void ibx_init_clock_gating(struct drm_device *dev)
8808{
8809 struct drm_i915_private *dev_priv = dev->dev_private;
8810
8811 /*
8812 * On Ibex Peak and Cougar Point, we need to disable clock
8813 * gating for the panel power sequencer or it will fail to
8814 * start up when no ports are active.
8815 */
8816 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8817}
8818
8819static void cpt_init_clock_gating(struct drm_device *dev)
8820{
8821 struct drm_i915_private *dev_priv = dev->dev_private;
8822 int pipe;
8823
8824 /*
8825 * On Ibex Peak and Cougar Point, we need to disable clock
8826 * gating for the panel power sequencer or it will fail to
8827 * start up when no ports are active.
8828 */
8829 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8830 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8831 DPLS_EDP_PPS_FIX_DIS);
8832 /* Without this, mode sets may fail silently on FDI */
8833 for_each_pipe(pipe)
8834 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8835}
8836
8837static void ironlake_teardown_rc6(struct drm_device *dev)
8838{
8839 struct drm_i915_private *dev_priv = dev->dev_private;
8840
8841 if (dev_priv->renderctx) {
8842 i915_gem_object_unpin(dev_priv->renderctx);
8843 drm_gem_object_unreference(&dev_priv->renderctx->base);
8844 dev_priv->renderctx = NULL;
8845 }
8846
8847 if (dev_priv->pwrctx) {
8848 i915_gem_object_unpin(dev_priv->pwrctx);
8849 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8850 dev_priv->pwrctx = NULL;
8851 }
8852}
8853
8854static void ironlake_disable_rc6(struct drm_device *dev)
8855{
8856 struct drm_i915_private *dev_priv = dev->dev_private;
8857
8858 if (I915_READ(PWRCTXA)) {
8859 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8860 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8861 (void)_intel_wait_for(dev,
8862 ((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8863 50, 1, "915pro");
8864
8865 I915_WRITE(PWRCTXA, 0);
8866 POSTING_READ(PWRCTXA);
8867
8868 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8869 POSTING_READ(RSTDBYCTL);
8870 }
8871
8872 ironlake_teardown_rc6(dev);
8873}
8874
8875static int ironlake_setup_rc6(struct drm_device *dev)
8876{
8877 struct drm_i915_private *dev_priv = dev->dev_private;
8878
8879 if (dev_priv->renderctx == NULL)
8880 dev_priv->renderctx = intel_alloc_context_page(dev);
8881 if (!dev_priv->renderctx)
8882 return -ENOMEM;
8883
8884 if (dev_priv->pwrctx == NULL)
8885 dev_priv->pwrctx = intel_alloc_context_page(dev);
8886 if (!dev_priv->pwrctx) {
8887 ironlake_teardown_rc6(dev);
8888 return -ENOMEM;
8889 }
8890
8891 return 0;
8892}
8893
8894void ironlake_enable_rc6(struct drm_device *dev)
8895{
8896 struct drm_i915_private *dev_priv = dev->dev_private;
8897 int ret;
8898
8899 /* rc6 disabled by default due to repeated reports of hanging during
8900 * boot and resume.
8901 */
8902 if (!intel_enable_rc6(dev))
8903 return;
8904
8905 DRM_LOCK(dev);
8906 ret = ironlake_setup_rc6(dev);
8907 if (ret) {
8908 DRM_UNLOCK(dev);
8909 return;
8910 }
8911
8912 /*
8913 * GPU can automatically power down the render unit if given a page
8914 * to save state.
8915 */
8916 ret = BEGIN_LP_RING(6);
8917 if (ret) {
8918 ironlake_teardown_rc6(dev);
8919 DRM_UNLOCK(dev);
8920 return;
8921 }
8922
8923 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8924 OUT_RING(MI_SET_CONTEXT);
8925 OUT_RING(dev_priv->renderctx->gtt_offset |
8926 MI_MM_SPACE_GTT |
8927 MI_SAVE_EXT_STATE_EN |
8928 MI_RESTORE_EXT_STATE_EN |
8929 MI_RESTORE_INHIBIT);
8930 OUT_RING(MI_SUSPEND_FLUSH);
8931 OUT_RING(MI_NOOP);
8932 OUT_RING(MI_FLUSH);
8933 ADVANCE_LP_RING();
8934
8935 /*
8936 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8937 * does an implicit flush, combined with MI_FLUSH above, it should be
8938 * safe to assume that renderctx is valid
8939 */
8940 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8941 if (ret) {
8942 DRM_ERROR("failed to enable ironlake power power savings\n");
8943 ironlake_teardown_rc6(dev);
8944 DRM_UNLOCK(dev);
8945 return;
8946 }
8947
8948 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8949 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8950 DRM_UNLOCK(dev);
8951}
8952
8953void intel_init_clock_gating(struct drm_device *dev)
8954{
8955 struct drm_i915_private *dev_priv = dev->dev_private;
8956
8957 dev_priv->display.init_clock_gating(dev);
8958
8959 if (dev_priv->display.init_pch_clock_gating)
8960 dev_priv->display.init_pch_clock_gating(dev);
8961}
8962
8963/* Set up chip specific display functions */
8964static void intel_init_display(struct drm_device *dev)
8965{
8966 struct drm_i915_private *dev_priv = dev->dev_private;
8967
8968 /* We always want a DPMS function */
8969 if (HAS_PCH_SPLIT(dev)) {
8970 dev_priv->display.dpms = ironlake_crtc_dpms;
8971 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8972 dev_priv->display.update_plane = ironlake_update_plane;
8973 } else {
8974 dev_priv->display.dpms = i9xx_crtc_dpms;
8975 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8976 dev_priv->display.update_plane = i9xx_update_plane;
8977 }
8978
8979 if (I915_HAS_FBC(dev)) {
8980 if (HAS_PCH_SPLIT(dev)) {
8981 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8982 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8983 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8984 } else if (IS_GM45(dev)) {
8985 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8986 dev_priv->display.enable_fbc = g4x_enable_fbc;
8987 dev_priv->display.disable_fbc = g4x_disable_fbc;
8988 } else if (IS_CRESTLINE(dev)) {
8989 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8990 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8991 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8992 }
8993 /* 855GM needs testing */
8994 }
8995
8996 /* Returns the core display clock speed */
8997 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8998 dev_priv->display.get_display_clock_speed =
8999 i945_get_display_clock_speed;
9000 else if (IS_I915G(dev))
9001 dev_priv->display.get_display_clock_speed =
9002 i915_get_display_clock_speed;
9003 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9004 dev_priv->display.get_display_clock_speed =
9005 i9xx_misc_get_display_clock_speed;
9006 else if (IS_I915GM(dev))
9007 dev_priv->display.get_display_clock_speed =
9008 i915gm_get_display_clock_speed;
9009 else if (IS_I865G(dev))
9010 dev_priv->display.get_display_clock_speed =
9011 i865_get_display_clock_speed;
9012 else if (IS_I85X(dev))
9013 dev_priv->display.get_display_clock_speed =
9014 i855_get_display_clock_speed;
9015 else /* 852, 830 */
9016 dev_priv->display.get_display_clock_speed =
9017 i830_get_display_clock_speed;
9018
9019 /* For FIFO watermark updates */
9020 if (HAS_PCH_SPLIT(dev)) {
9021 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
9022 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
9023
9024 /* IVB configs may use multi-threaded forcewake */
9025 if (IS_IVYBRIDGE(dev)) {
9026 u32 ecobus;
9027
9028 /* A small trick here - if the bios hasn't configured MT forcewake,
9029 * and if the device is in RC6, then force_wake_mt_get will not wake
9030 * the device and the ECOBUS read will return zero. Which will be
9031 * (correctly) interpreted by the test below as MT forcewake being
9032 * disabled.
9033 */
9034 DRM_LOCK(dev);
9035 __gen6_gt_force_wake_mt_get(dev_priv);
9036 ecobus = I915_READ_NOTRACE(ECOBUS);
9037 __gen6_gt_force_wake_mt_put(dev_priv);
9038 DRM_UNLOCK(dev);
9039
9040 if (ecobus & FORCEWAKE_MT_ENABLE) {
9041 DRM_DEBUG_KMS("Using MT version of forcewake\n");
9042 dev_priv->display.force_wake_get =
9043 __gen6_gt_force_wake_mt_get;
9044 dev_priv->display.force_wake_put =
9045 __gen6_gt_force_wake_mt_put;
9046 }
9047 }
9048
9049 if (HAS_PCH_IBX(dev))
9050 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
9051 else if (HAS_PCH_CPT(dev))
9052 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
9053
9054 if (IS_GEN5(dev)) {
9055 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
9056 dev_priv->display.update_wm = ironlake_update_wm;
9057 else {
9058 DRM_DEBUG_KMS("Failed to get proper latency. "
9059 "Disable CxSR\n");
9060 dev_priv->display.update_wm = NULL;
9061 }
9062 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9063 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
9064 dev_priv->display.write_eld = ironlake_write_eld;
9065 } else if (IS_GEN6(dev)) {
9066 if (SNB_READ_WM0_LATENCY()) {
9067 dev_priv->display.update_wm = sandybridge_update_wm;
9068 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9069 } else {
9070 DRM_DEBUG_KMS("Failed to read display plane latency. "
9071 "Disable CxSR\n");
9072 dev_priv->display.update_wm = NULL;
9073 }
9074 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9075 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9076 dev_priv->display.write_eld = ironlake_write_eld;
9077 } else if (IS_IVYBRIDGE(dev)) {
9078 /* FIXME: detect B0+ stepping and use auto training */
9079 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9080 if (SNB_READ_WM0_LATENCY()) {
9081 dev_priv->display.update_wm = sandybridge_update_wm;
9082 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9083 } else {
9084 DRM_DEBUG_KMS("Failed to read display plane latency. "
9085 "Disable CxSR\n");
9086 dev_priv->display.update_wm = NULL;
9087 }
9088 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
9089 dev_priv->display.write_eld = ironlake_write_eld;
9090 } else
9091 dev_priv->display.update_wm = NULL;
9092 } else if (IS_PINEVIEW(dev)) {
9093 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
9094 dev_priv->is_ddr3,
9095 dev_priv->fsb_freq,
9096 dev_priv->mem_freq)) {
9097 DRM_INFO("failed to find known CxSR latency "
9098 "(found ddr%s fsb freq %d, mem freq %d), "
9099 "disabling CxSR\n",
9100 (dev_priv->is_ddr3 == 1) ? "3" : "2",
9101 dev_priv->fsb_freq, dev_priv->mem_freq);
9102 /* Disable CxSR and never update its watermark again */
9103 pineview_disable_cxsr(dev);
9104 dev_priv->display.update_wm = NULL;
9105 } else
9106 dev_priv->display.update_wm = pineview_update_wm;
9107 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9108 } else if (IS_G4X(dev)) {
9109 dev_priv->display.write_eld = g4x_write_eld;
9110 dev_priv->display.update_wm = g4x_update_wm;
9111 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9112 } else if (IS_GEN4(dev)) {
9113 dev_priv->display.update_wm = i965_update_wm;
9114 if (IS_CRESTLINE(dev))
9115 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9116 else if (IS_BROADWATER(dev))
9117 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9118 } else if (IS_GEN3(dev)) {
9119 dev_priv->display.update_wm = i9xx_update_wm;
9120 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9121 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9122 } else if (IS_I865G(dev)) {
9123 dev_priv->display.update_wm = i830_update_wm;
9124 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9125 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9126 } else if (IS_I85X(dev)) {
9127 dev_priv->display.update_wm = i9xx_update_wm;
9128 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
9129 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9130 } else {
9131 dev_priv->display.update_wm = i830_update_wm;
9132 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9133 if (IS_845G(dev))
9134 dev_priv->display.get_fifo_size = i845_get_fifo_size;
9135 else
9136 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9137 }
9138
9139 /* Default just returns -ENODEV to indicate unsupported */
9140 dev_priv->display.queue_flip = intel_default_queue_flip;
9141
9142 switch (INTEL_INFO(dev)->gen) {
9143 case 2:
9144 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9145 break;
9146
9147 case 3:
9148 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9149 break;
9150
9151 case 4:
9152 case 5:
9153 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9154 break;
9155
9156 case 6:
9157 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9158 break;
9159 case 7:
9160 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9161 break;
9162 }
9163}
9164
9165/*
9166 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9167 * resume, or other times. This quirk makes sure that's the case for
9168 * affected systems.
9169 */
9170static void quirk_pipea_force(struct drm_device *dev)
9171{
9172 struct drm_i915_private *dev_priv = dev->dev_private;
9173
9174 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9175 DRM_DEBUG("applying pipe a force quirk\n");
9176}
9177
9178/*
9179 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9180 */
9181static void quirk_ssc_force_disable(struct drm_device *dev)
9182{
9183 struct drm_i915_private *dev_priv = dev->dev_private;
9184 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9185}
9186
9187struct intel_quirk {
9188 int device;
9189 int subsystem_vendor;
9190 int subsystem_device;
9191 void (*hook)(struct drm_device *dev);
9192};
9193
9194#define PCI_ANY_ID (~0u)
9195
9196struct intel_quirk intel_quirks[] = {
9197 /* HP Mini needs pipe A force quirk (LP: #322104) */
9198 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9199
9200 /* Thinkpad R31 needs pipe A force quirk */
9201 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9202 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9203 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9204
9205 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9206 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9207 /* ThinkPad X40 needs pipe A force quirk */
9208
9209 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9210 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9211
9212 /* 855 & before need to leave pipe A & dpll A up */
9213 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9214 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9215
9216 /* Lenovo U160 cannot use SSC on LVDS */
9217 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9218
9219 /* Sony Vaio Y cannot use SSC on LVDS */
9220 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9221};
9222
9223static void intel_init_quirks(struct drm_device *dev)
9224{
9225 struct intel_quirk *q;
9226 device_t d;
9227 int i;
9228
9229 d = dev->device;
9230 for (i = 0; i < DRM_ARRAY_SIZE(intel_quirks); i++) {
9231 q = &intel_quirks[i];
9232 if (pci_get_device(d) == q->device &&
9233 (pci_get_subvendor(d) == q->subsystem_vendor ||
9234 q->subsystem_vendor == PCI_ANY_ID) &&
9235 (pci_get_subdevice(d) == q->subsystem_device ||
9236 q->subsystem_device == PCI_ANY_ID))
9237 q->hook(dev);
9238 }
9239}
9240
9241/* Disable the VGA plane that we never use */
9242static void i915_disable_vga(struct drm_device *dev)
9243{
9244 struct drm_i915_private *dev_priv = dev->dev_private;
9245 u8 sr1;
9246 u32 vga_reg;
9247
9248 if (HAS_PCH_SPLIT(dev))
9249 vga_reg = CPU_VGACNTRL;
9250 else
9251 vga_reg = VGACNTRL;
9252
9253#if 0
9254 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9255#endif
9256 outb(VGA_SR_INDEX, 1);
9257 sr1 = inb(VGA_SR_DATA);
9258 outb(VGA_SR_DATA, sr1 | 1 << 5);
9259#if 0
9260 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9261#endif
9262 DELAY(300);
9263
9264 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9265 POSTING_READ(vga_reg);
9266}
9267
9268void intel_modeset_init(struct drm_device *dev)
9269{
9270 struct drm_i915_private *dev_priv = dev->dev_private;
9271 int i, ret;
9272
9273 drm_mode_config_init(dev);
9274
9275 dev->mode_config.min_width = 0;
9276 dev->mode_config.min_height = 0;
9277
9278 dev->mode_config.preferred_depth = 24;
9279 dev->mode_config.prefer_shadow = 1;
9280
9281 dev->mode_config.funcs = __DECONST(struct drm_mode_config_funcs *,
9282 &intel_mode_funcs);
9283
9284 intel_init_quirks(dev);
9285
9286 intel_init_display(dev);
9287
9288 if (IS_GEN2(dev)) {
9289 dev->mode_config.max_width = 2048;
9290 dev->mode_config.max_height = 2048;
9291 } else if (IS_GEN3(dev)) {
9292 dev->mode_config.max_width = 4096;
9293 dev->mode_config.max_height = 4096;
9294 } else {
9295 dev->mode_config.max_width = 8192;
9296 dev->mode_config.max_height = 8192;
9297 }
9298 dev->mode_config.fb_base = dev->agp->base;
9299
9300 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9301 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9302
9303 for (i = 0; i < dev_priv->num_pipe; i++) {
9304 intel_crtc_init(dev, i);
9305 ret = intel_plane_init(dev, i);
9306 if (ret)
9307 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9308 }
9309
9310 /* Just disable it once at startup */
9311 i915_disable_vga(dev);
9312 intel_setup_outputs(dev);
9313
9314 intel_init_clock_gating(dev);
9315
9316 if (IS_IRONLAKE_M(dev)) {
9317 ironlake_enable_drps(dev);
9318 intel_init_emon(dev);
9319 }
9320
9321 if (IS_GEN6(dev)) {
9322 gen6_enable_rps(dev_priv);
9323 gen6_update_ring_freq(dev_priv);
9324 }
9325
9326 TASK_INIT(&dev_priv->idle_task, 0, intel_idle_update, dev_priv);
9327 callout_init(&dev_priv->idle_callout, CALLOUT_MPSAFE);
9328}
9329
9330void intel_modeset_gem_init(struct drm_device *dev)
9331{
9332 if (IS_IRONLAKE_M(dev))
9333 ironlake_enable_rc6(dev);
9334
9335 intel_setup_overlay(dev);
9336}
9337
9338void intel_modeset_cleanup(struct drm_device *dev)
9339{
9340 struct drm_i915_private *dev_priv = dev->dev_private;
9341 struct drm_crtc *crtc;
9342 struct intel_crtc *intel_crtc;
9343
9344 drm_kms_helper_poll_fini(dev);
9345 DRM_LOCK(dev);
9346
9347#if 0
9348 intel_unregister_dsm_handler();
9349#endif
9350
9351 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9352 /* Skip inactive CRTCs */
9353 if (!crtc->fb)
9354 continue;
9355
9356 intel_crtc = to_intel_crtc(crtc);
9357 intel_increase_pllclock(crtc);
9358 }
9359
9360 intel_disable_fbc(dev);
9361
9362 if (IS_IRONLAKE_M(dev))
9363 ironlake_disable_drps(dev);
9364 if (IS_GEN6(dev))
9365 gen6_disable_rps(dev);
9366
9367 if (IS_IRONLAKE_M(dev))
9368 ironlake_disable_rc6(dev);
9369
9370 /* Disable the irq before mode object teardown, for the irq might
9371 * enqueue unpin/hotplug work. */
9372 drm_irq_uninstall(dev);
9373 DRM_UNLOCK(dev);
9374
9375 if (taskqueue_cancel(dev_priv->tq, &dev_priv->hotplug_task, NULL))
9376 taskqueue_drain(dev_priv->tq, &dev_priv->hotplug_task);
9377 if (taskqueue_cancel(dev_priv->tq, &dev_priv->rps_task, NULL))
9378 taskqueue_drain(dev_priv->tq, &dev_priv->rps_task);
9379
9380 /* Shut off idle work before the crtcs get freed. */
9381 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9382 intel_crtc = to_intel_crtc(crtc);
9383 callout_drain(&intel_crtc->idle_callout);
9384 }
9385 callout_drain(&dev_priv->idle_callout);
9386 if (taskqueue_cancel(dev_priv->tq, &dev_priv->idle_task, NULL))
9387 taskqueue_drain(dev_priv->tq, &dev_priv->idle_task);
9388
9389 drm_mode_config_cleanup(dev);
9390}
9391
9392/*
9393 * Return which encoder is currently attached for connector.
9394 */
9395struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9396{
9397 return &intel_attached_encoder(connector)->base;
9398}
9399
9400void intel_connector_attach_encoder(struct intel_connector *connector,
9401 struct intel_encoder *encoder)
9402{
9403 connector->encoder = encoder;
9404 drm_mode_connector_attach_encoder(&connector->base,
9405 &encoder->base);
9406}
9407
9408/*
9409 * set vga decode state - true == enable VGA decode
9410 */
9411int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9412{
9413 struct drm_i915_private *dev_priv;
9414 device_t bridge_dev;
9415 u16 gmch_ctrl;
9416
9417 dev_priv = dev->dev_private;
9418 bridge_dev = intel_gtt_get_bridge_device();
9419 gmch_ctrl = pci_read_config(bridge_dev, INTEL_GMCH_CTRL, 2);
9420 if (state)
9421 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9422 else
9423 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9424 pci_write_config(bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl, 2);
9425 return (0);
9426}
9427
9428struct intel_display_error_state {
9429 struct intel_cursor_error_state {
9430 u32 control;
9431 u32 position;
9432 u32 base;
9433 u32 size;
9434 } cursor[2];
9435
9436 struct intel_pipe_error_state {
9437 u32 conf;
9438 u32 source;
9439
9440 u32 htotal;
9441 u32 hblank;
9442 u32 hsync;
9443 u32 vtotal;
9444 u32 vblank;
9445 u32 vsync;
9446 } pipe[2];
9447
9448 struct intel_plane_error_state {
9449 u32 control;
9450 u32 stride;
9451 u32 size;
9452 u32 pos;
9453 u32 addr;
9454 u32 surface;
9455 u32 tile_offset;
9456 } plane[2];
9457};
9458
9459struct intel_display_error_state *
9460intel_display_capture_error_state(struct drm_device *dev)
9461{
9462 drm_i915_private_t *dev_priv = dev->dev_private;
9463 struct intel_display_error_state *error;
9464 int i;
9465
9466 error = malloc(sizeof(*error), DRM_MEM_KMS, M_NOWAIT);
9467 if (error == NULL)
9468 return NULL;
9469
9470 for (i = 0; i < 2; i++) {
9471 error->cursor[i].control = I915_READ(CURCNTR(i));
9472 error->cursor[i].position = I915_READ(CURPOS(i));
9473 error->cursor[i].base = I915_READ(CURBASE(i));
9474
9475 error->plane[i].control = I915_READ(DSPCNTR(i));
9476 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9477 error->plane[i].size = I915_READ(DSPSIZE(i));
9478 error->plane[i].pos = I915_READ(DSPPOS(i));
9479 error->plane[i].addr = I915_READ(DSPADDR(i));
9480 if (INTEL_INFO(dev)->gen >= 4) {
9481 error->plane[i].surface = I915_READ(DSPSURF(i));
9482 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9483 }
9484
9485 error->pipe[i].conf = I915_READ(PIPECONF(i));
9486 error->pipe[i].source = I915_READ(PIPESRC(i));
9487 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9488 error->pipe[i].hblank = I915_READ(HBLANK(i));
9489 error->pipe[i].hsync = I915_READ(HSYNC(i));
9490 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9491 error->pipe[i].vblank = I915_READ(VBLANK(i));
9492 error->pipe[i].vsync = I915_READ(VSYNC(i));
9493 }
9494
9495 return error;
9496}
9497
9498void
9499intel_display_print_error_state(struct sbuf *m,
9500 struct drm_device *dev,
9501 struct intel_display_error_state *error)
9502{
9503 int i;
9504
9505 for (i = 0; i < 2; i++) {
9506 sbuf_printf(m, "Pipe [%d]:\n", i);
9507 sbuf_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9508 sbuf_printf(m, " SRC: %08x\n", error->pipe[i].source);
9509 sbuf_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9510 sbuf_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9511 sbuf_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9512 sbuf_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9513 sbuf_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9514 sbuf_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9515
9516 sbuf_printf(m, "Plane [%d]:\n", i);
9517 sbuf_printf(m, " CNTR: %08x\n", error->plane[i].control);
9518 sbuf_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9519 sbuf_printf(m, " SIZE: %08x\n", error->plane[i].size);
9520 sbuf_printf(m, " POS: %08x\n", error->plane[i].pos);
9521 sbuf_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9522 if (INTEL_INFO(dev)->gen >= 4) {
9523 sbuf_printf(m, " SURF: %08x\n", error->plane[i].surface);
9524 sbuf_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9525 }
9526
9527 sbuf_printf(m, "Cursor [%d]:\n", i);
9528 sbuf_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9529 sbuf_printf(m, " POS: %08x\n", error->cursor[i].position);
9530 sbuf_printf(m, " BASE: %08x\n", error->cursor[i].base);
9531 }
9532}
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