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radeon_state.c (153087) radeon_state.c (157617)
1/* radeon_state.c -- State support for Radeon -*- linux-c -*- */
2/*-
3 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 14 unchanged lines hidden (view full) ---

23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Gareth Hughes <gareth@valinux.com>
27 * Kevin E. Martin <martin@valinux.com>
28 */
29
30#include <sys/cdefs.h>
1/* radeon_state.c -- State support for Radeon -*- linux-c -*- */
2/*-
3 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 14 unchanged lines hidden (view full) ---

23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Gareth Hughes <gareth@valinux.com>
27 * Kevin E. Martin <martin@valinux.com>
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_state.c 153087 2005-12-04 12:37:19Z ru $");
31__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_state.c 157617 2006-04-09 20:45:45Z anholt $");
32
33#include "dev/drm/drmP.h"
34#include "dev/drm/drm.h"
35#include "dev/drm/drm_sarea.h"
36#include "dev/drm/radeon_drm.h"
37#include "dev/drm/radeon_drv.h"
38
39/* ================================================================
40 * Helper functions for client state checking and fixup
41 */
42
43static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
44 dev_priv,
45 drm_file_t * filp_priv,
46 u32 * offset)
47{
48 u32 off = *offset;
49 struct drm_radeon_driver_file_fields *radeon_priv;
50
32
33#include "dev/drm/drmP.h"
34#include "dev/drm/drm.h"
35#include "dev/drm/drm_sarea.h"
36#include "dev/drm/radeon_drm.h"
37#include "dev/drm/radeon_drv.h"
38
39/* ================================================================
40 * Helper functions for client state checking and fixup
41 */
42
43static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
44 dev_priv,
45 drm_file_t * filp_priv,
46 u32 * offset)
47{
48 u32 off = *offset;
49 struct drm_radeon_driver_file_fields *radeon_priv;
50
51 if (off >= dev_priv->fb_location &&
52 off < (dev_priv->gart_vm_start + dev_priv->gart_size))
51 /* Hrm ... the story of the offset ... So this function converts
52 * the various ideas of what userland clients might have for an
53 * offset in the card address space into an offset into the card
54 * address space :) So with a sane client, it should just keep
55 * the value intact and just do some boundary checking. However,
56 * not all clients are sane. Some older clients pass us 0 based
57 * offsets relative to the start of the framebuffer and some may
58 * assume the AGP aperture it appended to the framebuffer, so we
59 * try to detect those cases and fix them up.
60 *
61 * Note: It might be a good idea here to make sure the offset lands
62 * in some "allowed" area to protect things like the PCIE GART...
63 */
64
65 /* First, the best case, the offset already lands in either the
66 * framebuffer or the GART mapped space
67 */
68 if ((off >= dev_priv->fb_location &&
69 off < (dev_priv->fb_location + dev_priv->fb_size)) ||
70 (off >= dev_priv->gart_vm_start &&
71 off < (dev_priv->gart_vm_start + dev_priv->gart_size)))
53 return 0;
54
72 return 0;
73
55 radeon_priv = filp_priv->driver_priv;
74 /* Ok, that didn't happen... now check if we have a zero based
75 * offset that fits in the framebuffer + gart space, apply the
76 * magic offset we get from SETPARAM or calculated from fb_location
77 */
78 if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
79 radeon_priv = filp_priv->driver_priv;
80 off += radeon_priv->radeon_fb_delta;
81 }
56
82
57 off += radeon_priv->radeon_fb_delta;
83 /* Finally, assume we aimed at a GART offset if beyond the fb */
84 if (off > (dev_priv->fb_location + dev_priv->fb_size))
85 off = off - (dev_priv->fb_location + dev_priv->fb_size) +
86 dev_priv->gart_vm_start;
58
87
59 DRM_DEBUG("offset fixed up to 0x%x\n", off);
60
61 if (off < dev_priv->fb_location ||
62 off >= (dev_priv->gart_vm_start + dev_priv->gart_size))
63 return DRM_ERR(EINVAL);
64
65 *offset = off;
66
67 return 0;
88 /* Now recheck and fail if out of bounds */
89 if ((off >= dev_priv->fb_location &&
90 off < (dev_priv->fb_location + dev_priv->fb_size)) ||
91 (off >= dev_priv->gart_vm_start &&
92 off < (dev_priv->gart_vm_start + dev_priv->gart_size))) {
93 DRM_DEBUG("offset fixed up to 0x%x\n", off);
94 *offset = off;
95 return 0;
96 }
97 return DRM_ERR(EINVAL);
68}
69
70static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
71 dev_priv,
72 drm_file_t * filp_priv,
98}
99
100static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
101 dev_priv,
102 drm_file_t * filp_priv,
73 int id, u32 __user * data)
103 int id, u32 *data)
74{
75 switch (id) {
76
77 case RADEON_EMIT_PP_MISC:
78 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
79 &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) {
80 DRM_ERROR("Invalid depth buffer offset\n");
81 return DRM_ERR(EINVAL);

--- 148 unchanged lines hidden (view full) ---

230 return DRM_ERR(EINVAL);
231 }
232
233 return 0;
234}
235
236static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
237 dev_priv,
104{
105 switch (id) {
106
107 case RADEON_EMIT_PP_MISC:
108 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
109 &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) {
110 DRM_ERROR("Invalid depth buffer offset\n");
111 return DRM_ERR(EINVAL);

--- 148 unchanged lines hidden (view full) ---

260 return DRM_ERR(EINVAL);
261 }
262
263 return 0;
264}
265
266static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
267 dev_priv,
238 drm_file_t * filp_priv,
239 drm_radeon_cmd_buffer_t *
268 drm_file_t *filp_priv,
269 drm_radeon_kcmd_buffer_t *
240 cmdbuf,
241 unsigned int *cmdsz)
242{
243 u32 *cmd = (u32 *) cmdbuf->buf;
244
245 *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
246
247 if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) {

--- 270 unchanged lines hidden (view full) ---

518 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
519 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
520 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
521 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
522 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
523 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
524 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
525 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
270 cmdbuf,
271 unsigned int *cmdsz)
272{
273 u32 *cmd = (u32 *) cmdbuf->buf;
274
275 *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
276
277 if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) {

--- 270 unchanged lines hidden (view full) ---

548 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
549 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
550 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
551 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
552 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
553 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
554 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
555 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
526 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
556 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
527 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
528 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
529 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
530 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
531 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
532 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
533 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
534 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},

--- 25 unchanged lines hidden (view full) ---

560 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
561 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
562 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
563 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
564 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
565 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
566 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
567 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
557 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
558 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
559 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
560 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
561 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
562 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
563 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
564 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},

--- 25 unchanged lines hidden (view full) ---

590 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
591 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
592 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
593 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
594 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
595 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
596 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
597 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
568 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
598 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
569 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
570 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
571 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
572 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
573 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
574 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
575 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
576 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},

--- 231 unchanged lines hidden (view full) ---

808
809 ADVANCE_RING();
810 }
811 }
812 }
813
814 /* hyper z clear */
815 /* no docs available, based on reverse engeneering by Stephane Marchesin */
599 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
600 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
601 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
602 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
603 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
604 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
605 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
606 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},

--- 231 unchanged lines hidden (view full) ---

838
839 ADVANCE_RING();
840 }
841 }
842 }
843
844 /* hyper z clear */
845 /* no docs available, based on reverse engeneering by Stephane Marchesin */
816 if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) && (flags & RADEON_CLEAR_FASTZ)) {
846 if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
847 && (flags & RADEON_CLEAR_FASTZ)) {
817
818 int i;
848
849 int i;
819 int depthpixperline = dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z?
820 (dev_priv->depth_pitch / 2): (dev_priv->depth_pitch / 4);
821
850 int depthpixperline =
851 dev_priv->depth_fmt ==
852 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
853 2) : (dev_priv->
854 depth_pitch / 4);
855
822 u32 clearmask;
823
824 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
856 u32 clearmask;
857
858 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
825 ((clear->depth_mask & 0xff) << 24);
826
827
859 ((clear->depth_mask & 0xff) << 24);
860
828 /* Make sure we restore the 3D state next time.
829 * we haven't touched any "normal" state - still need this?
830 */
831 dev_priv->sarea_priv->ctx_owner = 0;
832
861 /* Make sure we restore the 3D state next time.
862 * we haven't touched any "normal" state - still need this?
863 */
864 dev_priv->sarea_priv->ctx_owner = 0;
865
833 if ((dev_priv->flags & CHIP_HAS_HIERZ) && (flags & RADEON_USE_HIERZ)) {
834 /* FIXME : reverse engineer that for Rx00 cards */
835 /* FIXME : the mask supposedly contains low-res z values. So can't set
836 just to the max (0xff? or actually 0x3fff?), need to take z clear
837 value into account? */
838 /* pattern seems to work for r100, though get slight
839 rendering errors with glxgears. If hierz is not enabled for r100,
840 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
841 other ones are ignored, and the same clear mask can be used. That's
842 very different behaviour than R200 which needs different clear mask
843 and different number of tiles to clear if hierz is enabled or not !?!
844 */
845 clearmask = (0xff<<22)|(0xff<<6)| 0x003f003f;
846 }
847 else {
848 /* clear mask : chooses the clearing pattern.
849 rv250: could be used to clear only parts of macrotiles
850 (but that would get really complicated...)?
851 bit 0 and 1 (either or both of them ?!?!) are used to
852 not clear tile (or maybe one of the bits indicates if the tile is
853 compressed or not), bit 2 and 3 to not clear tile 1,...,.
854 Pattern is as follows:
855 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
856 bits -------------------------------------------------
857 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
858 rv100: clearmask covers 2x8 4x1 tiles, but one clear still
859 covers 256 pixels ?!?
860 */
866 if ((dev_priv->flags & CHIP_HAS_HIERZ)
867 && (flags & RADEON_USE_HIERZ)) {
868 /* FIXME : reverse engineer that for Rx00 cards */
869 /* FIXME : the mask supposedly contains low-res z values. So can't set
870 just to the max (0xff? or actually 0x3fff?), need to take z clear
871 value into account? */
872 /* pattern seems to work for r100, though get slight
873 rendering errors with glxgears. If hierz is not enabled for r100,
874 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
875 other ones are ignored, and the same clear mask can be used. That's
876 very different behaviour than R200 which needs different clear mask
877 and different number of tiles to clear if hierz is enabled or not !?!
878 */
879 clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
880 } else {
881 /* clear mask : chooses the clearing pattern.
882 rv250: could be used to clear only parts of macrotiles
883 (but that would get really complicated...)?
884 bit 0 and 1 (either or both of them ?!?!) are used to
885 not clear tile (or maybe one of the bits indicates if the tile is
886 compressed or not), bit 2 and 3 to not clear tile 1,...,.
887 Pattern is as follows:
888 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
889 bits -------------------------------------------------
890 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
891 rv100: clearmask covers 2x8 4x1 tiles, but one clear still
892 covers 256 pixels ?!?
893 */
861 clearmask = 0x0;
862 }
863
894 clearmask = 0x0;
895 }
896
864 BEGIN_RING( 8 );
897 BEGIN_RING(8);
865 RADEON_WAIT_UNTIL_2D_IDLE();
898 RADEON_WAIT_UNTIL_2D_IDLE();
866 OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE,
867 tempRB3D_DEPTHCLEARVALUE);
899 OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
900 tempRB3D_DEPTHCLEARVALUE);
868 /* what offset is this exactly ? */
901 /* what offset is this exactly ? */
869 OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 );
902 OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
870 /* need ctlstat, otherwise get some strange black flickering */
903 /* need ctlstat, otherwise get some strange black flickering */
871 OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL );
904 OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
905 RADEON_RB3D_ZC_FLUSH_ALL);
872 ADVANCE_RING();
873
874 for (i = 0; i < nbox; i++) {
875 int tileoffset, nrtilesx, nrtilesy, j;
876 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
906 ADVANCE_RING();
907
908 for (i = 0; i < nbox; i++) {
909 int tileoffset, nrtilesx, nrtilesy, j;
910 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
877 if ((dev_priv->flags&CHIP_HAS_HIERZ) && !(dev_priv->microcode_version==UCODE_R200)) {
911 if ((dev_priv->flags & CHIP_HAS_HIERZ)
912 && !(dev_priv->microcode_version == UCODE_R200)) {
878 /* FIXME : figure this out for r200 (when hierz is enabled). Or
879 maybe r200 actually doesn't need to put the low-res z value into
880 the tile cache like r100, but just needs to clear the hi-level z-buffer?
881 Works for R100, both with hierz and without.
882 R100 seems to operate on 2x1 8x8 tiles, but...
883 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
884 problematic with resolutions which are not 64 pix aligned? */
913 /* FIXME : figure this out for r200 (when hierz is enabled). Or
914 maybe r200 actually doesn't need to put the low-res z value into
915 the tile cache like r100, but just needs to clear the hi-level z-buffer?
916 Works for R100, both with hierz and without.
917 R100 seems to operate on 2x1 8x8 tiles, but...
918 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
919 problematic with resolutions which are not 64 pix aligned? */
885 tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 6;
886 nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4;
887 nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
920 tileoffset =
921 ((pbox[i].y1 >> 3) * depthpixperline +
922 pbox[i].x1) >> 6;
923 nrtilesx =
924 ((pbox[i].x2 & ~63) -
925 (pbox[i].x1 & ~63)) >> 4;
926 nrtilesy =
927 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
888 for (j = 0; j <= nrtilesy; j++) {
928 for (j = 0; j <= nrtilesy; j++) {
889 BEGIN_RING( 4 );
890 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) );
929 BEGIN_RING(4);
930 OUT_RING(CP_PACKET3
931 (RADEON_3D_CLEAR_ZMASK, 2));
891 /* first tile */
932 /* first tile */
892 OUT_RING( tileoffset * 8 );
933 OUT_RING(tileoffset * 8);
893 /* the number of tiles to clear */
934 /* the number of tiles to clear */
894 OUT_RING( nrtilesx + 4 );
935 OUT_RING(nrtilesx + 4);
895 /* clear mask : chooses the clearing pattern. */
936 /* clear mask : chooses the clearing pattern. */
896 OUT_RING( clearmask );
937 OUT_RING(clearmask);
897 ADVANCE_RING();
898 tileoffset += depthpixperline >> 6;
899 }
938 ADVANCE_RING();
939 tileoffset += depthpixperline >> 6;
940 }
900 }
901 else if (dev_priv->microcode_version==UCODE_R200) {
941 } else if (dev_priv->microcode_version == UCODE_R200) {
902 /* works for rv250. */
903 /* find first macro tile (8x2 4x4 z-pixels on rv250) */
942 /* works for rv250. */
943 /* find first macro tile (8x2 4x4 z-pixels on rv250) */
904 tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 5;
905 nrtilesx = (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
906 nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
944 tileoffset =
945 ((pbox[i].y1 >> 3) * depthpixperline +
946 pbox[i].x1) >> 5;
947 nrtilesx =
948 (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
949 nrtilesy =
950 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
907 for (j = 0; j <= nrtilesy; j++) {
951 for (j = 0; j <= nrtilesy; j++) {
908 BEGIN_RING( 4 );
909 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) );
952 BEGIN_RING(4);
953 OUT_RING(CP_PACKET3
954 (RADEON_3D_CLEAR_ZMASK, 2));
910 /* first tile */
911 /* judging by the first tile offset needed, could possibly
912 directly address/clear 4x4 tiles instead of 8x2 * 4x4
913 macro tiles, though would still need clear mask for
914 right/bottom if truely 4x4 granularity is desired ? */
955 /* first tile */
956 /* judging by the first tile offset needed, could possibly
957 directly address/clear 4x4 tiles instead of 8x2 * 4x4
958 macro tiles, though would still need clear mask for
959 right/bottom if truely 4x4 granularity is desired ? */
915 OUT_RING( tileoffset * 16 );
960 OUT_RING(tileoffset * 16);
916 /* the number of tiles to clear */
961 /* the number of tiles to clear */
917 OUT_RING( nrtilesx + 1 );
962 OUT_RING(nrtilesx + 1);
918 /* clear mask : chooses the clearing pattern. */
963 /* clear mask : chooses the clearing pattern. */
919 OUT_RING( clearmask );
964 OUT_RING(clearmask);
920 ADVANCE_RING();
921 tileoffset += depthpixperline >> 5;
922 }
965 ADVANCE_RING();
966 tileoffset += depthpixperline >> 5;
967 }
923 }
924 else { /* rv 100 */
968 } else { /* rv 100 */
925 /* rv100 might not need 64 pix alignment, who knows */
926 /* offsets are, hmm, weird */
969 /* rv100 might not need 64 pix alignment, who knows */
970 /* offsets are, hmm, weird */
927 tileoffset = ((pbox[i].y1 >> 4) * depthpixperline + pbox[i].x1) >> 6;
928 nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4;
929 nrtilesy = (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
971 tileoffset =
972 ((pbox[i].y1 >> 4) * depthpixperline +
973 pbox[i].x1) >> 6;
974 nrtilesx =
975 ((pbox[i].x2 & ~63) -
976 (pbox[i].x1 & ~63)) >> 4;
977 nrtilesy =
978 (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
930 for (j = 0; j <= nrtilesy; j++) {
979 for (j = 0; j <= nrtilesy; j++) {
931 BEGIN_RING( 4 );
932 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) );
933 OUT_RING( tileoffset * 128 );
980 BEGIN_RING(4);
981 OUT_RING(CP_PACKET3
982 (RADEON_3D_CLEAR_ZMASK, 2));
983 OUT_RING(tileoffset * 128);
934 /* the number of tiles to clear */
984 /* the number of tiles to clear */
935 OUT_RING( nrtilesx + 4 );
985 OUT_RING(nrtilesx + 4);
936 /* clear mask : chooses the clearing pattern. */
986 /* clear mask : chooses the clearing pattern. */
937 OUT_RING( clearmask );
987 OUT_RING(clearmask);
938 ADVANCE_RING();
939 tileoffset += depthpixperline >> 6;
940 }
941 }
942 }
943
944 /* TODO don't always clear all hi-level z tiles */
988 ADVANCE_RING();
989 tileoffset += depthpixperline >> 6;
990 }
991 }
992 }
993
994 /* TODO don't always clear all hi-level z tiles */
945 if ((dev_priv->flags & CHIP_HAS_HIERZ) && (dev_priv->microcode_version==UCODE_R200)
946 && (flags & RADEON_USE_HIERZ))
947 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
948 /* FIXME : the mask supposedly contains low-res z values. So can't set
949 just to the max (0xff? or actually 0x3fff?), need to take z clear
950 value into account? */
995 if ((dev_priv->flags & CHIP_HAS_HIERZ)
996 && (dev_priv->microcode_version == UCODE_R200)
997 && (flags & RADEON_USE_HIERZ))
998 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
999 /* FIXME : the mask supposedly contains low-res z values. So can't set
1000 just to the max (0xff? or actually 0x3fff?), need to take z clear
1001 value into account? */
951 {
1002 {
952 BEGIN_RING( 4 );
953 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) );
954 OUT_RING( 0x0 ); /* First tile */
955 OUT_RING( 0x3cc0 );
956 OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
1003 BEGIN_RING(4);
1004 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
1005 OUT_RING(0x0); /* First tile */
1006 OUT_RING(0x3cc0);
1007 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
957 ADVANCE_RING();
958 }
959 }
960
961 /* We have to clear the depth and/or stencil buffers by
962 * rendering a quad into just those buffers. Thus, we have to
963 * make sure the 3D engine is configured correctly.
964 */

--- 61 unchanged lines hidden (view full) ---

1026 tempRB3D_STENCILREFMASK = clear->depth_mask;
1027 } else {
1028 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
1029 tempRB3D_STENCILREFMASK = 0x00000000;
1030 }
1031
1032 if (flags & RADEON_USE_COMP_ZBUF) {
1033 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1008 ADVANCE_RING();
1009 }
1010 }
1011
1012 /* We have to clear the depth and/or stencil buffers by
1013 * rendering a quad into just those buffers. Thus, we have to
1014 * make sure the 3D engine is configured correctly.
1015 */

--- 61 unchanged lines hidden (view full) ---

1077 tempRB3D_STENCILREFMASK = clear->depth_mask;
1078 } else {
1079 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
1080 tempRB3D_STENCILREFMASK = 0x00000000;
1081 }
1082
1083 if (flags & RADEON_USE_COMP_ZBUF) {
1084 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1034 RADEON_Z_DECOMPRESSION_ENABLE;
1085 RADEON_Z_DECOMPRESSION_ENABLE;
1035 }
1036 if (flags & RADEON_USE_HIERZ) {
1037 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1038 }
1039
1040 BEGIN_RING(26);
1041 RADEON_WAIT_UNTIL_2D_IDLE();
1042

--- 40 unchanged lines hidden (view full) ---

1083 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1084 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1085 OUT_RING(0x3f800000);
1086 ADVANCE_RING();
1087 }
1088 } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1089
1090 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1086 }
1087 if (flags & RADEON_USE_HIERZ) {
1088 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1089 }
1090
1091 BEGIN_RING(26);
1092 RADEON_WAIT_UNTIL_2D_IDLE();
1093

--- 40 unchanged lines hidden (view full) ---

1134 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1135 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1136 OUT_RING(0x3f800000);
1137 ADVANCE_RING();
1138 }
1139 } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1140
1141 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1091
1142
1092 rb3d_cntl = depth_clear->rb3d_cntl;
1093
1094 if (flags & RADEON_DEPTH) {
1095 rb3d_cntl |= RADEON_Z_ENABLE;
1096 } else {
1097 rb3d_cntl &= ~RADEON_Z_ENABLE;
1098 }
1099
1100 if (flags & RADEON_STENCIL) {
1101 rb3d_cntl |= RADEON_STENCIL_ENABLE;
1102 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
1103 } else {
1104 rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
1105 rb3d_stencilrefmask = 0x00000000;
1106 }
1107
1108 if (flags & RADEON_USE_COMP_ZBUF) {
1109 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1143 rb3d_cntl = depth_clear->rb3d_cntl;
1144
1145 if (flags & RADEON_DEPTH) {
1146 rb3d_cntl |= RADEON_Z_ENABLE;
1147 } else {
1148 rb3d_cntl &= ~RADEON_Z_ENABLE;
1149 }
1150
1151 if (flags & RADEON_STENCIL) {
1152 rb3d_cntl |= RADEON_STENCIL_ENABLE;
1153 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
1154 } else {
1155 rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
1156 rb3d_stencilrefmask = 0x00000000;
1157 }
1158
1159 if (flags & RADEON_USE_COMP_ZBUF) {
1160 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1110 RADEON_Z_DECOMPRESSION_ENABLE;
1161 RADEON_Z_DECOMPRESSION_ENABLE;
1111 }
1112 if (flags & RADEON_USE_HIERZ) {
1113 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1114 }
1115
1116 BEGIN_RING(13);
1117 RADEON_WAIT_UNTIL_2D_IDLE();
1118

--- 445 unchanged lines hidden (view full) ---

1564 texpitch = tex->pitch;
1565 if ((texpitch << 22) & RADEON_DST_TILE_MICRO) {
1566 microtile = 1;
1567 if (tex_width < 64) {
1568 texpitch &= ~(RADEON_DST_TILE_MICRO >> 22);
1569 /* we got tiled coordinates, untile them */
1570 image->x *= 2;
1571 }
1162 }
1163 if (flags & RADEON_USE_HIERZ) {
1164 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1165 }
1166
1167 BEGIN_RING(13);
1168 RADEON_WAIT_UNTIL_2D_IDLE();
1169

--- 445 unchanged lines hidden (view full) ---

1615 texpitch = tex->pitch;
1616 if ((texpitch << 22) & RADEON_DST_TILE_MICRO) {
1617 microtile = 1;
1618 if (tex_width < 64) {
1619 texpitch &= ~(RADEON_DST_TILE_MICRO >> 22);
1620 /* we got tiled coordinates, untile them */
1621 image->x *= 2;
1622 }
1572 }
1573 else microtile = 0;
1623 } else
1624 microtile = 0;
1574
1575 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1576
1577 do {
1578 DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1579 tex->offset >> 10, tex->pitch, tex->format,
1580 image->x, image->y, image->width, image->height);
1581

--- 27 unchanged lines hidden (view full) ---

1609 }
1610
1611 /* Dispatch the indirect buffer.
1612 */
1613 buffer =
1614 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
1615 dwords = size / 4;
1616
1625
1626 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1627
1628 do {
1629 DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1630 tex->offset >> 10, tex->pitch, tex->format,
1631 image->x, image->y, image->width, image->height);
1632

--- 27 unchanged lines hidden (view full) ---

1660 }
1661
1662 /* Dispatch the indirect buffer.
1663 */
1664 buffer =
1665 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
1666 dwords = size / 4;
1667
1668#define RADEON_COPY_MT(_buf, _data, _width) \
1669 do { \
1670 if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\
1671 DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \
1672 return DRM_ERR(EFAULT); \
1673 } \
1674 } while(0)
1675
1617 if (microtile) {
1618 /* texture micro tiling in use, minimum texture width is thus 16 bytes.
1619 however, we cannot use blitter directly for texture width < 64 bytes,
1620 since minimum tex pitch is 64 bytes and we need this to match
1621 the texture width, otherwise the blitter will tile it wrong.
1622 Thus, tiling manually in this case. Additionally, need to special
1623 case tex height = 1, since our actual image will have height 2
1624 and we need to ensure we don't read beyond the texture size
1625 from user space. */
1626 if (tex->height == 1) {
1627 if (tex_width >= 64 || tex_width <= 16) {
1676 if (microtile) {
1677 /* texture micro tiling in use, minimum texture width is thus 16 bytes.
1678 however, we cannot use blitter directly for texture width < 64 bytes,
1679 since minimum tex pitch is 64 bytes and we need this to match
1680 the texture width, otherwise the blitter will tile it wrong.
1681 Thus, tiling manually in this case. Additionally, need to special
1682 case tex height = 1, since our actual image will have height 2
1683 and we need to ensure we don't read beyond the texture size
1684 from user space. */
1685 if (tex->height == 1) {
1686 if (tex_width >= 64 || tex_width <= 16) {
1628 if (DRM_COPY_FROM_USER(buffer, data,
1629 tex_width * sizeof(u32))) {
1630 DRM_ERROR("EFAULT on pad, %d bytes\n",
1631 tex_width);
1632 return DRM_ERR(EFAULT);
1633 }
1687 RADEON_COPY_MT(buffer, data,
1688 (int)(tex_width * sizeof(u32)));
1634 } else if (tex_width == 32) {
1689 } else if (tex_width == 32) {
1635 if (DRM_COPY_FROM_USER(buffer, data, 16)) {
1636 DRM_ERROR("EFAULT on pad, %d bytes\n",
1637 tex_width);
1638 return DRM_ERR(EFAULT);
1639 }
1640 if (DRM_COPY_FROM_USER(buffer + 8, data + 16, 16)) {
1641 DRM_ERROR("EFAULT on pad, %d bytes\n",
1642 tex_width);
1643 return DRM_ERR(EFAULT);
1644 }
1690 RADEON_COPY_MT(buffer, data, 16);
1691 RADEON_COPY_MT(buffer + 8,
1692 data + 16, 16);
1645 }
1646 } else if (tex_width >= 64 || tex_width == 16) {
1693 }
1694 } else if (tex_width >= 64 || tex_width == 16) {
1647 if (DRM_COPY_FROM_USER(buffer, data,
1648 dwords * sizeof(u32))) {
1649 DRM_ERROR("EFAULT on data, %d dwords\n",
1650 dwords);
1651 return DRM_ERR(EFAULT);
1652 }
1695 RADEON_COPY_MT(buffer, data,
1696 (int)(dwords * sizeof(u32)));
1653 } else if (tex_width < 16) {
1654 for (i = 0; i < tex->height; i++) {
1697 } else if (tex_width < 16) {
1698 for (i = 0; i < tex->height; i++) {
1655 if (DRM_COPY_FROM_USER(buffer, data, tex_width)) {
1656 DRM_ERROR("EFAULT on pad, %d bytes\n",
1657 tex_width);
1658 return DRM_ERR(EFAULT);
1659 }
1699 RADEON_COPY_MT(buffer, data, tex_width);
1660 buffer += 4;
1661 data += tex_width;
1662 }
1663 } else if (tex_width == 32) {
1700 buffer += 4;
1701 data += tex_width;
1702 }
1703 } else if (tex_width == 32) {
1664 /* TODO: make sure this works when not fitting in one buffer
1665 (i.e. 32bytes x 2048...) */
1704 /* TODO: make sure this works when not fitting in one buffer
1705 (i.e. 32bytes x 2048...) */
1666 for (i = 0; i < tex->height; i += 2) {
1706 for (i = 0; i < tex->height; i += 2) {
1667 if (DRM_COPY_FROM_USER(buffer, data, 16)) {
1668 DRM_ERROR("EFAULT on pad, %d bytes\n",
1669 tex_width);
1670 return DRM_ERR(EFAULT);
1671 }
1707 RADEON_COPY_MT(buffer, data, 16);
1672 data += 16;
1708 data += 16;
1673 if (DRM_COPY_FROM_USER(buffer + 8, data, 16)) {
1674 DRM_ERROR("EFAULT on pad, %d bytes\n",
1675 tex_width);
1676 return DRM_ERR(EFAULT);
1677 }
1709 RADEON_COPY_MT(buffer + 8, data, 16);
1678 data += 16;
1710 data += 16;
1679 if (DRM_COPY_FROM_USER(buffer + 4, data, 16)) {
1680 DRM_ERROR("EFAULT on pad, %d bytes\n",
1681 tex_width);
1682 return DRM_ERR(EFAULT);
1683 }
1711 RADEON_COPY_MT(buffer + 4, data, 16);
1684 data += 16;
1712 data += 16;
1685 if (DRM_COPY_FROM_USER(buffer + 12, data, 16)) {
1686 DRM_ERROR("EFAULT on pad, %d bytes\n",
1687 tex_width);
1688 return DRM_ERR(EFAULT);
1689 }
1713 RADEON_COPY_MT(buffer + 12, data, 16);
1690 data += 16;
1691 buffer += 16;
1692 }
1693 }
1714 data += 16;
1715 buffer += 16;
1716 }
1717 }
1694 }
1695 else {
1718 } else {
1696 if (tex_width >= 32) {
1697 /* Texture image width is larger than the minimum, so we
1698 * can upload it directly.
1699 */
1719 if (tex_width >= 32) {
1720 /* Texture image width is larger than the minimum, so we
1721 * can upload it directly.
1722 */
1700 if (DRM_COPY_FROM_USER(buffer, data,
1701 dwords * sizeof(u32))) {
1702 DRM_ERROR("EFAULT on data, %d dwords\n",
1703 dwords);
1704 return DRM_ERR(EFAULT);
1705 }
1723 RADEON_COPY_MT(buffer, data,
1724 (int)(dwords * sizeof(u32)));
1706 } else {
1707 /* Texture image width is less than the minimum, so we
1708 * need to pad out each image scanline to the minimum
1709 * width.
1710 */
1711 for (i = 0; i < tex->height; i++) {
1725 } else {
1726 /* Texture image width is less than the minimum, so we
1727 * need to pad out each image scanline to the minimum
1728 * width.
1729 */
1730 for (i = 0; i < tex->height; i++) {
1712 if (DRM_COPY_FROM_USER(buffer, data, tex_width)) {
1713 DRM_ERROR("EFAULT on pad, %d bytes\n",
1714 tex_width);
1715 return DRM_ERR(EFAULT);
1716 }
1731 RADEON_COPY_MT(buffer, data, tex_width);
1717 buffer += 8;
1718 data += tex_width;
1719 }
1720 }
1721 }
1722
1732 buffer += 8;
1733 data += tex_width;
1734 }
1735 }
1736 }
1737
1738#undef RADEON_COPY_MT
1723 buf->filp = filp;
1724 buf->used = size;
1725 offset = dev_priv->gart_buffers_offset + buf->offset;
1726 BEGIN_RING(9);
1727 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
1728 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1729 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1730 RADEON_GMC_BRUSH_NONE |
1731 (format << 8) |
1732 RADEON_GMC_SRC_DATATYPE_COLOR |
1733 RADEON_ROP3_S |
1734 RADEON_DP_SRC_SOURCE_MEMORY |
1739 buf->filp = filp;
1740 buf->used = size;
1741 offset = dev_priv->gart_buffers_offset + buf->offset;
1742 BEGIN_RING(9);
1743 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
1744 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1745 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1746 RADEON_GMC_BRUSH_NONE |
1747 (format << 8) |
1748 RADEON_GMC_SRC_DATATYPE_COLOR |
1749 RADEON_ROP3_S |
1750 RADEON_DP_SRC_SOURCE_MEMORY |
1735 RADEON_GMC_CLR_CMP_CNTL_DIS |
1736 RADEON_GMC_WR_MSK_DIS );
1751 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1737 OUT_RING((spitch << 22) | (offset >> 10));
1738 OUT_RING((texpitch << 22) | (tex->offset >> 10));
1739 OUT_RING(0);
1740 OUT_RING((image->x << 16) | image->y);
1741 OUT_RING((image->width << 16) | height);
1742 RADEON_WAIT_UNTIL_2D_IDLE();
1743 ADVANCE_RING();
1744

--- 31 unchanged lines hidden (view full) ---

1776 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
1777 for (i = 0; i < 32; i++) {
1778 OUT_RING(stipple[i]);
1779 }
1780
1781 ADVANCE_RING();
1782}
1783
1752 OUT_RING((spitch << 22) | (offset >> 10));
1753 OUT_RING((texpitch << 22) | (tex->offset >> 10));
1754 OUT_RING(0);
1755 OUT_RING((image->x << 16) | image->y);
1756 OUT_RING((image->width << 16) | height);
1757 RADEON_WAIT_UNTIL_2D_IDLE();
1758 ADVANCE_RING();
1759

--- 31 unchanged lines hidden (view full) ---

1791 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
1792 for (i = 0; i < 32; i++) {
1793 OUT_RING(stipple[i]);
1794 }
1795
1796 ADVANCE_RING();
1797}
1798
1784static void radeon_apply_surface_regs(int surf_index, drm_radeon_private_t *dev_priv)
1799static void radeon_apply_surface_regs(int surf_index,
1800 drm_radeon_private_t *dev_priv)
1785{
1786 if (!dev_priv->mmio)
1787 return;
1788
1789 radeon_do_cp_idle(dev_priv);
1790
1801{
1802 if (!dev_priv->mmio)
1803 return;
1804
1805 radeon_do_cp_idle(dev_priv);
1806
1791 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*surf_index,
1792 dev_priv->surfaces[surf_index].flags);
1793 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*surf_index,
1794 dev_priv->surfaces[surf_index].lower);
1795 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*surf_index,
1796 dev_priv->surfaces[surf_index].upper);
1807 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
1808 dev_priv->surfaces[surf_index].flags);
1809 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
1810 dev_priv->surfaces[surf_index].lower);
1811 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
1812 dev_priv->surfaces[surf_index].upper);
1797}
1798
1799/* Allocates a virtual surface
1813}
1814
1815/* Allocates a virtual surface
1800 * doesn't always allocate a real surface, will stretch an existing
1816 * doesn't always allocate a real surface, will stretch an existing
1801 * surface when possible.
1802 *
1803 * Note that refcount can be at most 2, since during a free refcount=3
1804 * might mean we have to allocate a new surface which might not always
1805 * be available.
1817 * surface when possible.
1818 *
1819 * Note that refcount can be at most 2, since during a free refcount=3
1820 * might mean we have to allocate a new surface which might not always
1821 * be available.
1806 * For example : we allocate three contigous surfaces ABC. If B is
1822 * For example : we allocate three contigous surfaces ABC. If B is
1807 * freed, we suddenly need two surfaces to store A and C, which might
1808 * not always be available.
1809 */
1823 * freed, we suddenly need two surfaces to store A and C, which might
1824 * not always be available.
1825 */
1810static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *dev_priv, DRMFILE filp)
1826static int alloc_surface(drm_radeon_surface_alloc_t *new,
1827 drm_radeon_private_t *dev_priv, DRMFILE filp)
1811{
1812 struct radeon_virt_surface *s;
1813 int i;
1814 int virt_surface_index;
1815 uint32_t new_upper, new_lower;
1816
1817 new_lower = new->address;
1818 new_upper = new_lower + new->size - 1;
1819
1820 /* sanity check */
1821 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
1828{
1829 struct radeon_virt_surface *s;
1830 int i;
1831 int virt_surface_index;
1832 uint32_t new_upper, new_lower;
1833
1834 new_lower = new->address;
1835 new_upper = new_lower + new->size - 1;
1836
1837 /* sanity check */
1838 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
1822 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) != RADEON_SURF_ADDRESS_FIXED_MASK) ||
1823 ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
1839 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
1840 RADEON_SURF_ADDRESS_FIXED_MASK)
1841 || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
1824 return -1;
1825
1826 /* make sure there is no overlap with existing surfaces */
1827 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1828 if ((dev_priv->surfaces[i].refcount != 0) &&
1842 return -1;
1843
1844 /* make sure there is no overlap with existing surfaces */
1845 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1846 if ((dev_priv->surfaces[i].refcount != 0) &&
1829 (( (new_lower >= dev_priv->surfaces[i].lower) &&
1830 (new_lower < dev_priv->surfaces[i].upper) ) ||
1831 ( (new_lower < dev_priv->surfaces[i].lower) &&
1832 (new_upper > dev_priv->surfaces[i].lower) )) ){
1833 return -1;}
1847 (((new_lower >= dev_priv->surfaces[i].lower) &&
1848 (new_lower < dev_priv->surfaces[i].upper)) ||
1849 ((new_lower < dev_priv->surfaces[i].lower) &&
1850 (new_upper > dev_priv->surfaces[i].lower)))) {
1851 return -1;
1852 }
1834 }
1835
1836 /* find a virtual surface */
1853 }
1854
1855 /* find a virtual surface */
1837 for (i = 0; i < 2*RADEON_MAX_SURFACES; i++)
1856 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
1838 if (dev_priv->virt_surfaces[i].filp == 0)
1839 break;
1857 if (dev_priv->virt_surfaces[i].filp == 0)
1858 break;
1840 if (i == 2*RADEON_MAX_SURFACES) {
1841 return -1;}
1859 if (i == 2 * RADEON_MAX_SURFACES) {
1860 return -1;
1861 }
1842 virt_surface_index = i;
1843
1844 /* try to reuse an existing surface */
1845 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1846 /* extend before */
1847 if ((dev_priv->surfaces[i].refcount == 1) &&
1862 virt_surface_index = i;
1863
1864 /* try to reuse an existing surface */
1865 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1866 /* extend before */
1867 if ((dev_priv->surfaces[i].refcount == 1) &&
1848 (new->flags == dev_priv->surfaces[i].flags) &&
1849 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
1868 (new->flags == dev_priv->surfaces[i].flags) &&
1869 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
1850 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1851 s->surface_index = i;
1852 s->lower = new_lower;
1853 s->upper = new_upper;
1854 s->flags = new->flags;
1855 s->filp = filp;
1856 dev_priv->surfaces[i].refcount++;
1857 dev_priv->surfaces[i].lower = s->lower;
1858 radeon_apply_surface_regs(s->surface_index, dev_priv);
1859 return virt_surface_index;
1860 }
1861
1862 /* extend after */
1863 if ((dev_priv->surfaces[i].refcount == 1) &&
1870 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1871 s->surface_index = i;
1872 s->lower = new_lower;
1873 s->upper = new_upper;
1874 s->flags = new->flags;
1875 s->filp = filp;
1876 dev_priv->surfaces[i].refcount++;
1877 dev_priv->surfaces[i].lower = s->lower;
1878 radeon_apply_surface_regs(s->surface_index, dev_priv);
1879 return virt_surface_index;
1880 }
1881
1882 /* extend after */
1883 if ((dev_priv->surfaces[i].refcount == 1) &&
1864 (new->flags == dev_priv->surfaces[i].flags) &&
1865 (new_lower == dev_priv->surfaces[i].upper + 1)) {
1884 (new->flags == dev_priv->surfaces[i].flags) &&
1885 (new_lower == dev_priv->surfaces[i].upper + 1)) {
1866 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1867 s->surface_index = i;
1868 s->lower = new_lower;
1869 s->upper = new_upper;
1870 s->flags = new->flags;
1871 s->filp = filp;
1872 dev_priv->surfaces[i].refcount++;
1873 dev_priv->surfaces[i].upper = s->upper;

--- 19 unchanged lines hidden (view full) ---

1893 return virt_surface_index;
1894 }
1895 }
1896
1897 /* we didn't find anything */
1898 return -1;
1899}
1900
1886 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1887 s->surface_index = i;
1888 s->lower = new_lower;
1889 s->upper = new_upper;
1890 s->flags = new->flags;
1891 s->filp = filp;
1892 dev_priv->surfaces[i].refcount++;
1893 dev_priv->surfaces[i].upper = s->upper;

--- 19 unchanged lines hidden (view full) ---

1913 return virt_surface_index;
1914 }
1915 }
1916
1917 /* we didn't find anything */
1918 return -1;
1919}
1920
1901static int free_surface(DRMFILE filp, drm_radeon_private_t *dev_priv, int lower)
1921static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv,
1922 int lower)
1902{
1903 struct radeon_virt_surface *s;
1904 int i;
1905 /* find the virtual surface */
1923{
1924 struct radeon_virt_surface *s;
1925 int i;
1926 /* find the virtual surface */
1906 for(i = 0; i < 2*RADEON_MAX_SURFACES; i++) {
1927 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
1907 s = &(dev_priv->virt_surfaces[i]);
1908 if (s->filp) {
1909 if ((lower == s->lower) && (filp == s->filp)) {
1928 s = &(dev_priv->virt_surfaces[i]);
1929 if (s->filp) {
1930 if ((lower == s->lower) && (filp == s->filp)) {
1910 if (dev_priv->surfaces[s->surface_index].lower == s->lower)
1911 dev_priv->surfaces[s->surface_index].lower = s->upper;
1931 if (dev_priv->surfaces[s->surface_index].
1932 lower == s->lower)
1933 dev_priv->surfaces[s->surface_index].
1934 lower = s->upper;
1912
1935
1913 if (dev_priv->surfaces[s->surface_index].upper == s->upper)
1914 dev_priv->surfaces[s->surface_index].upper = s->lower;
1936 if (dev_priv->surfaces[s->surface_index].
1937 upper == s->upper)
1938 dev_priv->surfaces[s->surface_index].
1939 upper = s->lower;
1915
1916 dev_priv->surfaces[s->surface_index].refcount--;
1940
1941 dev_priv->surfaces[s->surface_index].refcount--;
1917 if (dev_priv->surfaces[s->surface_index].refcount == 0)
1918 dev_priv->surfaces[s->surface_index].flags = 0;
1919 s->filp = 0;
1920 radeon_apply_surface_regs(s->surface_index, dev_priv);
1942 if (dev_priv->surfaces[s->surface_index].
1943 refcount == 0)
1944 dev_priv->surfaces[s->surface_index].
1945 flags = 0;
1946 s->filp = NULL;
1947 radeon_apply_surface_regs(s->surface_index,
1948 dev_priv);
1921 return 0;
1922 }
1923 }
1924 }
1925 return 1;
1926}
1927
1949 return 0;
1950 }
1951 }
1952 }
1953 return 1;
1954}
1955
1928static void radeon_surfaces_release(DRMFILE filp, drm_radeon_private_t *dev_priv)
1956static void radeon_surfaces_release(DRMFILE filp,
1957 drm_radeon_private_t * dev_priv)
1929{
1930 int i;
1958{
1959 int i;
1931 for( i = 0; i < 2*RADEON_MAX_SURFACES; i++)
1932 {
1960 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
1933 if (dev_priv->virt_surfaces[i].filp == filp)
1961 if (dev_priv->virt_surfaces[i].filp == filp)
1934 free_surface(filp, dev_priv, dev_priv->virt_surfaces[i].lower);
1962 free_surface(filp, dev_priv,
1963 dev_priv->virt_surfaces[i].lower);
1935 }
1936}
1937
1938/* ================================================================
1939 * IOCTL functions
1940 */
1964 }
1965}
1966
1967/* ================================================================
1968 * IOCTL functions
1969 */
1941
1942static int radeon_surface_alloc(DRM_IOCTL_ARGS)
1943{
1944 DRM_DEVICE;
1945 drm_radeon_private_t *dev_priv = dev->dev_private;
1946 drm_radeon_surface_alloc_t alloc;
1947
1948 if (!dev_priv) {
1970static int radeon_surface_alloc(DRM_IOCTL_ARGS)
1971{
1972 DRM_DEVICE;
1973 drm_radeon_private_t *dev_priv = dev->dev_private;
1974 drm_radeon_surface_alloc_t alloc;
1975
1976 if (!dev_priv) {
1949 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1977 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1950 return DRM_ERR(EINVAL);
1951 }
1952
1978 return DRM_ERR(EINVAL);
1979 }
1980
1953 DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_surface_alloc_t __user *)data,
1954 sizeof(alloc));
1981 DRM_COPY_FROM_USER_IOCTL(alloc,
1982 (drm_radeon_surface_alloc_t __user *) data,
1983 sizeof(alloc));
1955
1956 if (alloc_surface(&alloc, dev_priv, filp) == -1)
1957 return DRM_ERR(EINVAL);
1958 else
1959 return 0;
1960}
1961
1962static int radeon_surface_free(DRM_IOCTL_ARGS)
1963{
1964 DRM_DEVICE;
1965 drm_radeon_private_t *dev_priv = dev->dev_private;
1966 drm_radeon_surface_free_t memfree;
1967
1968 if (!dev_priv) {
1984
1985 if (alloc_surface(&alloc, dev_priv, filp) == -1)
1986 return DRM_ERR(EINVAL);
1987 else
1988 return 0;
1989}
1990
1991static int radeon_surface_free(DRM_IOCTL_ARGS)
1992{
1993 DRM_DEVICE;
1994 drm_radeon_private_t *dev_priv = dev->dev_private;
1995 drm_radeon_surface_free_t memfree;
1996
1997 if (!dev_priv) {
1969 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1998 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1970 return DRM_ERR(EINVAL);
1971 }
1972
1999 return DRM_ERR(EINVAL);
2000 }
2001
1973 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_surface_free_t __user *)data,
1974 sizeof(memfree) );
2002 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_surface_free_t __user *) data,
2003 sizeof(memfree));
1975
1976 if (free_surface(filp, dev_priv, memfree.address))
1977 return DRM_ERR(EINVAL);
1978 else
1979 return 0;
1980}
1981
1982static int radeon_cp_clear(DRM_IOCTL_ARGS)

--- 109 unchanged lines hidden (view full) ---

2092 return 0;
2093}
2094
2095static int radeon_cp_vertex(DRM_IOCTL_ARGS)
2096{
2097 DRM_DEVICE;
2098 drm_radeon_private_t *dev_priv = dev->dev_private;
2099 drm_file_t *filp_priv;
2004
2005 if (free_surface(filp, dev_priv, memfree.address))
2006 return DRM_ERR(EINVAL);
2007 else
2008 return 0;
2009}
2010
2011static int radeon_cp_clear(DRM_IOCTL_ARGS)

--- 109 unchanged lines hidden (view full) ---

2121 return 0;
2122}
2123
2124static int radeon_cp_vertex(DRM_IOCTL_ARGS)
2125{
2126 DRM_DEVICE;
2127 drm_radeon_private_t *dev_priv = dev->dev_private;
2128 drm_file_t *filp_priv;
2100 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2129 drm_radeon_sarea_t *sarea_priv;
2101 drm_device_dma_t *dma = dev->dma;
2102 drm_buf_t *buf;
2103 drm_radeon_vertex_t vertex;
2104 drm_radeon_tcl_prim_t prim;
2105
2106 LOCK_TEST_WITH_RETURN(dev, filp);
2107
2108 if (!dev_priv) {
2109 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2110 return DRM_ERR(EINVAL);
2111 }
2112
2130 drm_device_dma_t *dma = dev->dma;
2131 drm_buf_t *buf;
2132 drm_radeon_vertex_t vertex;
2133 drm_radeon_tcl_prim_t prim;
2134
2135 LOCK_TEST_WITH_RETURN(dev, filp);
2136
2137 if (!dev_priv) {
2138 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2139 return DRM_ERR(EINVAL);
2140 }
2141
2142 sarea_priv = dev_priv->sarea_priv;
2143
2113 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2114
2115 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data,
2116 sizeof(vertex));
2117
2118 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
2119 DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
2120

--- 59 unchanged lines hidden (view full) ---

2180 return 0;
2181}
2182
2183static int radeon_cp_indices(DRM_IOCTL_ARGS)
2184{
2185 DRM_DEVICE;
2186 drm_radeon_private_t *dev_priv = dev->dev_private;
2187 drm_file_t *filp_priv;
2144 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2145
2146 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data,
2147 sizeof(vertex));
2148
2149 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
2150 DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
2151

--- 59 unchanged lines hidden (view full) ---

2211 return 0;
2212}
2213
2214static int radeon_cp_indices(DRM_IOCTL_ARGS)
2215{
2216 DRM_DEVICE;
2217 drm_radeon_private_t *dev_priv = dev->dev_private;
2218 drm_file_t *filp_priv;
2188 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2219 drm_radeon_sarea_t *sarea_priv;
2189 drm_device_dma_t *dma = dev->dma;
2190 drm_buf_t *buf;
2191 drm_radeon_indices_t elts;
2192 drm_radeon_tcl_prim_t prim;
2193 int count;
2194
2195 LOCK_TEST_WITH_RETURN(dev, filp);
2196
2197 if (!dev_priv) {
2198 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2199 return DRM_ERR(EINVAL);
2200 }
2220 drm_device_dma_t *dma = dev->dma;
2221 drm_buf_t *buf;
2222 drm_radeon_indices_t elts;
2223 drm_radeon_tcl_prim_t prim;
2224 int count;
2225
2226 LOCK_TEST_WITH_RETURN(dev, filp);
2227
2228 if (!dev_priv) {
2229 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2230 return DRM_ERR(EINVAL);
2231 }
2232 sarea_priv = dev_priv->sarea_priv;
2201
2202 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2203
2204 DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data,
2205 sizeof(elts));
2206
2207 DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
2208 DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard);

--- 199 unchanged lines hidden (view full) ---

2408 return 0;
2409}
2410
2411static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
2412{
2413 DRM_DEVICE;
2414 drm_radeon_private_t *dev_priv = dev->dev_private;
2415 drm_file_t *filp_priv;
2233
2234 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2235
2236 DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data,
2237 sizeof(elts));
2238
2239 DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
2240 DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard);

--- 199 unchanged lines hidden (view full) ---

2440 return 0;
2441}
2442
2443static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
2444{
2445 DRM_DEVICE;
2446 drm_radeon_private_t *dev_priv = dev->dev_private;
2447 drm_file_t *filp_priv;
2416 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2448 drm_radeon_sarea_t *sarea_priv;
2417 drm_device_dma_t *dma = dev->dma;
2418 drm_buf_t *buf;
2419 drm_radeon_vertex2_t vertex;
2420 int i;
2421 unsigned char laststate;
2422
2423 LOCK_TEST_WITH_RETURN(dev, filp);
2424
2425 if (!dev_priv) {
2426 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2427 return DRM_ERR(EINVAL);
2428 }
2429
2449 drm_device_dma_t *dma = dev->dma;
2450 drm_buf_t *buf;
2451 drm_radeon_vertex2_t vertex;
2452 int i;
2453 unsigned char laststate;
2454
2455 LOCK_TEST_WITH_RETURN(dev, filp);
2456
2457 if (!dev_priv) {
2458 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2459 return DRM_ERR(EINVAL);
2460 }
2461
2462 sarea_priv = dev_priv->sarea_priv;
2463
2430 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2431
2432 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data,
2433 sizeof(vertex));
2434
2435 DRM_DEBUG("pid=%d index=%d discard=%d\n",
2436 DRM_CURRENTPID, vertex.idx, vertex.discard);
2437

--- 72 unchanged lines hidden (view full) ---

2510
2511 COMMIT_RING();
2512 return 0;
2513}
2514
2515static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2516 drm_file_t * filp_priv,
2517 drm_radeon_cmd_header_t header,
2464 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2465
2466 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data,
2467 sizeof(vertex));
2468
2469 DRM_DEBUG("pid=%d index=%d discard=%d\n",
2470 DRM_CURRENTPID, vertex.idx, vertex.discard);
2471

--- 72 unchanged lines hidden (view full) ---

2544
2545 COMMIT_RING();
2546 return 0;
2547}
2548
2549static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2550 drm_file_t * filp_priv,
2551 drm_radeon_cmd_header_t header,
2518 drm_radeon_cmd_buffer_t * cmdbuf)
2552 drm_radeon_kcmd_buffer_t *cmdbuf)
2519{
2520 int id = (int)header.packet.packet_id;
2521 int sz, reg;
2522 int *data = (int *)cmdbuf->buf;
2523 RING_LOCALS;
2524
2525 if (id >= RADEON_MAX_STATE_PACKETS)
2526 return DRM_ERR(EINVAL);

--- 16 unchanged lines hidden (view full) ---

2543 OUT_RING_TABLE(data, sz);
2544 ADVANCE_RING();
2545
2546 cmdbuf->buf += sz * sizeof(int);
2547 cmdbuf->bufsz -= sz * sizeof(int);
2548 return 0;
2549}
2550
2553{
2554 int id = (int)header.packet.packet_id;
2555 int sz, reg;
2556 int *data = (int *)cmdbuf->buf;
2557 RING_LOCALS;
2558
2559 if (id >= RADEON_MAX_STATE_PACKETS)
2560 return DRM_ERR(EINVAL);

--- 16 unchanged lines hidden (view full) ---

2577 OUT_RING_TABLE(data, sz);
2578 ADVANCE_RING();
2579
2580 cmdbuf->buf += sz * sizeof(int);
2581 cmdbuf->bufsz -= sz * sizeof(int);
2582 return 0;
2583}
2584
2551static __inline__ int radeon_emit_scalars(drm_radeon_private_t * dev_priv,
2585static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
2552 drm_radeon_cmd_header_t header,
2586 drm_radeon_cmd_header_t header,
2553 drm_radeon_cmd_buffer_t * cmdbuf)
2587 drm_radeon_kcmd_buffer_t *cmdbuf)
2554{
2555 int sz = header.scalars.count;
2556 int start = header.scalars.offset;
2557 int stride = header.scalars.stride;
2558 RING_LOCALS;
2559
2560 BEGIN_RING(3 + sz);
2561 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2562 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2563 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2564 OUT_RING_TABLE(cmdbuf->buf, sz);
2565 ADVANCE_RING();
2566 cmdbuf->buf += sz * sizeof(int);
2567 cmdbuf->bufsz -= sz * sizeof(int);
2568 return 0;
2569}
2570
2571/* God this is ugly
2572 */
2588{
2589 int sz = header.scalars.count;
2590 int start = header.scalars.offset;
2591 int stride = header.scalars.stride;
2592 RING_LOCALS;
2593
2594 BEGIN_RING(3 + sz);
2595 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2596 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2597 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2598 OUT_RING_TABLE(cmdbuf->buf, sz);
2599 ADVANCE_RING();
2600 cmdbuf->buf += sz * sizeof(int);
2601 cmdbuf->bufsz -= sz * sizeof(int);
2602 return 0;
2603}
2604
2605/* God this is ugly
2606 */
2573static __inline__ int radeon_emit_scalars2(drm_radeon_private_t * dev_priv,
2607static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
2574 drm_radeon_cmd_header_t header,
2608 drm_radeon_cmd_header_t header,
2575 drm_radeon_cmd_buffer_t * cmdbuf)
2609 drm_radeon_kcmd_buffer_t *cmdbuf)
2576{
2577 int sz = header.scalars.count;
2578 int start = ((unsigned int)header.scalars.offset) + 0x100;
2579 int stride = header.scalars.stride;
2580 RING_LOCALS;
2581
2582 BEGIN_RING(3 + sz);
2583 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2584 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2585 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2586 OUT_RING_TABLE(cmdbuf->buf, sz);
2587 ADVANCE_RING();
2588 cmdbuf->buf += sz * sizeof(int);
2589 cmdbuf->bufsz -= sz * sizeof(int);
2590 return 0;
2591}
2592
2610{
2611 int sz = header.scalars.count;
2612 int start = ((unsigned int)header.scalars.offset) + 0x100;
2613 int stride = header.scalars.stride;
2614 RING_LOCALS;
2615
2616 BEGIN_RING(3 + sz);
2617 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2618 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2619 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2620 OUT_RING_TABLE(cmdbuf->buf, sz);
2621 ADVANCE_RING();
2622 cmdbuf->buf += sz * sizeof(int);
2623 cmdbuf->bufsz -= sz * sizeof(int);
2624 return 0;
2625}
2626
2593static __inline__ int radeon_emit_vectors(drm_radeon_private_t * dev_priv,
2627static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
2594 drm_radeon_cmd_header_t header,
2628 drm_radeon_cmd_header_t header,
2595 drm_radeon_cmd_buffer_t * cmdbuf)
2629 drm_radeon_kcmd_buffer_t *cmdbuf)
2596{
2597 int sz = header.vectors.count;
2598 int start = header.vectors.offset;
2599 int stride = header.vectors.stride;
2600 RING_LOCALS;
2601
2602 BEGIN_RING(3 + sz);
2603 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));

--- 4 unchanged lines hidden (view full) ---

2608
2609 cmdbuf->buf += sz * sizeof(int);
2610 cmdbuf->bufsz -= sz * sizeof(int);
2611 return 0;
2612}
2613
2614static int radeon_emit_packet3(drm_device_t * dev,
2615 drm_file_t * filp_priv,
2630{
2631 int sz = header.vectors.count;
2632 int start = header.vectors.offset;
2633 int stride = header.vectors.stride;
2634 RING_LOCALS;
2635
2636 BEGIN_RING(3 + sz);
2637 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));

--- 4 unchanged lines hidden (view full) ---

2642
2643 cmdbuf->buf += sz * sizeof(int);
2644 cmdbuf->bufsz -= sz * sizeof(int);
2645 return 0;
2646}
2647
2648static int radeon_emit_packet3(drm_device_t * dev,
2649 drm_file_t * filp_priv,
2616 drm_radeon_cmd_buffer_t * cmdbuf)
2650 drm_radeon_kcmd_buffer_t *cmdbuf)
2617{
2618 drm_radeon_private_t *dev_priv = dev->dev_private;
2619 unsigned int cmdsz;
2620 int ret;
2621 RING_LOCALS;
2622
2623 DRM_DEBUG("\n");
2624

--- 7 unchanged lines hidden (view full) ---

2632 OUT_RING_TABLE(cmdbuf->buf, cmdsz);
2633 ADVANCE_RING();
2634
2635 cmdbuf->buf += cmdsz * 4;
2636 cmdbuf->bufsz -= cmdsz * 4;
2637 return 0;
2638}
2639
2651{
2652 drm_radeon_private_t *dev_priv = dev->dev_private;
2653 unsigned int cmdsz;
2654 int ret;
2655 RING_LOCALS;
2656
2657 DRM_DEBUG("\n");
2658

--- 7 unchanged lines hidden (view full) ---

2666 OUT_RING_TABLE(cmdbuf->buf, cmdsz);
2667 ADVANCE_RING();
2668
2669 cmdbuf->buf += cmdsz * 4;
2670 cmdbuf->bufsz -= cmdsz * 4;
2671 return 0;
2672}
2673
2640static int radeon_emit_packet3_cliprect(drm_device_t * dev,
2641 drm_file_t * filp_priv,
2642 drm_radeon_cmd_buffer_t * cmdbuf,
2674static int radeon_emit_packet3_cliprect(drm_device_t *dev,
2675 drm_file_t *filp_priv,
2676 drm_radeon_kcmd_buffer_t *cmdbuf,
2643 int orig_nbox)
2644{
2645 drm_radeon_private_t *dev_priv = dev->dev_private;
2646 drm_clip_rect_t box;
2647 unsigned int cmdsz;
2648 int ret;
2649 drm_clip_rect_t __user *boxes = cmdbuf->boxes;
2650 int i = 0;

--- 80 unchanged lines hidden (view full) ---

2731static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2732{
2733 DRM_DEVICE;
2734 drm_radeon_private_t *dev_priv = dev->dev_private;
2735 drm_file_t *filp_priv;
2736 drm_device_dma_t *dma = dev->dma;
2737 drm_buf_t *buf = NULL;
2738 int idx;
2677 int orig_nbox)
2678{
2679 drm_radeon_private_t *dev_priv = dev->dev_private;
2680 drm_clip_rect_t box;
2681 unsigned int cmdsz;
2682 int ret;
2683 drm_clip_rect_t __user *boxes = cmdbuf->boxes;
2684 int i = 0;

--- 80 unchanged lines hidden (view full) ---

2765static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2766{
2767 DRM_DEVICE;
2768 drm_radeon_private_t *dev_priv = dev->dev_private;
2769 drm_file_t *filp_priv;
2770 drm_device_dma_t *dma = dev->dma;
2771 drm_buf_t *buf = NULL;
2772 int idx;
2739 drm_radeon_cmd_buffer_t cmdbuf;
2773 drm_radeon_kcmd_buffer_t cmdbuf;
2740 drm_radeon_cmd_header_t header;
2741 int orig_nbox, orig_bufsz;
2742 char *kbuf = NULL;
2743
2744 LOCK_TEST_WITH_RETURN(dev, filp);
2745
2746 if (!dev_priv) {
2747 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2748 return DRM_ERR(EINVAL);
2749 }
2750
2751 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2752
2753 DRM_COPY_FROM_USER_IOCTL(cmdbuf,
2774 drm_radeon_cmd_header_t header;
2775 int orig_nbox, orig_bufsz;
2776 char *kbuf = NULL;
2777
2778 LOCK_TEST_WITH_RETURN(dev, filp);
2779
2780 if (!dev_priv) {
2781 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2782 return DRM_ERR(EINVAL);
2783 }
2784
2785 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2786
2787 DRM_COPY_FROM_USER_IOCTL(cmdbuf,
2754 (drm_radeon_cmd_buffer_t __user *) data,
2788 (drm_radeon_kcmd_buffer_t __user *) data,
2755 sizeof(cmdbuf));
2756
2757 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2758 VB_AGE_TEST_WITH_RETURN(dev_priv);
2759
2760 if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) {
2761 return DRM_ERR(EINVAL);
2762 }
2763
2764 /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid
2765 * races between checking values and using those values in other code,
2766 * and simply to avoid a lot of function calls to copy in data.
2767 */
2768 orig_bufsz = cmdbuf.bufsz;
2769 if (orig_bufsz != 0) {
2770 kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER);
2771 if (kbuf == NULL)
2772 return DRM_ERR(ENOMEM);
2789 sizeof(cmdbuf));
2790
2791 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2792 VB_AGE_TEST_WITH_RETURN(dev_priv);
2793
2794 if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) {
2795 return DRM_ERR(EINVAL);
2796 }
2797
2798 /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid
2799 * races between checking values and using those values in other code,
2800 * and simply to avoid a lot of function calls to copy in data.
2801 */
2802 orig_bufsz = cmdbuf.bufsz;
2803 if (orig_bufsz != 0) {
2804 kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER);
2805 if (kbuf == NULL)
2806 return DRM_ERR(ENOMEM);
2773 if (DRM_COPY_FROM_USER(kbuf, cmdbuf.buf, cmdbuf.bufsz)) {
2807 if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf.buf,
2808 cmdbuf.bufsz)) {
2774 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2775 return DRM_ERR(EFAULT);
2776 }
2777 cmdbuf.buf = kbuf;
2778 }
2779
2780 orig_nbox = cmdbuf.nbox;
2809 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2810 return DRM_ERR(EFAULT);
2811 }
2812 cmdbuf.buf = kbuf;
2813 }
2814
2815 orig_nbox = cmdbuf.nbox;
2781
2782 if(dev_priv->microcode_version == UCODE_R300) {
2816
2817 if (dev_priv->microcode_version == UCODE_R300) {
2783 int temp;
2818 int temp;
2784 temp=r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf);
2785
2819 temp = r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf);
2820
2786 if (orig_bufsz != 0)
2787 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2821 if (orig_bufsz != 0)
2822 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2788
2823
2789 return temp;
2790 }
2824 return temp;
2825 }
2791
2826
2792 /* microcode_version != r300 */
2793 while (cmdbuf.bufsz >= sizeof(header)) {
2827 /* microcode_version != r300 */
2828 while (cmdbuf.bufsz >= sizeof(header)) {
2829
2794 header.i = *(int *)cmdbuf.buf;
2795 cmdbuf.buf += sizeof(header);
2796 cmdbuf.bufsz -= sizeof(header);
2797
2798 switch (header.header.cmd_type) {
2799 case RADEON_CMD_PACKET:
2800 DRM_DEBUG("RADEON_CMD_PACKET\n");
2801 if (radeon_emit_packets

--- 75 unchanged lines hidden (view full) ---

2877 header.header.cmd_type,
2878 cmdbuf.buf - sizeof(header));
2879 goto err;
2880 }
2881 }
2882
2883 if (orig_bufsz != 0)
2884 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2830 header.i = *(int *)cmdbuf.buf;
2831 cmdbuf.buf += sizeof(header);
2832 cmdbuf.bufsz -= sizeof(header);
2833
2834 switch (header.header.cmd_type) {
2835 case RADEON_CMD_PACKET:
2836 DRM_DEBUG("RADEON_CMD_PACKET\n");
2837 if (radeon_emit_packets

--- 75 unchanged lines hidden (view full) ---

2913 header.header.cmd_type,
2914 cmdbuf.buf - sizeof(header));
2915 goto err;
2916 }
2917 }
2918
2919 if (orig_bufsz != 0)
2920 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2921
2885 DRM_DEBUG("DONE\n");
2886 COMMIT_RING();
2922 DRM_DEBUG("DONE\n");
2923 COMMIT_RING();
2887
2888 return 0;
2889
2924 return 0;
2925
2890err:
2926 err:
2891 if (orig_bufsz != 0)
2892 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2893 return DRM_ERR(EINVAL);
2894}
2895
2896static int radeon_cp_getparam(DRM_IOCTL_ARGS)
2897{
2898 DRM_DEVICE;

--- 33 unchanged lines hidden (view full) ---

2932 value = dev_priv->gart_vm_start;
2933 break;
2934 case RADEON_PARAM_REGISTER_HANDLE:
2935 value = dev_priv->mmio->offset;
2936 break;
2937 case RADEON_PARAM_STATUS_HANDLE:
2938 value = dev_priv->ring_rptr_offset;
2939 break;
2927 if (orig_bufsz != 0)
2928 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2929 return DRM_ERR(EINVAL);
2930}
2931
2932static int radeon_cp_getparam(DRM_IOCTL_ARGS)
2933{
2934 DRM_DEVICE;

--- 33 unchanged lines hidden (view full) ---

2968 value = dev_priv->gart_vm_start;
2969 break;
2970 case RADEON_PARAM_REGISTER_HANDLE:
2971 value = dev_priv->mmio->offset;
2972 break;
2973 case RADEON_PARAM_STATUS_HANDLE:
2974 value = dev_priv->ring_rptr_offset;
2975 break;
2940#ifndef __LP64__
2976#if BITS_PER_LONG == 32
2941 /*
2942 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
2943 * pointer which can't fit into an int-sized variable. According to
2944 * Michel D��nzer, the ioctl() is only used on embedded platforms, so
2945 * not supporting it shouldn't be a problem. If the same functionality
2946 * is needed on 64-bit platforms, a new ioctl() would have to be added,
2947 * so backwards-compatibility for the embedded platforms can be
2948 * maintained. --davidm 4-Feb-2004.
2949 */
2950 case RADEON_PARAM_SAREA_HANDLE:
2951 /* The lock is the first dword in the sarea. */
2952 value = (long)dev->lock.hw_lock;
2953 break;
2954#endif
2955 case RADEON_PARAM_GART_TEX_HANDLE:
2956 value = dev_priv->gart_textures_offset;
2957 break;
2977 /*
2978 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
2979 * pointer which can't fit into an int-sized variable. According to
2980 * Michel D��nzer, the ioctl() is only used on embedded platforms, so
2981 * not supporting it shouldn't be a problem. If the same functionality
2982 * is needed on 64-bit platforms, a new ioctl() would have to be added,
2983 * so backwards-compatibility for the embedded platforms can be
2984 * maintained. --davidm 4-Feb-2004.
2985 */
2986 case RADEON_PARAM_SAREA_HANDLE:
2987 /* The lock is the first dword in the sarea. */
2988 value = (long)dev->lock.hw_lock;
2989 break;
2990#endif
2991 case RADEON_PARAM_GART_TEX_HANDLE:
2992 value = dev_priv->gart_textures_offset;
2993 break;
2994
2995 case RADEON_PARAM_CARD_TYPE:
2996 if (dev_priv->flags & CHIP_IS_PCIE)
2997 value = RADEON_CARD_PCIE;
2998 else if (dev_priv->flags & CHIP_IS_AGP)
2999 value = RADEON_CARD_AGP;
3000 else
3001 value = RADEON_CARD_PCI;
3002 break;
2958 default:
2959 return DRM_ERR(EINVAL);
2960 }
2961
2962 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
2963 DRM_ERROR("copy_to_user\n");
2964 return DRM_ERR(EFAULT);
2965 }

--- 21 unchanged lines hidden (view full) ---

2987
2988 switch (sp.param) {
2989 case RADEON_SETPARAM_FB_LOCATION:
2990 radeon_priv = filp_priv->driver_priv;
2991 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value;
2992 break;
2993 case RADEON_SETPARAM_SWITCH_TILING:
2994 if (sp.value == 0) {
3003 default:
3004 return DRM_ERR(EINVAL);
3005 }
3006
3007 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
3008 DRM_ERROR("copy_to_user\n");
3009 return DRM_ERR(EFAULT);
3010 }

--- 21 unchanged lines hidden (view full) ---

3032
3033 switch (sp.param) {
3034 case RADEON_SETPARAM_FB_LOCATION:
3035 radeon_priv = filp_priv->driver_priv;
3036 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value;
3037 break;
3038 case RADEON_SETPARAM_SWITCH_TILING:
3039 if (sp.value == 0) {
2995 DRM_DEBUG( "color tiling disabled\n" );
3040 DRM_DEBUG("color tiling disabled\n");
2996 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
2997 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
2998 dev_priv->sarea_priv->tiling_enabled = 0;
3041 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3042 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3043 dev_priv->sarea_priv->tiling_enabled = 0;
2999 }
3000 else if (sp.value == 1) {
3001 DRM_DEBUG( "color tiling enabled\n" );
3044 } else if (sp.value == 1) {
3045 DRM_DEBUG("color tiling enabled\n");
3002 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3003 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
3004 dev_priv->sarea_priv->tiling_enabled = 1;
3005 }
3006 break;
3007 case RADEON_SETPARAM_PCIGART_LOCATION:
3008 dev_priv->pcigart_offset = sp.value;
3009 break;
3046 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3047 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
3048 dev_priv->sarea_priv->tiling_enabled = 1;
3049 }
3050 break;
3051 case RADEON_SETPARAM_PCIGART_LOCATION:
3052 dev_priv->pcigart_offset = sp.value;
3053 break;
3054 case RADEON_SETPARAM_NEW_MEMMAP:
3055 dev_priv->new_memmap = sp.value;
3056 break;
3010 default:
3011 DRM_DEBUG("Invalid parameter %d\n", sp.param);
3012 return DRM_ERR(EINVAL);
3013 }
3014
3015 return 0;
3016}
3017

--- 86 unchanged lines hidden --- 		3057 default:
3058 DRM_DEBUG("Invalid parameter %d\n", sp.param);
3059 return DRM_ERR(EINVAL);
3060 }
3061
3062 return 0;
3063}
3064

--- 86 unchanged lines hidden ---