radeon_drv.h (152909) | radeon_drv.h (157617) |
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1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), --- 15 unchanged lines hidden (view full) --- 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h> | 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), --- 15 unchanged lines hidden (view full) --- 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h> |
32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 152909 2005-11-28 23:13:57Z anholt $"); | 32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 157617 2006-04-09 20:45:45Z anholt $"); |
33 34#ifndef __RADEON_DRV_H__ 35#define __RADEON_DRV_H__ 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42#define DRIVER_NAME "radeon" 43#define DRIVER_DESC "ATI Radeon" | 33 34#ifndef __RADEON_DRV_H__ 35#define __RADEON_DRV_H__ 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42#define DRIVER_NAME "radeon" 43#define DRIVER_DESC "ATI Radeon" |
44#define DRIVER_DATE "20050911" | 44#define DRIVER_DATE "20060225" |
45 46/* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) --- 28 unchanged lines hidden (view full) --- 81 * - Add hyperz support, add hyperz flags to clear ioctl. 82 * 1.14- Add support for color tiling 83 * - Add R100/R200 surface allocation/free support 84 * 1.15- Add support for texture micro tiling 85 * - Add support for r100 cube maps 86 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87 * texture filtering on r200 88 * 1.17- Add initial support for R300 (3D). | 45 46/* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) --- 28 unchanged lines hidden (view full) --- 81 * - Add hyperz support, add hyperz flags to clear ioctl. 82 * 1.14- Add support for color tiling 83 * - Add R100/R200 surface allocation/free support 84 * 1.15- Add support for texture micro tiling 85 * - Add support for r100 cube maps 86 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87 * texture filtering on r200 88 * 1.17- Add initial support for R300 (3D). |
89 * 1.18- Add support for GL_ATI_fragment_shader, new packets R200_EMIT_PP_AFS_0/1, 90 R200_EMIT_PP_TXCTLALL_0-5 (replaces R200_EMIT_PP_TXFILTER_0-5, 2 more regs) 91 and R200_EMIT_ATF_TFACTOR (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) | 89 * 1.18- Add support for GL_ATI_fragment_shader, new packets 90 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) |
92 * 1.19- Add support for gart table in FB memory and PCIE r300 | 93 * 1.19- Add support for gart table in FB memory and PCIE r300 |
94 * 1.20- Add support for r300 texrect 95 * 1.21- Add support for card type getparam 96 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97 * 1.23- Add new radeon memory map work from benh 98 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) |
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93 */ 94 95#define DRIVER_MAJOR 1 | 99 */ 100 101#define DRIVER_MAJOR 1 |
96#define DRIVER_MINOR 19 | 102#define DRIVER_MINOR 24 |
97#define DRIVER_PATCHLEVEL 0 98 | 103#define DRIVER_PATCHLEVEL 0 104 |
105/* 106 * Radeon chip families 107 */ |
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99enum radeon_family { 100 CHIP_R100, | 108enum radeon_family { 109 CHIP_R100, |
101 CHIP_RS100, | |
102 CHIP_RV100, | 110 CHIP_RV100, |
111 CHIP_RS100, |
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103 CHIP_RV200, | 112 CHIP_RV200, |
104 CHIP_R200, | |
105 CHIP_RS200, | 113 CHIP_RS200, |
106 CHIP_R250, 107 CHIP_RS250, | 114 CHIP_R200, |
108 CHIP_RV250, | 115 CHIP_RV250, |
116 CHIP_RS300, |
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109 CHIP_RV280, 110 CHIP_R300, | 117 CHIP_RV280, 118 CHIP_R300, |
111 CHIP_RS300, | |
112 CHIP_R350, 113 CHIP_RV350, | 119 CHIP_R350, 120 CHIP_RV350, |
121 CHIP_RV380, |
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114 CHIP_R420, | 122 CHIP_R420, |
123 CHIP_RV410, 124 CHIP_RS400, |
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115 CHIP_LAST, 116}; 117 118enum radeon_cp_microcode_version { 119 UCODE_R100, 120 UCODE_R200, 121 UCODE_R300, 122}; 123 124/* 125 * Chip flags 126 */ 127enum radeon_chip_flags { 128 CHIP_FAMILY_MASK = 0x0000ffffUL, 129 CHIP_FLAGS_MASK = 0xffff0000UL, 130 CHIP_IS_MOBILITY = 0x00010000UL, 131 CHIP_IS_IGP = 0x00020000UL, 132 CHIP_SINGLE_CRTC = 0x00040000UL, 133 CHIP_IS_AGP = 0x00080000UL, | 125 CHIP_LAST, 126}; 127 128enum radeon_cp_microcode_version { 129 UCODE_R100, 130 UCODE_R200, 131 UCODE_R300, 132}; 133 134/* 135 * Chip flags 136 */ 137enum radeon_chip_flags { 138 CHIP_FAMILY_MASK = 0x0000ffffUL, 139 CHIP_FLAGS_MASK = 0xffff0000UL, 140 CHIP_IS_MOBILITY = 0x00010000UL, 141 CHIP_IS_IGP = 0x00020000UL, 142 CHIP_SINGLE_CRTC = 0x00040000UL, 143 CHIP_IS_AGP = 0x00080000UL, |
134 CHIP_HAS_HIERZ = 0x00100000UL, | 144 CHIP_HAS_HIERZ = 0x00100000UL, |
135 CHIP_IS_PCIE = 0x00200000UL, | 145 CHIP_IS_PCIE = 0x00200000UL, |
146 CHIP_NEW_MEMMAP = 0x00400000UL, |
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136}; 137 | 147}; 148 |
138#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) | 149#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ 150 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) |
139#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 140 141typedef struct drm_radeon_freelist { 142 unsigned int age; 143 drm_buf_t *buf; 144 struct drm_radeon_freelist *next; 145 struct drm_radeon_freelist *prev; 146} drm_radeon_freelist_t; --- 45 unchanged lines hidden (view full) --- 192}; 193 194typedef struct drm_radeon_private { 195 196 drm_radeon_ring_buffer_t ring; 197 drm_radeon_sarea_t *sarea_priv; 198 199 u32 fb_location; | 151#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 152 153typedef struct drm_radeon_freelist { 154 unsigned int age; 155 drm_buf_t *buf; 156 struct drm_radeon_freelist *next; 157 struct drm_radeon_freelist *prev; 158} drm_radeon_freelist_t; --- 45 unchanged lines hidden (view full) --- 204}; 205 206typedef struct drm_radeon_private { 207 208 drm_radeon_ring_buffer_t ring; 209 drm_radeon_sarea_t *sarea_priv; 210 211 u32 fb_location; |
212 u32 fb_size; 213 int new_memmap; |
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200 201 int gart_size; 202 u32 gart_vm_start; 203 unsigned long gart_buffers_offset; 204 205 int cp_mode; 206 int cp_running; 207 --- 56 unchanged lines hidden (view full) --- 264 wait_queue_head_t swi_queue; 265 atomic_t swi_emitted; 266 267 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 268 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; 269 270 unsigned long pcigart_offset; 271 drm_ati_pcigart_info gart_info; | 214 215 int gart_size; 216 u32 gart_vm_start; 217 unsigned long gart_buffers_offset; 218 219 int cp_mode; 220 int cp_running; 221 --- 56 unchanged lines hidden (view full) --- 278 wait_queue_head_t swi_queue; 279 atomic_t swi_emitted; 280 281 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 282 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; 283 284 unsigned long pcigart_offset; 285 drm_ati_pcigart_info gart_info; |
286 287 u32 scratch_ages[5]; 288 |
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272 /* starting from here on, data is preserved accross an open */ 273 uint32_t flags; /* see radeon_chip_flags */ 274 275} drm_radeon_private_t; 276 277typedef struct drm_radeon_buf_priv { 278 u32 age; 279} drm_radeon_buf_priv_t; 280 | 289 /* starting from here on, data is preserved accross an open */ 290 uint32_t flags; /* see radeon_chip_flags */ 291 292} drm_radeon_private_t; 293 294typedef struct drm_radeon_buf_priv { 295 u32 age; 296} drm_radeon_buf_priv_t; 297 |
298typedef struct drm_radeon_kcmd_buffer { 299 int bufsz; 300 char *buf; 301 int nbox; 302 drm_clip_rect_t __user *boxes; 303} drm_radeon_kcmd_buffer_t; 304 |
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281extern int radeon_no_wb; 282extern drm_ioctl_desc_t radeon_ioctls[]; 283extern int radeon_max_ioctl; 284 285 /* radeon_cp.c */ 286extern int radeon_cp_init(DRM_IOCTL_ARGS); 287extern int radeon_cp_start(DRM_IOCTL_ARGS); 288extern int radeon_cp_stop(DRM_IOCTL_ARGS); --- 37 unchanged lines hidden (view full) --- 326extern void radeon_driver_lastclose(drm_device_t * dev); 327extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv); 328extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 329 unsigned long arg); 330 331/* r300_cmdbuf.c */ 332extern void r300_init_reg_flags(void); 333 | 305extern int radeon_no_wb; 306extern drm_ioctl_desc_t radeon_ioctls[]; 307extern int radeon_max_ioctl; 308 309 /* radeon_cp.c */ 310extern int radeon_cp_init(DRM_IOCTL_ARGS); 311extern int radeon_cp_start(DRM_IOCTL_ARGS); 312extern int radeon_cp_stop(DRM_IOCTL_ARGS); --- 37 unchanged lines hidden (view full) --- 350extern void radeon_driver_lastclose(drm_device_t * dev); 351extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv); 352extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 353 unsigned long arg); 354 355/* r300_cmdbuf.c */ 356extern void r300_init_reg_flags(void); 357 |
334extern int r300_do_cp_cmdbuf( drm_device_t* dev, 335 DRMFILE filp, 336 drm_file_t* filp_priv, 337 drm_radeon_cmd_buffer_t* cmdbuf ); | 358extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, 359 drm_file_t* filp_priv, 360 drm_radeon_kcmd_buffer_t* cmdbuf); |
338 339/* Flags for stats.boxes 340 */ 341#define RADEON_BOX_DMA_IDLE 0x1 342#define RADEON_BOX_RING_FULL 0x2 343#define RADEON_BOX_FLIP 0x4 344#define RADEON_BOX_WAIT_IDLE 0x8 345#define RADEON_BOX_TEXTURE_LOAD 0x10 346 347/* Register definitions, register access macros and drmAddMap constants 348 * for Radeon kernel driver. 349 */ 350#define RADEON_AGP_COMMAND 0x0f60 351#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 352# define RADEON_AGP_ENABLE (1<<8) | 361 362/* Flags for stats.boxes 363 */ 364#define RADEON_BOX_DMA_IDLE 0x1 365#define RADEON_BOX_RING_FULL 0x2 366#define RADEON_BOX_FLIP 0x4 367#define RADEON_BOX_WAIT_IDLE 0x8 368#define RADEON_BOX_TEXTURE_LOAD 0x10 369 370/* Register definitions, register access macros and drmAddMap constants 371 * for Radeon kernel driver. 372 */ 373#define RADEON_AGP_COMMAND 0x0f60 374#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 375# define RADEON_AGP_ENABLE (1<<8) |
353 | |
354#define RADEON_AUX_SCISSOR_CNTL 0x26f0 355# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 356# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 357# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 358# define RADEON_SCISSOR_0_ENABLE (1 << 28) 359# define RADEON_SCISSOR_1_ENABLE (1 << 29) 360# define RADEON_SCISSOR_2_ENABLE (1 << 30) 361 362#define RADEON_BUS_CNTL 0x0030 363# define RADEON_BUS_MASTER_DIS (1 << 6) 364 365#define RADEON_CLOCK_CNTL_DATA 0x000c 366# define RADEON_PLL_WR_EN (1 << 7) 367#define RADEON_CLOCK_CNTL_INDEX 0x0008 368#define RADEON_CONFIG_APER_SIZE 0x0108 | 376#define RADEON_AUX_SCISSOR_CNTL 0x26f0 377# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 378# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 379# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 380# define RADEON_SCISSOR_0_ENABLE (1 << 28) 381# define RADEON_SCISSOR_1_ENABLE (1 << 29) 382# define RADEON_SCISSOR_2_ENABLE (1 << 30) 383 384#define RADEON_BUS_CNTL 0x0030 385# define RADEON_BUS_MASTER_DIS (1 << 6) 386 387#define RADEON_CLOCK_CNTL_DATA 0x000c 388# define RADEON_PLL_WR_EN (1 << 7) 389#define RADEON_CLOCK_CNTL_INDEX 0x0008 390#define RADEON_CONFIG_APER_SIZE 0x0108 |
391#define RADEON_CONFIG_MEMSIZE 0x00f8 |
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369#define RADEON_CRTC_OFFSET 0x0224 370#define RADEON_CRTC_OFFSET_CNTL 0x0228 371# define RADEON_CRTC_TILE_EN (1 << 15) 372# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 373#define RADEON_CRTC2_OFFSET 0x0324 374#define RADEON_CRTC2_OFFSET_CNTL 0x0328 375 376#define RADEON_PCIE_INDEX 0x0030 --- 758 unchanged lines hidden --- | 392#define RADEON_CRTC_OFFSET 0x0224 393#define RADEON_CRTC_OFFSET_CNTL 0x0228 394# define RADEON_CRTC_TILE_EN (1 << 15) 395# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 396#define RADEON_CRTC2_OFFSET 0x0324 397#define RADEON_CRTC2_OFFSET_CNTL 0x0328 398 399#define RADEON_PCIE_INDEX 0x0030 --- 758 unchanged lines hidden --- |