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radeon_cp.c (152909) radeon_cp.c (157617)
1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),

--- 15 unchanged lines hidden (view full) ---

24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#include <sys/cdefs.h>
1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),

--- 15 unchanged lines hidden (view full) ---

24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_cp.c 152909 2005-11-28 23:13:57Z anholt $");
32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_cp.c 157617 2006-04-09 20:45:45Z anholt $");
33
34#include "dev/drm/drmP.h"
35#include "dev/drm/drm.h"
36#include "dev/drm/radeon_drm.h"
37#include "dev/drm/radeon_drv.h"
38#include "dev/drm/r300_reg.h"
39
40#define RADEON_FIFO_DEBUG 0

--- 901 unchanged lines hidden (view full) ---

942{
943 int i;
944 DRM_DEBUG("\n");
945
946 radeon_do_wait_for_idle(dev_priv);
947
948 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
949
33
34#include "dev/drm/drmP.h"
35#include "dev/drm/drm.h"
36#include "dev/drm/radeon_drm.h"
37#include "dev/drm/radeon_drv.h"
38#include "dev/drm/r300_reg.h"
39
40#define RADEON_FIFO_DEBUG 0

--- 901 unchanged lines hidden (view full) ---

942{
943 int i;
944 DRM_DEBUG("\n");
945
946 radeon_do_wait_for_idle(dev_priv);
947
948 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
949
950 if (dev_priv->microcode_version==UCODE_R200) {
950 if (dev_priv->microcode_version == UCODE_R200) {
951 DRM_INFO("Loading R200 Microcode\n");
952 for (i = 0; i < 256; i++) {
953 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
954 R200_cp_microcode[i][1]);
955 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
956 R200_cp_microcode[i][0]);
957 }
951 DRM_INFO("Loading R200 Microcode\n");
952 for (i = 0; i < 256; i++) {
953 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
954 R200_cp_microcode[i][1]);
955 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
956 R200_cp_microcode[i][0]);
957 }
958 } else if (dev_priv->microcode_version==UCODE_R300) {
958 } else if (dev_priv->microcode_version == UCODE_R300) {
959 DRM_INFO("Loading R300 Microcode\n");
959 DRM_INFO("Loading R300 Microcode\n");
960 for ( i = 0 ; i < 256 ; i++ ) {
961 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
962 R300_cp_microcode[i][1] );
963 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
964 R300_cp_microcode[i][0] );
960 for (i = 0; i < 256; i++) {
961 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
962 R300_cp_microcode[i][1]);
963 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
964 R300_cp_microcode[i][0]);
965 }
966 } else {
967 for (i = 0; i < 256; i++) {
968 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
969 radeon_cp_microcode[i][1]);
970 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
971 radeon_cp_microcode[i][0]);
972 }

--- 143 unchanged lines hidden (view full) ---

1116 return 0;
1117}
1118
1119static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1120 drm_radeon_private_t * dev_priv)
1121{
1122 u32 ring_start, cur_read_ptr;
1123 u32 tmp;
965 }
966 } else {
967 for (i = 0; i < 256; i++) {
968 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
969 radeon_cp_microcode[i][1]);
970 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
971 radeon_cp_microcode[i][0]);
972 }

--- 143 unchanged lines hidden (view full) ---

1116 return 0;
1117}
1118
1119static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1120 drm_radeon_private_t * dev_priv)
1121{
1122 u32 ring_start, cur_read_ptr;
1123 u32 tmp;
1124
1125 /* Initialize the memory controller. With new memory map, the fb location
1126 * is not changed, it should have been properly initialized already. Part
1127 * of the problem is that the code below is bogus, assuming the GART is
1128 * always appended to the fb which is not necessarily the case
1129 */
1130 if (!dev_priv->new_memmap)
1131 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1132 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1133 | (dev_priv->fb_location >> 16));
1124
1134
1125 /* Initialize the memory controller */
1126 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1127 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1128 | (dev_priv->fb_location >> 16));
1129
1130#if __OS_HAS_AGP
1131 if (dev_priv->flags & CHIP_IS_AGP) {
1135#if __OS_HAS_AGP
1136 if (dev_priv->flags & CHIP_IS_AGP) {
1137 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1132 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1133 (((dev_priv->gart_vm_start - 1 +
1134 dev_priv->gart_size) & 0xffff0000) |
1135 (dev_priv->gart_vm_start >> 16)));
1136
1137 ring_start = (dev_priv->cp_ring->offset
1138 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1139 (((dev_priv->gart_vm_start - 1 +
1140 dev_priv->gart_size) & 0xffff0000) |
1141 (dev_priv->gart_vm_start >> 16)));
1142
1143 ring_start = (dev_priv->cp_ring->offset
1138 - dev->agp->base + dev_priv->gart_vm_start);
1144 - dev->agp->base
1145 + dev_priv->gart_vm_start);
1139 } else
1140#endif
1141 ring_start = (dev_priv->cp_ring->offset
1146 } else
1147#endif
1148 ring_start = (dev_priv->cp_ring->offset
1142 - (unsigned long)dev->sg->virtual + dev_priv->gart_vm_start);
1149 - (unsigned long)dev->sg->virtual
1150 + dev_priv->gart_vm_start);
1143
1151
1144
1145 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1146
1147 /* Set the write pointer delay */
1148 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1149
1150 /* Initialize the ring buffer's read and write pointers */
1151 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1152 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1153 SET_RING_HEAD(dev_priv, cur_read_ptr);
1154 dev_priv->ring.tail = cur_read_ptr;
1155
1156#if __OS_HAS_AGP
1157 if (dev_priv->flags & CHIP_IS_AGP) {
1152 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1153
1154 /* Set the write pointer delay */
1155 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1156
1157 /* Initialize the ring buffer's read and write pointers */
1158 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1159 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1160 SET_RING_HEAD(dev_priv, cur_read_ptr);
1161 dev_priv->ring.tail = cur_read_ptr;
1162
1163#if __OS_HAS_AGP
1164 if (dev_priv->flags & CHIP_IS_AGP) {
1158 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1159 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1160 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1161 dev_priv->ring_rptr->offset
1162 - dev->agp->base + dev_priv->gart_vm_start);
1163 } else
1164#endif
1165 {
1166 drm_sg_mem_t *entry = dev->sg;
1167 unsigned long tmp_ofs, page_ofs;
1168
1165 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1166 dev_priv->ring_rptr->offset
1167 - dev->agp->base + dev_priv->gart_vm_start);
1168 } else
1169#endif
1170 {
1171 drm_sg_mem_t *entry = dev->sg;
1172 unsigned long tmp_ofs, page_ofs;
1173
1169 tmp_ofs = dev_priv->ring_rptr->offset - (unsigned long)dev->sg->virtual;
1174 tmp_ofs = dev_priv->ring_rptr->offset -
1175 (unsigned long)dev->sg->virtual;
1170 page_ofs = tmp_ofs >> PAGE_SHIFT;
1171
1172 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1173 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1174 (unsigned long)entry->busaddr[page_ofs],
1175 entry->handle + tmp_ofs);
1176 }
1177
1176 page_ofs = tmp_ofs >> PAGE_SHIFT;
1177
1178 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1179 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1180 (unsigned long)entry->busaddr[page_ofs],
1181 entry->handle + tmp_ofs);
1182 }
1183
1184 /* Set ring buffer size */
1185#ifdef __BIG_ENDIAN
1186 RADEON_WRITE(RADEON_CP_RB_CNTL,
1187 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1188#else
1189 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1190#endif
1191
1192 /* Start with assuming that writeback doesn't work */
1193 dev_priv->writeback_works = 0;
1194
1178 /* Initialize the scratch register pointer. This will cause
1179 * the scratch register values to be written out to memory
1180 * whenever they are updated.
1181 *
1182 * We simply put this behind the ring read pointer, this works
1183 * with PCI GART as well as (whatever kind of) AGP GART
1184 */
1185 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1186 + RADEON_SCRATCH_REG_OFFSET);
1187
1188 dev_priv->scratch = ((__volatile__ u32 *)
1189 dev_priv->ring_rptr->handle +
1190 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1191
1192 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1193
1195 /* Initialize the scratch register pointer. This will cause
1196 * the scratch register values to be written out to memory
1197 * whenever they are updated.
1198 *
1199 * We simply put this behind the ring read pointer, this works
1200 * with PCI GART as well as (whatever kind of) AGP GART
1201 */
1202 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1203 + RADEON_SCRATCH_REG_OFFSET);
1204
1205 dev_priv->scratch = ((__volatile__ u32 *)
1206 dev_priv->ring_rptr->handle +
1207 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1208
1209 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1210
1194 /* Writeback doesn't seem to work everywhere, test it first */
1195 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1196 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1211 /* Turn on bus mastering */
1212 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1213 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1197
1214
1198 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1199 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1200 0xdeadbeef)
1201 break;
1202 DRM_UDELAY(1);
1203 }
1204
1205 if (tmp < dev_priv->usec_timeout) {
1206 dev_priv->writeback_works = 1;
1207 DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp);
1208 } else {
1209 dev_priv->writeback_works = 0;
1210 DRM_DEBUG("writeback test failed\n");
1211 }
1212 if (radeon_no_wb == 1) {
1213 dev_priv->writeback_works = 0;
1214 DRM_DEBUG("writeback forced off\n");
1215 }
1216
1217 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1218 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1219
1220 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1221 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1222 dev_priv->sarea_priv->last_dispatch);
1223
1224 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1225 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1226
1215 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1216 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1217
1218 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1219 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1220 dev_priv->sarea_priv->last_dispatch);
1221
1222 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1223 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1224
1227 /* Set ring buffer size */
1228#ifdef __BIG_ENDIAN
1229 RADEON_WRITE(RADEON_CP_RB_CNTL,
1230 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1231#else
1232 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1233#endif
1234
1235 radeon_do_wait_for_idle(dev_priv);
1236
1225 radeon_do_wait_for_idle(dev_priv);
1226
1237 /* Turn on bus mastering */
1238 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1239 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1240
1241 /* Sync everything up */
1242 RADEON_WRITE(RADEON_ISYNC_CNTL,
1243 (RADEON_ISYNC_ANY2D_IDLE3D |
1244 RADEON_ISYNC_ANY3D_IDLE2D |
1245 RADEON_ISYNC_WAIT_IDLEGUI |
1246 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1227 /* Sync everything up */
1228 RADEON_WRITE(RADEON_ISYNC_CNTL,
1229 (RADEON_ISYNC_ANY2D_IDLE3D |
1230 RADEON_ISYNC_ANY3D_IDLE2D |
1231 RADEON_ISYNC_WAIT_IDLEGUI |
1232 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1233
1247}
1248
1234}
1235
1236static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1237{
1238 u32 tmp;
1239
1240 /* Writeback doesn't seem to work everywhere, test it here and possibly
1241 * enable it if it appears to work
1242 */
1243 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1244 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1245
1246 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1247 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1248 0xdeadbeef)
1249 break;
1250 DRM_UDELAY(1);
1251 }
1252
1253 if (tmp < dev_priv->usec_timeout) {
1254 dev_priv->writeback_works = 1;
1255 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
1256 } else {
1257 dev_priv->writeback_works = 0;
1258 DRM_INFO("writeback test failed\n");
1259 }
1260 if (radeon_no_wb == 1) {
1261 dev_priv->writeback_works = 0;
1262 DRM_INFO("writeback forced off\n");
1263 }
1264}
1265
1249/* Enable or disable PCI-E GART on the chip */
1250static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1251{
1252 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1253 if (on) {
1254
1255 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1266/* Enable or disable PCI-E GART on the chip */
1267static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1268{
1269 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1270 if (on) {
1271
1272 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1256 dev_priv->gart_vm_start, (long)dev_priv->gart_info.bus_addr,
1273 dev_priv->gart_vm_start,
1274 (long)dev_priv->gart_info.bus_addr,
1257 dev_priv->gart_size);
1275 dev_priv->gart_size);
1258 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, dev_priv->gart_vm_start);
1259 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, dev_priv->gart_info.bus_addr);
1260 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, dev_priv->gart_vm_start);
1261 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, dev_priv->gart_vm_start
1262 + dev_priv->gart_size - 1);
1276 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1277 dev_priv->gart_vm_start);
1278 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1279 dev_priv->gart_info.bus_addr);
1280 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1281 dev_priv->gart_vm_start);
1282 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1283 dev_priv->gart_vm_start +
1284 dev_priv->gart_size - 1);
1263
1264 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1265
1285
1286 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1287
1266 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, RADEON_PCIE_TX_GART_EN);
1288 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1289 RADEON_PCIE_TX_GART_EN);
1267 } else {
1290 } else {
1268 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, (tmp & ~RADEON_PCIE_TX_GART_EN) | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
1291 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1292 tmp & ~RADEON_PCIE_TX_GART_EN);
1269 }
1270}
1271
1272/* Enable or disable PCI GART on the chip */
1273static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1274{
1275 u32 tmp;
1276
1293 }
1294}
1295
1296/* Enable or disable PCI GART on the chip */
1297static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1298{
1299 u32 tmp;
1300
1277 if (dev_priv->flags & CHIP_IS_PCIE)
1278 {
1301 if (dev_priv->flags & CHIP_IS_PCIE) {
1279 radeon_set_pciegart(dev_priv, on);
1280 return;
1281 }
1282
1283 tmp = RADEON_READ(RADEON_AIC_CNTL);
1284
1285 if (on) {
1286 RADEON_WRITE(RADEON_AIC_CNTL,

--- 17 unchanged lines hidden (view full) ---

1304 RADEON_WRITE(RADEON_AIC_CNTL,
1305 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1306 }
1307}
1308
1309static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1310{
1311 drm_radeon_private_t *dev_priv = dev->dev_private;
1302 radeon_set_pciegart(dev_priv, on);
1303 return;
1304 }
1305
1306 tmp = RADEON_READ(RADEON_AIC_CNTL);
1307
1308 if (on) {
1309 RADEON_WRITE(RADEON_AIC_CNTL,

--- 17 unchanged lines hidden (view full) ---

1327 RADEON_WRITE(RADEON_AIC_CNTL,
1328 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1329 }
1330}
1331
1332static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1333{
1334 drm_radeon_private_t *dev_priv = dev->dev_private;
1335
1312 DRM_DEBUG("\n");
1313
1336 DRM_DEBUG("\n");
1337
1338 /* if we require new memory map but we don't have it fail */
1339 if ((dev_priv->flags & CHIP_NEW_MEMMAP) && !dev_priv->new_memmap)
1340 {
1341 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1342 radeon_do_cleanup_cp(dev);
1343 return DRM_ERR(EINVAL);
1344 }
1345
1314 if (init->is_pci && (dev_priv->flags & CHIP_IS_AGP))
1315 {
1316 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1317 dev_priv->flags &= ~CHIP_IS_AGP;
1318 }
1319
1320 if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) {
1321 DRM_ERROR("PCI GART memory not allocated!\n");

--- 6 unchanged lines hidden (view full) ---

1328 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1329 DRM_DEBUG("TIMEOUT problem!\n");
1330 radeon_do_cleanup_cp(dev);
1331 return DRM_ERR(EINVAL);
1332 }
1333
1334 switch(init->func) {
1335 case RADEON_INIT_R200_CP:
1346 if (init->is_pci && (dev_priv->flags & CHIP_IS_AGP))
1347 {
1348 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1349 dev_priv->flags &= ~CHIP_IS_AGP;
1350 }
1351
1352 if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) {
1353 DRM_ERROR("PCI GART memory not allocated!\n");

--- 6 unchanged lines hidden (view full) ---

1360 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1361 DRM_DEBUG("TIMEOUT problem!\n");
1362 radeon_do_cleanup_cp(dev);
1363 return DRM_ERR(EINVAL);
1364 }
1365
1366 switch(init->func) {
1367 case RADEON_INIT_R200_CP:
1336 dev_priv->microcode_version=UCODE_R200;
1368 dev_priv->microcode_version = UCODE_R200;
1337 break;
1338 case RADEON_INIT_R300_CP:
1369 break;
1370 case RADEON_INIT_R300_CP:
1339 dev_priv->microcode_version=UCODE_R300;
1371 dev_priv->microcode_version = UCODE_R300;
1340 break;
1341 default:
1372 break;
1373 default:
1342 dev_priv->microcode_version=UCODE_R100;
1343 break;
1374 dev_priv->microcode_version = UCODE_R100;
1344 }
1345
1346 dev_priv->do_boxes = 0;
1347 dev_priv->cp_mode = init->cp_mode;
1348
1349 /* We don't support anything other than bus-mastering ring mode,
1350 * but the ring can be in either AGP or PCI space for the ring
1351 * read pointer.

--- 33 unchanged lines hidden (view full) ---

1385
1386 /* Hardware state for depth clears. Remove this if/when we no
1387 * longer clear the depth buffer with a 3D rectangle. Hard-code
1388 * all values to prevent unwanted 3D state from slipping through
1389 * and screwing with the clear operation.
1390 */
1391 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1392 (dev_priv->color_fmt << 10) |
1375 }
1376
1377 dev_priv->do_boxes = 0;
1378 dev_priv->cp_mode = init->cp_mode;
1379
1380 /* We don't support anything other than bus-mastering ring mode,
1381 * but the ring can be in either AGP or PCI space for the ring
1382 * read pointer.

--- 33 unchanged lines hidden (view full) ---

1416
1417 /* Hardware state for depth clears. Remove this if/when we no
1418 * longer clear the depth buffer with a 3D rectangle. Hard-code
1419 * all values to prevent unwanted 3D state from slipping through
1420 * and screwing with the clear operation.
1421 */
1422 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1423 (dev_priv->color_fmt << 10) |
1393 (dev_priv->microcode_version == UCODE_R100 ?
1394 RADEON_ZBLOCK16 : 0));
1424 (dev_priv->microcode_version ==
1425 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1395
1396 dev_priv->depth_clear.rb3d_zstencilcntl =
1397 (dev_priv->depth_fmt |
1398 RADEON_Z_TEST_ALWAYS |
1399 RADEON_STENCIL_TEST_ALWAYS |
1400 RADEON_STENCIL_S_FAIL_REPLACE |
1401 RADEON_STENCIL_ZPASS_REPLACE |
1402 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);

--- 83 unchanged lines hidden (view full) ---

1486 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1487 dev_priv->ring_rptr->handle);
1488 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1489 dev->agp_buffer_map->handle);
1490 }
1491
1492 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1493 & 0xffff) << 16;
1426
1427 dev_priv->depth_clear.rb3d_zstencilcntl =
1428 (dev_priv->depth_fmt |
1429 RADEON_Z_TEST_ALWAYS |
1430 RADEON_STENCIL_TEST_ALWAYS |
1431 RADEON_STENCIL_S_FAIL_REPLACE |
1432 RADEON_STENCIL_ZPASS_REPLACE |
1433 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);

--- 83 unchanged lines hidden (view full) ---

1517 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1518 dev_priv->ring_rptr->handle);
1519 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1520 dev->agp_buffer_map->handle);
1521 }
1522
1523 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1524 & 0xffff) << 16;
1525 dev_priv->fb_size =
1526 ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
1527 - dev_priv->fb_location;
1494
1495 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1496 ((dev_priv->front_offset
1497 + dev_priv->fb_location) >> 10));
1498
1499 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1500 ((dev_priv->back_offset
1501 + dev_priv->fb_location) >> 10));
1502
1503 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1504 ((dev_priv->depth_offset
1505 + dev_priv->fb_location) >> 10));
1506
1507 dev_priv->gart_size = init->gart_size;
1528
1529 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1530 ((dev_priv->front_offset
1531 + dev_priv->fb_location) >> 10));
1532
1533 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1534 ((dev_priv->back_offset
1535 + dev_priv->fb_location) >> 10));
1536
1537 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1538 ((dev_priv->depth_offset
1539 + dev_priv->fb_location) >> 10));
1540
1541 dev_priv->gart_size = init->gart_size;
1508 dev_priv->gart_vm_start = dev_priv->fb_location
1509 + RADEON_READ(RADEON_CONFIG_APER_SIZE);
1510
1542
1543 /* New let's set the memory map ... */
1544 if (dev_priv->new_memmap) {
1545 u32 base = 0;
1546
1547 DRM_INFO("Setting GART location based on new memory map\n");
1548
1549 /* If using AGP, try to locate the AGP aperture at the same
1550 * location in the card and on the bus, though we have to
1551 * align it down.
1552 */
1511#if __OS_HAS_AGP
1553#if __OS_HAS_AGP
1554 if (dev_priv->flags & CHIP_IS_AGP) {
1555 base = dev->agp->base;
1556 /* Check if valid */
1557 if ((base + dev_priv->gart_size) > dev_priv->fb_location &&
1558 base < (dev_priv->fb_location + dev_priv->fb_size)) {
1559 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1560 dev->agp->base);
1561 base = 0;
1562 }
1563 }
1564#endif
1565 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1566 if (base == 0) {
1567 base = dev_priv->fb_location + dev_priv->fb_size;
1568 if (((base + dev_priv->gart_size) & 0xfffffffful)
1569 < base)
1570 base = dev_priv->fb_location
1571 - dev_priv->gart_size;
1572 }
1573 dev_priv->gart_vm_start = base & 0xffc00000u;
1574 if (dev_priv->gart_vm_start != base)
1575 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1576 base, dev_priv->gart_vm_start);
1577 } else {
1578 DRM_INFO("Setting GART location based on old memory map\n");
1579 dev_priv->gart_vm_start = dev_priv->fb_location +
1580 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1581 }
1582
1583#if __OS_HAS_AGP
1512 if (dev_priv->flags & CHIP_IS_AGP)
1513 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1514 - dev->agp->base
1515 + dev_priv->gart_vm_start);
1516 else
1517#endif
1518 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1584 if (dev_priv->flags & CHIP_IS_AGP)
1585 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1586 - dev->agp->base
1587 + dev_priv->gart_vm_start);
1588 else
1589#endif
1590 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1519 - (unsigned long)dev->sg->virtual
1520 + dev_priv->gart_vm_start);
1591 - (unsigned long)dev->sg->virtual
1592 + dev_priv->gart_vm_start);
1521
1522 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1523 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1524 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1525 dev_priv->gart_buffers_offset);
1526
1527 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1528 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle

--- 9 unchanged lines hidden (view full) ---

1538 if (dev_priv->flags & CHIP_IS_AGP) {
1539 /* Turn off PCI GART */
1540 radeon_set_pcigart(dev_priv, 0);
1541 } else
1542#endif
1543 {
1544 /* if we have an offset set from userspace */
1545 if (dev_priv->pcigart_offset) {
1593
1594 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1595 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1596 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1597 dev_priv->gart_buffers_offset);
1598
1599 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1600 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle

--- 9 unchanged lines hidden (view full) ---

1610 if (dev_priv->flags & CHIP_IS_AGP) {
1611 /* Turn off PCI GART */
1612 radeon_set_pcigart(dev_priv, 0);
1613 } else
1614#endif
1615 {
1616 /* if we have an offset set from userspace */
1617 if (dev_priv->pcigart_offset) {
1546 dev_priv->gart_info.bus_addr = dev_priv->pcigart_offset + dev_priv->fb_location;
1547 dev_priv->gart_info.mapping.offset = dev_priv->gart_info.bus_addr;
1548 dev_priv->gart_info.mapping.size = RADEON_PCIGART_TABLE_SIZE;
1618 dev_priv->gart_info.bus_addr =
1619 dev_priv->pcigart_offset + dev_priv->fb_location;
1620 dev_priv->gart_info.mapping.offset =
1621 dev_priv->gart_info.bus_addr;
1622 dev_priv->gart_info.mapping.size =
1623 RADEON_PCIGART_TABLE_SIZE;
1624
1549 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1625 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1550 dev_priv->gart_info.addr = dev_priv->gart_info.mapping.handle;
1626 dev_priv->gart_info.addr =
1627 dev_priv->gart_info.mapping.handle;
1551
1628
1552 dev_priv->gart_info.is_pcie = !!(dev_priv->flags & CHIP_IS_PCIE);
1553 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_FB;
1554
1555 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", dev_priv->gart_info.addr, dev_priv->pcigart_offset);
1556 }
1557 else {
1558 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
1629 dev_priv->gart_info.is_pcie =
1630 !!(dev_priv->flags & CHIP_IS_PCIE);
1631 dev_priv->gart_info.gart_table_location =
1632 DRM_ATI_GART_FB;
1633
1634 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1635 dev_priv->gart_info.addr,
1636 dev_priv->pcigart_offset);
1637 } else {
1638 dev_priv->gart_info.gart_table_location =
1639 DRM_ATI_GART_MAIN;
1559 dev_priv->gart_info.addr = NULL;
1560 dev_priv->gart_info.bus_addr = 0;
1640 dev_priv->gart_info.addr = NULL;
1641 dev_priv->gart_info.bus_addr = 0;
1561 if (dev_priv->flags & CHIP_IS_PCIE)
1562 {
1563 DRM_ERROR("Cannot use PCI Express without GART in FB memory\n");
1642 if (dev_priv->flags & CHIP_IS_PCIE) {
1643 DRM_ERROR
1644 ("Cannot use PCI Express without GART in FB memory\n");
1564 radeon_do_cleanup_cp(dev);
1565 return DRM_ERR(EINVAL);
1566 }
1567 }
1568
1569 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1570 DRM_ERROR("failed to init PCI GART!\n");
1571 radeon_do_cleanup_cp(dev);

--- 5 unchanged lines hidden (view full) ---

1577 }
1578
1579 radeon_cp_load_microcode(dev_priv);
1580 radeon_cp_init_ring_buffer(dev, dev_priv);
1581
1582 dev_priv->last_buf = 0;
1583
1584 radeon_do_engine_reset(dev);
1645 radeon_do_cleanup_cp(dev);
1646 return DRM_ERR(EINVAL);
1647 }
1648 }
1649
1650 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1651 DRM_ERROR("failed to init PCI GART!\n");
1652 radeon_do_cleanup_cp(dev);

--- 5 unchanged lines hidden (view full) ---

1658 }
1659
1660 radeon_cp_load_microcode(dev_priv);
1661 radeon_cp_init_ring_buffer(dev, dev_priv);
1662
1663 dev_priv->last_buf = 0;
1664
1665 radeon_do_engine_reset(dev);
1666 radeon_test_writeback(dev_priv);
1585
1586 return 0;
1587}
1588
1589static int radeon_do_cleanup_cp(drm_device_t * dev)
1590{
1591 drm_radeon_private_t *dev_priv = dev->dev_private;
1592 DRM_DEBUG("\n");

--- 86 unchanged lines hidden (view full) ---

1679 DRM_DEVICE;
1680 drm_radeon_init_t init;
1681
1682 LOCK_TEST_WITH_RETURN(dev, filp);
1683
1684 DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1685 sizeof(init));
1686
1667
1668 return 0;
1669}
1670
1671static int radeon_do_cleanup_cp(drm_device_t * dev)
1672{
1673 drm_radeon_private_t *dev_priv = dev->dev_private;
1674 DRM_DEBUG("\n");

--- 86 unchanged lines hidden (view full) ---

1761 DRM_DEVICE;
1762 drm_radeon_init_t init;
1763
1764 LOCK_TEST_WITH_RETURN(dev, filp);
1765
1766 DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1767 sizeof(init));
1768
1687 if(init.func == RADEON_INIT_R300_CP)
1769 if (init.func == RADEON_INIT_R300_CP)
1688 r300_init_reg_flags();
1770 r300_init_reg_flags();
1689
1771
1690 switch (init.func) {
1691 case RADEON_INIT_CP:
1692 case RADEON_INIT_R200_CP:
1693 case RADEON_INIT_R300_CP:
1694 return radeon_do_init_cp(dev, &init);
1695 case RADEON_CLEANUP_CP:
1696 return radeon_do_cleanup_cp(dev);
1697 }

--- 72 unchanged lines hidden (view full) ---

1770}
1771
1772void radeon_do_release(drm_device_t * dev)
1773{
1774 drm_radeon_private_t *dev_priv = dev->dev_private;
1775 int i, ret;
1776
1777 if (dev_priv) {
1772 switch (init.func) {
1773 case RADEON_INIT_CP:
1774 case RADEON_INIT_R200_CP:
1775 case RADEON_INIT_R300_CP:
1776 return radeon_do_init_cp(dev, &init);
1777 case RADEON_CLEANUP_CP:
1778 return radeon_do_cleanup_cp(dev);
1779 }

--- 72 unchanged lines hidden (view full) ---

1852}
1853
1854void radeon_do_release(drm_device_t * dev)
1855{
1856 drm_radeon_private_t *dev_priv = dev->dev_private;
1857 int i, ret;
1858
1859 if (dev_priv) {
1778
1779 if (dev_priv->cp_running) {
1780 /* Stop the cp */
1781 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1782 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1783#ifdef __linux__
1784 schedule();
1785#else
1786#if defined(__FreeBSD__) && __FreeBSD_version > 500000

--- 7 unchanged lines hidden (view full) ---

1794 radeon_do_cp_stop(dev_priv);
1795 radeon_do_engine_reset(dev);
1796 }
1797
1798 /* Disable *all* interrupts */
1799 if (dev_priv->mmio) /* remove this after permanent addmaps */
1800 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1801
1860 if (dev_priv->cp_running) {
1861 /* Stop the cp */
1862 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1863 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1864#ifdef __linux__
1865 schedule();
1866#else
1867#if defined(__FreeBSD__) && __FreeBSD_version > 500000

--- 7 unchanged lines hidden (view full) ---

1875 radeon_do_cp_stop(dev_priv);
1876 radeon_do_engine_reset(dev);
1877 }
1878
1879 /* Disable *all* interrupts */
1880 if (dev_priv->mmio) /* remove this after permanent addmaps */
1881 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1882
1802 if (dev_priv->mmio) {/* remove all surfaces */
1883 if (dev_priv->mmio) { /* remove all surfaces */
1803 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1884 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1804 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0);
1805 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0);
1806 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0);
1885 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1886 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1887 16 * i, 0);
1888 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1889 16 * i, 0);
1807 }
1808 }
1809
1810 /* Free memory heap structures */
1811 radeon_mem_takedown(&(dev_priv->gart_heap));
1812 radeon_mem_takedown(&(dev_priv->fb_heap));
1813
1814 /* deallocate kernel resources */

--- 287 unchanged lines hidden (view full) ---

2102 dev->dev_private = (void *)dev_priv;
2103 dev_priv->flags = flags;
2104
2105 switch (flags & CHIP_FAMILY_MASK) {
2106 case CHIP_R100:
2107 case CHIP_RV200:
2108 case CHIP_R200:
2109 case CHIP_R300:
1890 }
1891 }
1892
1893 /* Free memory heap structures */
1894 radeon_mem_takedown(&(dev_priv->gart_heap));
1895 radeon_mem_takedown(&(dev_priv->fb_heap));
1896
1897 /* deallocate kernel resources */

--- 287 unchanged lines hidden (view full) ---

2185 dev->dev_private = (void *)dev_priv;
2186 dev_priv->flags = flags;
2187
2188 switch (flags & CHIP_FAMILY_MASK) {
2189 case CHIP_R100:
2190 case CHIP_RV200:
2191 case CHIP_R200:
2192 case CHIP_R300:
2193 case CHIP_R350:
2110 case CHIP_R420:
2194 case CHIP_R420:
2195 case CHIP_RV410:
2111 dev_priv->flags |= CHIP_HAS_HIERZ;
2112 break;
2113 default:
2196 dev_priv->flags |= CHIP_HAS_HIERZ;
2197 break;
2198 default:
2114 /* all other chips have no hierarchical z buffer */
2199 /* all other chips have no hierarchical z buffer */
2115 break;
2116 }
2117
2118 if (drm_device_is_agp(dev))
2119 dev_priv->flags |= CHIP_IS_AGP;
2120
2121 if (drm_device_is_pcie(dev))
2122 dev_priv->flags |= CHIP_IS_PCIE;
2123
2124 DRM_DEBUG("%s card detected\n",
2125 ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : (((dev_priv->flags & CHIP_IS_PCIE) ? "PCIE" : "PCI"))));
2200 break;
2201 }
2202
2203 if (drm_device_is_agp(dev))
2204 dev_priv->flags |= CHIP_IS_AGP;
2205
2206 if (drm_device_is_pcie(dev))
2207 dev_priv->flags |= CHIP_IS_PCIE;
2208
2209 DRM_DEBUG("%s card detected\n",
2210 ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : (((dev_priv->flags & CHIP_IS_PCIE) ? "PCIE" : "PCI"))));
2126
2127 return ret;
2128}
2129
2130/* Create mappings for registers and framebuffer so userland doesn't necessarily
2131 * have to find them.
2132 */
2133int radeon_driver_firstopen(struct drm_device *dev)
2134{

--- 29 unchanged lines hidden --- 		2211 return ret;
2212}
2213
2214/* Create mappings for registers and framebuffer so userland doesn't necessarily
2215 * have to find them.
2216 */
2217int radeon_driver_firstopen(struct drm_device *dev)
2218{

--- 29 unchanged lines hidden ---