| r300_reg.h (152909) | r300_reg.h (157617) |
|---|---|
| 1/************************************************************************** 2 3Copyright (C) 2004-2005 Nicolai Haehnle et al. 4 5Permission is hereby granted, free of charge, to any person obtaining a 6copy of this software and associated documentation files (the "Software"), 7to deal in the Software without restriction, including without limitation 8on the rights to use, copy, modify, merge, publish, distribute, sub --- 10 unchanged lines hidden (view full) --- 19THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22USE OR OTHER DEALINGS IN THE SOFTWARE. 23 24**************************************************************************/ 25 26#include <sys/cdefs.h> | 1/************************************************************************** 2 3Copyright (C) 2004-2005 Nicolai Haehnle et al. 4 5Permission is hereby granted, free of charge, to any person obtaining a 6copy of this software and associated documentation files (the "Software"), 7to deal in the Software without restriction, including without limitation 8on the rights to use, copy, modify, merge, publish, distribute, sub --- 10 unchanged lines hidden (view full) --- 19THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22USE OR OTHER DEALINGS IN THE SOFTWARE. 23 24**************************************************************************/ 25 26#include <sys/cdefs.h> |
| 27__FBSDID("$FreeBSD: head/sys/dev/drm/r300_reg.h 152909 2005-11-28 23:13:57Z anholt $"); | 27__FBSDID("$FreeBSD: head/sys/dev/drm/r300_reg.h 157617 2006-04-09 20:45:45Z anholt $"); |
| 28 29#ifndef _R300_REG_H 30#define _R300_REG_H 31 32#define R300_MC_INIT_MISC_LAT_TIMER 0x180 33# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 34# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 35# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 --- 416 unchanged lines hidden (view full) --- 452# define R300_AA_SUBSAMPLES_2 0 453# define R300_AA_SUBSAMPLES_3 (1<<1) 454# define R300_AA_SUBSAMPLES_4 (2<<1) 455# define R300_AA_SUBSAMPLES_6 (3<<1) 456 457/* END */ 458 459/* gap */ | 28 29#ifndef _R300_REG_H 30#define _R300_REG_H 31 32#define R300_MC_INIT_MISC_LAT_TIMER 0x180 33# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 34# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 35# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 --- 416 unchanged lines hidden (view full) --- 452# define R300_AA_SUBSAMPLES_2 0 453# define R300_AA_SUBSAMPLES_3 (1<<1) 454# define R300_AA_SUBSAMPLES_4 (2<<1) 455# define R300_AA_SUBSAMPLES_6 (3<<1) 456 457/* END */ 458 459/* gap */ |
| 460/* Zero to flush caches. */ 461#define R300_TX_CNTL 0x4100 462 |
|
| 460/* The upper enable bits are guessed, based on fglrx reported limits. */ 461#define R300_TX_ENABLE 0x4104 462# define R300_TX_ENABLE_0 (1 << 0) 463# define R300_TX_ENABLE_1 (1 << 1) 464# define R300_TX_ENABLE_2 (1 << 2) 465# define R300_TX_ENABLE_3 (1 << 3) 466# define R300_TX_ENABLE_4 (1 << 4) 467# define R300_TX_ENABLE_5 (1 << 5) --- 242 unchanged lines hidden (view full) --- 710# define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) ) 711# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) 712# define R300_TX_MAX_ANISO_2_TO_1 (2 << 21) 713# define R300_TX_MAX_ANISO_4_TO_1 (4 << 21) 714# define R300_TX_MAX_ANISO_8_TO_1 (6 << 21) 715# define R300_TX_MAX_ANISO_16_TO_1 (8 << 21) 716# define R300_TX_MAX_ANISO_MASK (14 << 21) 717 | 463/* The upper enable bits are guessed, based on fglrx reported limits. */ 464#define R300_TX_ENABLE 0x4104 465# define R300_TX_ENABLE_0 (1 << 0) 466# define R300_TX_ENABLE_1 (1 << 1) 467# define R300_TX_ENABLE_2 (1 << 2) 468# define R300_TX_ENABLE_3 (1 << 3) 469# define R300_TX_ENABLE_4 (1 << 4) 470# define R300_TX_ENABLE_5 (1 << 5) --- 242 unchanged lines hidden (view full) --- 713# define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) ) 714# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) 715# define R300_TX_MAX_ANISO_2_TO_1 (2 << 21) 716# define R300_TX_MAX_ANISO_4_TO_1 (4 << 21) 717# define R300_TX_MAX_ANISO_8_TO_1 (6 << 21) 718# define R300_TX_MAX_ANISO_16_TO_1 (8 << 21) 719# define R300_TX_MAX_ANISO_MASK (14 << 21) 720 |
| 718#define R300_TX_UNK1_0 0x4440 | 721#define R300_TX_FILTER1_0 0x4440 722# define R300_CHROMA_KEY_MODE_DISABLE 0 723# define R300_CHROMA_KEY_FORCE 1 724# define R300_CHROMA_KEY_BLEND 2 725# define R300_MC_ROUND_NORMAL (0<<2) 726# define R300_MC_ROUND_MPEG4 (1<<2) |
| 719# define R300_LOD_BIAS_MASK 0x1fff | 727# define R300_LOD_BIAS_MASK 0x1fff |
| 728# define R300_EDGE_ANISO_EDGE_DIAG (0<<13) 729# define R300_EDGE_ANISO_EDGE_ONLY (1<<13) 730# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14) 731# define R300_MC_COORD_TRUNCATE_MPEG (1<<14) 732# define R300_TX_TRI_PERF_0_8 (0<<15) 733# define R300_TX_TRI_PERF_1_8 (1<<15) 734# define R300_TX_TRI_PERF_1_4 (2<<15) 735# define R300_TX_TRI_PERF_3_8 (3<<15) 736# define R300_ANISO_THRESHOLD_MASK (7<<17) |
|
| 720 721#define R300_TX_SIZE_0 0x4480 722# define R300_TX_WIDTHMASK_SHIFT 0 723# define R300_TX_WIDTHMASK_MASK (2047 << 0) 724# define R300_TX_HEIGHTMASK_SHIFT 11 725# define R300_TX_HEIGHTMASK_MASK (2047 << 11) 726# define R300_TX_UNK23 (1 << 23) 727# define R300_TX_SIZE_SHIFT 26 /* largest of width, height */ 728# define R300_TX_SIZE_MASK (15 << 26) | 737 738#define R300_TX_SIZE_0 0x4480 739# define R300_TX_WIDTHMASK_SHIFT 0 740# define R300_TX_WIDTHMASK_MASK (2047 << 0) 741# define R300_TX_HEIGHTMASK_SHIFT 11 742# define R300_TX_HEIGHTMASK_MASK (2047 << 11) 743# define R300_TX_UNK23 (1 << 23) 744# define R300_TX_SIZE_SHIFT 26 /* largest of width, height */ 745# define R300_TX_SIZE_MASK (15 << 26) |
| 746# define R300_TX_SIZE_PROJECTED (1<<30) 747# define R300_TX_SIZE_TXPITCH_EN (1<<31) |
|
| 729#define R300_TX_FORMAT_0 0x44C0 730 /* The interpretation of the format word by Wladimir van der Laan */ 731 /* The X, Y, Z and W refer to the layout of the components. 732 They are given meanings as R, G, B and Alpha by the swizzle 733 specification */ 734# define R300_TX_FORMAT_X8 0x0 735# define R300_TX_FORMAT_X16 0x1 736# define R300_TX_FORMAT_Y4X4 0x2 --- 13 unchanged lines hidden (view full) --- 750# define R300_TX_FORMAT_DXT3 0x10 751# define R300_TX_FORMAT_DXT5 0x11 752# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ 753# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ 754# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ 755# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ 756 /* 0x16 - some 16 bit green format.. ?? */ 757# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ | 748#define R300_TX_FORMAT_0 0x44C0 749 /* The interpretation of the format word by Wladimir van der Laan */ 750 /* The X, Y, Z and W refer to the layout of the components. 751 They are given meanings as R, G, B and Alpha by the swizzle 752 specification */ 753# define R300_TX_FORMAT_X8 0x0 754# define R300_TX_FORMAT_X16 0x1 755# define R300_TX_FORMAT_Y4X4 0x2 --- 13 unchanged lines hidden (view full) --- 769# define R300_TX_FORMAT_DXT3 0x10 770# define R300_TX_FORMAT_DXT5 0x11 771# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ 772# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ 773# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ 774# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ 775 /* 0x16 - some 16 bit green format.. ?? */ 776# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ |
| 777# define R300_TX_FORMAT_CUBIC_MAP (1 << 26) |
|
| 758 759 /* gap */ 760 /* Floating point formats */ 761 /* Note - hardware supports both 16 and 32 bit floating point */ 762# define R300_TX_FORMAT_FL_I16 0x18 763# define R300_TX_FORMAT_FL_I16A16 0x19 764# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A 765# define R300_TX_FORMAT_FL_I32 0x1B --- 33 unchanged lines hidden (view full) --- 799 /* We don't really know what they do. Take values from a constant color ? */ 800# define R300_TX_FORMAT_CONST_X (1<<5) 801# define R300_TX_FORMAT_CONST_Y (2<<5) 802# define R300_TX_FORMAT_CONST_Z (4<<5) 803# define R300_TX_FORMAT_CONST_W (8<<5) 804 805# define R300_TX_FORMAT_YUV_MODE 0x00800000 806 | 778 779 /* gap */ 780 /* Floating point formats */ 781 /* Note - hardware supports both 16 and 32 bit floating point */ 782# define R300_TX_FORMAT_FL_I16 0x18 783# define R300_TX_FORMAT_FL_I16A16 0x19 784# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A 785# define R300_TX_FORMAT_FL_I32 0x1B --- 33 unchanged lines hidden (view full) --- 819 /* We don't really know what they do. Take values from a constant color ? */ 820# define R300_TX_FORMAT_CONST_X (1<<5) 821# define R300_TX_FORMAT_CONST_Y (2<<5) 822# define R300_TX_FORMAT_CONST_Z (4<<5) 823# define R300_TX_FORMAT_CONST_W (8<<5) 824 825# define R300_TX_FORMAT_YUV_MODE 0x00800000 826 |
| 827#define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */ |
|
| 807#define R300_TX_OFFSET_0 0x4540 808/* BEGIN: Guess from R200 */ 809# define R300_TXO_ENDIAN_NO_SWAP (0 << 0) 810# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) 811# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) 812# define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) | 828#define R300_TX_OFFSET_0 0x4540 829/* BEGIN: Guess from R200 */ 830# define R300_TXO_ENDIAN_NO_SWAP (0 << 0) 831# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) 832# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) 833# define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) |
| 834# define R300_TXO_MACRO_TILE (1 << 2) 835# define R300_TXO_MICRO_TILE (1 << 3) |
|
| 813# define R300_TXO_OFFSET_MASK 0xffffffe0 814# define R300_TXO_OFFSET_SHIFT 5 815/* END */ | 836# define R300_TXO_OFFSET_MASK 0xffffffe0 837# define R300_TXO_OFFSET_SHIFT 5 838/* END */ |
| 816#define R300_TX_UNK4_0 0x4580 | 839#define R300_TX_CHROMA_KEY_0 0x4580 /* 32 bit chroma key */ |
| 817#define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 } 818 819/* END */ 820 821/* BEGIN: Fragment program instruction set 822// Fragment programs are written directly into register space. 823// There are separate instruction streams for texture instructions and ALU 824// instructions. --- 41 unchanged lines hidden (view full) --- 866# define R300_PFS_NODE_ALU_OFFSET_SHIFT 0 867# define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0) 868# define R300_PFS_NODE_ALU_END_SHIFT 6 869# define R300_PFS_NODE_ALU_END_MASK (63 << 6) 870# define R300_PFS_NODE_TEX_OFFSET_SHIFT 12 871# define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12) 872# define R300_PFS_NODE_TEX_END_SHIFT 17 873# define R300_PFS_NODE_TEX_END_MASK (31 << 17) | 840#define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 } 841 842/* END */ 843 844/* BEGIN: Fragment program instruction set 845// Fragment programs are written directly into register space. 846// There are separate instruction streams for texture instructions and ALU 847// instructions. --- 41 unchanged lines hidden (view full) --- 889# define R300_PFS_NODE_ALU_OFFSET_SHIFT 0 890# define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0) 891# define R300_PFS_NODE_ALU_END_SHIFT 6 892# define R300_PFS_NODE_ALU_END_MASK (63 << 6) 893# define R300_PFS_NODE_TEX_OFFSET_SHIFT 12 894# define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12) 895# define R300_PFS_NODE_TEX_END_SHIFT 17 896# define R300_PFS_NODE_TEX_END_MASK (31 << 17) |
| 874# define R300_PFS_NODE_LAST_NODE (1 << 22) | 897/*# define R300_PFS_NODE_LAST_NODE (1 << 22) */ 898# define R300_PFS_NODE_OUTPUT_COLOR (1 << 22) 899# define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23) |
| 875 876/* TEX 877// As far as I can tell, texture instructions cannot write into output 878// registers directly. A subsequent ALU instruction is always necessary, 879// even if it's just MAD o0, r0, 1, 0 */ 880#define R300_PFS_TEXI_0 0x4620 881# define R300_FPITX_SRC_SHIFT 0 882# define R300_FPITX_SRC_MASK (31 << 0) 883# define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */ 884# define R300_FPITX_DST_SHIFT 6 885# define R300_FPITX_DST_MASK (31 << 6) 886# define R300_FPITX_IMAGE_SHIFT 11 887# define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */ 888/* Unsure if these are opcodes, or some kind of bitfield, but this is how 889 * they were set when I checked 890 */ 891# define R300_FPITX_OPCODE_SHIFT 15 892# define R300_FPITX_OP_TEX 1 | 900 901/* TEX 902// As far as I can tell, texture instructions cannot write into output 903// registers directly. A subsequent ALU instruction is always necessary, 904// even if it's just MAD o0, r0, 1, 0 */ 905#define R300_PFS_TEXI_0 0x4620 906# define R300_FPITX_SRC_SHIFT 0 907# define R300_FPITX_SRC_MASK (31 << 0) 908# define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */ 909# define R300_FPITX_DST_SHIFT 6 910# define R300_FPITX_DST_MASK (31 << 6) 911# define R300_FPITX_IMAGE_SHIFT 11 912# define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */ 913/* Unsure if these are opcodes, or some kind of bitfield, but this is how 914 * they were set when I checked 915 */ 916# define R300_FPITX_OPCODE_SHIFT 15 917# define R300_FPITX_OP_TEX 1 |
| 918# define R300_FPITX_OP_KIL 2 |
|
| 893# define R300_FPITX_OP_TXP 3 894# define R300_FPITX_OP_TXB 4 895 896/* ALU 897// The ALU instructions register blocks are enumerated according to the order 898// in which fglrx. I assume there is space for 64 instructions, since 899// each block has space for a maximum of 64 DWORDs, and this matches reported 900// native limits. --- 59 unchanged lines hidden (view full) --- 960# define R300_FPI1_SRC1C_SHIFT 6 961# define R300_FPI1_SRC1C_MASK (31 << 6) 962# define R300_FPI1_SRC1C_CONST (1 << 11) 963# define R300_FPI1_SRC2C_SHIFT 12 964# define R300_FPI1_SRC2C_MASK (31 << 12) 965# define R300_FPI1_SRC2C_CONST (1 << 17) 966# define R300_FPI1_DSTC_SHIFT 18 967# define R300_FPI1_DSTC_MASK (31 << 18) | 919# define R300_FPITX_OP_TXP 3 920# define R300_FPITX_OP_TXB 4 921 922/* ALU 923// The ALU instructions register blocks are enumerated according to the order 924// in which fglrx. I assume there is space for 64 instructions, since 925// each block has space for a maximum of 64 DWORDs, and this matches reported 926// native limits. --- 59 unchanged lines hidden (view full) --- 986# define R300_FPI1_SRC1C_SHIFT 6 987# define R300_FPI1_SRC1C_MASK (31 << 6) 988# define R300_FPI1_SRC1C_CONST (1 << 11) 989# define R300_FPI1_SRC2C_SHIFT 12 990# define R300_FPI1_SRC2C_MASK (31 << 12) 991# define R300_FPI1_SRC2C_CONST (1 << 17) 992# define R300_FPI1_DSTC_SHIFT 18 993# define R300_FPI1_DSTC_MASK (31 << 18) |
| 994# define R300_FPI1_DSTC_REG_MASK_SHIFT 23 |
|
| 968# define R300_FPI1_DSTC_REG_X (1 << 23) 969# define R300_FPI1_DSTC_REG_Y (1 << 24) 970# define R300_FPI1_DSTC_REG_Z (1 << 25) | 995# define R300_FPI1_DSTC_REG_X (1 << 23) 996# define R300_FPI1_DSTC_REG_Y (1 << 24) 997# define R300_FPI1_DSTC_REG_Z (1 << 25) |
| 998# define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT 26 |
|
| 971# define R300_FPI1_DSTC_OUTPUT_X (1 << 26) 972# define R300_FPI1_DSTC_OUTPUT_Y (1 << 27) 973# define R300_FPI1_DSTC_OUTPUT_Z (1 << 28) 974 975#define R300_PFS_INSTR3_0 0x47C0 976# define R300_FPI3_SRC0A_SHIFT 0 977# define R300_FPI3_SRC0A_MASK (31 << 0) 978# define R300_FPI3_SRC0A_CONST (1 << 5) 979# define R300_FPI3_SRC1A_SHIFT 6 980# define R300_FPI3_SRC1A_MASK (31 << 6) 981# define R300_FPI3_SRC1A_CONST (1 << 11) 982# define R300_FPI3_SRC2A_SHIFT 12 983# define R300_FPI3_SRC2A_MASK (31 << 12) 984# define R300_FPI3_SRC2A_CONST (1 << 17) 985# define R300_FPI3_DSTA_SHIFT 18 986# define R300_FPI3_DSTA_MASK (31 << 18) 987# define R300_FPI3_DSTA_REG (1 << 23) 988# define R300_FPI3_DSTA_OUTPUT (1 << 24) | 999# define R300_FPI1_DSTC_OUTPUT_X (1 << 26) 1000# define R300_FPI1_DSTC_OUTPUT_Y (1 << 27) 1001# define R300_FPI1_DSTC_OUTPUT_Z (1 << 28) 1002 1003#define R300_PFS_INSTR3_0 0x47C0 1004# define R300_FPI3_SRC0A_SHIFT 0 1005# define R300_FPI3_SRC0A_MASK (31 << 0) 1006# define R300_FPI3_SRC0A_CONST (1 << 5) 1007# define R300_FPI3_SRC1A_SHIFT 6 1008# define R300_FPI3_SRC1A_MASK (31 << 6) 1009# define R300_FPI3_SRC1A_CONST (1 << 11) 1010# define R300_FPI3_SRC2A_SHIFT 12 1011# define R300_FPI3_SRC2A_MASK (31 << 12) 1012# define R300_FPI3_SRC2A_CONST (1 << 17) 1013# define R300_FPI3_DSTA_SHIFT 18 1014# define R300_FPI3_DSTA_MASK (31 << 18) 1015# define R300_FPI3_DSTA_REG (1 << 23) 1016# define R300_FPI3_DSTA_OUTPUT (1 << 24) |
| 1017# define R300_FPI3_DSTA_DEPTH (1 << 27) |
|
| 989 990#define R300_PFS_INSTR0_0 0x48C0 991# define R300_FPI0_ARGC_SRC0C_XYZ 0 992# define R300_FPI0_ARGC_SRC0C_XXX 1 993# define R300_FPI0_ARGC_SRC0C_YYY 2 994# define R300_FPI0_ARGC_SRC0C_ZZZ 3 995# define R300_FPI0_ARGC_SRC1C_XYZ 4 996# define R300_FPI0_ARGC_SRC1C_XXX 5 --- 37 unchanged lines hidden (view full) --- 1034# define R300_FPI0_OUTC_DP3 (1 << 23) 1035# define R300_FPI0_OUTC_DP4 (2 << 23) 1036# define R300_FPI0_OUTC_MIN (4 << 23) 1037# define R300_FPI0_OUTC_MAX (5 << 23) 1038# define R300_FPI0_OUTC_CMP (8 << 23) 1039# define R300_FPI0_OUTC_FRC (9 << 23) 1040# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) 1041# define R300_FPI0_OUTC_SAT (1 << 30) | 1018 1019#define R300_PFS_INSTR0_0 0x48C0 1020# define R300_FPI0_ARGC_SRC0C_XYZ 0 1021# define R300_FPI0_ARGC_SRC0C_XXX 1 1022# define R300_FPI0_ARGC_SRC0C_YYY 2 1023# define R300_FPI0_ARGC_SRC0C_ZZZ 3 1024# define R300_FPI0_ARGC_SRC1C_XYZ 4 1025# define R300_FPI0_ARGC_SRC1C_XXX 5 --- 37 unchanged lines hidden (view full) --- 1063# define R300_FPI0_OUTC_DP3 (1 << 23) 1064# define R300_FPI0_OUTC_DP4 (2 << 23) 1065# define R300_FPI0_OUTC_MIN (4 << 23) 1066# define R300_FPI0_OUTC_MAX (5 << 23) 1067# define R300_FPI0_OUTC_CMP (8 << 23) 1068# define R300_FPI0_OUTC_FRC (9 << 23) 1069# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) 1070# define R300_FPI0_OUTC_SAT (1 << 30) |
| 1042# define R300_FPI0_UNKNOWN_31 (1 << 31) | 1071# define R300_FPI0_INSERT_NOP (1 << 31) |
| 1043 1044#define R300_PFS_INSTR2_0 0x49C0 1045# define R300_FPI2_ARGA_SRC0C_X 0 1046# define R300_FPI2_ARGA_SRC0C_Y 1 1047# define R300_FPI2_ARGA_SRC0C_Z 2 1048# define R300_FPI2_ARGA_SRC1C_X 3 1049# define R300_FPI2_ARGA_SRC1C_Y 4 1050# define R300_FPI2_ARGA_SRC1C_Z 5 --- 365 unchanged lines hidden --- | 1072 1073#define R300_PFS_INSTR2_0 0x49C0 1074# define R300_FPI2_ARGA_SRC0C_X 0 1075# define R300_FPI2_ARGA_SRC0C_Y 1 1076# define R300_FPI2_ARGA_SRC0C_Z 2 1077# define R300_FPI2_ARGA_SRC1C_X 3 1078# define R300_FPI2_ARGA_SRC1C_Y 4 1079# define R300_FPI2_ARGA_SRC1C_Z 5 --- 365 unchanged lines hidden --- |