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t4_main.c (269356) t4_main.c (270297)
1/*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: stable/10/sys/dev/cxgbe/t4_main.c 269356 2014-07-31 23:04:41Z np $");
29__FBSDID("$FreeBSD: stable/10/sys/dev/cxgbe/t4_main.c 270297 2014-08-21 19:54:02Z np $");
30
31#include "opt_inet.h"
32#include "opt_inet6.h"
33
34#include <sys/param.h>
35#include <sys/conf.h>
36#include <sys/priv.h>
37#include <sys/kernel.h>

--- 175 unchanged lines hidden (view full) ---

213static int t4_nofldtxq1g = -1;
214TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
215
216#define NOFLDRXQ_1G 1
217static int t4_nofldrxq1g = -1;
218TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
219#endif
220
30
31#include "opt_inet.h"
32#include "opt_inet6.h"
33
34#include <sys/param.h>
35#include <sys/conf.h>
36#include <sys/priv.h>
37#include <sys/kernel.h>

--- 175 unchanged lines hidden (view full) ---

213static int t4_nofldtxq1g = -1;
214TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
215
216#define NOFLDRXQ_1G 1
217static int t4_nofldrxq1g = -1;
218TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
219#endif
220
221#ifdef DEV_NETMAP
222#define NNMTXQ_10G 2
223static int t4_nnmtxq10g = -1;
224TUNABLE_INT("hw.cxgbe.nnmtxq10g", &t4_nnmtxq10g);
225
226#define NNMRXQ_10G 2
227static int t4_nnmrxq10g = -1;
228TUNABLE_INT("hw.cxgbe.nnmrxq10g", &t4_nnmrxq10g);
229
230#define NNMTXQ_1G 1
231static int t4_nnmtxq1g = -1;
232TUNABLE_INT("hw.cxgbe.nnmtxq1g", &t4_nnmtxq1g);
233
234#define NNMRXQ_1G 1
235static int t4_nnmrxq1g = -1;
236TUNABLE_INT("hw.cxgbe.nnmrxq1g", &t4_nnmrxq1g);
237#endif
238
221/*
222 * Holdoff parameters for 10G and 1G ports.
223 */
224#define TMR_IDX_10G 1
225static int t4_tmr_idx_10g = TMR_IDX_10G;
226TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
227
228#define PKTC_IDX_10G (-1)

--- 61 unchanged lines hidden (view full) ---

290
291static int t4_fcoecaps_allowed = 0;
292TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
293
294static int t5_write_combine = 0;
295TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
296
297struct intrs_and_queues {
239/*
240 * Holdoff parameters for 10G and 1G ports.
241 */
242#define TMR_IDX_10G 1
243static int t4_tmr_idx_10g = TMR_IDX_10G;
244TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
245
246#define PKTC_IDX_10G (-1)

--- 61 unchanged lines hidden (view full) ---

308
309static int t4_fcoecaps_allowed = 0;
310TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
311
312static int t5_write_combine = 0;
313TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
314
315struct intrs_and_queues {
298 int intr_type; /* INTx, MSI, or MSI-X */
299 int nirq; /* Number of vectors */
300 int intr_flags;
301 int ntxq10g; /* # of NIC txq's for each 10G port */
302 int nrxq10g; /* # of NIC rxq's for each 10G port */
303 int ntxq1g; /* # of NIC txq's for each 1G port */
304 int nrxq1g; /* # of NIC rxq's for each 1G port */
305 int rsrv_noflowq; /* Flag whether to reserve queue 0 */
316 uint16_t intr_type; /* INTx, MSI, or MSI-X */
317 uint16_t nirq; /* Total # of vectors */
318 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
319 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
320 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
321 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
322 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
323 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
324 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */
306#ifdef TCP_OFFLOAD
325#ifdef TCP_OFFLOAD
307 int nofldtxq10g; /* # of TOE txq's for each 10G port */
308 int nofldrxq10g; /* # of TOE rxq's for each 10G port */
309 int nofldtxq1g; /* # of TOE txq's for each 1G port */
310 int nofldrxq1g; /* # of TOE rxq's for each 1G port */
326 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */
327 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */
328 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */
329 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */
311#endif
330#endif
331#ifdef DEV_NETMAP
332 uint16_t nnmtxq10g; /* # of netmap txq's for each 10G port */
333 uint16_t nnmrxq10g; /* # of netmap rxq's for each 10G port */
334 uint16_t nnmtxq1g; /* # of netmap txq's for each 1G port */
335 uint16_t nnmrxq1g; /* # of netmap rxq's for each 1G port */
336#endif
312};
313
314struct filter_entry {
315 uint32_t valid:1; /* filter allocated and valid */
316 uint32_t locked:1; /* filter is administratively locked */
317 uint32_t pending:1; /* filter action is pending firmware reply */
318 uint32_t smtidx:8; /* Source MAC Table index for smac */
319 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
320
321 struct t4_filter_specification fs;
322};
323
337};
338
339struct filter_entry {
340 uint32_t valid:1; /* filter allocated and valid */
341 uint32_t locked:1; /* filter is administratively locked */
342 uint32_t pending:1; /* filter action is pending firmware reply */
343 uint32_t smtidx:8; /* Source MAC Table index for smac */
344 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
345
346 struct t4_filter_specification fs;
347};
348
324enum {
325 XGMAC_MTU = (1 << 0),
326 XGMAC_PROMISC = (1 << 1),
327 XGMAC_ALLMULTI = (1 << 2),
328 XGMAC_VLANEX = (1 << 3),
329 XGMAC_UCADDR = (1 << 4),
330 XGMAC_MCADDRS = (1 << 5),
331
332 XGMAC_ALL = 0xffff
333};
334
335static int map_bars_0_and_4(struct adapter *);
336static int map_bar_2(struct adapter *);
337static void setup_memwin(struct adapter *);
338static int validate_mem_range(struct adapter *, uint32_t, int);
339static int fwmtype_to_hwmtype(int);
340static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
341 uint32_t *);
342static void memwin_info(struct adapter *, int, uint32_t *, uint32_t *);
343static uint32_t position_memwin(struct adapter *, int, uint32_t);
344static int cfg_itype_and_nqueues(struct adapter *, int, int,
345 struct intrs_and_queues *);
346static int prep_firmware(struct adapter *);
347static int partition_resources(struct adapter *, const struct firmware *,
348 const char *);
349static int get_params__pre_init(struct adapter *);
350static int get_params__post_init(struct adapter *);
351static int set_params__post_init(struct adapter *);
352static void t4_set_desc(struct adapter *);
349static int map_bars_0_and_4(struct adapter *);
350static int map_bar_2(struct adapter *);
351static void setup_memwin(struct adapter *);
352static int validate_mem_range(struct adapter *, uint32_t, int);
353static int fwmtype_to_hwmtype(int);
354static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
355 uint32_t *);
356static void memwin_info(struct adapter *, int, uint32_t *, uint32_t *);
357static uint32_t position_memwin(struct adapter *, int, uint32_t);
358static int cfg_itype_and_nqueues(struct adapter *, int, int,
359 struct intrs_and_queues *);
360static int prep_firmware(struct adapter *);
361static int partition_resources(struct adapter *, const struct firmware *,
362 const char *);
363static int get_params__pre_init(struct adapter *);
364static int get_params__post_init(struct adapter *);
365static int set_params__post_init(struct adapter *);
366static void t4_set_desc(struct adapter *);
353static void build_medialist(struct port_info *);
354static int update_mac_settings(struct port_info *, int);
367static void build_medialist(struct port_info *, struct ifmedia *);
355static int cxgbe_init_synchronized(struct port_info *);
356static int cxgbe_uninit_synchronized(struct port_info *);
357static int setup_intr_handlers(struct adapter *);
368static int cxgbe_init_synchronized(struct port_info *);
369static int cxgbe_uninit_synchronized(struct port_info *);
370static int setup_intr_handlers(struct adapter *);
358static int adapter_full_init(struct adapter *);
359static int adapter_full_uninit(struct adapter *);
360static int port_full_init(struct port_info *);
361static int port_full_uninit(struct port_info *);
362static void quiesce_eq(struct adapter *, struct sge_eq *);
363static void quiesce_iq(struct adapter *, struct sge_iq *);
364static void quiesce_fl(struct adapter *, struct sge_fl *);
365static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
366 driver_intr_t *, void *, char *);
367static int t4_free_irq(struct adapter *, struct irq *);
368static void reg_block_dump(struct adapter *, uint8_t *, unsigned int,
369 unsigned int);

--- 181 unchanged lines hidden (view full) ---

551{
552 struct adapter *sc;
553 int rc = 0, i, n10g, n1g, rqidx, tqidx;
554 struct intrs_and_queues iaq;
555 struct sge *s;
556#ifdef TCP_OFFLOAD
557 int ofld_rqidx, ofld_tqidx;
558#endif
371static void quiesce_eq(struct adapter *, struct sge_eq *);
372static void quiesce_iq(struct adapter *, struct sge_iq *);
373static void quiesce_fl(struct adapter *, struct sge_fl *);
374static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
375 driver_intr_t *, void *, char *);
376static int t4_free_irq(struct adapter *, struct irq *);
377static void reg_block_dump(struct adapter *, uint8_t *, unsigned int,
378 unsigned int);

--- 181 unchanged lines hidden (view full) ---

560{
561 struct adapter *sc;
562 int rc = 0, i, n10g, n1g, rqidx, tqidx;
563 struct intrs_and_queues iaq;
564 struct sge *s;
565#ifdef TCP_OFFLOAD
566 int ofld_rqidx, ofld_tqidx;
567#endif
568#ifdef DEV_NETMAP
569 int nm_rqidx, nm_tqidx;
570#endif
559
560 sc = device_get_softc(dev);
561 sc->dev = dev;
562
563 pci_enable_busmaster(dev);
564 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
565 uint32_t v;
566

--- 112 unchanged lines hidden (view full) ---

679 rc = -t4_port_init(pi, sc->mbox, sc->pf, 0);
680 if (rc != 0) {
681 device_printf(dev, "unable to initialize port %d: %d\n",
682 i, rc);
683 free(pi, M_CXGBE);
684 sc->port[i] = NULL;
685 goto done;
686 }
571
572 sc = device_get_softc(dev);
573 sc->dev = dev;
574
575 pci_enable_busmaster(dev);
576 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
577 uint32_t v;
578

--- 112 unchanged lines hidden (view full) ---

691 rc = -t4_port_init(pi, sc->mbox, sc->pf, 0);
692 if (rc != 0) {
693 device_printf(dev, "unable to initialize port %d: %d\n",
694 i, rc);
695 free(pi, M_CXGBE);
696 sc->port[i] = NULL;
697 goto done;
698 }
699 rc = -t4_link_start(sc, sc->mbox, pi->tx_chan, &pi->link_cfg);
700 if (rc != 0) {
701 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc);
702 free(pi, M_CXGBE);
703 sc->port[i] = NULL;
704 goto done;
705 }
687
688 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
689 device_get_nameunit(dev), i);
690 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
691 sc->chan_map[pi->tx_chan] = i;
692
693 if (is_10G_port(pi) || is_40G_port(pi)) {
694 n10g++;

--- 25 unchanged lines hidden (view full) ---

720 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
721 */
722 rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq);
723 if (rc != 0)
724 goto done; /* error message displayed already */
725
726 sc->intr_type = iaq.intr_type;
727 sc->intr_count = iaq.nirq;
706
707 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
708 device_get_nameunit(dev), i);
709 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
710 sc->chan_map[pi->tx_chan] = i;
711
712 if (is_10G_port(pi) || is_40G_port(pi)) {
713 n10g++;

--- 25 unchanged lines hidden (view full) ---

739 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
740 */
741 rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq);
742 if (rc != 0)
743 goto done; /* error message displayed already */
744
745 sc->intr_type = iaq.intr_type;
746 sc->intr_count = iaq.nirq;
728 sc->flags |= iaq.intr_flags;
729
730 s = &sc->sge;
731 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
732 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
733 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
734 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
735 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
747
748 s = &sc->sge;
749 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
750 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
751 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
752 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
753 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
736
737#ifdef TCP_OFFLOAD
738 if (is_offload(sc)) {
754#ifdef TCP_OFFLOAD
755 if (is_offload(sc)) {
739
740 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
741 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
742 s->neq += s->nofldtxq + s->nofldrxq;
743 s->niq += s->nofldrxq;
744
745 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
746 M_CXGBE, M_ZERO | M_WAITOK);
747 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
748 M_CXGBE, M_ZERO | M_WAITOK);
749 }
750#endif
756 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
757 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
758 s->neq += s->nofldtxq + s->nofldrxq;
759 s->niq += s->nofldrxq;
760
761 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
762 M_CXGBE, M_ZERO | M_WAITOK);
763 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
764 M_CXGBE, M_ZERO | M_WAITOK);
765 }
766#endif
767#ifdef DEV_NETMAP
768 s->nnmrxq = n10g * iaq.nnmrxq10g + n1g * iaq.nnmrxq1g;
769 s->nnmtxq = n10g * iaq.nnmtxq10g + n1g * iaq.nnmtxq1g;
770 s->neq += s->nnmtxq + s->nnmrxq;
771 s->niq += s->nnmrxq;
751
772
773 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
774 M_CXGBE, M_ZERO | M_WAITOK);
775 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
776 M_CXGBE, M_ZERO | M_WAITOK);
777#endif
778
752 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
753 M_ZERO | M_WAITOK);
754 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
755 M_ZERO | M_WAITOK);
756 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
757 M_ZERO | M_WAITOK);
758 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
759 M_ZERO | M_WAITOK);

--- 8 unchanged lines hidden (view full) ---

768 /*
769 * Second pass over the ports. This time we know the number of rx and
770 * tx queues that each port should get.
771 */
772 rqidx = tqidx = 0;
773#ifdef TCP_OFFLOAD
774 ofld_rqidx = ofld_tqidx = 0;
775#endif
779 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
780 M_ZERO | M_WAITOK);
781 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
782 M_ZERO | M_WAITOK);
783 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
784 M_ZERO | M_WAITOK);
785 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
786 M_ZERO | M_WAITOK);

--- 8 unchanged lines hidden (view full) ---

795 /*
796 * Second pass over the ports. This time we know the number of rx and
797 * tx queues that each port should get.
798 */
799 rqidx = tqidx = 0;
800#ifdef TCP_OFFLOAD
801 ofld_rqidx = ofld_tqidx = 0;
802#endif
803#ifdef DEV_NETMAP
804 nm_rqidx = nm_tqidx = 0;
805#endif
776 for_each_port(sc, i) {
777 struct port_info *pi = sc->port[i];
778
779 if (pi == NULL)
780 continue;
781
782 pi->first_rxq = rqidx;
783 pi->first_txq = tqidx;
784 if (is_10G_port(pi) || is_40G_port(pi)) {
806 for_each_port(sc, i) {
807 struct port_info *pi = sc->port[i];
808
809 if (pi == NULL)
810 continue;
811
812 pi->first_rxq = rqidx;
813 pi->first_txq = tqidx;
814 if (is_10G_port(pi) || is_40G_port(pi)) {
815 pi->flags |= iaq.intr_flags_10g;
785 pi->nrxq = iaq.nrxq10g;
786 pi->ntxq = iaq.ntxq10g;
787 } else {
816 pi->nrxq = iaq.nrxq10g;
817 pi->ntxq = iaq.ntxq10g;
818 } else {
819 pi->flags |= iaq.intr_flags_1g;
788 pi->nrxq = iaq.nrxq1g;
789 pi->ntxq = iaq.ntxq1g;
790 }
791
792 if (pi->ntxq > 1)
793 pi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
794 else
795 pi->rsrv_noflowq = 0;
796
797 rqidx += pi->nrxq;
798 tqidx += pi->ntxq;
820 pi->nrxq = iaq.nrxq1g;
821 pi->ntxq = iaq.ntxq1g;
822 }
823
824 if (pi->ntxq > 1)
825 pi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
826 else
827 pi->rsrv_noflowq = 0;
828
829 rqidx += pi->nrxq;
830 tqidx += pi->ntxq;
799
800#ifdef TCP_OFFLOAD
801 if (is_offload(sc)) {
802 pi->first_ofld_rxq = ofld_rqidx;
803 pi->first_ofld_txq = ofld_tqidx;
804 if (is_10G_port(pi) || is_40G_port(pi)) {
805 pi->nofldrxq = iaq.nofldrxq10g;
806 pi->nofldtxq = iaq.nofldtxq10g;
807 } else {
808 pi->nofldrxq = iaq.nofldrxq1g;
809 pi->nofldtxq = iaq.nofldtxq1g;
810 }
811 ofld_rqidx += pi->nofldrxq;
812 ofld_tqidx += pi->nofldtxq;
813 }
814#endif
831#ifdef TCP_OFFLOAD
832 if (is_offload(sc)) {
833 pi->first_ofld_rxq = ofld_rqidx;
834 pi->first_ofld_txq = ofld_tqidx;
835 if (is_10G_port(pi) || is_40G_port(pi)) {
836 pi->nofldrxq = iaq.nofldrxq10g;
837 pi->nofldtxq = iaq.nofldtxq10g;
838 } else {
839 pi->nofldrxq = iaq.nofldrxq1g;
840 pi->nofldtxq = iaq.nofldtxq1g;
841 }
842 ofld_rqidx += pi->nofldrxq;
843 ofld_tqidx += pi->nofldtxq;
844 }
845#endif
846#ifdef DEV_NETMAP
847 pi->first_nm_rxq = nm_rqidx;
848 pi->first_nm_txq = nm_tqidx;
849 if (is_10G_port(pi) || is_40G_port(pi)) {
850 pi->nnmrxq = iaq.nnmrxq10g;
851 pi->nnmtxq = iaq.nnmtxq10g;
852 } else {
853 pi->nnmrxq = iaq.nnmrxq1g;
854 pi->nnmtxq = iaq.nnmtxq1g;
855 }
856 nm_rqidx += pi->nnmrxq;
857 nm_tqidx += pi->nnmtxq;
858#endif
815 }
816
817 rc = setup_intr_handlers(sc);
818 if (rc != 0) {
819 device_printf(dev,
820 "failed to setup interrupt handlers: %d\n", rc);
821 goto done;
822 }

--- 58 unchanged lines hidden (view full) ---

881 }
882
883 for (i = 0; i < sc->intr_count; i++)
884 t4_free_irq(sc, &sc->irq[i]);
885
886 for (i = 0; i < MAX_NPORTS; i++) {
887 pi = sc->port[i];
888 if (pi) {
859 }
860
861 rc = setup_intr_handlers(sc);
862 if (rc != 0) {
863 device_printf(dev,
864 "failed to setup interrupt handlers: %d\n", rc);
865 goto done;
866 }

--- 58 unchanged lines hidden (view full) ---

925 }
926
927 for (i = 0; i < sc->intr_count; i++)
928 t4_free_irq(sc, &sc->irq[i]);
929
930 for (i = 0; i < MAX_NPORTS; i++) {
931 pi = sc->port[i];
932 if (pi) {
889 t4_free_vi(pi->adapter, sc->mbox, sc->pf, 0, pi->viid);
933 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->viid);
890 if (pi->dev)
891 device_delete_child(dev, pi->dev);
892
893 mtx_destroy(&pi->pi_lock);
894 free(pi, M_CXGBE);
895 }
896 }
897

--- 20 unchanged lines hidden (view full) ---

918
919 if (sc->l2t)
920 t4_free_l2t(sc->l2t);
921
922#ifdef TCP_OFFLOAD
923 free(sc->sge.ofld_rxq, M_CXGBE);
924 free(sc->sge.ofld_txq, M_CXGBE);
925#endif
934 if (pi->dev)
935 device_delete_child(dev, pi->dev);
936
937 mtx_destroy(&pi->pi_lock);
938 free(pi, M_CXGBE);
939 }
940 }
941

--- 20 unchanged lines hidden (view full) ---

962
963 if (sc->l2t)
964 t4_free_l2t(sc->l2t);
965
966#ifdef TCP_OFFLOAD
967 free(sc->sge.ofld_rxq, M_CXGBE);
968 free(sc->sge.ofld_txq, M_CXGBE);
969#endif
970#ifdef DEV_NETMAP
971 free(sc->sge.nm_rxq, M_CXGBE);
972 free(sc->sge.nm_txq, M_CXGBE);
973#endif
926 free(sc->irq, M_CXGBE);
927 free(sc->sge.rxq, M_CXGBE);
928 free(sc->sge.txq, M_CXGBE);
929 free(sc->sge.ctrlq, M_CXGBE);
930 free(sc->sge.iqmap, M_CXGBE);
931 free(sc->sge.eqmap, M_CXGBE);
932 free(sc->tids.ftid_tab, M_CXGBE);
933 t4_destroy_dma_tag(sc);

--- 11 unchanged lines hidden (view full) ---

945 if (mtx_initialized(&sc->ifp_lock))
946 mtx_destroy(&sc->ifp_lock);
947
948 bzero(sc, sizeof(*sc));
949
950 return (0);
951}
952
974 free(sc->irq, M_CXGBE);
975 free(sc->sge.rxq, M_CXGBE);
976 free(sc->sge.txq, M_CXGBE);
977 free(sc->sge.ctrlq, M_CXGBE);
978 free(sc->sge.iqmap, M_CXGBE);
979 free(sc->sge.eqmap, M_CXGBE);
980 free(sc->tids.ftid_tab, M_CXGBE);
981 t4_destroy_dma_tag(sc);

--- 11 unchanged lines hidden (view full) ---

993 if (mtx_initialized(&sc->ifp_lock))
994 mtx_destroy(&sc->ifp_lock);
995
996 bzero(sc, sizeof(*sc));
997
998 return (0);
999}
1000
953
954static int
955cxgbe_probe(device_t dev)
956{
957 char buf[128];
958 struct port_info *pi = device_get_softc(dev);
959
960 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
961 device_set_desc_copy(dev, buf);

--- 6 unchanged lines hidden (view full) ---

968 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
969#define T4_CAP_ENABLE (T4_CAP)
970
971static int
972cxgbe_attach(device_t dev)
973{
974 struct port_info *pi = device_get_softc(dev);
975 struct ifnet *ifp;
1001static int
1002cxgbe_probe(device_t dev)
1003{
1004 char buf[128];
1005 struct port_info *pi = device_get_softc(dev);
1006
1007 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1008 device_set_desc_copy(dev, buf);

--- 6 unchanged lines hidden (view full) ---

1015 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1016#define T4_CAP_ENABLE (T4_CAP)
1017
1018static int
1019cxgbe_attach(device_t dev)
1020{
1021 struct port_info *pi = device_get_softc(dev);
1022 struct ifnet *ifp;
1023 char *s;
1024 int n, o;
976
977 /* Allocate an ifnet and set it up */
978 ifp = if_alloc(IFT_ETHER);
979 if (ifp == NULL) {
980 device_printf(dev, "Cannot allocate ifnet\n");
981 return (ENOMEM);
982 }
983 pi->ifp = ifp;

--- 16 unchanged lines hidden (view full) ---

1000#endif
1001 ifp->if_capenable = T4_CAP_ENABLE;
1002 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1003 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1004
1005 /* Initialize ifmedia for this port */
1006 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1007 cxgbe_media_status);
1025
1026 /* Allocate an ifnet and set it up */
1027 ifp = if_alloc(IFT_ETHER);
1028 if (ifp == NULL) {
1029 device_printf(dev, "Cannot allocate ifnet\n");
1030 return (ENOMEM);
1031 }
1032 pi->ifp = ifp;

--- 16 unchanged lines hidden (view full) ---

1049#endif
1050 ifp->if_capenable = T4_CAP_ENABLE;
1051 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1052 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1053
1054 /* Initialize ifmedia for this port */
1055 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1056 cxgbe_media_status);
1008 build_medialist(pi);
1057 build_medialist(pi, &pi->media);
1009
1010 pi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1011 EVENTHANDLER_PRI_ANY);
1012
1013 ether_ifattach(ifp, pi->hw_addr);
1014
1058
1059 pi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1060 EVENTHANDLER_PRI_ANY);
1061
1062 ether_ifattach(ifp, pi->hw_addr);
1063
1064 n = 128;
1065 s = malloc(n, M_CXGBE, M_WAITOK);
1066 o = snprintf(s, n, "%d txq, %d rxq (NIC)", pi->ntxq, pi->nrxq);
1067 MPASS(n > o);
1015#ifdef TCP_OFFLOAD
1016 if (is_offload(pi->adapter)) {
1068#ifdef TCP_OFFLOAD
1069 if (is_offload(pi->adapter)) {
1017 device_printf(dev,
1018 "%d txq, %d rxq (NIC); %d txq, %d rxq (TOE)\n",
1019 pi->ntxq, pi->nrxq, pi->nofldtxq, pi->nofldrxq);
1020 } else
1070 o += snprintf(s + o, n - o, "; %d txq, %d rxq (TOE)",
1071 pi->nofldtxq, pi->nofldrxq);
1072 MPASS(n > o);
1073 }
1021#endif
1074#endif
1022 device_printf(dev, "%d txq, %d rxq\n", pi->ntxq, pi->nrxq);
1075#ifdef DEV_NETMAP
1076 o += snprintf(s + o, n - o, "; %d txq, %d rxq (netmap)", pi->nnmtxq,
1077 pi->nnmrxq);
1078 MPASS(n > o);
1079#endif
1080 device_printf(dev, "%s\n", s);
1081 free(s, M_CXGBE);
1023
1082
1083#ifdef DEV_NETMAP
1084 /* nm_media handled here to keep implementation private to this file */
1085 ifmedia_init(&pi->nm_media, IFM_IMASK, cxgbe_media_change,
1086 cxgbe_media_status);
1087 build_medialist(pi, &pi->nm_media);
1088 create_netmap_ifnet(pi); /* logs errors it something fails */
1089#endif
1024 cxgbe_sysctls(pi);
1025
1026 return (0);
1027}
1028
1029static int
1030cxgbe_detach(device_t dev)
1031{

--- 31 unchanged lines hidden (view full) ---

1063 /* Let detach proceed even if these fail. */
1064 cxgbe_uninit_synchronized(pi);
1065 port_full_uninit(pi);
1066
1067 ifmedia_removeall(&pi->media);
1068 ether_ifdetach(pi->ifp);
1069 if_free(pi->ifp);
1070
1090 cxgbe_sysctls(pi);
1091
1092 return (0);
1093}
1094
1095static int
1096cxgbe_detach(device_t dev)
1097{

--- 31 unchanged lines hidden (view full) ---

1129 /* Let detach proceed even if these fail. */
1130 cxgbe_uninit_synchronized(pi);
1131 port_full_uninit(pi);
1132
1133 ifmedia_removeall(&pi->media);
1134 ether_ifdetach(pi->ifp);
1135 if_free(pi->ifp);
1136
1137#ifdef DEV_NETMAP
1138 /* XXXNM: equivalent of cxgbe_uninit_synchronized to ifdown nm_ifp */
1139 destroy_netmap_ifnet(pi);
1140#endif
1141
1071 ADAPTER_LOCK(sc);
1072 CLR_BUSY(sc);
1073 wakeup(&sc->flags);
1074 ADAPTER_UNLOCK(sc);
1075
1076 return (0);
1077}
1078

--- 7 unchanged lines hidden (view full) ---

1086 return;
1087 cxgbe_init_synchronized(pi);
1088 end_synchronized_op(sc, 0);
1089}
1090
1091static int
1092cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1093{
1142 ADAPTER_LOCK(sc);
1143 CLR_BUSY(sc);
1144 wakeup(&sc->flags);
1145 ADAPTER_UNLOCK(sc);
1146
1147 return (0);
1148}
1149

--- 7 unchanged lines hidden (view full) ---

1157 return;
1158 cxgbe_init_synchronized(pi);
1159 end_synchronized_op(sc, 0);
1160}
1161
1162static int
1163cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1164{
1094 int rc = 0, mtu, flags;
1165 int rc = 0, mtu, flags, can_sleep;
1095 struct port_info *pi = ifp->if_softc;
1096 struct adapter *sc = pi->adapter;
1097 struct ifreq *ifr = (struct ifreq *)data;
1098 uint32_t mask;
1099
1100 switch (cmd) {
1101 case SIOCSIFMTU:
1102 mtu = ifr->ifr_mtu;
1103 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
1104 return (EINVAL);
1105
1106 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4mtu");
1107 if (rc)
1108 return (rc);
1109 ifp->if_mtu = mtu;
1110 if (pi->flags & PORT_INIT_DONE) {
1111 t4_update_fl_bufsize(ifp);
1112 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1166 struct port_info *pi = ifp->if_softc;
1167 struct adapter *sc = pi->adapter;
1168 struct ifreq *ifr = (struct ifreq *)data;
1169 uint32_t mask;
1170
1171 switch (cmd) {
1172 case SIOCSIFMTU:
1173 mtu = ifr->ifr_mtu;
1174 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
1175 return (EINVAL);
1176
1177 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4mtu");
1178 if (rc)
1179 return (rc);
1180 ifp->if_mtu = mtu;
1181 if (pi->flags & PORT_INIT_DONE) {
1182 t4_update_fl_bufsize(ifp);
1183 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1113 rc = update_mac_settings(pi, XGMAC_MTU);
1184 rc = update_mac_settings(ifp, XGMAC_MTU);
1114 }
1115 end_synchronized_op(sc, 0);
1116 break;
1117
1118 case SIOCSIFFLAGS:
1185 }
1186 end_synchronized_op(sc, 0);
1187 break;
1188
1189 case SIOCSIFFLAGS:
1119 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4flg");
1190 can_sleep = 0;
1191redo_sifflags:
1192 rc = begin_synchronized_op(sc, pi,
1193 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1120 if (rc)
1121 return (rc);
1122
1123 if (ifp->if_flags & IFF_UP) {
1124 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1125 flags = pi->if_flags;
1126 if ((ifp->if_flags ^ flags) &
1127 (IFF_PROMISC | IFF_ALLMULTI)) {
1194 if (rc)
1195 return (rc);
1196
1197 if (ifp->if_flags & IFF_UP) {
1198 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1199 flags = pi->if_flags;
1200 if ((ifp->if_flags ^ flags) &
1201 (IFF_PROMISC | IFF_ALLMULTI)) {
1128 rc = update_mac_settings(pi,
1202 if (can_sleep == 1) {
1203 end_synchronized_op(sc, 0);
1204 can_sleep = 0;
1205 goto redo_sifflags;
1206 }
1207 rc = update_mac_settings(ifp,
1129 XGMAC_PROMISC | XGMAC_ALLMULTI);
1130 }
1208 XGMAC_PROMISC | XGMAC_ALLMULTI);
1209 }
1131 } else
1210 } else {
1211 if (can_sleep == 0) {
1212 end_synchronized_op(sc, LOCK_HELD);
1213 can_sleep = 1;
1214 goto redo_sifflags;
1215 }
1132 rc = cxgbe_init_synchronized(pi);
1216 rc = cxgbe_init_synchronized(pi);
1217 }
1133 pi->if_flags = ifp->if_flags;
1218 pi->if_flags = ifp->if_flags;
1134 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1219 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1220 if (can_sleep == 0) {
1221 end_synchronized_op(sc, LOCK_HELD);
1222 can_sleep = 1;
1223 goto redo_sifflags;
1224 }
1135 rc = cxgbe_uninit_synchronized(pi);
1225 rc = cxgbe_uninit_synchronized(pi);
1136 end_synchronized_op(sc, 0);
1226 }
1227 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1137 break;
1138
1228 break;
1229
1139 case SIOCADDMULTI:
1230 case SIOCADDMULTI:
1140 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1141 rc = begin_synchronized_op(sc, pi, HOLD_LOCK, "t4multi");
1142 if (rc)
1143 return (rc);
1144 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1231 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1232 rc = begin_synchronized_op(sc, pi, HOLD_LOCK, "t4multi");
1233 if (rc)
1234 return (rc);
1235 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1145 rc = update_mac_settings(pi, XGMAC_MCADDRS);
1236 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1146 end_synchronized_op(sc, LOCK_HELD);
1147 break;
1148
1149 case SIOCSIFCAP:
1150 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4cap");
1151 if (rc)
1152 return (rc);
1153

--- 72 unchanged lines hidden (view full) ---

1226 goto fail;
1227
1228 ifp->if_capenable ^= mask;
1229 }
1230#endif
1231 if (mask & IFCAP_VLAN_HWTAGGING) {
1232 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1233 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1237 end_synchronized_op(sc, LOCK_HELD);
1238 break;
1239
1240 case SIOCSIFCAP:
1241 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4cap");
1242 if (rc)
1243 return (rc);
1244

--- 72 unchanged lines hidden (view full) ---

1317 goto fail;
1318
1319 ifp->if_capenable ^= mask;
1320 }
1321#endif
1322 if (mask & IFCAP_VLAN_HWTAGGING) {
1323 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1324 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1234 rc = update_mac_settings(pi, XGMAC_VLANEX);
1325 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1235 }
1236 if (mask & IFCAP_VLAN_MTU) {
1237 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1238
1239 /* Need to find out how to disable auto-mtu-inflation */
1240 }
1241 if (mask & IFCAP_VLAN_HWTSO)
1242 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;

--- 118 unchanged lines hidden (view full) ---

1361
1362 return (EOPNOTSUPP);
1363}
1364
1365static void
1366cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1367{
1368 struct port_info *pi = ifp->if_softc;
1326 }
1327 if (mask & IFCAP_VLAN_MTU) {
1328 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1329
1330 /* Need to find out how to disable auto-mtu-inflation */
1331 }
1332 if (mask & IFCAP_VLAN_HWTSO)
1333 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;

--- 118 unchanged lines hidden (view full) ---

1452
1453 return (EOPNOTSUPP);
1454}
1455
1456static void
1457cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1458{
1459 struct port_info *pi = ifp->if_softc;
1369 struct ifmedia_entry *cur = pi->media.ifm_cur;
1460 struct ifmedia *media = NULL;
1461 struct ifmedia_entry *cur;
1370 int speed = pi->link_cfg.speed;
1371 int data = (pi->port_type << 8) | pi->mod_type;
1372
1462 int speed = pi->link_cfg.speed;
1463 int data = (pi->port_type << 8) | pi->mod_type;
1464
1465 if (ifp == pi->ifp)
1466 media = &pi->media;
1467#ifdef DEV_NETMAP
1468 else if (ifp == pi->nm_ifp)
1469 media = &pi->nm_media;
1470#endif
1471 MPASS(media != NULL);
1472
1473 cur = media->ifm_cur;
1373 if (cur->ifm_data != data) {
1474 if (cur->ifm_data != data) {
1374 build_medialist(pi);
1375 cur = pi->media.ifm_cur;
1475 build_medialist(pi, media);
1476 cur = media->ifm_cur;
1376 }
1377
1378 ifmr->ifm_status = IFM_AVALID;
1379 if (!pi->link_cfg.link_ok)
1380 return;
1381
1382 ifmr->ifm_status |= IFM_ACTIVE;
1383

--- 336 unchanged lines hidden (view full) ---

1720}
1721
1722static int
1723cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g,
1724 struct intrs_and_queues *iaq)
1725{
1726 int rc, itype, navail, nrxq10g, nrxq1g, n;
1727 int nofldrxq10g = 0, nofldrxq1g = 0;
1477 }
1478
1479 ifmr->ifm_status = IFM_AVALID;
1480 if (!pi->link_cfg.link_ok)
1481 return;
1482
1483 ifmr->ifm_status |= IFM_ACTIVE;
1484

--- 336 unchanged lines hidden (view full) ---

1821}
1822
1823static int
1824cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g,
1825 struct intrs_and_queues *iaq)
1826{
1827 int rc, itype, navail, nrxq10g, nrxq1g, n;
1828 int nofldrxq10g = 0, nofldrxq1g = 0;
1829 int nnmrxq10g = 0, nnmrxq1g = 0;
1728
1729 bzero(iaq, sizeof(*iaq));
1730
1731 iaq->ntxq10g = t4_ntxq10g;
1732 iaq->ntxq1g = t4_ntxq1g;
1733 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
1734 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
1735 iaq->rsrv_noflowq = t4_rsrv_noflowq;
1736#ifdef TCP_OFFLOAD
1737 if (is_offload(sc)) {
1738 iaq->nofldtxq10g = t4_nofldtxq10g;
1739 iaq->nofldtxq1g = t4_nofldtxq1g;
1740 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
1741 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
1742 }
1743#endif
1830
1831 bzero(iaq, sizeof(*iaq));
1832
1833 iaq->ntxq10g = t4_ntxq10g;
1834 iaq->ntxq1g = t4_ntxq1g;
1835 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
1836 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
1837 iaq->rsrv_noflowq = t4_rsrv_noflowq;
1838#ifdef TCP_OFFLOAD
1839 if (is_offload(sc)) {
1840 iaq->nofldtxq10g = t4_nofldtxq10g;
1841 iaq->nofldtxq1g = t4_nofldtxq1g;
1842 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
1843 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
1844 }
1845#endif
1846#ifdef DEV_NETMAP
1847 iaq->nnmtxq10g = t4_nnmtxq10g;
1848 iaq->nnmtxq1g = t4_nnmtxq1g;
1849 iaq->nnmrxq10g = nnmrxq10g = t4_nnmrxq10g;
1850 iaq->nnmrxq1g = nnmrxq1g = t4_nnmrxq1g;
1851#endif
1744
1745 for (itype = INTR_MSIX; itype; itype >>= 1) {
1746
1747 if ((itype & t4_intr_types) == 0)
1748 continue; /* not allowed */
1749
1750 if (itype == INTR_MSIX)
1751 navail = pci_msix_count(sc->dev);
1752 else if (itype == INTR_MSI)
1753 navail = pci_msi_count(sc->dev);
1754 else
1755 navail = 1;
1756restart:
1757 if (navail == 0)
1758 continue;
1759
1760 iaq->intr_type = itype;
1852
1853 for (itype = INTR_MSIX; itype; itype >>= 1) {
1854
1855 if ((itype & t4_intr_types) == 0)
1856 continue; /* not allowed */
1857
1858 if (itype == INTR_MSIX)
1859 navail = pci_msix_count(sc->dev);
1860 else if (itype == INTR_MSI)
1861 navail = pci_msi_count(sc->dev);
1862 else
1863 navail = 1;
1864restart:
1865 if (navail == 0)
1866 continue;
1867
1868 iaq->intr_type = itype;
1761 iaq->intr_flags = 0;
1869 iaq->intr_flags_10g = 0;
1870 iaq->intr_flags_1g = 0;
1762
1763 /*
1764 * Best option: an interrupt vector for errors, one for the
1871
1872 /*
1873 * Best option: an interrupt vector for errors, one for the
1765 * firmware event queue, and one each for each rxq (NIC as well
1766 * as offload).
1874 * firmware event queue, and one for every rxq (NIC, TOE, and
1875 * netmap).
1767 */
1768 iaq->nirq = T4_EXTRA_INTR;
1876 */
1877 iaq->nirq = T4_EXTRA_INTR;
1769 iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
1770 iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
1878 iaq->nirq += n10g * (nrxq10g + nofldrxq10g + nnmrxq10g);
1879 iaq->nirq += n1g * (nrxq1g + nofldrxq1g + nnmrxq1g);
1771 if (iaq->nirq <= navail &&
1772 (itype != INTR_MSI || powerof2(iaq->nirq))) {
1880 if (iaq->nirq <= navail &&
1881 (itype != INTR_MSI || powerof2(iaq->nirq))) {
1773 iaq->intr_flags |= INTR_DIRECT;
1882 iaq->intr_flags_10g = INTR_ALL;
1883 iaq->intr_flags_1g = INTR_ALL;
1774 goto allocate;
1775 }
1776
1777 /*
1884 goto allocate;
1885 }
1886
1887 /*
1778 * Second best option: an interrupt vector for errors, one for
1779 * the firmware event queue, and one each for either NIC or
1780 * offload rxq's.
1888 * Second best option: a vector for errors, one for the firmware
1889 * event queue, and vectors for either all the NIC rx queues or
1890 * all the TOE rx queues. The queues that don't get vectors
1891 * will forward their interrupts to those that do.
1892 *
1893 * Note: netmap rx queues cannot be created early and so they
1894 * can't be setup to receive forwarded interrupts for others.
1781 */
1782 iaq->nirq = T4_EXTRA_INTR;
1895 */
1896 iaq->nirq = T4_EXTRA_INTR;
1783 iaq->nirq += n10g * max(nrxq10g, nofldrxq10g);
1784 iaq->nirq += n1g * max(nrxq1g, nofldrxq1g);
1897 if (nrxq10g >= nofldrxq10g) {
1898 iaq->intr_flags_10g = INTR_RXQ;
1899 iaq->nirq += n10g * nrxq10g;
1900#ifdef DEV_NETMAP
1901 iaq->nnmrxq10g = min(nnmrxq10g, nrxq10g);
1902#endif
1903 } else {
1904 iaq->intr_flags_10g = INTR_OFLD_RXQ;
1905 iaq->nirq += n10g * nofldrxq10g;
1906#ifdef DEV_NETMAP
1907 iaq->nnmrxq10g = min(nnmrxq10g, nofldrxq10g);
1908#endif
1909 }
1910 if (nrxq1g >= nofldrxq1g) {
1911 iaq->intr_flags_1g = INTR_RXQ;
1912 iaq->nirq += n1g * nrxq1g;
1913#ifdef DEV_NETMAP
1914 iaq->nnmrxq1g = min(nnmrxq1g, nrxq1g);
1915#endif
1916 } else {
1917 iaq->intr_flags_1g = INTR_OFLD_RXQ;
1918 iaq->nirq += n1g * nofldrxq1g;
1919#ifdef DEV_NETMAP
1920 iaq->nnmrxq1g = min(nnmrxq1g, nofldrxq1g);
1921#endif
1922 }
1785 if (iaq->nirq <= navail &&
1786 (itype != INTR_MSI || powerof2(iaq->nirq)))
1787 goto allocate;
1788
1789 /*
1790 * Next best option: an interrupt vector for errors, one for the
1791 * firmware event queue, and at least one per port. At this
1923 if (iaq->nirq <= navail &&
1924 (itype != INTR_MSI || powerof2(iaq->nirq)))
1925 goto allocate;
1926
1927 /*
1928 * Next best option: an interrupt vector for errors, one for the
1929 * firmware event queue, and at least one per port. At this
1792 * point we know we'll have to downsize nrxq or nofldrxq to fit
1793 * what's available to us.
1930 * point we know we'll have to downsize nrxq and/or nofldrxq
1931 * and/or nnmrxq to fit what's available to us.
1794 */
1795 iaq->nirq = T4_EXTRA_INTR;
1796 iaq->nirq += n10g + n1g;
1797 if (iaq->nirq <= navail) {
1798 int leftover = navail - iaq->nirq;
1799
1800 if (n10g > 0) {
1801 int target = max(nrxq10g, nofldrxq10g);
1802
1932 */
1933 iaq->nirq = T4_EXTRA_INTR;
1934 iaq->nirq += n10g + n1g;
1935 if (iaq->nirq <= navail) {
1936 int leftover = navail - iaq->nirq;
1937
1938 if (n10g > 0) {
1939 int target = max(nrxq10g, nofldrxq10g);
1940
1941 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ?
1942 INTR_RXQ : INTR_OFLD_RXQ;
1943
1803 n = 1;
1804 while (n < target && leftover >= n10g) {
1805 leftover -= n10g;
1806 iaq->nirq += n10g;
1807 n++;
1808 }
1809 iaq->nrxq10g = min(n, nrxq10g);
1810#ifdef TCP_OFFLOAD
1944 n = 1;
1945 while (n < target && leftover >= n10g) {
1946 leftover -= n10g;
1947 iaq->nirq += n10g;
1948 n++;
1949 }
1950 iaq->nrxq10g = min(n, nrxq10g);
1951#ifdef TCP_OFFLOAD
1811 if (is_offload(sc))
1812 iaq->nofldrxq10g = min(n, nofldrxq10g);
1952 iaq->nofldrxq10g = min(n, nofldrxq10g);
1813#endif
1953#endif
1954#ifdef DEV_NETMAP
1955 iaq->nnmrxq10g = min(n, nnmrxq10g);
1956#endif
1814 }
1815
1816 if (n1g > 0) {
1817 int target = max(nrxq1g, nofldrxq1g);
1818
1957 }
1958
1959 if (n1g > 0) {
1960 int target = max(nrxq1g, nofldrxq1g);
1961
1962 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ?
1963 INTR_RXQ : INTR_OFLD_RXQ;
1964
1819 n = 1;
1820 while (n < target && leftover >= n1g) {
1821 leftover -= n1g;
1822 iaq->nirq += n1g;
1823 n++;
1824 }
1825 iaq->nrxq1g = min(n, nrxq1g);
1826#ifdef TCP_OFFLOAD
1965 n = 1;
1966 while (n < target && leftover >= n1g) {
1967 leftover -= n1g;
1968 iaq->nirq += n1g;
1969 n++;
1970 }
1971 iaq->nrxq1g = min(n, nrxq1g);
1972#ifdef TCP_OFFLOAD
1827 if (is_offload(sc))
1828 iaq->nofldrxq1g = min(n, nofldrxq1g);
1973 iaq->nofldrxq1g = min(n, nofldrxq1g);
1829#endif
1974#endif
1975#ifdef DEV_NETMAP
1976 iaq->nnmrxq1g = min(n, nnmrxq1g);
1977#endif
1830 }
1831
1832 if (itype != INTR_MSI || powerof2(iaq->nirq))
1833 goto allocate;
1834 }
1835
1836 /*
1837 * Least desirable option: one interrupt vector for everything.
1838 */
1839 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
1978 }
1979
1980 if (itype != INTR_MSI || powerof2(iaq->nirq))
1981 goto allocate;
1982 }
1983
1984 /*
1985 * Least desirable option: one interrupt vector for everything.
1986 */
1987 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
1988 iaq->intr_flags_10g = iaq->intr_flags_1g = 0;
1840#ifdef TCP_OFFLOAD
1841 if (is_offload(sc))
1842 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
1843#endif
1989#ifdef TCP_OFFLOAD
1990 if (is_offload(sc))
1991 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
1992#endif
1993#ifdef DEV_NETMAP
1994 iaq->nnmrxq10g = iaq->nnmrxq1g = 1;
1995#endif
1844
1845allocate:
1846 navail = iaq->nirq;
1847 rc = 0;
1848 if (itype == INTR_MSIX)
1849 rc = pci_alloc_msix(sc->dev, &navail);
1850 else if (itype == INTR_MSI)
1851 rc = pci_alloc_msi(sc->dev, &navail);

--- 763 unchanged lines hidden (view full) ---

2615 snprintf(buf, sizeof(buf), "Chelsio %s %sNIC (rev %d), S/N:%s, "
2616 "P/N:%s, E/C:%s", p->vpd.id, is_offload(sc) ? "R" : "",
2617 chip_rev(sc), p->vpd.sn, p->vpd.pn, p->vpd.ec);
2618
2619 device_set_desc_copy(sc->dev, buf);
2620}
2621
2622static void
1996
1997allocate:
1998 navail = iaq->nirq;
1999 rc = 0;
2000 if (itype == INTR_MSIX)
2001 rc = pci_alloc_msix(sc->dev, &navail);
2002 else if (itype == INTR_MSI)
2003 rc = pci_alloc_msi(sc->dev, &navail);

--- 763 unchanged lines hidden (view full) ---

2767 snprintf(buf, sizeof(buf), "Chelsio %s %sNIC (rev %d), S/N:%s, "
2768 "P/N:%s, E/C:%s", p->vpd.id, is_offload(sc) ? "R" : "",
2769 chip_rev(sc), p->vpd.sn, p->vpd.pn, p->vpd.ec);
2770
2771 device_set_desc_copy(sc->dev, buf);
2772}
2773
2774static void
2623build_medialist(struct port_info *pi)
2775build_medialist(struct port_info *pi, struct ifmedia *media)
2624{
2776{
2625 struct ifmedia *media = &pi->media;
2626 int data, m;
2627
2628 PORT_LOCK(pi);
2629
2630 ifmedia_removeall(media);
2631
2632 m = IFM_ETHER | IFM_FDX;
2633 data = (pi->port_type << 8) | pi->mod_type;

--- 112 unchanged lines hidden (view full) ---

2746}
2747
2748#define FW_MAC_EXACT_CHUNK 7
2749
2750/*
2751 * Program the port's XGMAC based on parameters in ifnet. The caller also
2752 * indicates which parameters should be programmed (the rest are left alone).
2753 */
2777 int data, m;
2778
2779 PORT_LOCK(pi);
2780
2781 ifmedia_removeall(media);
2782
2783 m = IFM_ETHER | IFM_FDX;
2784 data = (pi->port_type << 8) | pi->mod_type;

--- 112 unchanged lines hidden (view full) ---

2897}
2898
2899#define FW_MAC_EXACT_CHUNK 7
2900
2901/*
2902 * Program the port's XGMAC based on parameters in ifnet. The caller also
2903 * indicates which parameters should be programmed (the rest are left alone).
2904 */
2754static int
2755update_mac_settings(struct port_info *pi, int flags)
2905int
2906update_mac_settings(struct ifnet *ifp, int flags)
2756{
2907{
2757 int rc;
2758 struct ifnet *ifp = pi->ifp;
2908 int rc = 0;
2909 struct port_info *pi = ifp->if_softc;
2759 struct adapter *sc = pi->adapter;
2760 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
2910 struct adapter *sc = pi->adapter;
2911 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
2912 uint16_t viid = 0xffff;
2913 int16_t *xact_addr_filt = NULL;
2761
2762 ASSERT_SYNCHRONIZED_OP(sc);
2763 KASSERT(flags, ("%s: not told what to update.", __func__));
2764
2914
2915 ASSERT_SYNCHRONIZED_OP(sc);
2916 KASSERT(flags, ("%s: not told what to update.", __func__));
2917
2918 if (ifp == pi->ifp) {
2919 viid = pi->viid;
2920 xact_addr_filt = &pi->xact_addr_filt;
2921 }
2922#ifdef DEV_NETMAP
2923 else if (ifp == pi->nm_ifp) {
2924 viid = pi->nm_viid;
2925 xact_addr_filt = &pi->nm_xact_addr_filt;
2926 }
2927#endif
2765 if (flags & XGMAC_MTU)
2766 mtu = ifp->if_mtu;
2767
2768 if (flags & XGMAC_PROMISC)
2769 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
2770
2771 if (flags & XGMAC_ALLMULTI)
2772 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
2773
2774 if (flags & XGMAC_VLANEX)
2775 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
2776
2928 if (flags & XGMAC_MTU)
2929 mtu = ifp->if_mtu;
2930
2931 if (flags & XGMAC_PROMISC)
2932 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
2933
2934 if (flags & XGMAC_ALLMULTI)
2935 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
2936
2937 if (flags & XGMAC_VLANEX)
2938 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
2939
2777 rc = -t4_set_rxmode(sc, sc->mbox, pi->viid, mtu, promisc, allmulti, 1,
2778 vlanex, false);
2779 if (rc) {
2780 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, rc);
2781 return (rc);
2940 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
2941 rc = -t4_set_rxmode(sc, sc->mbox, viid, mtu, promisc, allmulti,
2942 1, vlanex, false);
2943 if (rc) {
2944 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
2945 rc);
2946 return (rc);
2947 }
2782 }
2783
2784 if (flags & XGMAC_UCADDR) {
2785 uint8_t ucaddr[ETHER_ADDR_LEN];
2786
2787 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
2948 }
2949
2950 if (flags & XGMAC_UCADDR) {
2951 uint8_t ucaddr[ETHER_ADDR_LEN];
2952
2953 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
2788 rc = t4_change_mac(sc, sc->mbox, pi->viid, pi->xact_addr_filt,
2789 ucaddr, true, true);
2954 rc = t4_change_mac(sc, sc->mbox, viid, *xact_addr_filt, ucaddr,
2955 true, true);
2790 if (rc < 0) {
2791 rc = -rc;
2792 if_printf(ifp, "change_mac failed: %d\n", rc);
2793 return (rc);
2794 } else {
2956 if (rc < 0) {
2957 rc = -rc;
2958 if_printf(ifp, "change_mac failed: %d\n", rc);
2959 return (rc);
2960 } else {
2795 pi->xact_addr_filt = rc;
2961 *xact_addr_filt = rc;
2796 rc = 0;
2797 }
2798 }
2799
2800 if (flags & XGMAC_MCADDRS) {
2801 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
2802 int del = 1;
2803 uint64_t hash = 0;
2804 struct ifmultiaddr *ifma;
2805 int i = 0, j;
2806
2807 if_maddr_rlock(ifp);
2808 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2809 if (ifma->ifma_addr->sa_family != AF_LINK)
2810 continue;
2811 mcaddr[i++] =
2812 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2813
2814 if (i == FW_MAC_EXACT_CHUNK) {
2962 rc = 0;
2963 }
2964 }
2965
2966 if (flags & XGMAC_MCADDRS) {
2967 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
2968 int del = 1;
2969 uint64_t hash = 0;
2970 struct ifmultiaddr *ifma;
2971 int i = 0, j;
2972
2973 if_maddr_rlock(ifp);
2974 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2975 if (ifma->ifma_addr->sa_family != AF_LINK)
2976 continue;
2977 mcaddr[i++] =
2978 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2979
2980 if (i == FW_MAC_EXACT_CHUNK) {
2815 rc = t4_alloc_mac_filt(sc, sc->mbox, pi->viid,
2816 del, i, mcaddr, NULL, &hash, 0);
2981 rc = t4_alloc_mac_filt(sc, sc->mbox, viid, del,
2982 i, mcaddr, NULL, &hash, 0);
2817 if (rc < 0) {
2818 rc = -rc;
2819 for (j = 0; j < i; j++) {
2820 if_printf(ifp,
2821 "failed to add mc address"
2822 " %02x:%02x:%02x:"
2823 "%02x:%02x:%02x rc=%d\n",
2824 mcaddr[j][0], mcaddr[j][1],
2825 mcaddr[j][2], mcaddr[j][3],
2826 mcaddr[j][4], mcaddr[j][5],
2827 rc);
2828 }
2829 goto mcfail;
2830 }
2831 del = 0;
2832 i = 0;
2833 }
2834 }
2835 if (i > 0) {
2983 if (rc < 0) {
2984 rc = -rc;
2985 for (j = 0; j < i; j++) {
2986 if_printf(ifp,
2987 "failed to add mc address"
2988 " %02x:%02x:%02x:"
2989 "%02x:%02x:%02x rc=%d\n",
2990 mcaddr[j][0], mcaddr[j][1],
2991 mcaddr[j][2], mcaddr[j][3],
2992 mcaddr[j][4], mcaddr[j][5],
2993 rc);
2994 }
2995 goto mcfail;
2996 }
2997 del = 0;
2998 i = 0;
2999 }
3000 }
3001 if (i > 0) {
2836 rc = t4_alloc_mac_filt(sc, sc->mbox, pi->viid,
2837 del, i, mcaddr, NULL, &hash, 0);
3002 rc = t4_alloc_mac_filt(sc, sc->mbox, viid, del, i,
3003 mcaddr, NULL, &hash, 0);
2838 if (rc < 0) {
2839 rc = -rc;
2840 for (j = 0; j < i; j++) {
2841 if_printf(ifp,
2842 "failed to add mc address"
2843 " %02x:%02x:%02x:"
2844 "%02x:%02x:%02x rc=%d\n",
2845 mcaddr[j][0], mcaddr[j][1],
2846 mcaddr[j][2], mcaddr[j][3],
2847 mcaddr[j][4], mcaddr[j][5],
2848 rc);
2849 }
2850 goto mcfail;
2851 }
2852 }
2853
3004 if (rc < 0) {
3005 rc = -rc;
3006 for (j = 0; j < i; j++) {
3007 if_printf(ifp,
3008 "failed to add mc address"
3009 " %02x:%02x:%02x:"
3010 "%02x:%02x:%02x rc=%d\n",
3011 mcaddr[j][0], mcaddr[j][1],
3012 mcaddr[j][2], mcaddr[j][3],
3013 mcaddr[j][4], mcaddr[j][5],
3014 rc);
3015 }
3016 goto mcfail;
3017 }
3018 }
3019
2854 rc = -t4_set_addr_hash(sc, sc->mbox, pi->viid, 0, hash, 0);
3020 rc = -t4_set_addr_hash(sc, sc->mbox, viid, 0, hash, 0);
2855 if (rc != 0)
2856 if_printf(ifp, "failed to set mc address hash: %d", rc);
2857mcfail:
2858 if_maddr_runlock(ifp);
2859 }
2860
2861 return (rc);
2862}

--- 86 unchanged lines hidden (view full) ---

2949 if (!(sc->flags & FULL_INIT_DONE) &&
2950 ((rc = adapter_full_init(sc)) != 0))
2951 return (rc); /* error message displayed already */
2952
2953 if (!(pi->flags & PORT_INIT_DONE) &&
2954 ((rc = port_full_init(pi)) != 0))
2955 return (rc); /* error message displayed already */
2956
3021 if (rc != 0)
3022 if_printf(ifp, "failed to set mc address hash: %d", rc);
3023mcfail:
3024 if_maddr_runlock(ifp);
3025 }
3026
3027 return (rc);
3028}

--- 86 unchanged lines hidden (view full) ---

3115 if (!(sc->flags & FULL_INIT_DONE) &&
3116 ((rc = adapter_full_init(sc)) != 0))
3117 return (rc); /* error message displayed already */
3118
3119 if (!(pi->flags & PORT_INIT_DONE) &&
3120 ((rc = port_full_init(pi)) != 0))
3121 return (rc); /* error message displayed already */
3122
2957 rc = update_mac_settings(pi, XGMAC_ALL);
3123 rc = update_mac_settings(ifp, XGMAC_ALL);
2958 if (rc)
2959 goto done; /* error message displayed already */
2960
3124 if (rc)
3125 goto done; /* error message displayed already */
3126
2961 rc = -t4_link_start(sc, sc->mbox, pi->tx_chan, &pi->link_cfg);
2962 if (rc != 0) {
2963 if_printf(ifp, "start_link failed: %d\n", rc);
2964 goto done;
2965 }
2966
2967 rc = -t4_enable_vi(sc, sc->mbox, pi->viid, true, true);
2968 if (rc != 0) {
2969 if_printf(ifp, "enable_vi failed: %d\n", rc);
2970 goto done;
2971 }
2972
2973 /*
2974 * The first iq of the first port to come up is used for tracing.

--- 68 unchanged lines hidden (view full) ---

3043 int rc, rid, p, q;
3044 char s[8];
3045 struct irq *irq;
3046 struct port_info *pi;
3047 struct sge_rxq *rxq;
3048#ifdef TCP_OFFLOAD
3049 struct sge_ofld_rxq *ofld_rxq;
3050#endif
3127 rc = -t4_enable_vi(sc, sc->mbox, pi->viid, true, true);
3128 if (rc != 0) {
3129 if_printf(ifp, "enable_vi failed: %d\n", rc);
3130 goto done;
3131 }
3132
3133 /*
3134 * The first iq of the first port to come up is used for tracing.

--- 68 unchanged lines hidden (view full) ---

3203 int rc, rid, p, q;
3204 char s[8];
3205 struct irq *irq;
3206 struct port_info *pi;
3207 struct sge_rxq *rxq;
3208#ifdef TCP_OFFLOAD
3209 struct sge_ofld_rxq *ofld_rxq;
3210#endif
3211#ifdef DEV_NETMAP
3212 struct sge_nm_rxq *nm_rxq;
3213#endif
3051
3052 /*
3053 * Setup interrupts.
3054 */
3055 irq = &sc->irq[0];
3056 rid = sc->intr_type == INTR_INTX ? 0 : 1;
3214
3215 /*
3216 * Setup interrupts.
3217 */
3218 irq = &sc->irq[0];
3219 rid = sc->intr_type == INTR_INTX ? 0 : 1;
3057 if (sc->intr_count == 1) {
3058 KASSERT(!(sc->flags & INTR_DIRECT),
3059 ("%s: single interrupt && INTR_DIRECT?", __func__));
3220 if (sc->intr_count == 1)
3221 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
3060
3222
3061 rc = t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all");
3062 if (rc != 0)
3063 return (rc);
3064 } else {
3065 /* Multiple interrupts. */
3066 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3067 ("%s: too few intr.", __func__));
3223 /* Multiple interrupts. */
3224 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3225 ("%s: too few intr.", __func__));
3068
3226
3069 /* The first one is always error intr */
3070 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3071 if (rc != 0)
3072 return (rc);
3073 irq++;
3074 rid++;
3227 /* The first one is always error intr */
3228 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3229 if (rc != 0)
3230 return (rc);
3231 irq++;
3232 rid++;
3075
3233
3076 /* The second one is always the firmware event queue */
3077 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sc->sge.fwq,
3078 "evt");
3079 if (rc != 0)
3080 return (rc);
3081 irq++;
3082 rid++;
3234 /* The second one is always the firmware event queue */
3235 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sc->sge.fwq, "evt");
3236 if (rc != 0)
3237 return (rc);
3238 irq++;
3239 rid++;
3083
3240
3084 /*
3085 * Note that if INTR_DIRECT is not set then either the NIC rx
3086 * queues or (exclusive or) the TOE rx queueus will be taking
3087 * direct interrupts.
3088 *
3089 * There is no need to check for is_offload(sc) as nofldrxq
3090 * will be 0 if offload is disabled.
3091 */
3092 for_each_port(sc, p) {
3093 pi = sc->port[p];
3241 for_each_port(sc, p) {
3242 pi = sc->port[p];
3094
3243
3095#ifdef TCP_OFFLOAD
3096 /*
3097 * Skip over the NIC queues if they aren't taking direct
3098 * interrupts.
3099 */
3100 if (!(sc->flags & INTR_DIRECT) &&
3101 pi->nofldrxq > pi->nrxq)
3102 goto ofld_queues;
3103#endif
3104 rxq = &sc->sge.rxq[pi->first_rxq];
3105 for (q = 0; q < pi->nrxq; q++, rxq++) {
3244 if (pi->flags & INTR_RXQ) {
3245 for_each_rxq(pi, q, rxq) {
3106 snprintf(s, sizeof(s), "%d.%d", p, q);
3107 rc = t4_alloc_irq(sc, irq, rid, t4_intr, rxq,
3108 s);
3109 if (rc != 0)
3110 return (rc);
3111 irq++;
3112 rid++;
3113 }
3246 snprintf(s, sizeof(s), "%d.%d", p, q);
3247 rc = t4_alloc_irq(sc, irq, rid, t4_intr, rxq,
3248 s);
3249 if (rc != 0)
3250 return (rc);
3251 irq++;
3252 rid++;
3253 }
3114
3254 }
3115#ifdef TCP_OFFLOAD
3255#ifdef TCP_OFFLOAD
3116 /*
3117 * Skip over the offload queues if they aren't taking
3118 * direct interrupts.
3119 */
3120 if (!(sc->flags & INTR_DIRECT))
3121 continue;
3122ofld_queues:
3123 ofld_rxq = &sc->sge.ofld_rxq[pi->first_ofld_rxq];
3124 for (q = 0; q < pi->nofldrxq; q++, ofld_rxq++) {
3256 if (pi->flags & INTR_OFLD_RXQ) {
3257 for_each_ofld_rxq(pi, q, ofld_rxq) {
3125 snprintf(s, sizeof(s), "%d,%d", p, q);
3126 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
3127 ofld_rxq, s);
3128 if (rc != 0)
3129 return (rc);
3130 irq++;
3131 rid++;
3132 }
3258 snprintf(s, sizeof(s), "%d,%d", p, q);
3259 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
3260 ofld_rxq, s);
3261 if (rc != 0)
3262 return (rc);
3263 irq++;
3264 rid++;
3265 }
3266 }
3133#endif
3267#endif
3268#ifdef DEV_NETMAP
3269 if (pi->flags & INTR_NM_RXQ) {
3270 for_each_nm_rxq(pi, q, nm_rxq) {
3271 snprintf(s, sizeof(s), "%d-%d", p, q);
3272 rc = t4_alloc_irq(sc, irq, rid, t4_nm_intr,
3273 nm_rxq, s);
3274 if (rc != 0)
3275 return (rc);
3276 irq++;
3277 rid++;
3278 }
3134 }
3279 }
3280#endif
3135 }
3281 }
3282 MPASS(irq == &sc->irq[sc->intr_count]);
3136
3137 return (0);
3138}
3139
3283
3284 return (0);
3285}
3286
3140static int
3287int
3141adapter_full_init(struct adapter *sc)
3142{
3143 int rc, i;
3144
3145 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3146 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
3147 ("%s: FULL_INIT_DONE already", __func__));
3148

--- 21 unchanged lines hidden (view full) ---

3170 sc->flags |= FULL_INIT_DONE;
3171done:
3172 if (rc != 0)
3173 adapter_full_uninit(sc);
3174
3175 return (rc);
3176}
3177
3288adapter_full_init(struct adapter *sc)
3289{
3290 int rc, i;
3291
3292 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3293 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
3294 ("%s: FULL_INIT_DONE already", __func__));
3295

--- 21 unchanged lines hidden (view full) ---

3317 sc->flags |= FULL_INIT_DONE;
3318done:
3319 if (rc != 0)
3320 adapter_full_uninit(sc);
3321
3322 return (rc);
3323}
3324
3178static int
3325int
3179adapter_full_uninit(struct adapter *sc)
3180{
3181 int i;
3182
3183 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3184
3185 t4_teardown_adapter_queues(sc);
3186
3187 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
3188 taskqueue_free(sc->tq[i]);
3189 sc->tq[i] = NULL;
3190 }
3191
3192 sc->flags &= ~FULL_INIT_DONE;
3193
3194 return (0);
3195}
3196
3326adapter_full_uninit(struct adapter *sc)
3327{
3328 int i;
3329
3330 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3331
3332 t4_teardown_adapter_queues(sc);
3333
3334 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
3335 taskqueue_free(sc->tq[i]);
3336 sc->tq[i] = NULL;
3337 }
3338
3339 sc->flags &= ~FULL_INIT_DONE;
3340
3341 return (0);
3342}
3343
3197static int
3344int
3198port_full_init(struct port_info *pi)
3199{
3200 struct adapter *sc = pi->adapter;
3201 struct ifnet *ifp = pi->ifp;
3202 uint16_t *rss;
3203 struct sge_rxq *rxq;
3204 int rc, i, j;
3205

--- 37 unchanged lines hidden (view full) ---

3243 port_full_uninit(pi);
3244
3245 return (rc);
3246}
3247
3248/*
3249 * Idempotent.
3250 */
3345port_full_init(struct port_info *pi)
3346{
3347 struct adapter *sc = pi->adapter;
3348 struct ifnet *ifp = pi->ifp;
3349 uint16_t *rss;
3350 struct sge_rxq *rxq;
3351 int rc, i, j;
3352

--- 37 unchanged lines hidden (view full) ---

3390 port_full_uninit(pi);
3391
3392 return (rc);
3393}
3394
3395/*
3396 * Idempotent.
3397 */
3251static int
3398int
3252port_full_uninit(struct port_info *pi)
3253{
3254 struct adapter *sc = pi->adapter;
3255 int i;
3256 struct sge_rxq *rxq;
3257 struct sge_txq *txq;
3258#ifdef TCP_OFFLOAD
3259 struct sge_ofld_rxq *ofld_rxq;

--- 1316 unchanged lines hidden (view full) ---

4576 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
4577 CTLFLAG_RD, &pi->first_ofld_rxq, 0,
4578 "index of first TOE rx queue");
4579 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
4580 CTLFLAG_RD, &pi->first_ofld_txq, 0,
4581 "index of first TOE tx queue");
4582 }
4583#endif
3399port_full_uninit(struct port_info *pi)
3400{
3401 struct adapter *sc = pi->adapter;
3402 int i;
3403 struct sge_rxq *rxq;
3404 struct sge_txq *txq;
3405#ifdef TCP_OFFLOAD
3406 struct sge_ofld_rxq *ofld_rxq;

--- 1316 unchanged lines hidden (view full) ---

4723 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
4724 CTLFLAG_RD, &pi->first_ofld_rxq, 0,
4725 "index of first TOE rx queue");
4726 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
4727 CTLFLAG_RD, &pi->first_ofld_txq, 0,
4728 "index of first TOE tx queue");
4729 }
4730#endif
4731#ifdef DEV_NETMAP
4732 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
4733 &pi->nnmrxq, 0, "# of rx queues for netmap");
4734 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
4735 &pi->nnmtxq, 0, "# of tx queues for netmap");
4736 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
4737 CTLFLAG_RD, &pi->first_nm_rxq, 0,
4738 "index of first netmap rx queue");
4739 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
4740 CTLFLAG_RD, &pi->first_nm_txq, 0,
4741 "index of first netmap tx queue");
4742#endif
4584
4585 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
4586 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_tmr_idx, "I",
4587 "holdoff timer index");
4588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
4589 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_pktc_idx, "I",
4590 "holdoff packet counter index");
4591

--- 2845 unchanged lines hidden (view full) ---

7437 if (fw_subcmd == FW_SCHED_SC_CONFIG) {
7438 /* Vet our parameters ..*/
7439 if (p->u.config.minmax < 0) {
7440 rc = EINVAL;
7441 goto done;
7442 }
7443
7444 /* And pass the request to the firmware ...*/
4743
4744 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
4745 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_tmr_idx, "I",
4746 "holdoff timer index");
4747 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
4748 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_pktc_idx, "I",
4749 "holdoff packet counter index");
4750

--- 2845 unchanged lines hidden (view full) ---

7596 if (fw_subcmd == FW_SCHED_SC_CONFIG) {
7597 /* Vet our parameters ..*/
7598 if (p->u.config.minmax < 0) {
7599 rc = EINVAL;
7600 goto done;
7601 }
7602
7603 /* And pass the request to the firmware ...*/
7445 rc = -t4_sched_config(sc, fw_type, p->u.config.minmax);
7604 rc = -t4_sched_config(sc, fw_type, p->u.config.minmax, 1);
7446 goto done;
7447 }
7448
7449 if (fw_subcmd == FW_SCHED_SC_PARAMS) {
7450 int fw_level;
7451 int fw_mode;
7452 int fw_rateunit;
7453 int fw_ratemode;

--- 81 unchanged lines hidden (view full) ---

7535 } else
7536 p->u.params.pktsize = 0;
7537 }
7538
7539 /* See what the firmware thinks of the request ... */
7540 rc = -t4_sched_params(sc, fw_type, fw_level, fw_mode,
7541 fw_rateunit, fw_ratemode, p->u.params.channel,
7542 p->u.params.cl, p->u.params.minrate, p->u.params.maxrate,
7605 goto done;
7606 }
7607
7608 if (fw_subcmd == FW_SCHED_SC_PARAMS) {
7609 int fw_level;
7610 int fw_mode;
7611 int fw_rateunit;
7612 int fw_ratemode;

--- 81 unchanged lines hidden (view full) ---

7694 } else
7695 p->u.params.pktsize = 0;
7696 }
7697
7698 /* See what the firmware thinks of the request ... */
7699 rc = -t4_sched_params(sc, fw_type, fw_level, fw_mode,
7700 fw_rateunit, fw_ratemode, p->u.params.channel,
7701 p->u.params.cl, p->u.params.minrate, p->u.params.maxrate,
7543 p->u.params.weight, p->u.params.pktsize);
7702 p->u.params.weight, p->u.params.pktsize, 1);
7544 goto done;
7545 }
7546
7547 rc = EINVAL;
7548done:
7549 end_synchronized_op(sc, 0);
7550 return (rc);
7551}

--- 322 unchanged lines hidden (view full) ---

7874 default:
7875 rc = EINVAL;
7876 }
7877
7878 return (rc);
7879}
7880
7881#ifdef TCP_OFFLOAD
7703 goto done;
7704 }
7705
7706 rc = EINVAL;
7707done:
7708 end_synchronized_op(sc, 0);
7709 return (rc);
7710}

--- 322 unchanged lines hidden (view full) ---

8033 default:
8034 rc = EINVAL;
8035 }
8036
8037 return (rc);
8038}
8039
8040#ifdef TCP_OFFLOAD
8041void
8042t4_iscsi_init(struct ifnet *ifp, unsigned int tag_mask,
8043 const unsigned int *pgsz_order)
8044{
8045 struct port_info *pi = ifp->if_softc;
8046 struct adapter *sc = pi->adapter;
8047
8048 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
8049 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
8050 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
8051 V_HPZ3(pgsz_order[3]));
8052}
8053
7882static int
7883toe_capability(struct port_info *pi, int enable)
7884{
7885 int rc;
7886 struct adapter *sc = pi->adapter;
7887
7888 ASSERT_SYNCHRONIZED_OP(sc);
7889

--- 172 unchanged lines hidden (view full) ---

8062
8063 if (t4_toecaps_allowed == -1)
8064 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
8065#else
8066 if (t4_toecaps_allowed == -1)
8067 t4_toecaps_allowed = 0;
8068#endif
8069
8054static int
8055toe_capability(struct port_info *pi, int enable)
8056{
8057 int rc;
8058 struct adapter *sc = pi->adapter;
8059
8060 ASSERT_SYNCHRONIZED_OP(sc);
8061

--- 172 unchanged lines hidden (view full) ---

8234
8235 if (t4_toecaps_allowed == -1)
8236 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
8237#else
8238 if (t4_toecaps_allowed == -1)
8239 t4_toecaps_allowed = 0;
8240#endif
8241
8242#ifdef DEV_NETMAP
8243 if (t4_nnmtxq10g < 1)
8244 t4_nnmtxq10g = min(nc, NNMTXQ_10G);
8245
8246 if (t4_nnmtxq1g < 1)
8247 t4_nnmtxq1g = min(nc, NNMTXQ_1G);
8248
8249 if (t4_nnmrxq10g < 1)
8250 t4_nnmrxq10g = min(nc, NNMRXQ_10G);
8251
8252 if (t4_nnmrxq1g < 1)
8253 t4_nnmrxq1g = min(nc, NNMRXQ_1G);
8254#endif
8255
8070 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
8071 t4_tmr_idx_10g = TMR_IDX_10G;
8072
8073 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
8074 t4_pktc_idx_10g = PKTC_IDX_10G;
8075
8076 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
8077 t4_tmr_idx_1g = TMR_IDX_1G;

--- 109 unchanged lines hidden --- 		8256 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
8257 t4_tmr_idx_10g = TMR_IDX_10G;
8258
8259 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
8260 t4_pktc_idx_10g = PKTC_IDX_10G;
8261
8262 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
8263 t4_tmr_idx_1g = TMR_IDX_1G;

--- 109 unchanged lines hidden ---