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t4fw_interface.h (256791) t4fw_interface.h (267849)
1/*-
1/*-
2 * Copyright (c) 2012 Chelsio Communications, Inc.
2 * Copyright (c) 2012-2014 Chelsio Communications, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 7 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 7 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/sys/dev/cxgbe/firmware/t4fw_interface.h 256791 2013-10-20 15:24:44Z np $
26 * $FreeBSD: stable/10/sys/dev/cxgbe/firmware/t4fw_interface.h 267849 2014-06-25 02:14:55Z np $
27 *
28 */
29
30#ifndef _T4FW_INTERFACE_H_
31#define _T4FW_INTERFACE_H_
32
33/******************************************************************************
34 * R E T U R N V A L U E S

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95enum fw_wr_opcodes {
96 FW_FRAG_WR = 0x1d,
97 FW_FILTER_WR = 0x02,
98 FW_ULPTX_WR = 0x04,
99 FW_TP_WR = 0x05,
100 FW_ETH_TX_PKT_WR = 0x08,
101 FW_ETH_TX_PKT2_WR = 0x44,
102 FW_ETH_TX_PKTS_WR = 0x09,
27 *
28 */
29
30#ifndef _T4FW_INTERFACE_H_
31#define _T4FW_INTERFACE_H_
32
33/******************************************************************************
34 * R E T U R N V A L U E S

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95enum fw_wr_opcodes {
96 FW_FRAG_WR = 0x1d,
97 FW_FILTER_WR = 0x02,
98 FW_ULPTX_WR = 0x04,
99 FW_TP_WR = 0x05,
100 FW_ETH_TX_PKT_WR = 0x08,
101 FW_ETH_TX_PKT2_WR = 0x44,
102 FW_ETH_TX_PKTS_WR = 0x09,
103 FW_ETH_TX_UO_WR = 0x1c,
103 FW_ETH_TX_EO_WR = 0x1c,
104 FW_EQ_FLUSH_WR = 0x1b,
105 FW_OFLD_CONNECTION_WR = 0x2f,
106 FW_FLOWC_WR = 0x0a,
107 FW_OFLD_TX_DATA_WR = 0x0b,
108 FW_CMD_WR = 0x10,
109 FW_ETH_TX_PKT_VM_WR = 0x11,
110 FW_RI_RES_WR = 0x0c,
111 FW_RI_RDMA_WRITE_WR = 0x14,

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642 __be32 op_pkd;
643 __be32 equiq_to_len16;
644 __be32 r3;
645 __be16 plen;
646 __u8 npkt;
647 __u8 type;
648};
649
104 FW_EQ_FLUSH_WR = 0x1b,
105 FW_OFLD_CONNECTION_WR = 0x2f,
106 FW_FLOWC_WR = 0x0a,
107 FW_OFLD_TX_DATA_WR = 0x0b,
108 FW_CMD_WR = 0x10,
109 FW_ETH_TX_PKT_VM_WR = 0x11,
110 FW_RI_RES_WR = 0x0c,
111 FW_RI_RDMA_WRITE_WR = 0x14,

--- 530 unchanged lines hidden (view full) ---

642 __be32 op_pkd;
643 __be32 equiq_to_len16;
644 __be32 r3;
645 __be16 plen;
646 __u8 npkt;
647 __u8 type;
648};
649
650struct fw_eth_tx_uo_wr {
650enum fw_eth_tx_eo_type {
651 FW_ETH_TX_EO_TYPE_UDPSEG,
652 FW_ETH_TX_EO_TYPE_TCPSEG,
653 FW_ETH_TX_EO_TYPE_NVGRESEG,
654};
655
656struct fw_eth_tx_eo_wr {
651 __be32 op_immdlen;
652 __be32 equiq_to_len16;
653 __be64 r3;
657 __be32 op_immdlen;
658 __be32 equiq_to_len16;
659 __be64 r3;
654 __u8 r4;
655 __u8 ethlen;
656 __be16 iplen;
657 __u8 udplen;
658 __u8 rtplen;
659 __be16 r5;
660 __be16 mss;
661 __be16 schedpktsize;
662 __be32 length;
660 union fw_eth_tx_eo {
661 struct fw_eth_tx_eo_udpseg {
662 __u8 type;
663 __u8 ethlen;
664 __be16 iplen;
665 __u8 udplen;
666 __u8 rtplen;
667 __be16 r4;
668 __be16 mss;
669 __be16 schedpktsize;
670 __be32 plen;
671 } udpseg;
672 struct fw_eth_tx_eo_tcpseg {
673 __u8 type;
674 __u8 ethlen;
675 __be16 iplen;
676 __u8 tcplen;
677 __u8 tsclk_tsoff;
678 __be16 r4;
679 __be16 mss;
680 __be16 r5;
681 __be32 plen;
682 } tcpseg;
683 struct fw_eth_tx_eo_nvgreseg {
684 __u8 type;
685 __u8 iphdroffout;
686 __be16 grehdroff;
687 __be16 iphdroffin;
688 __be16 tcphdroffin;
689 __be16 mss;
690 __be16 r4;
691 __be32 plen;
692 } nvgreseg;
693 } u;
663};
664
694};
695
696#define S_FW_ETH_TX_EO_WR_IMMDLEN 0
697#define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff
698#define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN)
699#define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \
700 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN)
701
702#define S_FW_ETH_TX_EO_WR_TSCLK 6
703#define M_FW_ETH_TX_EO_WR_TSCLK 0x3
704#define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK)
705#define G_FW_ETH_TX_EO_WR_TSCLK(x) \
706 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK)
707
708#define S_FW_ETH_TX_EO_WR_TSOFF 0
709#define M_FW_ETH_TX_EO_WR_TSOFF 0x3f
710#define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF)
711#define G_FW_ETH_TX_EO_WR_TSOFF(x) \
712 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF)
713
665struct fw_eq_flush_wr {
666 __u8 opcode;
667 __u8 r1[3];
668 __be32 equiq_to_len16;
669 __be64 r3;
670};
671
672struct fw_ofld_connection_wr {

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789 * received FIN
790 */
791 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
792 * waiting for FIN
793 */
794 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
795};
796
714struct fw_eq_flush_wr {
715 __u8 opcode;
716 __u8 r1[3];
717 __be32 equiq_to_len16;
718 __be64 r3;
719};
720
721struct fw_ofld_connection_wr {

--- 116 unchanged lines hidden (view full) ---

838 * received FIN
839 */
840 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
841 * waiting for FIN
842 */
843 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
844};
845
797enum fw_flowc_mnem_uostate {
798 FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */
799 FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */
800 FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, /* graceful close, after sending
846enum fw_flowc_mnem_eostate {
847 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */
848 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
849 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending
801 * outstanding payload
802 */
850 * outstanding payload
851 */
803 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, /* immediate close, after
852 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after
804 * discarding outstanding payload
805 */
806};
807
808enum fw_flowc_mnem {
809 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */
810 FW_FLOWC_MNEM_CH = 1,
811 FW_FLOWC_MNEM_PORT = 2,
812 FW_FLOWC_MNEM_IQID = 3,
813 FW_FLOWC_MNEM_SNDNXT = 4,
814 FW_FLOWC_MNEM_RCVNXT = 5,
815 FW_FLOWC_MNEM_SNDBUF = 6,
816 FW_FLOWC_MNEM_MSS = 7,
817 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8,
818 FW_FLOWC_MNEM_TCPSTATE = 9,
853 * discarding outstanding payload
854 */
855};
856
857enum fw_flowc_mnem {
858 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */
859 FW_FLOWC_MNEM_CH = 1,
860 FW_FLOWC_MNEM_PORT = 2,
861 FW_FLOWC_MNEM_IQID = 3,
862 FW_FLOWC_MNEM_SNDNXT = 4,
863 FW_FLOWC_MNEM_RCVNXT = 5,
864 FW_FLOWC_MNEM_SNDBUF = 6,
865 FW_FLOWC_MNEM_MSS = 7,
866 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8,
867 FW_FLOWC_MNEM_TCPSTATE = 9,
819 FW_FLOWC_MNEM_UOSTATE = 10,
868 FW_FLOWC_MNEM_EOSTATE = 10,
820 FW_FLOWC_MNEM_SCHEDCLASS = 11,
821 FW_FLOWC_MNEM_DCBPRIO = 12,
822};
823
824struct fw_flowc_mnemval {
825 __u8 mnemonic;
826 __u8 r4[3];
827 __be32 val;

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3520enum fw_caps_config_fcoe {
3521 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
3522 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
3523 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
3524 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
3525 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010,
3526};
3527
869 FW_FLOWC_MNEM_SCHEDCLASS = 11,
870 FW_FLOWC_MNEM_DCBPRIO = 12,
871};
872
873struct fw_flowc_mnemval {
874 __u8 mnemonic;
875 __u8 r4[3];
876 __be32 val;

--- 2692 unchanged lines hidden (view full) ---

3569enum fw_caps_config_fcoe {
3570 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
3571 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
3572 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
3573 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
3574 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010,
3575};
3576
3577enum fw_memtype_cf {
3578 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0,
3579 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1,
3580 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM,
3581 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
3582 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL,
3583 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1,
3584};
3585
3528struct fw_caps_config_cmd {
3529 __be32 op_to_write;
3530 __be32 cfvalid_to_len16;
3531 __be32 r2;
3532 __be32 hwmbitmap;
3533 __be16 nbmcaps;
3534 __be16 linkcaps;
3535 __be16 switchcaps;

--- 71 unchanged lines hidden (view full) ---

3607 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */
3608 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD
3609 */
3610 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD
3611 */
3612 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
3613 FW_PARAMS_PARAM_DEV_MCINIT = 0x16,
3614 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
3586struct fw_caps_config_cmd {
3587 __be32 op_to_write;
3588 __be32 cfvalid_to_len16;
3589 __be32 r2;
3590 __be32 hwmbitmap;
3591 __be16 nbmcaps;
3592 __be16 linkcaps;
3593 __be16 switchcaps;

--- 71 unchanged lines hidden (view full) ---

3665 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */
3666 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD
3667 */
3668 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD
3669 */
3670 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
3671 FW_PARAMS_PARAM_DEV_MCINIT = 0x16,
3672 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
3673 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
3615};
3616
3617/*
3618 * physical and virtual function parameters
3619 */
3620enum fw_params_param_pfvf {
3621 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
3622 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,

--- 63 unchanged lines hidden (view full) ---

3686
3687 /* modes
3688 */
3689 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
3690 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1,
3691 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
3692};
3693
3674};
3675
3676/*
3677 * physical and virtual function parameters
3678 */
3679enum fw_params_param_pfvf {
3680 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
3681 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,

--- 63 unchanged lines hidden (view full) ---

3745
3746 /* modes
3747 */
3748 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
3749 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1,
3750 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
3751};
3752
3694enum fw_params_phyfw_actions {
3695 FW_PARAMS_PARAM_PHYFW_DOWNLOAD = 0x00,
3696 FW_PARAMS_PARAM_PHYFW_VERSION = 0x01,
3753enum fw_params_param_dev_phyfw {
3754 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
3755 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
3697};
3698
3699enum fw_params_param_dev_diag {
3756};
3757
3758enum fw_params_param_dev_diag {
3700 FW_PARAM_DEV_DIAG_TMP = 0x00,
3701 FW_PARAM_DEV_DIAG_VDD = 0x01,
3759 FW_PARAM_DEV_DIAG_TMP = 0x00,
3760 FW_PARAM_DEV_DIAG_VDD = 0x01,
3702};
3703
3761};
3762
3763enum fw_params_param_dev_fwcache {
3764 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00,
3765 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01,
3766};
3767
3704#define S_FW_PARAMS_MNEM 24
3705#define M_FW_PARAMS_MNEM 0xff
3706#define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
3707#define G_FW_PARAMS_MNEM(x) \
3708 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
3709
3710#define S_FW_PARAMS_PARAM_X 16
3711#define M_FW_PARAMS_PARAM_X 0xff

--- 836 unchanged lines hidden (view full) ---

4548struct fw_eq_eth_cmd {
4549 __be32 op_to_vfn;
4550 __be32 alloc_to_len16;
4551 __be32 eqid_pkd;
4552 __be32 physeqid_pkd;
4553 __be32 fetchszm_to_iqid;
4554 __be32 dcaen_to_eqsize;
4555 __be64 eqaddr;
3768#define S_FW_PARAMS_MNEM 24
3769#define M_FW_PARAMS_MNEM 0xff
3770#define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
3771#define G_FW_PARAMS_MNEM(x) \
3772 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
3773
3774#define S_FW_PARAMS_PARAM_X 16
3775#define M_FW_PARAMS_PARAM_X 0xff

--- 836 unchanged lines hidden (view full) ---

4612struct fw_eq_eth_cmd {
4613 __be32 op_to_vfn;
4614 __be32 alloc_to_len16;
4615 __be32 eqid_pkd;
4616 __be32 physeqid_pkd;
4617 __be32 fetchszm_to_iqid;
4618 __be32 dcaen_to_eqsize;
4619 __be64 eqaddr;
4556 __be32 viid_pkd;
4620 __be32 autoequiqe_to_viid;
4557 __be32 r8_lo;
4558 __be64 r9;
4559};
4560
4561#define S_FW_EQ_ETH_CMD_PFN 8
4562#define M_FW_EQ_ETH_CMD_PFN 0x7
4563#define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
4564#define G_FW_EQ_ETH_CMD_PFN(x) \

--- 158 unchanged lines hidden (view full) ---

4723 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
4724
4725#define S_FW_EQ_ETH_CMD_EQSIZE 0
4726#define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
4727#define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
4728#define G_FW_EQ_ETH_CMD_EQSIZE(x) \
4729 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
4730
4621 __be32 r8_lo;
4622 __be64 r9;
4623};
4624
4625#define S_FW_EQ_ETH_CMD_PFN 8
4626#define M_FW_EQ_ETH_CMD_PFN 0x7
4627#define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
4628#define G_FW_EQ_ETH_CMD_PFN(x) \

--- 158 unchanged lines hidden (view full) ---

4787 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
4788
4789#define S_FW_EQ_ETH_CMD_EQSIZE 0
4790#define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
4791#define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
4792#define G_FW_EQ_ETH_CMD_EQSIZE(x) \
4793 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
4794
4795#define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31
4796#define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1
4797#define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE)
4798#define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \
4799 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE)
4800#define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U)
4801
4802#define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
4803#define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
4804#define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
4805#define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
4806 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
4807#define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
4808
4731#define S_FW_EQ_ETH_CMD_VIID 16
4732#define M_FW_EQ_ETH_CMD_VIID 0xfff
4733#define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
4734#define G_FW_EQ_ETH_CMD_VIID(x) \
4735 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
4736
4737struct fw_eq_ctrl_cmd {
4738 __be32 op_to_vfn;

--- 936 unchanged lines hidden (view full) ---

5675 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
5676 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
5677 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
5678 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
5679 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
5680 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
5681 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
5682 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
4809#define S_FW_EQ_ETH_CMD_VIID 16
4810#define M_FW_EQ_ETH_CMD_VIID 0xfff
4811#define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
4812#define G_FW_EQ_ETH_CMD_VIID(x) \
4813 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
4814
4815struct fw_eq_ctrl_cmd {
4816 __be32 op_to_vfn;

--- 936 unchanged lines hidden (view full) ---

5753 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
5754 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
5755 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
5756 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
5757 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
5758 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
5759 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
5760 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
5683 FW_PORT_ACTION_L1_SS_LPBK_ASIC = 0x0021,
5684 FW_PORT_ACTION_MAC_LPBK = 0x0022,
5685 FW_PORT_ACTION_L1_WS_LPBK_ASIC = 0x0023,
5686 FW_PORT_ACTION_L1_EXT_LPBK = 0x0026,
5761 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022,
5762 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023,
5763 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025,
5764 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026,
5687 FW_PORT_ACTION_DIAGNOSTICS = 0x0027,
5765 FW_PORT_ACTION_DIAGNOSTICS = 0x0027,
5688 FW_PORT_ACTION_PCS_LPBK = 0x0028,
5766 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028,
5689 FW_PORT_ACTION_PHY_RESET = 0x0040,
5690 FW_PORT_ACTION_PMA_RESET = 0x0041,
5691 FW_PORT_ACTION_PCS_RESET = 0x0042,
5692 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
5693 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
5694 FW_PORT_ACTION_AN_RESET = 0x0045,
5767 FW_PORT_ACTION_PHY_RESET = 0x0040,
5768 FW_PORT_ACTION_PMA_RESET = 0x0041,
5769 FW_PORT_ACTION_PCS_RESET = 0x0042,
5770 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
5771 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
5772 FW_PORT_ACTION_AN_RESET = 0x0045,
5773
5695};
5696
5697enum fw_port_l2cfg_ctlbf {
5698 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
5699 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
5700 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
5701 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
5702 FW_PORT_L2_CTLBF_IVLAN = 0x10,
5703 FW_PORT_L2_CTLBF_TXIPG = 0x20,
5704 FW_PORT_L2_CTLBF_MTU = 0x40
5705};
5706
5774};
5775
5776enum fw_port_l2cfg_ctlbf {
5777 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
5778 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
5779 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
5780 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
5781 FW_PORT_L2_CTLBF_IVLAN = 0x10,
5782 FW_PORT_L2_CTLBF_TXIPG = 0x20,
5783 FW_PORT_L2_CTLBF_MTU = 0x40
5784};
5785
5786enum fw_dcb_app_tlv_sf {
5787 FW_DCB_APP_SF_ETHERTYPE,
5788 FW_DCB_APP_SF_SOCKET_TCP,
5789 FW_DCB_APP_SF_SOCKET_UDP,
5790 FW_DCB_APP_SF_SOCKET_ALL,
5791};
5792
5793enum fw_port_dcb_versions {
5794 FW_PORT_DCB_VER_CEE1D0,
5795 FW_PORT_DCB_VER_CEE1D01,
5796 FW_PORT_DCB_VER_IEEE,
5797 FW_PORT_DCB_VER_UNKNOWN=7
5798};
5799
5707enum fw_port_dcb_cfg {
5708 FW_PORT_DCB_CFG_PG = 0x01,
5709 FW_PORT_DCB_CFG_PFC = 0x02,
5710 FW_PORT_DCB_CFG_APPL = 0x04
5711};
5712
5713enum fw_port_dcb_cfg_rc {
5714 FW_PORT_DCB_CFG_SUCCESS = 0x0,

--- 4 unchanged lines hidden (view full) ---

5719 FW_PORT_DCB_TYPE_PGID = 0x00,
5720 FW_PORT_DCB_TYPE_PGRATE = 0x01,
5721 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
5722 FW_PORT_DCB_TYPE_PFC = 0x03,
5723 FW_PORT_DCB_TYPE_APP_ID = 0x04,
5724 FW_PORT_DCB_TYPE_CONTROL = 0x05,
5725};
5726
5800enum fw_port_dcb_cfg {
5801 FW_PORT_DCB_CFG_PG = 0x01,
5802 FW_PORT_DCB_CFG_PFC = 0x02,
5803 FW_PORT_DCB_CFG_APPL = 0x04
5804};
5805
5806enum fw_port_dcb_cfg_rc {
5807 FW_PORT_DCB_CFG_SUCCESS = 0x0,

--- 4 unchanged lines hidden (view full) ---

5812 FW_PORT_DCB_TYPE_PGID = 0x00,
5813 FW_PORT_DCB_TYPE_PGRATE = 0x01,
5814 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
5815 FW_PORT_DCB_TYPE_PFC = 0x03,
5816 FW_PORT_DCB_TYPE_APP_ID = 0x04,
5817 FW_PORT_DCB_TYPE_CONTROL = 0x05,
5818};
5819
5820enum fw_port_dcb_feature_state {
5821 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
5822 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
5823 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
5824 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
5825};
5826
5727enum fw_port_diag_ops {
5728 FW_PORT_DIAGS_TEMP = 0x00,
5729 FW_PORT_DIAGS_TX_POWER = 0x01,
5730 FW_PORT_DIAGS_RX_POWER = 0x02,
5827enum fw_port_diag_ops {
5828 FW_PORT_DIAGS_TEMP = 0x00,
5829 FW_PORT_DIAGS_TX_POWER = 0x01,
5830 FW_PORT_DIAGS_RX_POWER = 0x02,
5831 FW_PORT_DIAGS_TX_DIS = 0x03,
5731};
5732
5733struct fw_port_cmd {
5734 __be32 op_to_portid;
5735 __be32 action_to_len16;
5736 union fw_port {
5737 struct fw_port_l1cfg {
5738 __be32 rcap;

--- 16 unchanged lines hidden (view full) ---

5755 } l2cfg;
5756 struct fw_port_info {
5757 __be32 lstatus_to_modtype;
5758 __be16 pcap;
5759 __be16 acap;
5760 __be16 mtu;
5761 __u8 cbllen;
5762 __u8 auxlinfo;
5832};
5833
5834struct fw_port_cmd {
5835 __be32 op_to_portid;
5836 __be32 action_to_len16;
5837 union fw_port {
5838 struct fw_port_l1cfg {
5839 __be32 rcap;

--- 16 unchanged lines hidden (view full) ---

5856 } l2cfg;
5857 struct fw_port_info {
5858 __be32 lstatus_to_modtype;
5859 __be16 pcap;
5860 __be16 acap;
5861 __be16 mtu;
5862 __u8 cbllen;
5863 __u8 auxlinfo;
5763 __be32 r8;
5864 __u8 dcbxdis_pkd;
5865 __u8 r8_lo;
5866 __be16 lpcap;
5764 __be64 r9;
5765 } info;
5766 struct fw_port_diags {
5767 __u8 diagop;
5768 __u8 r[3];
5769 __be32 diagval;
5770 } diags;
5771 union fw_port_dcb {

--- 15 unchanged lines hidden (view full) ---

5787 __u8 type;
5788 __u8 apply_pkd;
5789 __u8 r10_lo[6];
5790 __u8 strict_priorate[8];
5791 } priorate;
5792 struct fw_port_dcb_pfc {
5793 __u8 type;
5794 __u8 pfcen;
5867 __be64 r9;
5868 } info;
5869 struct fw_port_diags {
5870 __u8 diagop;
5871 __u8 r[3];
5872 __be32 diagval;
5873 } diags;
5874 union fw_port_dcb {

--- 15 unchanged lines hidden (view full) ---

5890 __u8 type;
5891 __u8 apply_pkd;
5892 __u8 r10_lo[6];
5893 __u8 strict_priorate[8];
5894 } priorate;
5895 struct fw_port_dcb_pfc {
5896 __u8 type;
5897 __u8 pfcen;
5795 __be16 r10[3];
5898 __u8 r10[5];
5899 __u8 max_pfc_tcs;
5796 __be64 r11;
5797 } pfc;
5798 struct fw_port_app_priority {
5799 __u8 type;
5800 __u8 r10[2];
5801 __u8 idx;
5802 __u8 user_prio_map;
5803 __u8 sel_field;
5804 __be16 protocolid;
5805 __be64 r12;
5806 } app_priority;
5807 struct fw_port_dcb_control {
5808 __u8 type;
5809 __u8 all_syncd_pkd;
5900 __be64 r11;
5901 } pfc;
5902 struct fw_port_app_priority {
5903 __u8 type;
5904 __u8 r10[2];
5905 __u8 idx;
5906 __u8 user_prio_map;
5907 __u8 sel_field;
5908 __be16 protocolid;
5909 __be64 r12;
5910 } app_priority;
5911 struct fw_port_dcb_control {
5912 __u8 type;
5913 __u8 all_syncd_pkd;
5810 __be16 r10_lo[3];
5811 __be64 r11;
5914 __be16 pfc_state_to_app_state;
5915 __be32 r11;
5916 __be64 r12;
5812 } control;
5813 } dcb;
5814 } u;
5815};
5816
5817#define S_FW_PORT_CMD_READ 22
5818#define M_FW_PORT_CMD_READ 0x1
5819#define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ)

--- 128 unchanged lines hidden (view full) ---

5948 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
5949
5950#define S_FW_PORT_CMD_MODTYPE 0
5951#define M_FW_PORT_CMD_MODTYPE 0x1f
5952#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
5953#define G_FW_PORT_CMD_MODTYPE(x) \
5954 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
5955
5917 } control;
5918 } dcb;
5919 } u;
5920};
5921
5922#define S_FW_PORT_CMD_READ 22
5923#define M_FW_PORT_CMD_READ 0x1
5924#define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ)

--- 128 unchanged lines hidden (view full) ---

6053 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
6054
6055#define S_FW_PORT_CMD_MODTYPE 0
6056#define M_FW_PORT_CMD_MODTYPE 0x1f
6057#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
6058#define G_FW_PORT_CMD_MODTYPE(x) \
6059 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
6060
6061#define S_FW_PORT_CMD_DCBXDIS 7
6062#define M_FW_PORT_CMD_DCBXDIS 0x1
6063#define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS)
6064#define G_FW_PORT_CMD_DCBXDIS(x) \
6065 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS)
6066#define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U)
6067
5956#define S_FW_PORT_CMD_APPLY 7
5957#define M_FW_PORT_CMD_APPLY 0x1
5958#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY)
5959#define G_FW_PORT_CMD_APPLY(x) \
5960 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
5961#define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U)
5962
5963#define S_FW_PORT_CMD_ALL_SYNCD 7
5964#define M_FW_PORT_CMD_ALL_SYNCD 0x1
5965#define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD)
5966#define G_FW_PORT_CMD_ALL_SYNCD(x) \
5967 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
5968#define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U)
5969
6068#define S_FW_PORT_CMD_APPLY 7
6069#define M_FW_PORT_CMD_APPLY 0x1
6070#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY)
6071#define G_FW_PORT_CMD_APPLY(x) \
6072 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
6073#define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U)
6074
6075#define S_FW_PORT_CMD_ALL_SYNCD 7
6076#define M_FW_PORT_CMD_ALL_SYNCD 0x1
6077#define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD)
6078#define G_FW_PORT_CMD_ALL_SYNCD(x) \
6079 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
6080#define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U)
6081
6082#define S_FW_PORT_CMD_PFC_STATE 8
6083#define M_FW_PORT_CMD_PFC_STATE 0xf
6084#define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE)
6085#define G_FW_PORT_CMD_PFC_STATE(x) \
6086 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE)
6087
6088#define S_FW_PORT_CMD_ETS_STATE 4
6089#define M_FW_PORT_CMD_ETS_STATE 0xf
6090#define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE)
6091#define G_FW_PORT_CMD_ETS_STATE(x) \
6092 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE)
6093
6094#define S_FW_PORT_CMD_APP_STATE 0
6095#define M_FW_PORT_CMD_APP_STATE 0xf
6096#define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE)
6097#define G_FW_PORT_CMD_APP_STATE(x) \
6098 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)
6099
5970/*
5971 * These are configured into the VPD and hence tools that generate
5972 * VPD may use this enumeration.
5973 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
6100/*
6101 * These are configured into the VPD and hence tools that generate
6102 * VPD may use this enumeration.
6103 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
6104 *
6105 * REMEMBER:
6106 * Update the Common Code t4_hw.c:t4_get_port_type_description()
6107 * with any new Firmware Port Technology Types!
5974 */
5975enum fw_port_type {
5976 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
5977 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
5978 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
5979 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
5980 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
5981 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */

--- 1671 unchanged lines hidden (view full) ---

7653#define S_PCIE_FW_REGISTERED 0
7654#define M_PCIE_FW_REGISTERED 0xff
7655#define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED)
7656#define G_PCIE_FW_REGISTERED(x) \
7657 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
7658
7659
7660/******************************************************************************
6108 */
6109enum fw_port_type {
6110 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
6111 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
6112 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
6113 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
6114 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
6115 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */

--- 1671 unchanged lines hidden (view full) ---

7787#define S_PCIE_FW_REGISTERED 0
7788#define M_PCIE_FW_REGISTERED 0xff
7789#define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED)
7790#define G_PCIE_FW_REGISTERED(x) \
7791 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
7792
7793
7794/******************************************************************************
7795 * P C I E F W P F 0 R E G I S T E R
7796 **********************************************/
7797
7798/*
7799 * this register is available as 32-bit of persistent storage (accross
7800 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver
7801 * will not write it)
7802 */
7803
7804
7805/******************************************************************************
7661 * B I N A R Y H E A D E R F O R M A T
7662 **********************************************/
7663
7664/*
7665 * firmware binary header format
7666 */
7667struct fw_hdr {
7668 __u8 ver;

--- 46 unchanged lines hidden (view full) ---

7715#define M_FW_HDR_FW_VER_BUILD 0xff
7716#define V_FW_HDR_FW_VER_BUILD(x) \
7717 ((x) << S_FW_HDR_FW_VER_BUILD)
7718#define G_FW_HDR_FW_VER_BUILD(x) \
7719 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
7720
7721enum {
7722 T4FW_VERSION_MAJOR = 0x01,
7806 * B I N A R Y H E A D E R F O R M A T
7807 **********************************************/
7808
7809/*
7810 * firmware binary header format
7811 */
7812struct fw_hdr {
7813 __u8 ver;

--- 46 unchanged lines hidden (view full) ---

7860#define M_FW_HDR_FW_VER_BUILD 0xff
7861#define V_FW_HDR_FW_VER_BUILD(x) \
7862 ((x) << S_FW_HDR_FW_VER_BUILD)
7863#define G_FW_HDR_FW_VER_BUILD(x) \
7864 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
7865
7866enum {
7867 T4FW_VERSION_MAJOR = 0x01,
7723 T4FW_VERSION_MINOR = 0x09,
7724 T4FW_VERSION_MICRO = 0x0c,
7868 T4FW_VERSION_MINOR = 0x0b,
7869 T4FW_VERSION_MICRO = 0x1b,
7725 T4FW_VERSION_BUILD = 0x00,
7726
7727 T5FW_VERSION_MAJOR = 0x01,
7870 T4FW_VERSION_BUILD = 0x00,
7871
7872 T5FW_VERSION_MAJOR = 0x01,
7728 T5FW_VERSION_MINOR = 0x09,
7729 T5FW_VERSION_MICRO = 0x0c,
7873 T5FW_VERSION_MINOR = 0x0b,
7874 T5FW_VERSION_MICRO = 0x1b,
7730 T5FW_VERSION_BUILD = 0x00,
7731};
7732
7733enum {
7734 T4FW_HDR_INTFVER_NIC = 0x00,
7735 T4FW_HDR_INTFVER_VNIC = 0x00,
7736 T4FW_HDR_INTFVER_OFLD = 0x00,
7737 T4FW_HDR_INTFVER_RI = 0x00,

--- 25 unchanged lines hidden --- 		7875 T5FW_VERSION_BUILD = 0x00,
7876};
7877
7878enum {
7879 T4FW_HDR_INTFVER_NIC = 0x00,
7880 T4FW_HDR_INTFVER_VNIC = 0x00,
7881 T4FW_HDR_INTFVER_OFLD = 0x00,
7882 T4FW_HDR_INTFVER_RI = 0x00,

--- 25 unchanged lines hidden ---