t4fw_interface.h (256281) | t4fw_interface.h (256791) |
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1/*- 2 * Copyright (c) 2012 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2012 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
26 * $FreeBSD: stable/10/sys/dev/cxgbe/firmware/t4fw_interface.h 252661 2013-07-03 23:52:15Z np $ | 26 * $FreeBSD: stable/10/sys/dev/cxgbe/firmware/t4fw_interface.h 256791 2013-10-20 15:24:44Z np $ |
27 * 28 */ 29 30#ifndef _T4FW_INTERFACE_H_ 31#define _T4FW_INTERFACE_H_ 32 33/****************************************************************************** 34 * R E T U R N V A L U E S --- 36 unchanged lines hidden (view full) --- 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76}; 77 78/****************************************************************************** | 27 * 28 */ 29 30#ifndef _T4FW_INTERFACE_H_ 31#define _T4FW_INTERFACE_H_ 32 33/****************************************************************************** 34 * R E T U R N V A L U E S --- 36 unchanged lines hidden (view full) --- 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76}; 77 78/****************************************************************************** |
79 * M E M O R Y T Y P E s 80 ******************************/ 81 82enum fw_memtype { 83 FW_MEMTYPE_EDC0 = 0x0, 84 FW_MEMTYPE_EDC1 = 0x1, 85 FW_MEMTYPE_EXTMEM = 0x2, 86 FW_MEMTYPE_FLASH = 0x4, 87 FW_MEMTYPE_INTERNAL = 0x5, 88 FW_MEMTYPE_EXTMEM1 = 0x6, 89}; 90 91/****************************************************************************** |
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79 * W O R K R E Q U E S T s 80 ********************************/ 81 82enum fw_wr_opcodes { 83 FW_FRAG_WR = 0x1d, 84 FW_FILTER_WR = 0x02, 85 FW_ULPTX_WR = 0x04, 86 FW_TP_WR = 0x05, 87 FW_ETH_TX_PKT_WR = 0x08, | 92 * W O R K R E Q U E S T s 93 ********************************/ 94 95enum fw_wr_opcodes { 96 FW_FRAG_WR = 0x1d, 97 FW_FILTER_WR = 0x02, 98 FW_ULPTX_WR = 0x04, 99 FW_TP_WR = 0x05, 100 FW_ETH_TX_PKT_WR = 0x08, |
101 FW_ETH_TX_PKT2_WR = 0x44, |
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88 FW_ETH_TX_PKTS_WR = 0x09, 89 FW_ETH_TX_UO_WR = 0x1c, 90 FW_EQ_FLUSH_WR = 0x1b, 91 FW_OFLD_CONNECTION_WR = 0x2f, 92 FW_FLOWC_WR = 0x0a, 93 FW_OFLD_TX_DATA_WR = 0x0b, 94 FW_CMD_WR = 0x10, 95 FW_ETH_TX_PKT_VM_WR = 0x11, --- 465 unchanged lines hidden (view full) --- 561}; 562 563#define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 564#define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 565#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 566#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 567 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 568 | 102 FW_ETH_TX_PKTS_WR = 0x09, 103 FW_ETH_TX_UO_WR = 0x1c, 104 FW_EQ_FLUSH_WR = 0x1b, 105 FW_OFLD_CONNECTION_WR = 0x2f, 106 FW_FLOWC_WR = 0x0a, 107 FW_OFLD_TX_DATA_WR = 0x0b, 108 FW_CMD_WR = 0x10, 109 FW_ETH_TX_PKT_VM_WR = 0x11, --- 465 unchanged lines hidden (view full) --- 575}; 576 577#define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 578#define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 579#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 580#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 581 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 582 |
583struct fw_eth_tx_pkt2_wr { 584 __be32 op_immdlen; 585 __be32 equiq_to_len16; 586 __be32 r3; 587 __be32 L4ChkDisable_to_IpHdrLen; 588}; 589 590#define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 591#define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 592#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 593#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 594 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 595 596#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 597#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 598#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 599 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 600#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 601 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 602 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 603#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 604 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 605 606#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 607#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 608#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 609 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 610#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 611 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 612 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 613#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 614 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 615 616#define S_FW_ETH_TX_PKT2_WR_IVLAN 28 617#define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 618#define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 619#define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 620 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 621#define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 622 623#define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 624#define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 625#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 626#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 627 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 628 629#define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 630#define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 631#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 632#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 633 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 634 635#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 636#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 637#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 638#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 639 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 640 |
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569struct fw_eth_tx_pkts_wr { 570 __be32 op_pkd; 571 __be32 equiq_to_len16; 572 __be32 r3; 573 __be16 plen; 574 __u8 npkt; 575 __u8 type; 576}; --- 191 unchanged lines hidden (view full) --- 768#define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 769#define G_FW_FLOWC_WR_NPARAMS(x) \ 770 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 771 772struct fw_ofld_tx_data_wr { 773 __be32 op_to_immdlen; 774 __be32 flowid_len16; 775 __be32 plen; | 641struct fw_eth_tx_pkts_wr { 642 __be32 op_pkd; 643 __be32 equiq_to_len16; 644 __be32 r3; 645 __be16 plen; 646 __u8 npkt; 647 __u8 type; 648}; --- 191 unchanged lines hidden (view full) --- 840#define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 841#define G_FW_FLOWC_WR_NPARAMS(x) \ 842 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 843 844struct fw_ofld_tx_data_wr { 845 __be32 op_to_immdlen; 846 __be32 flowid_len16; 847 __be32 plen; |
776 __be32 tunnel_to_proxy; | 848 __be32 lsodisable_to_proxy; |
777}; 778 | 849}; 850 |
851#define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 852#define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 853#define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 854 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 855#define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 856 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 857 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 858#define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 859 860#define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 861#define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 862#define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 863 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 864#define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 865 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 866#define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 867 868#define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 869#define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 870#define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 871 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 872#define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 873 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 874 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 875#define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 876 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 877 |
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779#define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 780#define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 781#define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) 782#define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ 783 (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) 784#define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) 785 786#define S_FW_OFLD_TX_DATA_WR_SAVE 18 --- 2604 unchanged lines hidden (view full) --- 3391}; 3392 3393enum fw_caps_config_nic { 3394 FW_CAPS_CONFIG_NIC = 0x00000001, 3395 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 3396 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 3397 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 3398 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, | 878#define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 879#define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 880#define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) 881#define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ 882 (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) 883#define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) 884 885#define S_FW_OFLD_TX_DATA_WR_SAVE 18 --- 2604 unchanged lines hidden (view full) --- 3490}; 3491 3492enum fw_caps_config_nic { 3493 FW_CAPS_CONFIG_NIC = 0x00000001, 3494 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 3495 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 3496 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 3497 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, |
3498 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 3499 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, |
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3399}; 3400 3401enum fw_caps_config_toe { 3402 FW_CAPS_CONFIG_TOE = 0x00000001, 3403}; 3404 3405enum fw_caps_config_rdma { 3406 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, --- 12 unchanged lines hidden (view full) --- 3419enum fw_caps_config_fcoe { 3420 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3421 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3422 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3423 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 3424 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 3425}; 3426 | 3500}; 3501 3502enum fw_caps_config_toe { 3503 FW_CAPS_CONFIG_TOE = 0x00000001, 3504}; 3505 3506enum fw_caps_config_rdma { 3507 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, --- 12 unchanged lines hidden (view full) --- 3520enum fw_caps_config_fcoe { 3521 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3522 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3523 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3524 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 3525 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 3526}; 3527 |
3427enum fw_memtype_cf { 3428 FW_MEMTYPE_CF_EDC0 = 0x0, 3429 FW_MEMTYPE_CF_EDC1 = 0x1, 3430 FW_MEMTYPE_CF_EXTMEM = 0x2, 3431 FW_MEMTYPE_CF_FLASH = 0x4, 3432 FW_MEMTYPE_CF_INTERNAL = 0x5, 3433 FW_MEMTYPE_CF_EXTMEM1 = 0x6, 3434}; 3435 | |
3436struct fw_caps_config_cmd { 3437 __be32 op_to_write; 3438 __be32 cfvalid_to_len16; 3439 __be32 r2; 3440 __be32 hwmbitmap; 3441 __be16 nbmcaps; 3442 __be16 linkcaps; 3443 __be16 switchcaps; --- 2475 unchanged lines hidden (view full) --- 5919/* used by FW and tools may use this to generate VPD */ 5920enum fw_port_mod_sub_type { 5921 FW_PORT_MOD_SUB_TYPE_NA, 5922 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 5923 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 5924 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 5925 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 5926 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, | 3528struct fw_caps_config_cmd { 3529 __be32 op_to_write; 3530 __be32 cfvalid_to_len16; 3531 __be32 r2; 3532 __be32 hwmbitmap; 3533 __be16 nbmcaps; 3534 __be16 linkcaps; 3535 __be16 switchcaps; --- 2475 unchanged lines hidden (view full) --- 6011/* used by FW and tools may use this to generate VPD */ 6012enum fw_port_mod_sub_type { 6013 FW_PORT_MOD_SUB_TYPE_NA, 6014 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 6015 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 6016 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 6017 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 6018 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, |
6019 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, |
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5927 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 5928 5929 /* 5930 * The following will never been in the VPD. They are TWINAX cable 5931 * lengths decoded from SFP+ module i2c PROMs. These should almost 5932 * certainly go somewhere else ... 5933 */ 5934 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, --- 1687 unchanged lines hidden (view full) --- 7622#define M_FW_HDR_FW_VER_BUILD 0xff 7623#define V_FW_HDR_FW_VER_BUILD(x) \ 7624 ((x) << S_FW_HDR_FW_VER_BUILD) 7625#define G_FW_HDR_FW_VER_BUILD(x) \ 7626 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 7627 7628enum { 7629 T4FW_VERSION_MAJOR = 0x01, | 6020 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 6021 6022 /* 6023 * The following will never been in the VPD. They are TWINAX cable 6024 * lengths decoded from SFP+ module i2c PROMs. These should almost 6025 * certainly go somewhere else ... 6026 */ 6027 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, --- 1687 unchanged lines hidden (view full) --- 7715#define M_FW_HDR_FW_VER_BUILD 0xff 7716#define V_FW_HDR_FW_VER_BUILD(x) \ 7717 ((x) << S_FW_HDR_FW_VER_BUILD) 7718#define G_FW_HDR_FW_VER_BUILD(x) \ 7719 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 7720 7721enum { 7722 T4FW_VERSION_MAJOR = 0x01, |
7630 T4FW_VERSION_MINOR = 0x08, 7631 T4FW_VERSION_MICRO = 0x0b, | 7723 T4FW_VERSION_MINOR = 0x09, 7724 T4FW_VERSION_MICRO = 0x0c, |
7632 T4FW_VERSION_BUILD = 0x00, 7633 7634 T5FW_VERSION_MAJOR = 0x01, | 7725 T4FW_VERSION_BUILD = 0x00, 7726 7727 T5FW_VERSION_MAJOR = 0x01, |
7635 T5FW_VERSION_MINOR = 0x08, 7636 T5FW_VERSION_MICRO = 0x16, | 7728 T5FW_VERSION_MINOR = 0x09, 7729 T5FW_VERSION_MICRO = 0x0c, |
7637 T5FW_VERSION_BUILD = 0x00, 7638}; 7639 7640enum { 7641 T4FW_HDR_INTFVER_NIC = 0x00, 7642 T4FW_HDR_INTFVER_VNIC = 0x00, 7643 T4FW_HDR_INTFVER_OFLD = 0x00, 7644 T4FW_HDR_INTFVER_RI = 0x00, --- 25 unchanged lines hidden --- | 7730 T5FW_VERSION_BUILD = 0x00, 7731}; 7732 7733enum { 7734 T4FW_HDR_INTFVER_NIC = 0x00, 7735 T4FW_HDR_INTFVER_VNIC = 0x00, 7736 T4FW_HDR_INTFVER_OFLD = 0x00, 7737 T4FW_HDR_INTFVER_RI = 0x00, --- 25 unchanged lines hidden --- |