t4fw_interface.h (240443) | t4fw_interface.h (247289) |
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1/*- 2 * Copyright (c) 2012 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2012 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
26 * $FreeBSD: head/sys/dev/cxgbe/firmware/t4fw_interface.h 240443 2012-09-13 06:32:52Z np $ | 26 * $FreeBSD: head/sys/dev/cxgbe/firmware/t4fw_interface.h 247289 2013-02-26 00:10:28Z np $ |
27 * 28 */ 29 30#ifndef _T4FW_INTERFACE_H_ 31#define _T4FW_INTERFACE_H_ 32 33/****************************************************************************** 34 * R E T U R N V A L U E S --- 5 unchanged lines hidden (view full) --- 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ | 27 * 28 */ 29 30#ifndef _T4FW_INTERFACE_H_ 31#define _T4FW_INTERFACE_H_ 32 33/****************************************************************************** 34 * R E T U R N V A L U E S --- 5 unchanged lines hidden (view full) --- 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ |
48 FW_ENODEV = 19, /* no such device */ |
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48 FW_EINVAL = 22, /* invalid argument */ 49 FW_ENOSPC = 28, /* no space left on device */ 50 FW_ENOSYS = 38, /* functionality not implemented */ | 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ |
52 FW_ENODATA = 61, /* no data available */ |
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51 FW_EPROTO = 71, /* protocol error */ 52 FW_EADDRINUSE = 98, /* address already in use */ 53 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 54 FW_ENETDOWN = 100, /* network is down */ 55 FW_ENETUNREACH = 101, /* network is unreachable */ 56 FW_ENOBUFS = 105, /* no buffer space available */ 57 FW_ETIMEDOUT = 110, /* timeout */ 58 FW_EINPROGRESS = 115, /* fw internal */ --- 50 unchanged lines hidden (view full) --- 109 FW_FCOE_ELS_CT_WR = 0x30, 110 FW_SCSI_WRITE_WR = 0x31, 111 FW_SCSI_READ_WR = 0x32, 112 FW_SCSI_CMD_WR = 0x33, 113 FW_SCSI_ABRT_CLS_WR = 0x34, 114 FW_SCSI_TGT_ACC_WR = 0x35, 115 FW_SCSI_TGT_XMIT_WR = 0x36, 116 FW_SCSI_TGT_RSP_WR = 0x37, | 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ --- 50 unchanged lines hidden (view full) --- 111 FW_FCOE_ELS_CT_WR = 0x30, 112 FW_SCSI_WRITE_WR = 0x31, 113 FW_SCSI_READ_WR = 0x32, 114 FW_SCSI_CMD_WR = 0x33, 115 FW_SCSI_ABRT_CLS_WR = 0x34, 116 FW_SCSI_TGT_ACC_WR = 0x35, 117 FW_SCSI_TGT_XMIT_WR = 0x36, 118 FW_SCSI_TGT_RSP_WR = 0x37, |
119 FW_POFCOE_TCB_WR = 0x42, 120 FW_POFCOE_ULPTX_WR = 0x43, |
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117 FW_LASTC2E_WR = 0x70 118}; 119 120/* 121 * Generic work request header flit0 122 */ 123struct fw_wr_hdr { 124 __be32 hi; --- 426 unchanged lines hidden (view full) --- 551 __u8 npkt; 552 __u8 type; 553}; 554 555struct fw_eth_tx_uo_wr { 556 __be32 op_immdlen; 557 __be32 equiq_to_len16; 558 __be64 r3; | 121 FW_LASTC2E_WR = 0x70 122}; 123 124/* 125 * Generic work request header flit0 126 */ 127struct fw_wr_hdr { 128 __be32 hi; --- 426 unchanged lines hidden (view full) --- 555 __u8 npkt; 556 __u8 type; 557}; 558 559struct fw_eth_tx_uo_wr { 560 __be32 op_immdlen; 561 __be32 equiq_to_len16; 562 __be64 r3; |
559 __be16 ethlen; | 563 __u8 r4; 564 __u8 ethlen; |
560 __be16 iplen; | 565 __be16 iplen; |
561 __be16 udplen; | 566 __u8 udplen; 567 __u8 rtplen; 568 __be16 r5; |
562 __be16 mss; | 569 __be16 mss; |
570 __be16 schedpktsize; |
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563 __be32 length; | 571 __be32 length; |
564 __be32 r4; | |
565}; 566 567struct fw_eq_flush_wr { 568 __u8 opcode; 569 __u8 r1[3]; 570 __be32 equiq_to_len16; 571 __be64 r3; 572}; --- 130 unchanged lines hidden (view full) --- 703 * outstanding payload 704 */ 705 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, /* immediate close, after 706 * discarding outstanding payload 707 */ 708}; 709 710enum fw_flowc_mnem { | 572}; 573 574struct fw_eq_flush_wr { 575 __u8 opcode; 576 __u8 r1[3]; 577 __be32 equiq_to_len16; 578 __be64 r3; 579}; --- 130 unchanged lines hidden (view full) --- 710 * outstanding payload 711 */ 712 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, /* immediate close, after 713 * discarding outstanding payload 714 */ 715}; 716 717enum fw_flowc_mnem { |
711 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 712 FW_FLOWC_MNEM_CH, 713 FW_FLOWC_MNEM_PORT, 714 FW_FLOWC_MNEM_IQID, 715 FW_FLOWC_MNEM_SNDNXT, 716 FW_FLOWC_MNEM_RCVNXT, 717 FW_FLOWC_MNEM_SNDBUF, 718 FW_FLOWC_MNEM_MSS, 719 FW_FLOWC_MNEM_TXDATAPLEN_MAX, 720 FW_FLOWC_MNEM_TCPSTATE, 721 FW_FLOWC_MNEM_UOSTATE, 722 FW_FLOWC_MNEM_SCHEDCLASS, 723 FW_FLOWC_MNEM_DCBPRIO, | 718 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 719 FW_FLOWC_MNEM_CH = 1, 720 FW_FLOWC_MNEM_PORT = 2, 721 FW_FLOWC_MNEM_IQID = 3, 722 FW_FLOWC_MNEM_SNDNXT = 4, 723 FW_FLOWC_MNEM_RCVNXT = 5, 724 FW_FLOWC_MNEM_SNDBUF = 6, 725 FW_FLOWC_MNEM_MSS = 7, 726 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 727 FW_FLOWC_MNEM_TCPSTATE = 9, 728 FW_FLOWC_MNEM_UOSTATE = 10, 729 FW_FLOWC_MNEM_SCHEDCLASS = 11, 730 FW_FLOWC_MNEM_DCBPRIO = 12, |
724}; 725 726struct fw_flowc_mnemval { 727 __u8 mnemonic; 728 __u8 r4[3]; 729 __be32 val; 730}; 731 --- 2052 unchanged lines hidden (view full) --- 2784 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 2785 2786#define S_FW_SCSI_TGT_RSP_WR_CLASS 4 2787#define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 2788#define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 2789#define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 2790 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 2791 | 731}; 732 733struct fw_flowc_mnemval { 734 __u8 mnemonic; 735 __u8 r4[3]; 736 __be32 val; 737}; 738 --- 2052 unchanged lines hidden (view full) --- 2791 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 2792 2793#define S_FW_SCSI_TGT_RSP_WR_CLASS 4 2794#define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 2795#define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 2796#define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 2797 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 2798 |
2799struct fw_pofcoe_tcb_wr { 2800 __be32 op_compl; 2801 __be32 equiq_to_len16; 2802 __be64 cookie; 2803 __be32 tid_to_port; 2804 __be16 x_id; 2805 __be16 vlan_id; 2806 __be32 s_id; 2807 __be32 d_id; 2808 __be32 tag; 2809 __be32 xfer_len; 2810 __be32 r4; 2811 __be16 r5; 2812 __be16 iqid; 2813}; 2814 2815#define S_FW_POFCOE_TCB_WR_TID 12 2816#define M_FW_POFCOE_TCB_WR_TID 0xfffff 2817#define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 2818#define G_FW_POFCOE_TCB_WR_TID(x) \ 2819 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 2820 2821#define S_FW_POFCOE_TCB_WR_ALLOC 4 2822#define M_FW_POFCOE_TCB_WR_ALLOC 0x1 2823#define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 2824#define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 2825 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 2826#define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 2827 2828#define S_FW_POFCOE_TCB_WR_FREE 3 2829#define M_FW_POFCOE_TCB_WR_FREE 0x1 2830#define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 2831#define G_FW_POFCOE_TCB_WR_FREE(x) \ 2832 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 2833#define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 2834 2835#define S_FW_POFCOE_TCB_WR_PORT 0 2836#define M_FW_POFCOE_TCB_WR_PORT 0x7 2837#define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 2838#define G_FW_POFCOE_TCB_WR_PORT(x) \ 2839 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 2840 2841struct fw_pofcoe_ulptx_wr { 2842 __be32 op_pkd; 2843 __be32 equiq_to_len16; 2844 __u64 cookie; 2845}; 2846 2847 |
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2792/****************************************************************************** 2793 * C O M M A N D s 2794 *********************/ 2795 2796/* 2797 * The maximum length of time, in miliseconds, that we expect any firmware 2798 * command to take to execute and return a reply to the host. The RESET 2799 * and INITIALIZE commands can take a fair amount of time to execute but --- 132 unchanged lines hidden (view full) --- 2932 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 2933 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 2934 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 2935 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 2936 FW_LDST_ADDRSPC_MDIO = 0x0018, 2937 FW_LDST_ADDRSPC_MPS = 0x0020, 2938 FW_LDST_ADDRSPC_FUNC = 0x0028, 2939 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, | 2848/****************************************************************************** 2849 * C O M M A N D s 2850 *********************/ 2851 2852/* 2853 * The maximum length of time, in miliseconds, that we expect any firmware 2854 * command to take to execute and return a reply to the host. The RESET 2855 * and INITIALIZE commands can take a fair amount of time to execute but --- 132 unchanged lines hidden (view full) --- 2988 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 2989 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 2990 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 2991 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 2992 FW_LDST_ADDRSPC_MDIO = 0x0018, 2993 FW_LDST_ADDRSPC_MPS = 0x0020, 2994 FW_LDST_ADDRSPC_FUNC = 0x0028, 2995 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, |
2940 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, | 2996 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ |
2941 FW_LDST_ADDRSPC_LE = 0x0030, | 2997 FW_LDST_ADDRSPC_LE = 0x0030, |
2998 FW_LDST_ADDRSPC_I2C = 0x0038, |
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2942}; 2943 2944/* 2945 * MDIO VSC8634 register access control field 2946 */ 2947enum fw_ldst_mdio_vsc8634_aid { 2948 FW_LDST_MDIO_VS_STANDARD, 2949 FW_LDST_MDIO_VS_EXTENDED, --- 63 unchanged lines hidden (view full) --- 3013 __u8 bnum; 3014 __u8 r; 3015 __u8 ext_r; 3016 __u8 select_naccess; 3017 __u8 pcie_fn; 3018 __be16 nset_pkd; 3019 __be32 data[12]; 3020 } pcie; | 2999}; 3000 3001/* 3002 * MDIO VSC8634 register access control field 3003 */ 3004enum fw_ldst_mdio_vsc8634_aid { 3005 FW_LDST_MDIO_VS_STANDARD, 3006 FW_LDST_MDIO_VS_EXTENDED, --- 63 unchanged lines hidden (view full) --- 3070 __u8 bnum; 3071 __u8 r; 3072 __u8 ext_r; 3073 __u8 select_naccess; 3074 __u8 pcie_fn; 3075 __be16 nset_pkd; 3076 __be32 data[12]; 3077 } pcie; |
3021 struct fw_ldst_i2c { | 3078 struct fw_ldst_i2c_deprecated { |
3022 __u8 pid_pkd; 3023 __u8 base; 3024 __u8 boffset; 3025 __u8 data; 3026 __be32 r9; | 3079 __u8 pid_pkd; 3080 __u8 base; 3081 __u8 boffset; 3082 __u8 data; 3083 __be32 r9; |
3084 } i2c_deprecated; 3085 struct fw_ldst_i2c { 3086 __u8 pid; 3087 __u8 did; 3088 __u8 boffset; 3089 __u8 blen; 3090 __be32 r9; 3091 __u8 data[48]; |
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3027 } i2c; 3028 struct fw_ldst_le { | 3092 } i2c; 3093 struct fw_ldst_le { |
3029 __be16 region; 3030 __be16 nval; 3031 __u32 val[12]; | 3094 __be32 index; 3095 __be32 r9; 3096 __u8 val[33]; 3097 __u8 r11[7]; |
3032 } le; 3033 } u; 3034}; 3035 3036#define S_FW_LDST_CMD_ADDRSPACE 0 3037#define M_FW_LDST_CMD_ADDRSPACE 0xff 3038#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3039#define G_FW_LDST_CMD_ADDRSPACE(x) \ --- 287 unchanged lines hidden (view full) --- 3327 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 3328 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 3329}; 3330 3331enum fw_caps_config_fcoe { 3332 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3333 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3334 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, | 3098 } le; 3099 } u; 3100}; 3101 3102#define S_FW_LDST_CMD_ADDRSPACE 0 3103#define M_FW_LDST_CMD_ADDRSPACE 0xff 3104#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3105#define G_FW_LDST_CMD_ADDRSPACE(x) \ --- 287 unchanged lines hidden (view full) --- 3393 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 3394 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 3395}; 3396 3397enum fw_caps_config_fcoe { 3398 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3399 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3400 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, |
3401 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 3402 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, |
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3335}; 3336 3337enum fw_memtype_cf { 3338 FW_MEMTYPE_CF_EDC0 = 0x0, 3339 FW_MEMTYPE_CF_EDC1 = 0x1, 3340 FW_MEMTYPE_CF_EXTMEM = 0x2, 3341 FW_MEMTYPE_CF_FLASH = 0x4, 3342 FW_MEMTYPE_CF_INTERNAL = 0x5, --- 117 unchanged lines hidden (view full) --- 3460 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 3461 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 3462 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 3463 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 3464 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 3465 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 3466 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 3467 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, | 3403}; 3404 3405enum fw_memtype_cf { 3406 FW_MEMTYPE_CF_EDC0 = 0x0, 3407 FW_MEMTYPE_CF_EDC1 = 0x1, 3408 FW_MEMTYPE_CF_EXTMEM = 0x2, 3409 FW_MEMTYPE_CF_FLASH = 0x4, 3410 FW_MEMTYPE_CF_INTERNAL = 0x5, --- 117 unchanged lines hidden (view full) --- 3528 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 3529 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 3530 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 3531 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 3532 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 3533 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 3534 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 3535 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, |
3468 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30 | 3536 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 3537 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_CPLSGEEGRUPDATE = 0x31 |
3469}; 3470 3471/* 3472 * dma queue parameters 3473 */ 3474enum fw_params_param_dmaq { 3475 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 3476 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, | 3538}; 3539 3540/* 3541 * dma queue parameters 3542 */ 3543enum fw_params_param_dmaq { 3544 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 3545 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, |
3546 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, |
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3477 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 3478 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 3479 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 3480 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13 3481}; 3482 3483/* 3484 * dev bypass parameters; actions and modes --- 1453 unchanged lines hidden (view full) --- 4938struct fw_vi_cmd { 4939 __be32 op_to_vfn; 4940 __be32 alloc_to_len16; 4941 __be16 type_to_viid; 4942 __u8 mac[6]; 4943 __u8 portid_pkd; 4944 __u8 nmac; 4945 __u8 nmac0[6]; | 3547 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 3548 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 3549 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 3550 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13 3551}; 3552 3553/* 3554 * dev bypass parameters; actions and modes --- 1453 unchanged lines hidden (view full) --- 5008struct fw_vi_cmd { 5009 __be32 op_to_vfn; 5010 __be32 alloc_to_len16; 5011 __be16 type_to_viid; 5012 __u8 mac[6]; 5013 __u8 portid_pkd; 5014 __u8 nmac; 5015 __u8 nmac0[6]; |
4946 __be16 rsssize_pkd; | 5016 __be16 norss_rsssize; |
4947 __u8 nmac1[6]; 4948 __be16 idsiiq_pkd; 4949 __u8 nmac2[6]; 4950 __be16 idseiq_pkd; 4951 __u8 nmac3[6]; 4952 __be64 r9; 4953 __be64 r10; 4954}; --- 38 unchanged lines hidden (view full) --- 4993#define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 4994 4995#define S_FW_VI_CMD_PORTID 4 4996#define M_FW_VI_CMD_PORTID 0xf 4997#define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 4998#define G_FW_VI_CMD_PORTID(x) \ 4999 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 5000 | 5017 __u8 nmac1[6]; 5018 __be16 idsiiq_pkd; 5019 __u8 nmac2[6]; 5020 __be16 idseiq_pkd; 5021 __u8 nmac3[6]; 5022 __be64 r9; 5023 __be64 r10; 5024}; --- 38 unchanged lines hidden (view full) --- 5063#define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 5064 5065#define S_FW_VI_CMD_PORTID 4 5066#define M_FW_VI_CMD_PORTID 0xf 5067#define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 5068#define G_FW_VI_CMD_PORTID(x) \ 5069 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 5070 |
5071#define S_FW_VI_CMD_NORSS 11 5072#define M_FW_VI_CMD_NORSS 0x1 5073#define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 5074#define G_FW_VI_CMD_NORSS(x) \ 5075 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 5076#define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 5077 |
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5001#define S_FW_VI_CMD_RSSSIZE 0 5002#define M_FW_VI_CMD_RSSSIZE 0x7ff 5003#define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 5004#define G_FW_VI_CMD_RSSSIZE(x) \ 5005 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 5006 5007#define S_FW_VI_CMD_IDSIIQ 0 5008#define M_FW_VI_CMD_IDSIIQ 0x3ff --- 510 unchanged lines hidden (view full) --- 5519 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 5520 FW_PORT_DCB_TYPE_PFC = 0x03, 5521 FW_PORT_DCB_TYPE_APP_ID = 0x04, 5522 FW_PORT_DCB_TYPE_CONTROL = 0x05, 5523}; 5524 5525enum fw_port_diag_ops { 5526 FW_PORT_DIAGS_TEMP = 0x00, | 5078#define S_FW_VI_CMD_RSSSIZE 0 5079#define M_FW_VI_CMD_RSSSIZE 0x7ff 5080#define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 5081#define G_FW_VI_CMD_RSSSIZE(x) \ 5082 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 5083 5084#define S_FW_VI_CMD_IDSIIQ 0 5085#define M_FW_VI_CMD_IDSIIQ 0x3ff --- 510 unchanged lines hidden (view full) --- 5596 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 5597 FW_PORT_DCB_TYPE_PFC = 0x03, 5598 FW_PORT_DCB_TYPE_APP_ID = 0x04, 5599 FW_PORT_DCB_TYPE_CONTROL = 0x05, 5600}; 5601 5602enum fw_port_diag_ops { 5603 FW_PORT_DIAGS_TEMP = 0x00, |
5604 FW_PORT_DIAGS_TX_POWER = 0x01, 5605 FW_PORT_DIAGS_RX_POWER = 0x02, |
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5527}; 5528 5529struct fw_port_cmd { 5530 __be32 op_to_portid; 5531 __be32 action_to_len16; 5532 union fw_port { 5533 struct fw_port_l1cfg { 5534 __be32 rcap; --- 20 unchanged lines hidden (view full) --- 5555 __be16 acap; 5556 __be16 mtu; 5557 __u8 cbllen; 5558 __u8 auxlinfo; 5559 __be32 r8; 5560 __be64 r9; 5561 } info; 5562 struct fw_port_diags { | 5606}; 5607 5608struct fw_port_cmd { 5609 __be32 op_to_portid; 5610 __be32 action_to_len16; 5611 union fw_port { 5612 struct fw_port_l1cfg { 5613 __be32 rcap; --- 20 unchanged lines hidden (view full) --- 5634 __be16 acap; 5635 __be16 mtu; 5636 __u8 cbllen; 5637 __u8 auxlinfo; 5638 __be32 r8; 5639 __be64 r9; 5640 } info; 5641 struct fw_port_diags { |
5563 __be32 diagop_diagval; 5564 __be32 r; | 5642 __u8 diagop; 5643 __u8 r[3]; 5644 __be32 diagval; |
5565 } diags; 5566 union fw_port_dcb { 5567 struct fw_port_dcb_pgid { 5568 __u8 type; 5569 __u8 apply_pkd; 5570 __u8 r10_lo[2]; 5571 __be32 pgid; 5572 __be64 r11; --- 24 unchanged lines hidden (view full) --- 5597 __u8 user_prio_map; 5598 __u8 sel_field; 5599 __be16 protocolid; 5600 __be64 r12; 5601 } app_priority; 5602 struct fw_port_dcb_control { 5603 __u8 type; 5604 __u8 all_syncd_pkd; | 5645 } diags; 5646 union fw_port_dcb { 5647 struct fw_port_dcb_pgid { 5648 __u8 type; 5649 __u8 apply_pkd; 5650 __u8 r10_lo[2]; 5651 __be32 pgid; 5652 __be64 r11; --- 24 unchanged lines hidden (view full) --- 5677 __u8 user_prio_map; 5678 __u8 sel_field; 5679 __be16 protocolid; 5680 __be64 r12; 5681 } app_priority; 5682 struct fw_port_dcb_control { 5683 __u8 type; 5684 __u8 all_syncd_pkd; |
5605 __be16 r10_lo[3]; | 5685 __be16 r10_lo[3]; |
5606 __be64 r11; 5607 } control; 5608 } dcb; 5609 } u; 5610}; 5611 5612#define S_FW_PORT_CMD_READ 22 5613#define M_FW_PORT_CMD_READ 0x1 --- 129 unchanged lines hidden (view full) --- 5743 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 5744 5745#define S_FW_PORT_CMD_MODTYPE 0 5746#define M_FW_PORT_CMD_MODTYPE 0x1f 5747#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 5748#define G_FW_PORT_CMD_MODTYPE(x) \ 5749 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 5750 | 5686 __be64 r11; 5687 } control; 5688 } dcb; 5689 } u; 5690}; 5691 5692#define S_FW_PORT_CMD_READ 22 5693#define M_FW_PORT_CMD_READ 0x1 --- 129 unchanged lines hidden (view full) --- 5823 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 5824 5825#define S_FW_PORT_CMD_MODTYPE 0 5826#define M_FW_PORT_CMD_MODTYPE 0x1f 5827#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 5828#define G_FW_PORT_CMD_MODTYPE(x) \ 5829 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 5830 |
5751#define S_FW_PORT_CMD_DIAGOP 24 5752#define M_FW_PORT_CMD_DIAGOP 0xff 5753#define V_FW_PORT_CMD_DIAGOP(x) ((x) << S_FW_PORT_CMD_DIAGOP) 5754#define G_FW_PORT_CMD_DIAGOP(x) \ 5755 (((x) >> S_FW_PORT_CMD_DIAGOP) & M_FW_PORT_CMD_DIAGOP) 5756 5757#define S_FW_PORT_CMD_DIAGVAL 0 5758#define M_FW_PORT_CMD_DIAGVAL 0xffffff 5759#define V_FW_PORT_CMD_DIAGVAL(x) ((x) << S_FW_PORT_CMD_DIAGVAL) 5760#define G_FW_PORT_CMD_DIAGVAL(x) \ 5761 (((x) >> S_FW_PORT_CMD_DIAGVAL) & M_FW_PORT_CMD_DIAGVAL) 5762 | |
5763#define S_FW_PORT_CMD_APPLY 7 5764#define M_FW_PORT_CMD_APPLY 0x1 5765#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 5766#define G_FW_PORT_CMD_APPLY(x) \ 5767 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 5768#define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 5769 5770#define S_FW_PORT_CMD_ALL_SYNCD 7 --- 40 unchanged lines hidden (view full) --- 5811 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 5812 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 5813}; 5814 5815/* used by FW and tools may use this to generate VPD */ 5816enum fw_port_mod_sub_type { 5817 FW_PORT_MOD_SUB_TYPE_NA, 5818 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, | 5831#define S_FW_PORT_CMD_APPLY 7 5832#define M_FW_PORT_CMD_APPLY 0x1 5833#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 5834#define G_FW_PORT_CMD_APPLY(x) \ 5835 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 5836#define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 5837 5838#define S_FW_PORT_CMD_ALL_SYNCD 7 --- 40 unchanged lines hidden (view full) --- 5879 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 5880 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 5881}; 5882 5883/* used by FW and tools may use this to generate VPD */ 5884enum fw_port_mod_sub_type { 5885 FW_PORT_MOD_SUB_TYPE_NA, 5886 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, |
5887 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 5888 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 5889 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 5890 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, |
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5819 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 5820 5821 /* 5822 * The following will never been in the VPD. They are TWINAX cable 5823 * lengths decoded from SFP+ module i2c PROMs. These should almost 5824 * certainly go somewhere else ... 5825 */ 5826 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 5827 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 5828 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 5829 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 5830}; 5831 5832/* link down reason codes (3b) */ 5833enum fw_port_link_dn_rc { 5834 FW_PORT_LINK_DN_RC_NONE, | 5891 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 5892 5893 /* 5894 * The following will never been in the VPD. They are TWINAX cable 5895 * lengths decoded from SFP+ module i2c PROMs. These should almost 5896 * certainly go somewhere else ... 5897 */ 5898 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 5899 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 5900 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 5901 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 5902}; 5903 5904/* link down reason codes (3b) */ 5905enum fw_port_link_dn_rc { 5906 FW_PORT_LINK_DN_RC_NONE, |
5835 FW_PORT_LINK_DN_RC_REMFLT, 5836 FW_PORT_LINK_DN_ANEG_F, 5837 FW_PORT_LINK_DN_MS_RES_F, 5838 FW_PORT_LINK_DN_OVERHEAT, 5839 FW_PORT_LINK_DN_UNKNOWN | 5907 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 5908 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 5909 FW_PORT_LINK_DN_RESERVED3, 5910 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 5911 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 5912 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 5913 FW_PORT_LINK_DN_RESERVED7 |
5840}; 5841 5842/* port stats */ 5843#define FW_NUM_PORT_STATS 50 5844#define FW_NUM_PORT_TX_STATS 23 5845#define FW_NUM_PORT_RX_STATS 27 5846 5847enum fw_port_stats_tx_index { --- 782 unchanged lines hidden (view full) --- 6630 FW_SCHED_TYPE_PKTSCHED = 0, 6631 FW_SCHED_TYPE_STREAMSCHED = 1, 6632}; 6633 6634enum fw_sched_params_level { 6635 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 6636 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 6637 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, | 5914}; 5915 5916/* port stats */ 5917#define FW_NUM_PORT_STATS 50 5918#define FW_NUM_PORT_TX_STATS 23 5919#define FW_NUM_PORT_RX_STATS 27 5920 5921enum fw_port_stats_tx_index { --- 782 unchanged lines hidden (view full) --- 6704 FW_SCHED_TYPE_PKTSCHED = 0, 6705 FW_SCHED_TYPE_STREAMSCHED = 1, 6706}; 6707 6708enum fw_sched_params_level { 6709 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 6710 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 6711 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, |
6638 FW_SCHED_PARAMS_LEVEL_CH_WRR = 3, | |
6639}; 6640 6641enum fw_sched_params_mode { 6642 FW_SCHED_PARAMS_MODE_CLASS = 0, 6643 FW_SCHED_PARAMS_MODE_FLOW = 1, 6644}; 6645 6646enum fw_sched_params_unit { --- 24 unchanged lines hidden (view full) --- 6671 __u8 unit; 6672 __u8 rate; 6673 __u8 ch; 6674 __u8 cl; 6675 __be32 min; 6676 __be32 max; 6677 __be16 weight; 6678 __be16 pktsize; | 6712}; 6713 6714enum fw_sched_params_mode { 6715 FW_SCHED_PARAMS_MODE_CLASS = 0, 6716 FW_SCHED_PARAMS_MODE_FLOW = 1, 6717}; 6718 6719enum fw_sched_params_unit { --- 24 unchanged lines hidden (view full) --- 6744 __u8 unit; 6745 __u8 rate; 6746 __u8 ch; 6747 __u8 cl; 6748 __be32 min; 6749 __be32 max; 6750 __be16 weight; 6751 __be16 pktsize; |
6679 __be32 r4; | 6752 __be16 burstsize; 6753 __be16 r4; |
6680 } params; 6681 } u; 6682}; 6683 6684/* 6685 * length of the formatting string 6686 */ 6687#define FW_DEVLOG_FMT_LEN 192 --- 660 unchanged lines hidden (view full) --- 7348#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 7349#define G_FW_DEBUG_CMD_TYPE(x) \ 7350 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 7351 7352/****************************************************************************** 7353 * P C I E F W R E G I S T E R 7354 **************************************/ 7355 | 6754 } params; 6755 } u; 6756}; 6757 6758/* 6759 * length of the formatting string 6760 */ 6761#define FW_DEVLOG_FMT_LEN 192 --- 660 unchanged lines hidden (view full) --- 7422#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 7423#define G_FW_DEBUG_CMD_TYPE(x) \ 7424 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 7425 7426/****************************************************************************** 7427 * P C I E F W R E G I S T E R 7428 **************************************/ 7429 |
7430enum pcie_fw_eval { 7431 PCIE_FW_EVAL_CRASH = 0, 7432 PCIE_FW_EVAL_PREP = 1, 7433 PCIE_FW_EVAL_CONF = 2, 7434 PCIE_FW_EVAL_INIT = 3, 7435 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 7436 PCIE_FW_EVAL_OVERHEAT = 5, 7437 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 7438}; 7439 |
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7356/** 7357 * Register definitions for the PCIE_FW register which the firmware uses 7358 * to retain status across RESETs. This register should be considered 7359 * as a READ-ONLY register for Host Software and only to be used to 7360 * track firmware initialization/error state, etc. 7361 */ 7362#define S_PCIE_FW_ERR 31 7363#define M_PCIE_FW_ERR 0x1 --- 8 unchanged lines hidden (view full) --- 7372#define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 7373 7374#define S_PCIE_FW_HALT 29 7375#define M_PCIE_FW_HALT 0x1 7376#define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 7377#define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 7378#define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 7379 | 7440/** 7441 * Register definitions for the PCIE_FW register which the firmware uses 7442 * to retain status across RESETs. This register should be considered 7443 * as a READ-ONLY register for Host Software and only to be used to 7444 * track firmware initialization/error state, etc. 7445 */ 7446#define S_PCIE_FW_ERR 31 7447#define M_PCIE_FW_ERR 0x1 --- 8 unchanged lines hidden (view full) --- 7456#define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 7457 7458#define S_PCIE_FW_HALT 29 7459#define M_PCIE_FW_HALT 0x1 7460#define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 7461#define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 7462#define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 7463 |
7464#define S_PCIE_FW_EVAL 24 7465#define M_PCIE_FW_EVAL 0x7 7466#define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 7467#define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 7468 |
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7380#define S_PCIE_FW_STAGE 21 7381#define M_PCIE_FW_STAGE 0x7 7382#define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 7383#define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 7384 7385#define S_PCIE_FW_ASYNCNOT_VLD 20 7386#define M_PCIE_FW_ASYNCNOT_VLD 0x1 7387#define V_PCIE_FW_ASYNCNOT_VLD(x) \ --- 62 unchanged lines hidden (view full) --- 7450 __be32 fw_ver; /* firmware version */ 7451 __be32 tp_microcode_ver; /* tcp processor microcode version */ 7452 __u8 intfver_nic; 7453 __u8 intfver_vnic; 7454 __u8 intfver_ofld; 7455 __u8 intfver_ri; 7456 __u8 intfver_iscsipdu; 7457 __u8 intfver_iscsi; | 7469#define S_PCIE_FW_STAGE 21 7470#define M_PCIE_FW_STAGE 0x7 7471#define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 7472#define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 7473 7474#define S_PCIE_FW_ASYNCNOT_VLD 20 7475#define M_PCIE_FW_ASYNCNOT_VLD 0x1 7476#define V_PCIE_FW_ASYNCNOT_VLD(x) \ --- 62 unchanged lines hidden (view full) --- 7539 __be32 fw_ver; /* firmware version */ 7540 __be32 tp_microcode_ver; /* tcp processor microcode version */ 7541 __u8 intfver_nic; 7542 __u8 intfver_vnic; 7543 __u8 intfver_ofld; 7544 __u8 intfver_ri; 7545 __u8 intfver_iscsipdu; 7546 __u8 intfver_iscsi; |
7547 __u8 intfver_fcoepdu; |
|
7458 __u8 intfver_fcoe; | 7548 __u8 intfver_fcoe; |
7459 __u8 reserved2; | 7549 __u32 reserved2; |
7460 __u32 reserved3; 7461 __u32 reserved4; | 7550 __u32 reserved3; 7551 __u32 reserved4; |
7462 __u32 reserved5; | |
7463 __be32 flags; 7464 __be32 reserved6[23]; 7465}; 7466 7467enum fw_hdr_chip { 7468 FW_HDR_CHIP_T4, 7469 FW_HDR_CHIP_T5 7470}; --- 28 unchanged lines hidden (view full) --- 7499 7500enum { 7501 FW_HDR_INTFVER_NIC = 0x00, 7502 FW_HDR_INTFVER_VNIC = 0x00, 7503 FW_HDR_INTFVER_OFLD = 0x00, 7504 FW_HDR_INTFVER_RI = 0x00, 7505 FW_HDR_INTFVER_ISCSIPDU = 0x00, 7506 FW_HDR_INTFVER_ISCSI = 0x00, | 7552 __be32 flags; 7553 __be32 reserved6[23]; 7554}; 7555 7556enum fw_hdr_chip { 7557 FW_HDR_CHIP_T4, 7558 FW_HDR_CHIP_T5 7559}; --- 28 unchanged lines hidden (view full) --- 7588 7589enum { 7590 FW_HDR_INTFVER_NIC = 0x00, 7591 FW_HDR_INTFVER_VNIC = 0x00, 7592 FW_HDR_INTFVER_OFLD = 0x00, 7593 FW_HDR_INTFVER_RI = 0x00, 7594 FW_HDR_INTFVER_ISCSIPDU = 0x00, 7595 FW_HDR_INTFVER_ISCSI = 0x00, |
7596 FW_HDR_INTFVER_FCOEPDU = 0x00, |
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7507 FW_HDR_INTFVER_FCOE = 0x00, 7508}; 7509 7510enum fw_hdr_flags { 7511 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 7512}; 7513 7514#endif /* _T4FW_INTERFACE_H_ */ | 7597 FW_HDR_INTFVER_FCOE = 0x00, 7598}; 7599 7600enum fw_hdr_flags { 7601 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 7602}; 7603 7604#endif /* _T4FW_INTERFACE_H_ */ |