t4fw_interface.h (228561) | t4fw_interface.h (237436) |
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1/*- | 1/*- |
2 * Copyright (c) 2011 Chelsio Communications, Inc. | 2 * Copyright (c) 2012 Chelsio Communications, Inc. |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright --- 7 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright --- 7 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
26 * $FreeBSD: head/sys/dev/cxgbe/firmware/t4fw_interface.h 228561 2011-12-16 02:09:51Z np $ | 26 * $FreeBSD: head/sys/dev/cxgbe/firmware/t4fw_interface.h 237436 2012-06-22 07:51:15Z np $ |
27 * 28 */ 29 30#ifndef _T4FW_INTERFACE_H_ 31#define _T4FW_INTERFACE_H_ 32 33/****************************************************************************** 34 * R E T U R N V A L U E S --- 43 unchanged lines hidden (view full) --- 78 ********************************/ 79 80enum fw_wr_opcodes { 81 FW_FILTER_WR = 0x02, 82 FW_ULPTX_WR = 0x04, 83 FW_TP_WR = 0x05, 84 FW_ETH_TX_PKT_WR = 0x08, 85 FW_ETH_TX_PKTS_WR = 0x09, | 27 * 28 */ 29 30#ifndef _T4FW_INTERFACE_H_ 31#define _T4FW_INTERFACE_H_ 32 33/****************************************************************************** 34 * R E T U R N V A L U E S --- 43 unchanged lines hidden (view full) --- 78 ********************************/ 79 80enum fw_wr_opcodes { 81 FW_FILTER_WR = 0x02, 82 FW_ULPTX_WR = 0x04, 83 FW_TP_WR = 0x05, 84 FW_ETH_TX_PKT_WR = 0x08, 85 FW_ETH_TX_PKTS_WR = 0x09, |
86 FW_ETH_TX_UO_WR = 0x1c, |
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86 FW_EQ_FLUSH_WR = 0x1b, | 87 FW_EQ_FLUSH_WR = 0x1b, |
88 FW_OFLD_CONNECTION_WR = 0x2f, |
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87 FW_FLOWC_WR = 0x0a, 88 FW_OFLD_TX_DATA_WR = 0x0b, 89 FW_CMD_WR = 0x10, 90 FW_ETH_TX_PKT_VM_WR = 0x11, 91 FW_RI_RES_WR = 0x0c, 92 FW_RI_RDMA_WRITE_WR = 0x14, 93 FW_RI_SEND_WR = 0x15, 94 FW_RI_RDMA_READ_WR = 0x16, 95 FW_RI_RECV_WR = 0x17, 96 FW_RI_BIND_MW_WR = 0x18, 97 FW_RI_FR_NSMR_WR = 0x19, 98 FW_RI_INV_LSTAG_WR = 0x1a, | 89 FW_FLOWC_WR = 0x0a, 90 FW_OFLD_TX_DATA_WR = 0x0b, 91 FW_CMD_WR = 0x10, 92 FW_ETH_TX_PKT_VM_WR = 0x11, 93 FW_RI_RES_WR = 0x0c, 94 FW_RI_RDMA_WRITE_WR = 0x14, 95 FW_RI_SEND_WR = 0x15, 96 FW_RI_RDMA_READ_WR = 0x16, 97 FW_RI_RECV_WR = 0x17, 98 FW_RI_BIND_MW_WR = 0x18, 99 FW_RI_FR_NSMR_WR = 0x19, 100 FW_RI_INV_LSTAG_WR = 0x1a, |
101 FW_RI_SEND_IMMEDIATE_WR = 0x15, 102 FW_RI_ATOMIC_WR = 0x16, |
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99 FW_RI_WR = 0x0d, | 103 FW_RI_WR = 0x0d, |
100 FW_ISCSI_NODE_WR = 0x4a, 101 FW_LASTC2E_WR = 0x50 | 104 FW_CHNET_IFCONF_WR = 0x6b, 105 FW_RDEV_WR = 0x38, 106 FW_FOISCSI_NODE_WR = 0x60, 107 FW_FOISCSI_CTRL_WR = 0x6a, 108 FW_FOISCSI_CHAP_WR = 0x6c, 109 FW_FCOE_ELS_CT_WR = 0x30, 110 FW_SCSI_WRITE_WR = 0x31, 111 FW_SCSI_READ_WR = 0x32, 112 FW_SCSI_CMD_WR = 0x33, 113 FW_SCSI_ABRT_CLS_WR = 0x34, 114 FW_SCSI_TGT_ACC_WR = 0x35, 115 FW_SCSI_TGT_XMIT_WR = 0x36, 116 FW_SCSI_TGT_RSP_WR = 0x37, 117 FW_LASTC2E_WR = 0x70 |
102}; 103 104/* 105 * Generic work request header flit0 106 */ 107struct fw_wr_hdr { 108 __be32 hi; 109 __be32 lo; --- 421 unchanged lines hidden (view full) --- 531 __be32 op_pkd; 532 __be32 equiq_to_len16; 533 __be32 r3; 534 __be16 plen; 535 __u8 npkt; 536 __u8 type; 537}; 538 | 118}; 119 120/* 121 * Generic work request header flit0 122 */ 123struct fw_wr_hdr { 124 __be32 hi; 125 __be32 lo; --- 421 unchanged lines hidden (view full) --- 547 __be32 op_pkd; 548 __be32 equiq_to_len16; 549 __be32 r3; 550 __be16 plen; 551 __u8 npkt; 552 __u8 type; 553}; 554 |
555struct fw_eth_tx_uo_wr { 556 __be32 op_immdlen; 557 __be32 equiq_to_len16; 558 __be64 r3; 559 __be16 ethlen; 560 __be16 iplen; 561 __be16 udplen; 562 __be16 mss; 563 __be32 length; 564 __be32 r4; 565}; 566 |
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539struct fw_eq_flush_wr { 540 __u8 opcode; 541 __u8 r1[3]; 542 __be32 equiq_to_len16; 543 __be64 r3; 544}; 545 | 567struct fw_eq_flush_wr { 568 __u8 opcode; 569 __u8 r1[3]; 570 __be32 equiq_to_len16; 571 __be64 r3; 572}; 573 |
574struct fw_ofld_connection_wr { 575 __be32 op_compl; 576 __be32 len16_pkd; 577 __u64 cookie; 578 __be64 r2; 579 __be64 r3; 580 struct fw_ofld_connection_le { 581 __be32 version_cpl; 582 __be32 filter; 583 __be32 r1; 584 __be16 lport; 585 __be16 pport; 586 union fw_ofld_connection_leip { 587 struct fw_ofld_connection_le_ipv4 { 588 __be32 pip; 589 __be32 lip; 590 __be64 r0; 591 __be64 r1; 592 __be64 r2; 593 } ipv4; 594 struct fw_ofld_connection_le_ipv6 { 595 __be64 pip_hi; 596 __be64 pip_lo; 597 __be64 lip_hi; 598 __be64 lip_lo; 599 } ipv6; 600 } u; 601 } le; 602 struct fw_ofld_connection_tcb { 603 __be32 t_state_to_astid; 604 __be16 cplrxdataack_cplpassacceptrpl; 605 __be16 rcv_adv; 606 __be32 rcv_nxt; 607 __be32 tx_max; 608 __be64 opt0; 609 __be32 opt2; 610 __be32 r1; 611 __be64 r2; 612 __be64 r3; 613 } tcb; 614}; 615 616#define S_FW_OFLD_CONNECTION_WR_VERSION 31 617#define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 618#define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 619 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 620#define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 621 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 622 M_FW_OFLD_CONNECTION_WR_VERSION) 623#define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 624 625#define S_FW_OFLD_CONNECTION_WR_CPL 30 626#define M_FW_OFLD_CONNECTION_WR_CPL 0x1 627#define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 628#define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 629 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 630#define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 631 632#define S_FW_OFLD_CONNECTION_WR_T_STATE 28 633#define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 634#define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 635 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 636#define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 637 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 638 M_FW_OFLD_CONNECTION_WR_T_STATE) 639 640#define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 641#define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 642#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 643 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 644#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 645 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 646 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 647 648#define S_FW_OFLD_CONNECTION_WR_ASTID 0 649#define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 650#define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 651 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 652#define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 653 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 654 655#define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 656#define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 657#define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 658 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 659#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 660 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 661 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 662#define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 663 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 664 665#define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 666#define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 667#define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 668 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 669#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 670 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 671 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 672#define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 673 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 674 675enum fw_flowc_mnem_tcpstate { 676 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 677 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 678 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 679 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 680 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 681 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 682 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 683 * will resend FIN - equiv ESTAB 684 */ 685 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 686 * will resend FIN but have 687 * received FIN 688 */ 689 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 690 * will resend FIN but have 691 * received FIN 692 */ 693 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 694 * waiting for FIN 695 */ 696 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 697}; 698 699enum fw_flowc_mnem_uostate { 700 FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */ 701 FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */ 702 FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, /* graceful close, after sending 703 * outstanding payload 704 */ 705 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, /* immediate close, after 706 * discarding outstanding payload 707 */ 708}; 709 |
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546enum fw_flowc_mnem { 547 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 548 FW_FLOWC_MNEM_CH, 549 FW_FLOWC_MNEM_PORT, 550 FW_FLOWC_MNEM_IQID, 551 FW_FLOWC_MNEM_SNDNXT, 552 FW_FLOWC_MNEM_RCVNXT, 553 FW_FLOWC_MNEM_SNDBUF, 554 FW_FLOWC_MNEM_MSS, 555 FW_FLOWC_MNEM_TXDATAPLEN_MAX, | 710enum fw_flowc_mnem { 711 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 712 FW_FLOWC_MNEM_CH, 713 FW_FLOWC_MNEM_PORT, 714 FW_FLOWC_MNEM_IQID, 715 FW_FLOWC_MNEM_SNDNXT, 716 FW_FLOWC_MNEM_RCVNXT, 717 FW_FLOWC_MNEM_SNDBUF, 718 FW_FLOWC_MNEM_MSS, 719 FW_FLOWC_MNEM_TXDATAPLEN_MAX, |
720 FW_FLOWC_MNEM_TCPSTATE, 721 FW_FLOWC_MNEM_UOSTATE, 722 FW_FLOWC_MNEM_SCHEDCLASS, |
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556}; 557 558struct fw_flowc_mnemval { 559 __u8 mnemonic; 560 __u8 r4[3]; 561 __be32 val; 562}; 563 --- 103 unchanged lines hidden (view full) --- 667 __be16 vlantci; 668}; 669 670/****************************************************************************** 671 * R I W O R K R E Q U E S T s 672 **************************************/ 673 674enum fw_ri_wr_opcode { | 723}; 724 725struct fw_flowc_mnemval { 726 __u8 mnemonic; 727 __u8 r4[3]; 728 __be32 val; 729}; 730 --- 103 unchanged lines hidden (view full) --- 834 __be16 vlantci; 835}; 836 837/****************************************************************************** 838 * R I W O R K R E Q U E S T s 839 **************************************/ 840 841enum fw_ri_wr_opcode { |
675 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ | 842 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ |
676 FW_RI_READ_REQ = 0x1, 677 FW_RI_READ_RESP = 0x2, 678 FW_RI_SEND = 0x3, 679 FW_RI_SEND_WITH_INV = 0x4, 680 FW_RI_SEND_WITH_SE = 0x5, 681 FW_RI_SEND_WITH_SE_INV = 0x6, 682 FW_RI_TERMINATE = 0x7, | 843 FW_RI_READ_REQ = 0x1, 844 FW_RI_READ_RESP = 0x2, 845 FW_RI_SEND = 0x3, 846 FW_RI_SEND_WITH_INV = 0x4, 847 FW_RI_SEND_WITH_SE = 0x5, 848 FW_RI_SEND_WITH_SE_INV = 0x6, 849 FW_RI_TERMINATE = 0x7, |
683 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ | 850 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ |
684 FW_RI_BIND_MW = 0x9, 685 FW_RI_FAST_REGISTER = 0xa, 686 FW_RI_LOCAL_INV = 0xb, 687 FW_RI_QP_MODIFY = 0xc, 688 FW_RI_BYPASS = 0xd, 689 FW_RI_RECEIVE = 0xe, | 851 FW_RI_BIND_MW = 0x9, 852 FW_RI_FAST_REGISTER = 0xa, 853 FW_RI_LOCAL_INV = 0xb, 854 FW_RI_QP_MODIFY = 0xc, 855 FW_RI_BYPASS = 0xd, 856 FW_RI_RECEIVE = 0xe, |
857#if 0 858 FW_RI_SEND_IMMEDIATE = 0x8, 859 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 860 FW_RI_ATOMIC_REQUEST = 0xa, 861 FW_RI_ATOMIC_RESPONSE = 0xb, |
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690 | 862 |
863 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 864 FW_RI_FAST_REGISTER = 0xd, 865 FW_RI_LOCAL_INV = 0xe, 866#endif |
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691 FW_RI_SGE_EC_CR_RETURN = 0xf 692}; 693 694enum fw_ri_wr_flags { 695 FW_RI_COMPLETION_FLAG = 0x01, 696 FW_RI_NOTIFICATION_FLAG = 0x02, 697 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 698 FW_RI_READ_FENCE_FLAG = 0x08, --- 699 unchanged lines hidden (view full) --- 1398 __u8 flags; 1399 __u16 wrid; 1400 __u8 r1[3]; 1401 __u8 len16; 1402 __be32 r2; 1403 __be32 stag_inv; 1404}; 1405 | 867 FW_RI_SGE_EC_CR_RETURN = 0xf 868}; 869 870enum fw_ri_wr_flags { 871 FW_RI_COMPLETION_FLAG = 0x01, 872 FW_RI_NOTIFICATION_FLAG = 0x02, 873 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 874 FW_RI_READ_FENCE_FLAG = 0x08, --- 699 unchanged lines hidden (view full) --- 1574 __u8 flags; 1575 __u16 wrid; 1576 __u8 r1[3]; 1577 __u8 len16; 1578 __be32 r2; 1579 __be32 stag_inv; 1580}; 1581 |
1582struct fw_ri_send_immediate_wr { 1583 __u8 opcode; 1584 __u8 flags; 1585 __u16 wrid; 1586 __u8 r1[3]; 1587 __u8 len16; 1588 __be32 sendimmop_pkd; 1589 __be32 r3; 1590 __be32 plen; 1591 __be32 r4; 1592 __be64 r5; 1593#ifndef C99_NOT_SUPPORTED 1594 struct fw_ri_immd immd_src[0]; 1595#endif 1596}; 1597 1598#define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1599#define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1600#define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1601 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1602#define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1603 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1604 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1605 1606enum fw_ri_atomic_op { 1607 FW_RI_ATOMIC_OP_FETCHADD, 1608 FW_RI_ATOMIC_OP_SWAP, 1609 FW_RI_ATOMIC_OP_CMDSWAP, 1610}; 1611 1612struct fw_ri_atomic_wr { 1613 __u8 opcode; 1614 __u8 flags; 1615 __u16 wrid; 1616 __u8 r1[3]; 1617 __u8 len16; 1618 __be32 atomicop_pkd; 1619 __be64 r3; 1620 __be32 aopcode_pkd; 1621 __be32 reqid; 1622 __be32 stag; 1623 __be32 to_hi; 1624 __be32 to_lo; 1625 __be32 addswap_data_hi; 1626 __be32 addswap_data_lo; 1627 __be32 addswap_mask_hi; 1628 __be32 addswap_mask_lo; 1629 __be32 compare_data_hi; 1630 __be32 compare_data_lo; 1631 __be32 compare_mask_hi; 1632 __be32 compare_mask_lo; 1633 __be32 r5; 1634}; 1635 1636#define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1637#define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1638#define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1639#define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1640 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1641 1642#define S_FW_RI_ATOMIC_WR_AOPCODE 0 1643#define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1644#define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1645#define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1646 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1647 |
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1406enum fw_ri_type { 1407 FW_RI_TYPE_INIT, 1408 FW_RI_TYPE_FINI, 1409 FW_RI_TYPE_TERMINATE 1410}; 1411 1412enum fw_ri_init_p2ptype { 1413 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, --- 66 unchanged lines hidden (view full) --- 1480 1481#define S_FW_RI_WR_P2PTYPE 0 1482#define M_FW_RI_WR_P2PTYPE 0xf 1483#define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1484#define G_FW_RI_WR_P2PTYPE(x) \ 1485 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1486 1487/****************************************************************************** | 1648enum fw_ri_type { 1649 FW_RI_TYPE_INIT, 1650 FW_RI_TYPE_FINI, 1651 FW_RI_TYPE_TERMINATE 1652}; 1653 1654enum fw_ri_init_p2ptype { 1655 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, --- 66 unchanged lines hidden (view full) --- 1722 1723#define S_FW_RI_WR_P2PTYPE 0 1724#define M_FW_RI_WR_P2PTYPE 0xf 1725#define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1726#define G_FW_RI_WR_P2PTYPE(x) \ 1727 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1728 1729/****************************************************************************** |
1488 * S C S I W O R K R E Q U E S T s 1489 **********************************************/ | 1730 * F O i S C S I W O R K R E Q U E S T s 1731 *********************************************/ |
1490 | 1732 |
1733#define FW_FOISCSI_NAME_MAX_LEN 224 1734#define FW_FOISCSI_ALIAS_MAX_LEN 224 1735#define FW_FOISCSI_MAX_CHAP_NAME_LEN 64 1736#define FW_FOISCSI_INIT_NODE_MAX 8 |
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1491 | 1737 |
1492/****************************************************************************** 1493 * F O i S C S I W O R K R E Q U E S T s 1494 **********************************************/ | 1738enum fw_chnet_ifconf_wr_subop { 1739 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1740 1741 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1742 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1743 1744 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1745 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, |
1495 | 1746 |
1496#define ISCSI_NAME_MAX_LEN 224 1497#define ISCSI_ALIAS_MAX_LEN 224 | 1747 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1748 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, |
1498 | 1749 |
1499enum session_type { 1500 ISCSI_SESSION_DISCOVERY = 0, 1501 ISCSI_SESSION_NORMAL, | 1750 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1751 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1752 1753 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1754 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1755 1756 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1757 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1758 1759 FW_CHNET_IFCONF_WR_SUBOP_MAX, |
1502}; 1503 | 1760}; 1761 |
1504enum digest_val { 1505 DIGEST_NONE = 0, 1506 DIGEST_CRC32, 1507 DIGEST_BOTH, | 1762struct fw_chnet_ifconf_wr { 1763 __be32 op_compl; 1764 __be32 flowid_len16; 1765 __be64 cookie; 1766 __be32 if_flowid; 1767 __u8 idx; 1768 __u8 subop; 1769 __u8 retval; 1770 __u8 r2; 1771 __be64 r3; 1772 struct fw_chnet_ifconf_params { 1773 __be32 r0; 1774 __be16 vlanid; 1775 __be16 mtu; 1776 union fw_chnet_ifconf_addr_type { 1777 struct fw_chnet_ifconf_ipv4 { 1778 __be32 addr; 1779 __be32 mask; 1780 __be32 router; 1781 __be32 r0; 1782 __be64 r1; 1783 } ipv4; 1784 struct fw_chnet_ifconf_ipv6 { 1785 __be64 linklocal_lo; 1786 __be64 linklocal_hi; 1787 __be64 router_hi; 1788 __be64 router_lo; 1789 __be64 aconf_hi; 1790 __be64 aconf_lo; 1791 __be64 linklocal_aconf_hi; 1792 __be64 linklocal_aconf_lo; 1793 __be64 router_aconf_hi; 1794 __be64 router_aconf_lo; 1795 __be64 r0; 1796 } ipv6; 1797 } in_attr; 1798 } param; |
1508}; 1509 | 1799}; 1800 |
1510enum fw_iscsi_subops { 1511 NODE_ONLINE = 1, 1512 SESS_ONLINE, 1513 CONN_ONLINE, 1514 NODE_OFFLINE, 1515 SESS_OFFLINE, 1516 CONN_OFFLINE, 1517 NODE_STATS, 1518 SESS_STATS, 1519 CONN_STATS, 1520 UPDATE_IOHANDLE, | 1801enum fw_foiscsi_session_type { 1802 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 1803 FW_FOISCSI_SESSION_TYPE_NORMAL, |
1521}; 1522 | 1804}; 1805 |
1523struct fw_iscsi_node_attr { 1524 __u8 name_len; 1525 __u8 node_name[ISCSI_NAME_MAX_LEN]; 1526 __u8 alias_len; 1527 __u8 node_alias[ISCSI_ALIAS_MAX_LEN]; | 1806enum fw_foiscsi_auth_policy { 1807 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 1808 FW_FOISCSI_AUTH_POLICY_MUTUAL, |
1528}; 1529 | 1809}; 1810 |
1530struct fw_iscsi_sess_attr { 1531 __u8 sess_type; 1532 __u8 seq_inorder; 1533 __u8 pdu_inorder; 1534 __u8 immd_data_en; 1535 __u8 init_r2t_en; 1536 __u8 erl; 1537 __be16 max_conn; 1538 __be16 max_r2t; 1539 __be16 time2wait; 1540 __be16 time2retain; 1541 __be32 max_burst; 1542 __be32 first_burst; | 1811enum fw_foiscsi_auth_method { 1812 FW_FOISCSI_AUTH_METHOD_NONE = 0, 1813 FW_FOISCSI_AUTH_METHOD_CHAP, 1814 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 1815 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, |
1543}; 1544 | 1816}; 1817 |
1545struct fw_iscsi_conn_attr { 1546 __u8 hdr_digest; 1547 __u8 data_digest; 1548 __be32 max_rcv_dsl; 1549 __be16 dst_port; 1550 __be32 dst_addr; 1551 __be16 src_port; 1552 __be32 src_addr; 1553 __be32 ping_tmo; | 1818enum fw_foiscsi_digest_type { 1819 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 1820 FW_FOISCSI_DIGEST_TYPE_CRC32, 1821 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 1822 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, |
1554}; 1555 | 1823}; 1824 |
1556struct fw_iscsi_node_stats { 1557 __be16 sess_count; 1558 __be16 chap_fail_count; 1559 __be16 login_count; 1560 __be16 r1; | 1825enum fw_foiscsi_wr_subop { 1826 FW_FOISCSI_WR_SUBOP_ADD = 1, 1827 FW_FOISCSI_WR_SUBOP_DEL = 2, 1828 FW_FOISCSI_WR_SUBOP_MOD = 4, |
1561}; 1562 | 1829}; 1830 |
1563struct fw_iscsi_sess_stats { 1564 __be32 rxbytes; 1565 __be32 txbytes; 1566 __be32 scmd_count; 1567 __be32 read_cmds; 1568 __be32 write_cmds; 1569 __be32 read_bytes; 1570 __be32 write_bytes; 1571 __be32 scsi_err_count; 1572 __be32 scsi_rst_count; 1573 __be32 iscsi_tmf_count; 1574 __be32 conn_count; | 1831enum fw_foiscsi_ctrl_state { 1832 FW_FOISCSI_CTRL_STATE_FREE = 0, 1833 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 1834 FW_FOISCSI_CTRL_STATE_FAILED, 1835 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 1836 FW_FOISCSI_CTRL_STATE_REDIRECT, |
1575}; 1576 | 1837}; 1838 |
1577struct fw_iscsi_conn_stats { 1578 __be32 txbytes; 1579 __be32 rxbytes; 1580 __be32 dataout; 1581 __be32 datain; | 1839struct fw_rdev_wr { 1840 __be32 op_to_immdlen; 1841 __be32 alloc_to_len16; 1842 __be64 cookie; 1843 __u8 protocol; 1844 __u8 event_cause; 1845 __u8 cur_state; 1846 __u8 prev_state; 1847 __be32 flags_to_assoc_flowid; 1848 union rdev_entry { 1849 struct fcoe_rdev_entry { 1850 __be32 flowid; 1851 __u8 protocol; 1852 __u8 event_cause; 1853 __u8 flags; 1854 __u8 rjt_reason; 1855 __u8 cur_login_st; 1856 __u8 prev_login_st; 1857 __be16 rcv_fr_sz; 1858 __u8 rd_xfer_rdy_to_rport_type; 1859 __u8 vft_to_qos; 1860 __u8 org_proc_assoc_to_acc_rsp_code; 1861 __u8 enh_disc_to_tgt; 1862 __u8 wwnn[8]; 1863 __u8 wwpn[8]; 1864 __be16 iqid; 1865 __u8 fc_oui[3]; 1866 __u8 r_id[3]; 1867 } fcoe_rdev; 1868 struct iscsi_rdev_entry { 1869 __be32 flowid; 1870 __u8 protocol; 1871 __u8 event_cause; 1872 __u8 flags; 1873 __u8 r3; 1874 __be16 iscsi_opts; 1875 __be16 tcp_opts; 1876 __be16 ip_opts; 1877 __be16 max_rcv_len; 1878 __be16 max_snd_len; 1879 __be16 first_brst_len; 1880 __be16 max_brst_len; 1881 __be16 r4; 1882 __be16 def_time2wait; 1883 __be16 def_time2ret; 1884 __be16 nop_out_intrvl; 1885 __be16 non_scsi_to; 1886 __be16 isid; 1887 __be16 tsid; 1888 __be16 port; 1889 __be16 tpgt; 1890 __u8 r5[6]; 1891 __be16 iqid; 1892 } iscsi_rdev; 1893 } u; |
1582}; 1583 | 1894}; 1895 |
1584struct fw_iscsi_node_wr { 1585 __u8 opcode; | 1896#define S_FW_RDEV_WR_IMMDLEN 0 1897#define M_FW_RDEV_WR_IMMDLEN 0xff 1898#define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 1899#define G_FW_RDEV_WR_IMMDLEN(x) \ 1900 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 1901 1902#define S_FW_RDEV_WR_ALLOC 31 1903#define M_FW_RDEV_WR_ALLOC 0x1 1904#define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 1905#define G_FW_RDEV_WR_ALLOC(x) \ 1906 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 1907#define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 1908 1909#define S_FW_RDEV_WR_FREE 30 1910#define M_FW_RDEV_WR_FREE 0x1 1911#define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 1912#define G_FW_RDEV_WR_FREE(x) \ 1913 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 1914#define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 1915 1916#define S_FW_RDEV_WR_MODIFY 29 1917#define M_FW_RDEV_WR_MODIFY 0x1 1918#define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 1919#define G_FW_RDEV_WR_MODIFY(x) \ 1920 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 1921#define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 1922 1923#define S_FW_RDEV_WR_FLOWID 8 1924#define M_FW_RDEV_WR_FLOWID 0xfffff 1925#define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 1926#define G_FW_RDEV_WR_FLOWID(x) \ 1927 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 1928 1929#define S_FW_RDEV_WR_LEN16 0 1930#define M_FW_RDEV_WR_LEN16 0xff 1931#define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 1932#define G_FW_RDEV_WR_LEN16(x) \ 1933 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 1934 1935#define S_FW_RDEV_WR_FLAGS 24 1936#define M_FW_RDEV_WR_FLAGS 0xff 1937#define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 1938#define G_FW_RDEV_WR_FLAGS(x) \ 1939 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 1940 1941#define S_FW_RDEV_WR_GET_NEXT 20 1942#define M_FW_RDEV_WR_GET_NEXT 0xf 1943#define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 1944#define G_FW_RDEV_WR_GET_NEXT(x) \ 1945 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 1946 1947#define S_FW_RDEV_WR_ASSOC_FLOWID 0 1948#define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 1949#define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 1950#define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 1951 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 1952 1953#define S_FW_RDEV_WR_RJT 7 1954#define M_FW_RDEV_WR_RJT 0x1 1955#define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 1956#define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 1957#define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 1958 1959#define S_FW_RDEV_WR_REASON 0 1960#define M_FW_RDEV_WR_REASON 0x7f 1961#define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 1962#define G_FW_RDEV_WR_REASON(x) \ 1963 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 1964 1965#define S_FW_RDEV_WR_RD_XFER_RDY 7 1966#define M_FW_RDEV_WR_RD_XFER_RDY 0x1 1967#define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 1968#define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 1969 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 1970#define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 1971 1972#define S_FW_RDEV_WR_WR_XFER_RDY 6 1973#define M_FW_RDEV_WR_WR_XFER_RDY 0x1 1974#define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 1975#define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 1976 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 1977#define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 1978 1979#define S_FW_RDEV_WR_FC_SP 5 1980#define M_FW_RDEV_WR_FC_SP 0x1 1981#define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 1982#define G_FW_RDEV_WR_FC_SP(x) \ 1983 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 1984#define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 1985 1986#define S_FW_RDEV_WR_RPORT_TYPE 0 1987#define M_FW_RDEV_WR_RPORT_TYPE 0x1f 1988#define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 1989#define G_FW_RDEV_WR_RPORT_TYPE(x) \ 1990 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 1991 1992#define S_FW_RDEV_WR_VFT 7 1993#define M_FW_RDEV_WR_VFT 0x1 1994#define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 1995#define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 1996#define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 1997 1998#define S_FW_RDEV_WR_NPIV 6 1999#define M_FW_RDEV_WR_NPIV 0x1 2000#define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2001#define G_FW_RDEV_WR_NPIV(x) \ 2002 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2003#define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2004 2005#define S_FW_RDEV_WR_CLASS 4 2006#define M_FW_RDEV_WR_CLASS 0x3 2007#define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2008#define G_FW_RDEV_WR_CLASS(x) \ 2009 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2010 2011#define S_FW_RDEV_WR_SEQ_DEL 3 2012#define M_FW_RDEV_WR_SEQ_DEL 0x1 2013#define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2014#define G_FW_RDEV_WR_SEQ_DEL(x) \ 2015 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2016#define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2017 2018#define S_FW_RDEV_WR_PRIO_PREEMP 2 2019#define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2020#define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2021#define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2022 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2023#define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2024 2025#define S_FW_RDEV_WR_PREF 1 2026#define M_FW_RDEV_WR_PREF 0x1 2027#define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2028#define G_FW_RDEV_WR_PREF(x) \ 2029 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2030#define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2031 2032#define S_FW_RDEV_WR_QOS 0 2033#define M_FW_RDEV_WR_QOS 0x1 2034#define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2035#define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2036#define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2037 2038#define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2039#define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2040#define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2041#define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2042 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2043#define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2044 2045#define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2046#define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2047#define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2048#define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2049 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2050#define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2051 2052#define S_FW_RDEV_WR_IMAGE_PAIR 5 2053#define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2054#define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2055#define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2056 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2057#define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2058 2059#define S_FW_RDEV_WR_ACC_RSP_CODE 0 2060#define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2061#define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2062#define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2063 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2064 2065#define S_FW_RDEV_WR_ENH_DISC 7 2066#define M_FW_RDEV_WR_ENH_DISC 0x1 2067#define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2068#define G_FW_RDEV_WR_ENH_DISC(x) \ 2069 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2070#define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2071 2072#define S_FW_RDEV_WR_REC 6 2073#define M_FW_RDEV_WR_REC 0x1 2074#define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2075#define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2076#define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2077 2078#define S_FW_RDEV_WR_TASK_RETRY_ID 5 2079#define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2080#define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2081#define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2082 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2083#define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2084 2085#define S_FW_RDEV_WR_RETRY 4 2086#define M_FW_RDEV_WR_RETRY 0x1 2087#define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2088#define G_FW_RDEV_WR_RETRY(x) \ 2089 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2090#define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2091 2092#define S_FW_RDEV_WR_CONF_CMPL 3 2093#define M_FW_RDEV_WR_CONF_CMPL 0x1 2094#define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2095#define G_FW_RDEV_WR_CONF_CMPL(x) \ 2096 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2097#define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2098 2099#define S_FW_RDEV_WR_DATA_OVLY 2 2100#define M_FW_RDEV_WR_DATA_OVLY 0x1 2101#define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2102#define G_FW_RDEV_WR_DATA_OVLY(x) \ 2103 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2104#define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2105 2106#define S_FW_RDEV_WR_INI 1 2107#define M_FW_RDEV_WR_INI 0x1 2108#define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2109#define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2110#define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2111 2112#define S_FW_RDEV_WR_TGT 0 2113#define M_FW_RDEV_WR_TGT 0x1 2114#define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2115#define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2116#define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2117 2118struct fw_foiscsi_node_wr { 2119 __be32 op_to_immdlen; 2120 __be32 flowid_len16; 2121 __u64 cookie; |
1586 __u8 subop; | 2122 __u8 subop; |
1587 __be16 immd_len; | 2123 __u8 status; 2124 __u8 alias_len; 2125 __u8 iqn_len; 2126 __be32 node_flowid; 2127 __be16 nodeid; 2128 __be16 login_retry; 2129 __be16 retry_timeout; 2130 __be16 r3; 2131 __u8 iqn[224]; 2132 __u8 alias[224]; 2133}; 2134 2135#define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2136#define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2137#define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2138#define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2139 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2140 2141struct fw_foiscsi_ctrl_wr { 2142 __be32 op_compl; |
1588 __be32 flowid_len16; | 2143 __be32 flowid_len16; |
1589 __be64 cookie; 1590 __u8 node_attr_to_compl; | 2144 __u64 cookie; 2145 __u8 subop; |
1591 __u8 status; | 2146 __u8 status; |
1592 __be16 r1; | 2147 __u8 ctrl_state; 2148 __u8 io_state; |
1593 __be32 node_id; | 2149 __be32 node_id; |
1594 __be32 ctrl_handle; 1595 __be32 io_handle; | 2150 __be32 ctrl_id; 2151 __be32 io_id; 2152 struct fw_foiscsi_sess_attr { 2153 __be32 sess_type_to_erl; 2154 __be16 max_conn; 2155 __be16 max_r2t; 2156 __be16 time2wait; 2157 __be16 time2retain; 2158 __be32 max_burst; 2159 __be32 first_burst; 2160 __be32 r1; 2161 } sess_attr; 2162 struct fw_foiscsi_conn_attr { 2163 __be32 hdigest_to_auth_policy; 2164 __be32 max_rcv_dsl; 2165 __be32 ping_tmo; 2166 __be16 dst_port; 2167 __be16 src_port; 2168 union fw_foiscsi_conn_attr_addr { 2169 struct fw_foiscsi_conn_attr_ipv6 { 2170 __be64 dst_addr[2]; 2171 __be64 src_addr[2]; 2172 } ipv6_addr; 2173 struct fw_foiscsi_conn_attr_ipv4 { 2174 __be32 dst_addr; 2175 __be32 src_addr; 2176 } ipv4_addr; 2177 } u; 2178 } conn_attr; 2179 __u8 tgt_name_len; 2180 __u8 r3[7]; 2181 __u8 tgt_name[224]; |
1596}; 1597 | 2182}; 2183 |
1598#define S_FW_ISCSI_NODE_WR_FLOWID 8 1599#define M_FW_ISCSI_NODE_WR_FLOWID 0xfffff 1600#define V_FW_ISCSI_NODE_WR_FLOWID(x) ((x) << S_FW_ISCSI_NODE_WR_FLOWID) 1601#define G_FW_ISCSI_NODE_WR_FLOWID(x) \ 1602 (((x) >> S_FW_ISCSI_NODE_WR_FLOWID) & M_FW_ISCSI_NODE_WR_FLOWID) | 2184#define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2185#define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2186#define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2187 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2188#define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2189 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) |
1603 | 2190 |
1604#define S_FW_ISCSI_NODE_WR_LEN16 0 1605#define M_FW_ISCSI_NODE_WR_LEN16 0xff 1606#define V_FW_ISCSI_NODE_WR_LEN16(x) ((x) << S_FW_ISCSI_NODE_WR_LEN16) 1607#define G_FW_ISCSI_NODE_WR_LEN16(x) \ 1608 (((x) >> S_FW_ISCSI_NODE_WR_LEN16) & M_FW_ISCSI_NODE_WR_LEN16) | 2191#define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2192#define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2193#define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2194 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2195#define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2196 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2197 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2198#define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2199 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) |
1609 | 2200 |
1610#define S_FW_ISCSI_NODE_WR_NODE_ATTR 7 1611#define M_FW_ISCSI_NODE_WR_NODE_ATTR 0x1 1612#define V_FW_ISCSI_NODE_WR_NODE_ATTR(x) ((x) << S_FW_ISCSI_NODE_WR_NODE_ATTR) 1613#define G_FW_ISCSI_NODE_WR_NODE_ATTR(x) \ 1614 (((x) >> S_FW_ISCSI_NODE_WR_NODE_ATTR) & M_FW_ISCSI_NODE_WR_NODE_ATTR) 1615#define F_FW_ISCSI_NODE_WR_NODE_ATTR V_FW_ISCSI_NODE_WR_NODE_ATTR(1U) | 2201#define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2202#define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2203#define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2204 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2205#define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2206 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2207 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2208#define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2209 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) |
1616 | 2210 |
1617#define S_FW_ISCSI_NODE_WR_SESS_ATTR 6 1618#define M_FW_ISCSI_NODE_WR_SESS_ATTR 0x1 1619#define V_FW_ISCSI_NODE_WR_SESS_ATTR(x) ((x) << S_FW_ISCSI_NODE_WR_SESS_ATTR) 1620#define G_FW_ISCSI_NODE_WR_SESS_ATTR(x) \ 1621 (((x) >> S_FW_ISCSI_NODE_WR_SESS_ATTR) & M_FW_ISCSI_NODE_WR_SESS_ATTR) 1622#define F_FW_ISCSI_NODE_WR_SESS_ATTR V_FW_ISCSI_NODE_WR_SESS_ATTR(1U) | 2211#define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2212#define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2213#define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2214 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2215#define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2216 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2217 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2218#define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2219 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) |
1623 | 2220 |
1624#define S_FW_ISCSI_NODE_WR_CONN_ATTR 5 1625#define M_FW_ISCSI_NODE_WR_CONN_ATTR 0x1 1626#define V_FW_ISCSI_NODE_WR_CONN_ATTR(x) ((x) << S_FW_ISCSI_NODE_WR_CONN_ATTR) 1627#define G_FW_ISCSI_NODE_WR_CONN_ATTR(x) \ 1628 (((x) >> S_FW_ISCSI_NODE_WR_CONN_ATTR) & M_FW_ISCSI_NODE_WR_CONN_ATTR) 1629#define F_FW_ISCSI_NODE_WR_CONN_ATTR V_FW_ISCSI_NODE_WR_CONN_ATTR(1U) | 2221#define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2222#define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2223#define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2224 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2225#define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2226 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2227 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2228#define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2229 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) |
1630 | 2230 |
1631#define S_FW_ISCSI_NODE_WR_TGT_ATTR 4 1632#define M_FW_ISCSI_NODE_WR_TGT_ATTR 0x1 1633#define V_FW_ISCSI_NODE_WR_TGT_ATTR(x) ((x) << S_FW_ISCSI_NODE_WR_TGT_ATTR) 1634#define G_FW_ISCSI_NODE_WR_TGT_ATTR(x) \ 1635 (((x) >> S_FW_ISCSI_NODE_WR_TGT_ATTR) & M_FW_ISCSI_NODE_WR_TGT_ATTR) 1636#define F_FW_ISCSI_NODE_WR_TGT_ATTR V_FW_ISCSI_NODE_WR_TGT_ATTR(1U) | 2231#define S_FW_FOISCSI_CTRL_WR_ERL 24 2232#define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2233#define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2234#define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2235 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) |
1637 | 2236 |
1638#define S_FW_ISCSI_NODE_WR_NODE_TYPE 3 1639#define M_FW_ISCSI_NODE_WR_NODE_TYPE 0x1 1640#define V_FW_ISCSI_NODE_WR_NODE_TYPE(x) ((x) << S_FW_ISCSI_NODE_WR_NODE_TYPE) 1641#define G_FW_ISCSI_NODE_WR_NODE_TYPE(x) \ 1642 (((x) >> S_FW_ISCSI_NODE_WR_NODE_TYPE) & M_FW_ISCSI_NODE_WR_NODE_TYPE) 1643#define F_FW_ISCSI_NODE_WR_NODE_TYPE V_FW_ISCSI_NODE_WR_NODE_TYPE(1U) | 2237#define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2238#define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2239#define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2240#define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2241 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) |
1644 | 2242 |
1645#define S_FW_ISCSI_NODE_WR_COMPL 0 1646#define M_FW_ISCSI_NODE_WR_COMPL 0x1 1647#define V_FW_ISCSI_NODE_WR_COMPL(x) ((x) << S_FW_ISCSI_NODE_WR_COMPL) 1648#define G_FW_ISCSI_NODE_WR_COMPL(x) \ 1649 (((x) >> S_FW_ISCSI_NODE_WR_COMPL) & M_FW_ISCSI_NODE_WR_COMPL) 1650#define F_FW_ISCSI_NODE_WR_COMPL V_FW_ISCSI_NODE_WR_COMPL(1U) | 2243#define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2244#define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2245#define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2246#define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2247 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) |
1651 | 2248 |
1652#define FW_ISCSI_NODE_INVALID_ID 0xffffffff | 2249#define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2250#define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2251#define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2252 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2253#define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2254 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2255 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) |
1653 | 2256 |
1654struct fw_scsi_iscsi_data { 1655 __u8 r0; 1656 __u8 fbit_to_tattr; 1657 __be16 r2; 1658 __be32 r3; 1659 __u8 lun[8]; | 2257#define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2258#define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2259#define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2260 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2261#define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2262 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2263 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2264 2265struct fw_foiscsi_chap_wr { 2266 __be32 op_compl; 2267 __be32 flowid_len16; 2268 __u64 cookie; 2269 __u8 status; 2270 __u8 id_len; 2271 __u8 sec_len; 2272 __u8 tgt_id_len; 2273 __u8 tgt_sec_len; 2274 __be16 node_id; 2275 __u8 r2; 2276 __u8 chap_id[64]; 2277 __u8 chap_sec[16]; 2278 __u8 tgt_id[64]; 2279 __u8 tgt_sec[16]; 2280}; 2281 2282/****************************************************************************** 2283 * F O F C O E W O R K R E Q U E S T s 2284 *******************************************/ 2285 2286struct fw_fcoe_els_ct_wr { 2287 __be32 op_immdlen; 2288 __be32 flowid_len16; 2289 __be64 cookie; 2290 __be16 iqid; 2291 __u8 tmo_val; 2292 __u8 els_ct_type; 2293 __u8 ctl_pri; 2294 __u8 cp_en_class; 2295 __be16 xfer_cnt; 2296 __u8 fl_to_sp; 2297 __u8 l_id[3]; 2298 __u8 r5; 2299 __u8 r_id[3]; 2300 __be64 rsp_dmaaddr; 2301 __be32 rsp_dmalen; 2302 __be32 r6; 2303}; 2304 2305#define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2306#define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2307#define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2308#define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2309 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2310 2311#define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2312#define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2313#define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2314#define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2315 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2316 2317#define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2318#define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2319#define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2320#define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2321 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2322 2323#define S_FW_FCOE_ELS_CT_WR_LEN16 0 2324#define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2325#define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2326#define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2327 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2328 2329#define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2330#define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2331#define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2332#define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2333 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2334 2335#define S_FW_FCOE_ELS_CT_WR_CLASS 4 2336#define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2337#define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2338#define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2339 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2340 2341#define S_FW_FCOE_ELS_CT_WR_FL 2 2342#define M_FW_FCOE_ELS_CT_WR_FL 0x1 2343#define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2344#define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2345 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2346#define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2347 2348#define S_FW_FCOE_ELS_CT_WR_NPIV 1 2349#define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2350#define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2351#define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2352 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2353#define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2354 2355#define S_FW_FCOE_ELS_CT_WR_SP 0 2356#define M_FW_FCOE_ELS_CT_WR_SP 0x1 2357#define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2358#define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2359 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2360#define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2361 2362/****************************************************************************** 2363 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2364 *****************************************************************************/ 2365 2366struct fw_scsi_write_wr { 2367 __be32 op_immdlen; 2368 __be32 flowid_len16; 2369 __be64 cookie; 2370 __be16 iqid; 2371 __u8 tmo_val; 2372 __u8 use_xfer_cnt; 2373 union fw_scsi_write_priv { 2374 struct fcoe_write_priv { 2375 __u8 ctl_pri; 2376 __u8 cp_en_class; 2377 __u8 r3_lo[2]; 2378 } fcoe; 2379 struct iscsi_write_priv { 2380 __u8 r3[4]; 2381 } iscsi; 2382 } u; 2383 __be32 xfer_cnt; 2384 __be32 ini_xfer_cnt; 2385 __be64 rsp_dmaaddr; 2386 __be32 rsp_dmalen; |
1660 __be32 r4; | 2387 __be32 r4; |
1661 __be32 dlen; 1662 __be32 r5; | 2388}; 2389 2390#define S_FW_SCSI_WRITE_WR_OPCODE 24 2391#define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2392#define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2393#define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2394 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2395 2396#define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2397#define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2398#define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2399#define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2400 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2401 2402#define S_FW_SCSI_WRITE_WR_FLOWID 8 2403#define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2404#define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2405#define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2406 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2407 2408#define S_FW_SCSI_WRITE_WR_LEN16 0 2409#define M_FW_SCSI_WRITE_WR_LEN16 0xff 2410#define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2411#define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2412 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2413 2414#define S_FW_SCSI_WRITE_WR_CP_EN 6 2415#define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2416#define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2417#define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2418 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2419 2420#define S_FW_SCSI_WRITE_WR_CLASS 4 2421#define M_FW_SCSI_WRITE_WR_CLASS 0x3 2422#define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2423#define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2424 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2425 2426struct fw_scsi_read_wr { 2427 __be32 op_immdlen; 2428 __be32 flowid_len16; 2429 __be64 cookie; 2430 __be16 iqid; 2431 __u8 tmo_val; 2432 __u8 use_xfer_cnt; 2433 union fw_scsi_read_priv { 2434 struct fcoe_read_priv { 2435 __u8 ctl_pri; 2436 __u8 cp_en_class; 2437 __u8 r3_lo[2]; 2438 } fcoe; 2439 struct iscsi_read_priv { 2440 __u8 r3[4]; 2441 } iscsi; 2442 } u; 2443 __be32 xfer_cnt; 2444 __be32 ini_xfer_cnt; 2445 __be64 rsp_dmaaddr; 2446 __be32 rsp_dmalen; 2447 __be32 r4; 2448}; 2449 2450#define S_FW_SCSI_READ_WR_OPCODE 24 2451#define M_FW_SCSI_READ_WR_OPCODE 0xff 2452#define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2453#define G_FW_SCSI_READ_WR_OPCODE(x) \ 2454 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2455 2456#define S_FW_SCSI_READ_WR_IMMDLEN 0 2457#define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2458#define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2459#define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2460 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2461 2462#define S_FW_SCSI_READ_WR_FLOWID 8 2463#define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2464#define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2465#define G_FW_SCSI_READ_WR_FLOWID(x) \ 2466 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2467 2468#define S_FW_SCSI_READ_WR_LEN16 0 2469#define M_FW_SCSI_READ_WR_LEN16 0xff 2470#define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2471#define G_FW_SCSI_READ_WR_LEN16(x) \ 2472 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2473 2474#define S_FW_SCSI_READ_WR_CP_EN 6 2475#define M_FW_SCSI_READ_WR_CP_EN 0x3 2476#define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2477#define G_FW_SCSI_READ_WR_CP_EN(x) \ 2478 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2479 2480#define S_FW_SCSI_READ_WR_CLASS 4 2481#define M_FW_SCSI_READ_WR_CLASS 0x3 2482#define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2483#define G_FW_SCSI_READ_WR_CLASS(x) \ 2484 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2485 2486struct fw_scsi_cmd_wr { 2487 __be32 op_immdlen; 2488 __be32 flowid_len16; 2489 __be64 cookie; 2490 __be16 iqid; 2491 __u8 tmo_val; 2492 __u8 r3; 2493 union fw_scsi_cmd_priv { 2494 struct fcoe_cmd_priv { 2495 __u8 ctl_pri; 2496 __u8 cp_en_class; 2497 __u8 r4_lo[2]; 2498 } fcoe; 2499 struct iscsi_cmd_priv { 2500 __u8 r4[4]; 2501 } iscsi; 2502 } u; 2503 __u8 r5[8]; 2504 __be64 rsp_dmaaddr; 2505 __be32 rsp_dmalen; |
1663 __be32 r6; | 2506 __be32 r6; |
1664 __u8 cdb[16]; | |
1665}; 1666 | 2507}; 2508 |
1667#define S_FW_SCSI_ISCSI_DATA_FBIT 7 1668#define M_FW_SCSI_ISCSI_DATA_FBIT 0x1 1669#define V_FW_SCSI_ISCSI_DATA_FBIT(x) ((x) << S_FW_SCSI_ISCSI_DATA_FBIT) 1670#define G_FW_SCSI_ISCSI_DATA_FBIT(x) \ 1671 (((x) >> S_FW_SCSI_ISCSI_DATA_FBIT) & M_FW_SCSI_ISCSI_DATA_FBIT) 1672#define F_FW_SCSI_ISCSI_DATA_FBIT V_FW_SCSI_ISCSI_DATA_FBIT(1U) | 2509#define S_FW_SCSI_CMD_WR_OPCODE 24 2510#define M_FW_SCSI_CMD_WR_OPCODE 0xff 2511#define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2512#define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2513 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) |
1673 | 2514 |
1674#define S_FW_SCSI_ISCSI_DATA_RBIT 6 1675#define M_FW_SCSI_ISCSI_DATA_RBIT 0x1 1676#define V_FW_SCSI_ISCSI_DATA_RBIT(x) ((x) << S_FW_SCSI_ISCSI_DATA_RBIT) 1677#define G_FW_SCSI_ISCSI_DATA_RBIT(x) \ 1678 (((x) >> S_FW_SCSI_ISCSI_DATA_RBIT) & M_FW_SCSI_ISCSI_DATA_RBIT) 1679#define F_FW_SCSI_ISCSI_DATA_RBIT V_FW_SCSI_ISCSI_DATA_RBIT(1U) | 2515#define S_FW_SCSI_CMD_WR_IMMDLEN 0 2516#define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2517#define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2518#define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2519 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) |
1680 | 2520 |
1681#define S_FW_SCSI_ISCSI_DATA_WBIT 5 1682#define M_FW_SCSI_ISCSI_DATA_WBIT 0x1 1683#define V_FW_SCSI_ISCSI_DATA_WBIT(x) ((x) << S_FW_SCSI_ISCSI_DATA_WBIT) 1684#define G_FW_SCSI_ISCSI_DATA_WBIT(x) \ 1685 (((x) >> S_FW_SCSI_ISCSI_DATA_WBIT) & M_FW_SCSI_ISCSI_DATA_WBIT) 1686#define F_FW_SCSI_ISCSI_DATA_WBIT V_FW_SCSI_ISCSI_DATA_WBIT(1U) | 2521#define S_FW_SCSI_CMD_WR_FLOWID 8 2522#define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2523#define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2524#define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2525 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) |
1687 | 2526 |
1688#define S_FW_SCSI_ISCSI_DATA_TATTR 0 1689#define M_FW_SCSI_ISCSI_DATA_TATTR 0x7 1690#define V_FW_SCSI_ISCSI_DATA_TATTR(x) ((x) << S_FW_SCSI_ISCSI_DATA_TATTR) 1691#define G_FW_SCSI_ISCSI_DATA_TATTR(x) \ 1692 (((x) >> S_FW_SCSI_ISCSI_DATA_TATTR) & M_FW_SCSI_ISCSI_DATA_TATTR) | 2527#define S_FW_SCSI_CMD_WR_LEN16 0 2528#define M_FW_SCSI_CMD_WR_LEN16 0xff 2529#define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2530#define G_FW_SCSI_CMD_WR_LEN16(x) \ 2531 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) |
1693 | 2532 |
1694#define FW_SCSI_ISCSI_DATA_TATTR_UNTAGGED 0 1695#define FW_SCSI_ISCSI_DATA_TATTR_SIMPLE 1 1696#define FW_SCSI_ISCSI_DATA_TATTR_ORDERED 2 1697#define FW_SCSI_ISCSI_DATA_TATTR_HEADOQ 3 1698#define FW_SCSI_ISCSI_DATA_TATTR_ACA 4 | 2533#define S_FW_SCSI_CMD_WR_CP_EN 6 2534#define M_FW_SCSI_CMD_WR_CP_EN 0x3 2535#define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2536#define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2537 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) |
1699 | 2538 |
1700#define FW_SCSI_ISCSI_TMF_OP 0x02 1701#define FW_SCSI_ISCSI_ABORT_FUNC 0x01 1702#define FW_SCSI_ISCSI_LUN_RESET_FUNC 0x05 1703#define FW_SCSI_ISCSI_RESERVED_TAG 0xffffffff | 2539#define S_FW_SCSI_CMD_WR_CLASS 4 2540#define M_FW_SCSI_CMD_WR_CLASS 0x3 2541#define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2542#define G_FW_SCSI_CMD_WR_CLASS(x) \ 2543 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) |
1704 | 2544 |
1705struct fw_scsi_iscsi_rsp { 1706 __u8 r0; 1707 __u8 sbit_to_uflow; 1708 __u8 response; 1709 __u8 status; | 2545struct fw_scsi_abrt_cls_wr { 2546 __be32 op_immdlen; 2547 __be32 flowid_len16; 2548 __be64 cookie; 2549 __be16 iqid; 2550 __u8 tmo_val; 2551 __u8 sub_opcode_to_chk_all_io; 2552 __u8 r3[4]; 2553 __be64 t_cookie; 2554}; 2555 2556#define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 2557#define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 2558#define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 2559#define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 2560 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 2561 2562#define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 2563#define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 2564#define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2565 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2566#define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2567 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2568 2569#define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 2570#define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 2571#define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 2572#define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 2573 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 2574 2575#define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 2576#define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 2577#define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 2578#define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 2579 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 2580 2581#define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 2582#define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 2583#define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2584 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2585#define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2586 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 2587 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2588 2589#define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 2590#define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 2591#define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 2592#define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 2593 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 2594#define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 2595 2596#define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 2597#define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 2598#define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2599 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2600#define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2601 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 2602 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2603#define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 2604 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 2605 2606struct fw_scsi_tgt_acc_wr { 2607 __be32 op_immdlen; 2608 __be32 flowid_len16; 2609 __be64 cookie; 2610 __be16 iqid; 2611 __u8 r3; 2612 __u8 use_burst_len; 2613 union fw_scsi_tgt_acc_priv { 2614 struct fcoe_tgt_acc_priv { 2615 __u8 ctl_pri; 2616 __u8 cp_en_class; 2617 __u8 r4_lo[2]; 2618 } fcoe; 2619 struct iscsi_tgt_acc_priv { 2620 __u8 r4[4]; 2621 } iscsi; 2622 } u; 2623 __be32 burst_len; 2624 __be32 rel_off; 2625 __be64 r5; 2626 __be32 r6; 2627 __be32 tot_xfer_len; 2628}; 2629 2630#define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 2631#define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 2632#define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 2633#define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 2634 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 2635 2636#define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 2637#define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 2638#define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2639#define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 2640 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2641 2642#define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 2643#define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 2644#define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 2645#define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 2646 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 2647 2648#define S_FW_SCSI_TGT_ACC_WR_LEN16 0 2649#define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 2650#define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 2651#define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 2652 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 2653 2654#define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 2655#define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 2656#define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 2657#define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 2658 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 2659 2660#define S_FW_SCSI_TGT_ACC_WR_CLASS 4 2661#define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 2662#define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 2663#define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 2664 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 2665 2666struct fw_scsi_tgt_xmit_wr { 2667 __be32 op_immdlen; 2668 __be32 flowid_len16; 2669 __be64 cookie; 2670 __be16 iqid; 2671 __u8 auto_rsp; 2672 __u8 use_xfer_cnt; 2673 union fw_scsi_tgt_xmit_priv { 2674 struct fcoe_tgt_xmit_priv { 2675 __u8 ctl_pri; 2676 __u8 cp_en_class; 2677 __u8 r3_lo[2]; 2678 } fcoe; 2679 struct iscsi_tgt_xmit_priv { 2680 __u8 r3[4]; 2681 } iscsi; 2682 } u; 2683 __be32 xfer_cnt; |
1710 __be32 r4; | 2684 __be32 r4; |
1711 __u8 r5[32]; 1712 __be32 bidir_res_cnt; 1713 __be32 res_cnt; 1714 __u8 sense_data[128]; | 2685 __be64 r5; 2686 __be32 r6; 2687 __be32 tot_xfer_len; |
1715}; 1716 | 2688}; 2689 |
1717#define S_FW_SCSI_ISCSI_RSP_SBIT 7 1718#define M_FW_SCSI_ISCSI_RSP_SBIT 0x1 1719#define V_FW_SCSI_ISCSI_RSP_SBIT(x) ((x) << S_FW_SCSI_ISCSI_RSP_SBIT) 1720#define G_FW_SCSI_ISCSI_RSP_SBIT(x) \ 1721 (((x) >> S_FW_SCSI_ISCSI_RSP_SBIT) & M_FW_SCSI_ISCSI_RSP_SBIT) 1722#define F_FW_SCSI_ISCSI_RSP_SBIT V_FW_SCSI_ISCSI_RSP_SBIT(1U) | 2690#define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 2691#define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 2692#define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 2693#define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 2694 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) |
1723 | 2695 |
1724#define S_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW 4 1725#define M_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW 0x1 1726#define V_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW(x) \ 1727 ((x) << S_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW) 1728#define G_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW(x) \ 1729 (((x) >> S_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW) & \ 1730 M_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW) 1731#define F_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW V_FW_SCSI_ISCSI_RSP_BIDIR_OFLOW(1U) | 2696#define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 2697#define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 2698#define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2699 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2700#define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2701 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) |
1732 | 2702 |
1733#define S_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW 3 1734#define M_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW 0x1 1735#define V_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW(x) \ 1736 ((x) << S_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW) 1737#define G_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW(x) \ 1738 (((x) >> S_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW) & \ 1739 M_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW) 1740#define F_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW V_FW_SCSI_ISCSI_RSP_BIDIR_UFLOW(1U) | 2703#define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 2704#define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 2705#define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 2706#define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 2707 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) |
1741 | 2708 |
1742#define S_FW_SCSI_ISCSI_RSP_OFLOW 2 1743#define M_FW_SCSI_ISCSI_RSP_OFLOW 0x1 1744#define V_FW_SCSI_ISCSI_RSP_OFLOW(x) ((x) << S_FW_SCSI_ISCSI_RSP_OFLOW) 1745#define G_FW_SCSI_ISCSI_RSP_OFLOW(x) \ 1746 (((x) >> S_FW_SCSI_ISCSI_RSP_OFLOW) & M_FW_SCSI_ISCSI_RSP_OFLOW) 1747#define F_FW_SCSI_ISCSI_RSP_OFLOW V_FW_SCSI_ISCSI_RSP_OFLOW(1U) | 2709#define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 2710#define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 2711#define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 2712#define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 2713 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) |
1748 | 2714 |
1749#define S_FW_SCSI_ISCSI_RSP_UFLOW 1 1750#define M_FW_SCSI_ISCSI_RSP_UFLOW 0x1 1751#define V_FW_SCSI_ISCSI_RSP_UFLOW(x) ((x) << S_FW_SCSI_ISCSI_RSP_UFLOW) 1752#define G_FW_SCSI_ISCSI_RSP_UFLOW(x) \ 1753 (((x) >> S_FW_SCSI_ISCSI_RSP_UFLOW) & M_FW_SCSI_ISCSI_RSP_UFLOW) 1754#define F_FW_SCSI_ISCSI_RSP_UFLOW V_FW_SCSI_ISCSI_RSP_UFLOW(1U) | 2715#define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 2716#define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 2717#define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 2718#define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 2719 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) |
1755 | 2720 |
2721#define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 2722#define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 2723#define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 2724#define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 2725 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 2726 2727struct fw_scsi_tgt_rsp_wr { 2728 __be32 op_immdlen; 2729 __be32 flowid_len16; 2730 __be64 cookie; 2731 __be16 iqid; 2732 __u8 r3[2]; 2733 union fw_scsi_tgt_rsp_priv { 2734 struct fcoe_tgt_rsp_priv { 2735 __u8 ctl_pri; 2736 __u8 cp_en_class; 2737 __u8 r4_lo[2]; 2738 } fcoe; 2739 struct iscsi_tgt_rsp_priv { 2740 __u8 r4[4]; 2741 } iscsi; 2742 } u; 2743 __u8 r5[8]; 2744}; 2745 2746#define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 2747#define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 2748#define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 2749#define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 2750 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 2751 2752#define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 2753#define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 2754#define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2755#define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 2756 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2757 2758#define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 2759#define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 2760#define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 2761#define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 2762 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 2763 2764#define S_FW_SCSI_TGT_RSP_WR_LEN16 0 2765#define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 2766#define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 2767#define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 2768 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 2769 2770#define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 2771#define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 2772#define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 2773#define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 2774 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 2775 2776#define S_FW_SCSI_TGT_RSP_WR_CLASS 4 2777#define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 2778#define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 2779#define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 2780 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 2781 |
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1756/****************************************************************************** 1757 * C O M M A N D s 1758 *********************/ 1759 1760/* 1761 * The maximum length of time, in miliseconds, that we expect any firmware 1762 * command to take to execute and return a reply to the host. The RESET 1763 * and INITIALIZE commands can take a fair amount of time to execute but --- 39 unchanged lines hidden (view full) --- 1803 FW_PORT_LB_STATS_CMD = 0x1d, 1804 FW_PORT_TRACE_CMD = 0x1e, 1805 FW_PORT_TRACE_MMAP_CMD = 0x1f, 1806 FW_RSS_IND_TBL_CMD = 0x20, 1807 FW_RSS_GLB_CONFIG_CMD = 0x22, 1808 FW_RSS_VI_CONFIG_CMD = 0x23, 1809 FW_SCHED_CMD = 0x24, 1810 FW_DEVLOG_CMD = 0x25, | 2782/****************************************************************************** 2783 * C O M M A N D s 2784 *********************/ 2785 2786/* 2787 * The maximum length of time, in miliseconds, that we expect any firmware 2788 * command to take to execute and return a reply to the host. The RESET 2789 * and INITIALIZE commands can take a fair amount of time to execute but --- 39 unchanged lines hidden (view full) --- 2829 FW_PORT_LB_STATS_CMD = 0x1d, 2830 FW_PORT_TRACE_CMD = 0x1e, 2831 FW_PORT_TRACE_MMAP_CMD = 0x1f, 2832 FW_RSS_IND_TBL_CMD = 0x20, 2833 FW_RSS_GLB_CONFIG_CMD = 0x22, 2834 FW_RSS_VI_CONFIG_CMD = 0x23, 2835 FW_SCHED_CMD = 0x24, 2836 FW_DEVLOG_CMD = 0x25, |
1811 FW_NETIF_CMD = 0x26, | |
1812 FW_WATCHDOG_CMD = 0x27, 1813 FW_CLIP_CMD = 0x28, | 2837 FW_WATCHDOG_CMD = 0x27, 2838 FW_CLIP_CMD = 0x28, |
2839 FW_CHNET_IFACE_CMD = 0x26, 2840 FW_FCOE_RES_INFO_CMD = 0x31, 2841 FW_FCOE_LINK_CMD = 0x32, 2842 FW_FCOE_VNP_CMD = 0x33, 2843 FW_FCOE_SPARAMS_CMD = 0x35, 2844 FW_FCOE_STATS_CMD = 0x37, 2845 FW_FCOE_FCF_CMD = 0x38, |
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1814 FW_LASTC2E_CMD = 0x40, 1815 FW_ERROR_CMD = 0x80, 1816 FW_DEBUG_CMD = 0x81, 1817}; 1818 1819enum fw_cmd_cap { 1820 FW_CMD_CAP_PF = 0x01, 1821 FW_CMD_CAP_DMAQ = 0x02, --- 69 unchanged lines hidden (view full) --- 1891 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 1892 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 1893 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 1894 FW_LDST_ADDRSPC_MDIO = 0x0018, 1895 FW_LDST_ADDRSPC_MPS = 0x0020, 1896 FW_LDST_ADDRSPC_FUNC = 0x0028, 1897 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 1898 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, | 2846 FW_LASTC2E_CMD = 0x40, 2847 FW_ERROR_CMD = 0x80, 2848 FW_DEBUG_CMD = 0x81, 2849}; 2850 2851enum fw_cmd_cap { 2852 FW_CMD_CAP_PF = 0x01, 2853 FW_CMD_CAP_DMAQ = 0x02, --- 69 unchanged lines hidden (view full) --- 2923 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 2924 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 2925 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 2926 FW_LDST_ADDRSPC_MDIO = 0x0018, 2927 FW_LDST_ADDRSPC_MPS = 0x0020, 2928 FW_LDST_ADDRSPC_FUNC = 0x0028, 2929 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 2930 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, |
2931 FW_LDST_ADDRSPC_LE = 0x0030, |
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1899}; 1900 1901/* 1902 * MDIO VSC8634 register access control field 1903 */ 1904enum fw_ldst_mdio_vsc8634_aid { 1905 FW_LDST_MDIO_VS_STANDARD, 1906 FW_LDST_MDIO_VS_EXTENDED, --- 70 unchanged lines hidden (view full) --- 1977 } pcie; 1978 struct fw_ldst_i2c { 1979 __u8 pid_pkd; 1980 __u8 base; 1981 __u8 boffset; 1982 __u8 data; 1983 __be32 r9; 1984 } i2c; | 2932}; 2933 2934/* 2935 * MDIO VSC8634 register access control field 2936 */ 2937enum fw_ldst_mdio_vsc8634_aid { 2938 FW_LDST_MDIO_VS_STANDARD, 2939 FW_LDST_MDIO_VS_EXTENDED, --- 70 unchanged lines hidden (view full) --- 3010 } pcie; 3011 struct fw_ldst_i2c { 3012 __u8 pid_pkd; 3013 __u8 base; 3014 __u8 boffset; 3015 __u8 data; 3016 __be32 r9; 3017 } i2c; |
3018 struct fw_ldst_le { 3019 __be16 region; 3020 __be16 nval; 3021 __u32 val[12]; 3022 } le; |
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1985 } u; 1986}; 1987 1988#define S_FW_LDST_CMD_ADDRSPACE 0 1989#define M_FW_LDST_CMD_ADDRSPACE 0xff 1990#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 1991#define G_FW_LDST_CMD_ADDRSPACE(x) \ 1992 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) --- 293 unchanged lines hidden (view full) --- 2286 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 2287}; 2288 2289enum fw_memtype_cf { 2290 FW_MEMTYPE_CF_EDC0 = 0x0, 2291 FW_MEMTYPE_CF_EDC1 = 0x1, 2292 FW_MEMTYPE_CF_EXTMEM = 0x2, 2293 FW_MEMTYPE_CF_FLASH = 0x4, | 3023 } u; 3024}; 3025 3026#define S_FW_LDST_CMD_ADDRSPACE 0 3027#define M_FW_LDST_CMD_ADDRSPACE 0xff 3028#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3029#define G_FW_LDST_CMD_ADDRSPACE(x) \ 3030 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) --- 293 unchanged lines hidden (view full) --- 3324 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3325}; 3326 3327enum fw_memtype_cf { 3328 FW_MEMTYPE_CF_EDC0 = 0x0, 3329 FW_MEMTYPE_CF_EDC1 = 0x1, 3330 FW_MEMTYPE_CF_EXTMEM = 0x2, 3331 FW_MEMTYPE_CF_FLASH = 0x4, |
3332 FW_MEMTYPE_CF_INTERNAL = 0x5, |
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2294}; 2295 2296struct fw_caps_config_cmd { 2297 __be32 op_to_write; 2298 __be32 cfvalid_to_len16; 2299 __be32 r2; 2300 __be32 hwmbitmap; 2301 __be16 nbmcaps; --- 102 unchanged lines hidden (view full) --- 2404 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 2405 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 2406 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 2407 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 2408 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 2409 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 2410 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 2411 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, | 3333}; 3334 3335struct fw_caps_config_cmd { 3336 __be32 op_to_write; 3337 __be32 cfvalid_to_len16; 3338 __be32 r2; 3339 __be32 hwmbitmap; 3340 __be16 nbmcaps; --- 102 unchanged lines hidden (view full) --- 3443 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 3444 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 3445 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 3446 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 3447 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 3448 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 3449 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 3450 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, |
2412 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C | 3451 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 3452 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 3453 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 3454 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 3455 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30 |
2413}; 2414 2415/* 2416 * dma queue parameters 2417 */ 2418enum fw_params_param_dmaq { 2419 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 2420 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 2421 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 2422 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 2423 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, | 3456}; 3457 3458/* 3459 * dma queue parameters 3460 */ 3461enum fw_params_param_dmaq { 3462 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 3463 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 3464 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 3465 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 3466 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, |
3467 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13 |
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2424}; 2425 2426/* 2427 * dev bypass parameters; actions and modes 2428 */ 2429enum fw_params_param_dev_bypass { 2430 2431 /* actions --- 1517 unchanged lines hidden (view full) --- 3949#define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 3950#define G_FW_VI_CMD_IDSEIQ(x) \ 3951 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 3952 3953/* Special VI_MAC command index ids */ 3954#define FW_VI_MAC_ADD_MAC 0x3FF 3955#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 3956#define FW_VI_MAC_MAC_BASED_FREE 0x3FD | 3468}; 3469 3470/* 3471 * dev bypass parameters; actions and modes 3472 */ 3473enum fw_params_param_dev_bypass { 3474 3475 /* actions --- 1517 unchanged lines hidden (view full) --- 4993#define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 4994#define G_FW_VI_CMD_IDSEIQ(x) \ 4995 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 4996 4997/* Special VI_MAC command index ids */ 4998#define FW_VI_MAC_ADD_MAC 0x3FF 4999#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 5000#define FW_VI_MAC_MAC_BASED_FREE 0x3FD |
3957#define FW_CLS_TCAM_NUM_ENTRIES 336 | |
3958 3959enum fw_vi_mac_smac { 3960 FW_VI_MAC_MPS_TCAM_ENTRY, 3961 FW_VI_MAC_MPS_TCAM_ONLY, 3962 FW_VI_MAC_SMT_ONLY, 3963 FW_VI_MAC_SMT_AND_MPSTCAM 3964}; 3965 --- 1691 unchanged lines hidden (view full) --- 5657#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 5658#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 5659#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 5660 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 5661#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 5662 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 5663 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 5664 | 5001 5002enum fw_vi_mac_smac { 5003 FW_VI_MAC_MPS_TCAM_ENTRY, 5004 FW_VI_MAC_MPS_TCAM_ONLY, 5005 FW_VI_MAC_SMT_ONLY, 5006 FW_VI_MAC_SMT_AND_MPSTCAM 5007}; 5008 --- 1691 unchanged lines hidden (view full) --- 6700#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 6701#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 6702#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6703 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6704#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6705 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 6706 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6707 |
5665struct fw_netif_cmd { 5666 __be32 op_to_ipv4gw; 5667 __be32 retval_len16; 5668 __be32 netifi_ifadridx; 5669 __be32 portid_to_mtuval; 5670 __be32 gwaddr; 5671 __be32 addr; 5672 __be32 nmask; 5673 __be32 bcaddr; 5674}; 5675 5676#define S_FW_NETIF_CMD_ADD 20 5677#define M_FW_NETIF_CMD_ADD 0x1 5678#define V_FW_NETIF_CMD_ADD(x) ((x) << S_FW_NETIF_CMD_ADD) 5679#define G_FW_NETIF_CMD_ADD(x) \ 5680 (((x) >> S_FW_NETIF_CMD_ADD) & M_FW_NETIF_CMD_ADD) 5681#define F_FW_NETIF_CMD_ADD V_FW_NETIF_CMD_ADD(1U) 5682 5683#define S_FW_NETIF_CMD_LINK 19 5684#define M_FW_NETIF_CMD_LINK 0x1 5685#define V_FW_NETIF_CMD_LINK(x) ((x) << S_FW_NETIF_CMD_LINK) 5686#define G_FW_NETIF_CMD_LINK(x) \ 5687 (((x) >> S_FW_NETIF_CMD_LINK) & M_FW_NETIF_CMD_LINK) 5688#define F_FW_NETIF_CMD_LINK V_FW_NETIF_CMD_LINK(1U) 5689 5690#define S_FW_NETIF_CMD_VLAN 18 5691#define M_FW_NETIF_CMD_VLAN 0x1 5692#define V_FW_NETIF_CMD_VLAN(x) ((x) << S_FW_NETIF_CMD_VLAN) 5693#define G_FW_NETIF_CMD_VLAN(x) \ 5694 (((x) >> S_FW_NETIF_CMD_VLAN) & M_FW_NETIF_CMD_VLAN) 5695#define F_FW_NETIF_CMD_VLAN V_FW_NETIF_CMD_VLAN(1U) 5696 5697#define S_FW_NETIF_CMD_MTU 17 5698#define M_FW_NETIF_CMD_MTU 0x1 5699#define V_FW_NETIF_CMD_MTU(x) ((x) << S_FW_NETIF_CMD_MTU) 5700#define G_FW_NETIF_CMD_MTU(x) \ 5701 (((x) >> S_FW_NETIF_CMD_MTU) & M_FW_NETIF_CMD_MTU) 5702#define F_FW_NETIF_CMD_MTU V_FW_NETIF_CMD_MTU(1U) 5703 5704#define S_FW_NETIF_CMD_DHCP 16 5705#define M_FW_NETIF_CMD_DHCP 0x1 5706#define V_FW_NETIF_CMD_DHCP(x) ((x) << S_FW_NETIF_CMD_DHCP) 5707#define G_FW_NETIF_CMD_DHCP(x) \ 5708 (((x) >> S_FW_NETIF_CMD_DHCP) & M_FW_NETIF_CMD_DHCP) 5709#define F_FW_NETIF_CMD_DHCP V_FW_NETIF_CMD_DHCP(1U) 5710 5711#define S_FW_NETIF_CMD_IPV4BCADDR 15 5712#define M_FW_NETIF_CMD_IPV4BCADDR 0x1 5713#define V_FW_NETIF_CMD_IPV4BCADDR(x) ((x) << S_FW_NETIF_CMD_IPV4BCADDR) 5714#define G_FW_NETIF_CMD_IPV4BCADDR(x) \ 5715 (((x) >> S_FW_NETIF_CMD_IPV4BCADDR) & M_FW_NETIF_CMD_IPV4BCADDR) 5716#define F_FW_NETIF_CMD_IPV4BCADDR V_FW_NETIF_CMD_IPV4BCADDR(1U) 5717 5718#define S_FW_NETIF_CMD_IPV4NMASK 14 5719#define M_FW_NETIF_CMD_IPV4NMASK 0x1 5720#define V_FW_NETIF_CMD_IPV4NMASK(x) ((x) << S_FW_NETIF_CMD_IPV4NMASK) 5721#define G_FW_NETIF_CMD_IPV4NMASK(x) \ 5722 (((x) >> S_FW_NETIF_CMD_IPV4NMASK) & M_FW_NETIF_CMD_IPV4NMASK) 5723#define F_FW_NETIF_CMD_IPV4NMASK V_FW_NETIF_CMD_IPV4NMASK(1U) 5724 5725#define S_FW_NETIF_CMD_IPV4ADDR 13 5726#define M_FW_NETIF_CMD_IPV4ADDR 0x1 5727#define V_FW_NETIF_CMD_IPV4ADDR(x) ((x) << S_FW_NETIF_CMD_IPV4ADDR) 5728#define G_FW_NETIF_CMD_IPV4ADDR(x) \ 5729 (((x) >> S_FW_NETIF_CMD_IPV4ADDR) & M_FW_NETIF_CMD_IPV4ADDR) 5730#define F_FW_NETIF_CMD_IPV4ADDR V_FW_NETIF_CMD_IPV4ADDR(1U) 5731 5732#define S_FW_NETIF_CMD_IPV4GW 12 5733#define M_FW_NETIF_CMD_IPV4GW 0x1 5734#define V_FW_NETIF_CMD_IPV4GW(x) ((x) << S_FW_NETIF_CMD_IPV4GW) 5735#define G_FW_NETIF_CMD_IPV4GW(x) \ 5736 (((x) >> S_FW_NETIF_CMD_IPV4GW) & M_FW_NETIF_CMD_IPV4GW) 5737#define F_FW_NETIF_CMD_IPV4GW V_FW_NETIF_CMD_IPV4GW(1U) 5738 5739#define S_FW_NETIF_CMD_NETIFI 8 5740#define M_FW_NETIF_CMD_NETIFI 0xffffff 5741#define V_FW_NETIF_CMD_NETIFI(x) ((x) << S_FW_NETIF_CMD_NETIFI) 5742#define G_FW_NETIF_CMD_NETIFI(x) \ 5743 (((x) >> S_FW_NETIF_CMD_NETIFI) & M_FW_NETIF_CMD_NETIFI) 5744 5745#define S_FW_NETIF_CMD_IFADRIDX 0 5746#define M_FW_NETIF_CMD_IFADRIDX 0xff 5747#define V_FW_NETIF_CMD_IFADRIDX(x) ((x) << S_FW_NETIF_CMD_IFADRIDX) 5748#define G_FW_NETIF_CMD_IFADRIDX(x) \ 5749 (((x) >> S_FW_NETIF_CMD_IFADRIDX) & M_FW_NETIF_CMD_IFADRIDX) 5750 5751#define S_FW_NETIF_CMD_PORTID 28 5752#define M_FW_NETIF_CMD_PORTID 0xf 5753#define V_FW_NETIF_CMD_PORTID(x) ((x) << S_FW_NETIF_CMD_PORTID) 5754#define G_FW_NETIF_CMD_PORTID(x) \ 5755 (((x) >> S_FW_NETIF_CMD_PORTID) & M_FW_NETIF_CMD_PORTID) 5756 5757#define S_FW_NETIF_CMD_VLANID 16 5758#define M_FW_NETIF_CMD_VLANID 0xfff 5759#define V_FW_NETIF_CMD_VLANID(x) ((x) << S_FW_NETIF_CMD_VLANID) 5760#define G_FW_NETIF_CMD_VLANID(x) \ 5761 (((x) >> S_FW_NETIF_CMD_VLANID) & M_FW_NETIF_CMD_VLANID) 5762 5763#define S_FW_NETIF_CMD_MTUVAL 0 5764#define M_FW_NETIF_CMD_MTUVAL 0xffff 5765#define V_FW_NETIF_CMD_MTUVAL(x) ((x) << S_FW_NETIF_CMD_MTUVAL) 5766#define G_FW_NETIF_CMD_MTUVAL(x) \ 5767 (((x) >> S_FW_NETIF_CMD_MTUVAL) & M_FW_NETIF_CMD_MTUVAL) 5768 | |
5769enum fw_watchdog_actions { 5770 FW_WATCHDOG_ACTION_FLR = 0x1, 5771 FW_WATCHDOG_ACTION_BYPASS = 0x2, 5772}; 5773 5774#define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 5775 5776struct fw_watchdog_cmd { --- 20 unchanged lines hidden (view full) --- 5797 5798#define S_FW_CLIP_CMD_FREE 30 5799#define M_FW_CLIP_CMD_FREE 0x1 5800#define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 5801#define G_FW_CLIP_CMD_FREE(x) \ 5802 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 5803#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 5804 | 6708enum fw_watchdog_actions { 6709 FW_WATCHDOG_ACTION_FLR = 0x1, 6710 FW_WATCHDOG_ACTION_BYPASS = 0x2, 6711}; 6712 6713#define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 6714 6715struct fw_watchdog_cmd { --- 20 unchanged lines hidden (view full) --- 6736 6737#define S_FW_CLIP_CMD_FREE 30 6738#define M_FW_CLIP_CMD_FREE 0x1 6739#define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 6740#define G_FW_CLIP_CMD_FREE(x) \ 6741 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 6742#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 6743 |
6744/****************************************************************************** 6745 * F O i S C S I C O M M A N D s 6746 **************************************/ 6747 6748#define FW_CHNET_IFACE_ADDR_MAX 3 6749 6750enum fw_chnet_iface_cmd_subop { 6751 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 6752 6753 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 6754 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 6755 6756 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 6757 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 6758 6759 FW_CHNET_IFACE_CMD_SUBOP_MAX, 6760}; 6761 6762struct fw_chnet_iface_cmd { 6763 __be32 op_to_portid; 6764 __be32 retval_len16; 6765 __u8 subop; 6766 __u8 r2[3]; 6767 __be32 ifid_ifstate; 6768 __be16 mtu; 6769 __be16 vlanid; 6770 __be32 r3; 6771 __be16 r4; 6772 __u8 mac[6]; 6773}; 6774 6775#define S_FW_CHNET_IFACE_CMD_PORTID 0 6776#define M_FW_CHNET_IFACE_CMD_PORTID 0xf 6777#define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 6778#define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 6779 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 6780 6781#define S_FW_CHNET_IFACE_CMD_IFID 8 6782#define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 6783#define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 6784#define G_FW_CHNET_IFACE_CMD_IFID(x) \ 6785 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 6786 6787#define S_FW_CHNET_IFACE_CMD_IFSTATE 0 6788#define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 6789#define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 6790#define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 6791 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 6792 6793/****************************************************************************** 6794 * F O F C O E C O M M A N D s 6795 ************************************/ 6796 6797struct fw_fcoe_res_info_cmd { 6798 __be32 op_to_read; 6799 __be32 retval_len16; 6800 __be16 e_d_tov; 6801 __be16 r_a_tov_seq; 6802 __be16 r_a_tov_els; 6803 __be16 r_r_tov; 6804 __be32 max_xchgs; 6805 __be32 max_ssns; 6806 __be32 used_xchgs; 6807 __be32 used_ssns; 6808 __be32 max_fcfs; 6809 __be32 max_vnps; 6810 __be32 used_fcfs; 6811 __be32 used_vnps; 6812}; 6813 6814struct fw_fcoe_link_cmd { 6815 __be32 op_to_portid; 6816 __be32 retval_len16; 6817 __be32 sub_opcode_fcfi; 6818 __u8 r3; 6819 __u8 lstatus; 6820 __be16 flags; 6821 __u8 r4; 6822 __u8 set_vlan; 6823 __be16 vlan_id; 6824 __be32 vnpi_pkd; 6825 __be16 r6; 6826 __u8 phy_mac[6]; 6827 __u8 vnport_wwnn[8]; 6828 __u8 vnport_wwpn[8]; 6829}; 6830 6831#define S_FW_FCOE_LINK_CMD_PORTID 0 6832#define M_FW_FCOE_LINK_CMD_PORTID 0xf 6833#define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 6834#define G_FW_FCOE_LINK_CMD_PORTID(x) \ 6835 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 6836 6837#define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 6838#define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 6839#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 6840 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 6841#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 6842 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 6843 6844#define S_FW_FCOE_LINK_CMD_FCFI 0 6845#define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 6846#define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 6847#define G_FW_FCOE_LINK_CMD_FCFI(x) \ 6848 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 6849 6850#define S_FW_FCOE_LINK_CMD_VNPI 0 6851#define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 6852#define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 6853#define G_FW_FCOE_LINK_CMD_VNPI(x) \ 6854 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 6855 6856struct fw_fcoe_vnp_cmd { 6857 __be32 op_to_fcfi; 6858 __be32 alloc_to_len16; 6859 __be32 gen_wwn_to_vnpi; 6860 __be32 vf_id; 6861 __be16 iqid; 6862 __u8 vnport_mac[6]; 6863 __u8 vnport_wwnn[8]; 6864 __u8 vnport_wwpn[8]; 6865 __u8 cmn_srv_parms[16]; 6866 __u8 clsp_word_0_1[8]; 6867}; 6868 6869#define S_FW_FCOE_VNP_CMD_FCFI 0 6870#define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 6871#define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 6872#define G_FW_FCOE_VNP_CMD_FCFI(x) \ 6873 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 6874 6875#define S_FW_FCOE_VNP_CMD_ALLOC 31 6876#define M_FW_FCOE_VNP_CMD_ALLOC 0x1 6877#define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 6878#define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 6879 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 6880#define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 6881 6882#define S_FW_FCOE_VNP_CMD_FREE 30 6883#define M_FW_FCOE_VNP_CMD_FREE 0x1 6884#define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 6885#define G_FW_FCOE_VNP_CMD_FREE(x) \ 6886 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 6887#define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 6888 6889#define S_FW_FCOE_VNP_CMD_MODIFY 29 6890#define M_FW_FCOE_VNP_CMD_MODIFY 0x1 6891#define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 6892#define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 6893 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 6894#define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 6895 6896#define S_FW_FCOE_VNP_CMD_GEN_WWN 22 6897#define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 6898#define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 6899#define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 6900 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 6901#define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 6902 6903#define S_FW_FCOE_VNP_CMD_PERSIST 21 6904#define M_FW_FCOE_VNP_CMD_PERSIST 0x1 6905#define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 6906#define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 6907 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 6908#define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 6909 6910#define S_FW_FCOE_VNP_CMD_VFID_EN 20 6911#define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 6912#define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 6913#define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 6914 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 6915#define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 6916 6917#define S_FW_FCOE_VNP_CMD_VNPI 0 6918#define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 6919#define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 6920#define G_FW_FCOE_VNP_CMD_VNPI(x) \ 6921 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 6922 6923struct fw_fcoe_sparams_cmd { 6924 __be32 op_to_portid; 6925 __be32 retval_len16; 6926 __u8 r3[7]; 6927 __u8 cos; 6928 __u8 lport_wwnn[8]; 6929 __u8 lport_wwpn[8]; 6930 __u8 cmn_srv_parms[16]; 6931 __u8 cls_srv_parms[16]; 6932}; 6933 6934#define S_FW_FCOE_SPARAMS_CMD_PORTID 0 6935#define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 6936#define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 6937#define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 6938 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 6939 6940struct fw_fcoe_stats_cmd { 6941 __be32 op_to_flowid; 6942 __be32 free_to_len16; 6943 union fw_fcoe_stats { 6944 struct fw_fcoe_stats_ctl { 6945 __u8 nstats_port; 6946 __u8 port_valid_ix; 6947 __be16 r6; 6948 __be32 r7; 6949 __be64 stat0; 6950 __be64 stat1; 6951 __be64 stat2; 6952 __be64 stat3; 6953 __be64 stat4; 6954 __be64 stat5; 6955 } ctl; 6956 struct fw_fcoe_port_stats { 6957 __be64 tx_bcast_bytes; 6958 __be64 tx_bcast_frames; 6959 __be64 tx_mcast_bytes; 6960 __be64 tx_mcast_frames; 6961 __be64 tx_ucast_bytes; 6962 __be64 tx_ucast_frames; 6963 __be64 tx_drop_frames; 6964 __be64 tx_offload_bytes; 6965 __be64 tx_offload_frames; 6966 __be64 rx_bcast_bytes; 6967 __be64 rx_bcast_frames; 6968 __be64 rx_mcast_bytes; 6969 __be64 rx_mcast_frames; 6970 __be64 rx_ucast_bytes; 6971 __be64 rx_ucast_frames; 6972 __be64 rx_err_frames; 6973 } port_stats; 6974 struct fw_fcoe_fcf_stats { 6975 __be32 fip_tx_bytes; 6976 __be32 fip_tx_fr; 6977 __be64 fcf_ka; 6978 __be64 mcast_adv_rcvd; 6979 __be16 ucast_adv_rcvd; 6980 __be16 sol_sent; 6981 __be16 vlan_req; 6982 __be16 vlan_rpl; 6983 __be16 clr_vlink; 6984 __be16 link_down; 6985 __be16 link_up; 6986 __be16 logo; 6987 __be16 flogi_req; 6988 __be16 flogi_rpl; 6989 __be16 fdisc_req; 6990 __be16 fdisc_rpl; 6991 __be16 fka_prd_chg; 6992 __be16 fc_map_chg; 6993 __be16 vfid_chg; 6994 __u8 no_fka_req; 6995 __u8 no_vnp; 6996 } fcf_stats; 6997 struct fw_fcoe_pcb_stats { 6998 __be64 tx_bytes; 6999 __be64 tx_frames; 7000 __be64 rx_bytes; 7001 __be64 rx_frames; 7002 __be32 vnp_ka; 7003 __be32 unsol_els_rcvd; 7004 __be64 unsol_cmd_rcvd; 7005 __be16 implicit_logo; 7006 __be16 flogi_inv_sparm; 7007 __be16 fdisc_inv_sparm; 7008 __be16 flogi_rjt; 7009 __be16 fdisc_rjt; 7010 __be16 no_ssn; 7011 __be16 mac_flt_fail; 7012 __be16 inv_fr_rcvd; 7013 } pcb_stats; 7014 struct fw_fcoe_scb_stats { 7015 __be64 tx_bytes; 7016 __be64 tx_frames; 7017 __be64 rx_bytes; 7018 __be64 rx_frames; 7019 __be32 host_abrt_req; 7020 __be32 adap_auto_abrt; 7021 __be32 adap_abrt_rsp; 7022 __be32 host_ios_req; 7023 __be16 ssn_offl_ios; 7024 __be16 ssn_not_rdy_ios; 7025 __u8 rx_data_ddp_err; 7026 __u8 ddp_flt_set_err; 7027 __be16 rx_data_fr_err; 7028 __u8 bad_st_abrt_req; 7029 __u8 no_io_abrt_req; 7030 __u8 abort_tmo; 7031 __u8 abort_tmo_2; 7032 __be32 abort_req; 7033 __u8 no_ppod_res_tmo; 7034 __u8 bp_tmo; 7035 __u8 adap_auto_cls; 7036 __u8 no_io_cls_req; 7037 __be32 host_cls_req; 7038 __be64 unsol_cmd_rcvd; 7039 __be32 plogi_req_rcvd; 7040 __be32 prli_req_rcvd; 7041 __be16 logo_req_rcvd; 7042 __be16 prlo_req_rcvd; 7043 __be16 plogi_rjt_rcvd; 7044 __be16 prli_rjt_rcvd; 7045 __be32 adisc_req_rcvd; 7046 __be32 rscn_rcvd; 7047 __be32 rrq_req_rcvd; 7048 __be32 unsol_els_rcvd; 7049 __u8 adisc_rjt_rcvd; 7050 __u8 scr_rjt; 7051 __u8 ct_rjt; 7052 __u8 inval_bls_rcvd; 7053 __be32 ba_rjt_rcvd; 7054 } scb_stats; 7055 } u; 7056}; 7057 7058#define S_FW_FCOE_STATS_CMD_FLOWID 0 7059#define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 7060#define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 7061#define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 7062 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 7063 7064#define S_FW_FCOE_STATS_CMD_FREE 30 7065#define M_FW_FCOE_STATS_CMD_FREE 0x1 7066#define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 7067#define G_FW_FCOE_STATS_CMD_FREE(x) \ 7068 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 7069#define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 7070 7071#define S_FW_FCOE_STATS_CMD_NSTATS 4 7072#define M_FW_FCOE_STATS_CMD_NSTATS 0x7 7073#define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 7074#define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 7075 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 7076 7077#define S_FW_FCOE_STATS_CMD_PORT 0 7078#define M_FW_FCOE_STATS_CMD_PORT 0x3 7079#define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 7080#define G_FW_FCOE_STATS_CMD_PORT(x) \ 7081 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 7082 7083#define S_FW_FCOE_STATS_CMD_PORT_VALID 7 7084#define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 7085#define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7086 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 7087#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7088 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 7089#define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 7090 7091#define S_FW_FCOE_STATS_CMD_IX 0 7092#define M_FW_FCOE_STATS_CMD_IX 0x3f 7093#define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 7094#define G_FW_FCOE_STATS_CMD_IX(x) \ 7095 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 7096 7097struct fw_fcoe_fcf_cmd { 7098 __be32 op_to_fcfi; 7099 __be32 retval_len16; 7100 __be16 priority_pkd; 7101 __u8 mac[6]; 7102 __u8 name_id[8]; 7103 __u8 fabric[8]; 7104 __be16 vf_id; 7105 __be16 max_fcoe_size; 7106 __u8 vlan_id; 7107 __u8 fc_map[3]; 7108 __be32 fka_adv; 7109 __be32 r6; 7110 __u8 r7_hi; 7111 __u8 fpma_to_portid; 7112 __u8 spma_mac[6]; 7113 __be64 r8; 7114}; 7115 7116#define S_FW_FCOE_FCF_CMD_FCFI 0 7117#define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 7118#define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 7119#define G_FW_FCOE_FCF_CMD_FCFI(x) \ 7120 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 7121 7122#define S_FW_FCOE_FCF_CMD_PRIORITY 0 7123#define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 7124#define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 7125#define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 7126 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 7127 7128#define S_FW_FCOE_FCF_CMD_FPMA 6 7129#define M_FW_FCOE_FCF_CMD_FPMA 0x1 7130#define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 7131#define G_FW_FCOE_FCF_CMD_FPMA(x) \ 7132 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 7133#define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 7134 7135#define S_FW_FCOE_FCF_CMD_SPMA 5 7136#define M_FW_FCOE_FCF_CMD_SPMA 0x1 7137#define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 7138#define G_FW_FCOE_FCF_CMD_SPMA(x) \ 7139 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 7140#define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 7141 7142#define S_FW_FCOE_FCF_CMD_LOGIN 4 7143#define M_FW_FCOE_FCF_CMD_LOGIN 0x1 7144#define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 7145#define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 7146 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 7147#define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 7148 7149#define S_FW_FCOE_FCF_CMD_PORTID 0 7150#define M_FW_FCOE_FCF_CMD_PORTID 0xf 7151#define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 7152#define G_FW_FCOE_FCF_CMD_PORTID(x) \ 7153 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 7154 7155/****************************************************************************** 7156 * E R R O R a n d D E B U G C O M M A N D s 7157 ******************************************************/ 7158 |
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5805enum fw_error_type { 5806 FW_ERROR_TYPE_EXCEPTION = 0x0, 5807 FW_ERROR_TYPE_HWMODULE = 0x1, 5808 FW_ERROR_TYPE_WR = 0x2, 5809 FW_ERROR_TYPE_ACL = 0x3, 5810}; 5811 5812struct fw_error_cmd { --- 93 unchanged lines hidden (view full) --- 5906}; 5907 5908#define S_FW_DEBUG_CMD_TYPE 0 5909#define M_FW_DEBUG_CMD_TYPE 0xff 5910#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 5911#define G_FW_DEBUG_CMD_TYPE(x) \ 5912 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 5913 | 7159enum fw_error_type { 7160 FW_ERROR_TYPE_EXCEPTION = 0x0, 7161 FW_ERROR_TYPE_HWMODULE = 0x1, 7162 FW_ERROR_TYPE_WR = 0x2, 7163 FW_ERROR_TYPE_ACL = 0x3, 7164}; 7165 7166struct fw_error_cmd { --- 93 unchanged lines hidden (view full) --- 7260}; 7261 7262#define S_FW_DEBUG_CMD_TYPE 0 7263#define M_FW_DEBUG_CMD_TYPE 0xff 7264#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 7265#define G_FW_DEBUG_CMD_TYPE(x) \ 7266 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 7267 |
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5915/****************************************************************************** 5916 * P C I E F W R E G I S T E R 5917 **************************************/ 5918 5919/** 5920 * Register definitions for the PCIE_FW register which the firmware uses 5921 * to retain status across RESETs. This register should be considered 5922 * as a READ-ONLY register for Host Software and only to be used to --- 155 unchanged lines hidden --- | 7268/****************************************************************************** 7269 * P C I E F W R E G I S T E R 7270 **************************************/ 7271 7272/** 7273 * Register definitions for the PCIE_FW register which the firmware uses 7274 * to retain status across RESETs. This register should be considered 7275 * as a READ-ONLY register for Host Software and only to be used to --- 155 unchanged lines hidden --- |