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t4_msg.h (247291) t4_msg.h (248925)
1/*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/cxgbe/common/t4_msg.h 247291 2013-02-26 00:27:27Z np $
26 * $FreeBSD: head/sys/dev/cxgbe/common/t4_msg.h 248925 2013-03-30 02:26:20Z np $
27 *
28 */
29
30#ifndef T4_MSG_H
31#define T4_MSG_H
32
33enum {
34 CPL_PASS_OPEN_REQ = 0x1,

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99 CPL_PASS_ACCEPT_REQ = 0x44,
100 CPL_RX2TX_PKT = 0x45,
101 CPL_RX_FCOE_DDP = 0x46,
102 CPL_FCOE_HDR = 0x47,
103 CPL_T5_TRACE_PKT = 0x48,
104 CPL_RX_ISCSI_DDP = 0x49,
105 CPL_RX_FCOE_DIF = 0x4A,
106 CPL_RX_DATA_DIF = 0x4B,
27 *
28 */
29
30#ifndef T4_MSG_H
31#define T4_MSG_H
32
33enum {
34 CPL_PASS_OPEN_REQ = 0x1,

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99 CPL_PASS_ACCEPT_REQ = 0x44,
100 CPL_RX2TX_PKT = 0x45,
101 CPL_RX_FCOE_DDP = 0x46,
102 CPL_FCOE_HDR = 0x47,
103 CPL_T5_TRACE_PKT = 0x48,
104 CPL_RX_ISCSI_DDP = 0x49,
105 CPL_RX_FCOE_DIF = 0x4A,
106 CPL_RX_DATA_DIF = 0x4B,
107 CPL_ERR_NOTIFY = 0x4D,
107
108 CPL_RDMA_READ_REQ = 0x60,
109 CPL_RX_ISCSI_DIF = 0x60,
110
111 CPL_SET_LE_REQ = 0x80,
112 CPL_PASS_OPEN_REQ6 = 0x81,
113 CPL_ACT_OPEN_REQ6 = 0x83,
114

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120 CPL_FW2_PLD = 0xA8,
121 CPL_T5_RDMA_READ_REQ = 0xA9,
122 CPL_RDMA_ATOMIC_REQ = 0xAA,
123 CPL_RDMA_ATOMIC_RPL = 0xAB,
124 CPL_RDMA_IMM_DATA = 0xAC,
125 CPL_RDMA_IMM_DATA_SE = 0xAD,
126
127 CPL_TRACE_PKT = 0xB0,
108
109 CPL_RDMA_READ_REQ = 0x60,
110 CPL_RX_ISCSI_DIF = 0x60,
111
112 CPL_SET_LE_REQ = 0x80,
113 CPL_PASS_OPEN_REQ6 = 0x81,
114 CPL_ACT_OPEN_REQ6 = 0x83,
115

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121 CPL_FW2_PLD = 0xA8,
122 CPL_T5_RDMA_READ_REQ = 0xA9,
123 CPL_RDMA_ATOMIC_REQ = 0xAA,
124 CPL_RDMA_ATOMIC_RPL = 0xAB,
125 CPL_RDMA_IMM_DATA = 0xAC,
126 CPL_RDMA_IMM_DATA_SE = 0xAD,
127
128 CPL_TRACE_PKT = 0xB0,
129 CPL_TRACE_PKT_T5 = 0x48,
128 CPL_RX2TX_DATA = 0xB1,
129 CPL_ISCSI_DATA = 0xB2,
130 CPL_FCOE_DATA = 0xB3,
131
132 CPL_FW4_MSG = 0xC0,
133 CPL_FW4_PLD = 0xC1,
134 CPL_FW4_ACK = 0xC3,
135

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473#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
474#define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
475
476#define S_CONN_POLICY 22
477#define M_CONN_POLICY 0x3
478#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
479#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
480
130 CPL_RX2TX_DATA = 0xB1,
131 CPL_ISCSI_DATA = 0xB2,
132 CPL_FCOE_DATA = 0xB3,
133
134 CPL_FW4_MSG = 0xC0,
135 CPL_FW4_PLD = 0xC1,
136 CPL_FW4_ACK = 0xC3,
137

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475#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
476#define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
477
478#define S_CONN_POLICY 22
479#define M_CONN_POLICY 0x3
480#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
481#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
482
483#define S_FILT_INFO 28
484#define M_FILT_INFO 0xfffffffffULL
485#define V_FILT_INFO(x) ((x) << S_FILT_INFO)
486#define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO)
487
481/* option 2 fields */
482#define S_RSS_QUEUE 0
483#define M_RSS_QUEUE 0x3FF
484#define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
485#define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
486
487#define S_RSS_QUEUE_VALID 10
488#define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)

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547#define S_TSTAMPS_EN 29
548#define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN)
549#define F_TSTAMPS_EN V_TSTAMPS_EN(1U)
550
551#define S_SACK_EN 30
552#define V_SACK_EN(x) ((x) << S_SACK_EN)
553#define F_SACK_EN V_SACK_EN(1U)
554
488/* option 2 fields */
489#define S_RSS_QUEUE 0
490#define M_RSS_QUEUE 0x3FF
491#define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
492#define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
493
494#define S_RSS_QUEUE_VALID 10
495#define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)

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554#define S_TSTAMPS_EN 29
555#define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN)
556#define F_TSTAMPS_EN V_TSTAMPS_EN(1U)
557
558#define S_SACK_EN 30
559#define V_SACK_EN(x) ((x) << S_SACK_EN)
560#define F_SACK_EN V_SACK_EN(1U)
561
562#define S_T5_OPT_2_VALID 31
563#define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID)
564#define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U)
565
555struct cpl_pass_open_req {
556 WR_HDR;
557 union opcode_tid ot;
558 __be16 local_port;
559 __be16 peer_port;
560 __be32 local_ip;
561 __be32 peer_ip;
562 __be64 opt0;

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674 __be16 peer_port;
675 __be32 local_ip;
676 __be32 peer_ip;
677 __be64 opt0;
678 __be32 params;
679 __be32 opt2;
680};
681
566struct cpl_pass_open_req {
567 WR_HDR;
568 union opcode_tid ot;
569 __be16 local_port;
570 __be16 peer_port;
571 __be32 local_ip;
572 __be32 peer_ip;
573 __be64 opt0;

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685 __be16 peer_port;
686 __be32 local_ip;
687 __be32 peer_ip;
688 __be64 opt0;
689 __be32 params;
690 __be32 opt2;
691};
692
693#define S_FILTER_TUPLE 24
694#define M_FILTER_TUPLE 0xFFFFFFFFFF
695#define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
696#define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
682struct cpl_t5_act_open_req {
683 WR_HDR;
684 union opcode_tid ot;
685 __be16 local_port;
686 __be16 peer_port;
687 __be32 local_ip;
688 __be32 peer_ip;
689 __be64 opt0;

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1048#define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD)
1049#define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U)
1050
1051#define S_TXPKT_OVLAN_IDX 12
1052#define M_TXPKT_OVLAN_IDX 0xF
1053#define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX)
1054#define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX)
1055
697struct cpl_t5_act_open_req {
698 WR_HDR;
699 union opcode_tid ot;
700 __be16 local_port;
701 __be16 peer_port;
702 __be32 local_ip;
703 __be32 peer_ip;
704 __be64 opt0;

--- 358 unchanged lines hidden (view full) ---

1063#define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD)
1064#define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U)
1065
1066#define S_TXPKT_OVLAN_IDX 12
1067#define M_TXPKT_OVLAN_IDX 0xF
1068#define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX)
1069#define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX)
1070
1071#define S_TXPKT_T5_OVLAN_IDX 12
1072#define M_TXPKT_T5_OVLAN_IDX 0x7
1073#define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX)
1074#define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \
1075 M_TXPKT_T5_OVLAN_IDX)
1076
1056#define S_TXPKT_INTF 16
1057#define M_TXPKT_INTF 0xF
1058#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1059#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1060
1061#define S_TXPKT_SPECIAL_STAT 20
1062#define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT)
1063#define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U)
1064
1077#define S_TXPKT_INTF 16
1078#define M_TXPKT_INTF 0xF
1079#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1080#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1081
1082#define S_TXPKT_SPECIAL_STAT 20
1083#define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT)
1084#define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U)
1085
1086#define S_TXPKT_T5_FCS_DIS 21
1087#define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS)
1088#define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U)
1089
1065#define S_TXPKT_INS_OVLAN 21
1066#define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN)
1067#define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U)
1068
1090#define S_TXPKT_INS_OVLAN 21
1091#define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN)
1092#define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U)
1093
1094#define S_TXPKT_T5_INS_OVLAN 15
1095#define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN)
1096#define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U)
1097
1069#define S_TXPKT_STAT_DIS 22
1070#define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS)
1071#define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U)
1072
1073#define S_TXPKT_LOOPBACK 23
1074#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1075#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1076

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1203#define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
1204#define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
1205
1206#define S_LSO_OPCODE 24
1207#define M_LSO_OPCODE 0xFF
1208#define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
1209#define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
1210
1098#define S_TXPKT_STAT_DIS 22
1099#define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS)
1100#define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U)
1101
1102#define S_TXPKT_LOOPBACK 23
1103#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1104#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1105

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1232#define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
1233#define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
1234
1235#define S_LSO_OPCODE 24
1236#define M_LSO_OPCODE 0xFF
1237#define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
1238#define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
1239
1240#define S_LSO_T5_XFER_SIZE 0
1241#define M_LSO_T5_XFER_SIZE 0xFFFFFFF
1242#define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
1243#define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
1244
1211/* cpl_tx_pkt_lso_core.mss fields */
1212#define S_LSO_MSS 0
1213#define M_LSO_MSS 0x3FFF
1214#define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1215#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1216
1217#define S_LSO_IPID_SPLIT 15
1218#define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT)

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1901
1902/* cpl_l2t_write_req.params fields */
1903#define S_L2T_W_INFO 2
1904#define M_L2T_W_INFO 0x3F
1905#define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO)
1906#define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO)
1907
1908#define S_L2T_W_PORT 8
1245/* cpl_tx_pkt_lso_core.mss fields */
1246#define S_LSO_MSS 0
1247#define M_LSO_MSS 0x3FFF
1248#define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1249#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1250
1251#define S_LSO_IPID_SPLIT 15
1252#define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT)

--- 682 unchanged lines hidden (view full) ---

1935
1936/* cpl_l2t_write_req.params fields */
1937#define S_L2T_W_INFO 2
1938#define M_L2T_W_INFO 0x3F
1939#define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO)
1940#define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO)
1941
1942#define S_L2T_W_PORT 8
1909#define M_L2T_W_PORT 0xF
1943#define M_L2T_W_PORT 0x3
1910#define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT)
1911#define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT)
1912
1944#define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT)
1945#define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT)
1946
1947#define S_L2T_W_LPBK 10
1948#define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK)
1949#define F_L2T_W_PKBK V_L2T_W_LPBK(1U)
1950
1951#define S_L2T_W_ARPMISS 11
1952#define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS)
1953#define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U)
1954
1913#define S_L2T_W_NOREPLY 15
1914#define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
1915#define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U)
1916
1955#define S_L2T_W_NOREPLY 15
1956#define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
1957#define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U)
1958
1959#define CPL_L2T_VLAN_NONE 0xfff
1960
1917struct cpl_l2t_write_rpl {
1918 RSS_HDR
1919 union opcode_tid ot;
1920 __u8 status;
1921 __u8 rsvd[3];
1922};
1923
1924struct cpl_l2t_read_req {

--- 464 unchanged lines hidden (view full) ---

2389 __be32 lock_addr;
2390};
2391
2392/* additional ulp_mem_io.cmd fields */
2393#define S_ULP_MEMIO_ORDER 23
2394#define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER)
2395#define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U)
2396
1961struct cpl_l2t_write_rpl {
1962 RSS_HDR
1963 union opcode_tid ot;
1964 __u8 status;
1965 __u8 rsvd[3];
1966};
1967
1968struct cpl_l2t_read_req {

--- 464 unchanged lines hidden (view full) ---

2433 __be32 lock_addr;
2434};
2435
2436/* additional ulp_mem_io.cmd fields */
2437#define S_ULP_MEMIO_ORDER 23
2438#define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER)
2439#define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U)
2440
2441#define S_T5_ULP_MEMIO_IMM 23
2442#define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM)
2443#define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U)
2444
2445#define S_T5_ULP_MEMIO_ORDER 22
2446#define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
2447#define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
2448
2397/* ulp_mem_io.lock_addr fields */
2398#define S_ULP_MEMIO_ADDR 0
2399#define M_ULP_MEMIO_ADDR 0x7FFFFFF
2400#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
2401
2402#define S_ULP_MEMIO_LOCK 31
2403#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
2404#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
2405
2406/* ulp_mem_io.dlen fields */
2407#define S_ULP_MEMIO_DATA_LEN 0
2408#define M_ULP_MEMIO_DATA_LEN 0x1F
2409#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
2410
2449/* ulp_mem_io.lock_addr fields */
2450#define S_ULP_MEMIO_ADDR 0
2451#define M_ULP_MEMIO_ADDR 0x7FFFFFF
2452#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
2453
2454#define S_ULP_MEMIO_LOCK 31
2455#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
2456#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
2457
2458/* ulp_mem_io.dlen fields */
2459#define S_ULP_MEMIO_DATA_LEN 0
2460#define M_ULP_MEMIO_DATA_LEN 0x1F
2461#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
2462
2463/* ULP_TXPKT field values */
2464enum {
2465 ULP_TXPKT_DEST_TP = 0,
2466 ULP_TXPKT_DEST_SGE,
2467 ULP_TXPKT_DEST_UP,
2468 ULP_TXPKT_DEST_DEVNULL,
2469};
2470
2411struct ulp_txpkt {
2412 __be32 cmd_dest;
2413 __be32 len;
2414};
2415
2416/* ulp_txpkt.cmd_dest fields */
2417#define S_ULP_TXPKT_DEST 16
2418#define M_ULP_TXPKT_DEST 0x3
2419#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
2420
2421#define S_ULP_TXPKT_FID 4
2422#define M_ULP_TXPKT_FID 0x7ff
2423#define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
2424
2425#define S_ULP_TXPKT_RO 3
2426#define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
2427#define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
2428
2429#endif /* T4_MSG_H */
2471struct ulp_txpkt {
2472 __be32 cmd_dest;
2473 __be32 len;
2474};
2475
2476/* ulp_txpkt.cmd_dest fields */
2477#define S_ULP_TXPKT_DEST 16
2478#define M_ULP_TXPKT_DEST 0x3
2479#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
2480
2481#define S_ULP_TXPKT_FID 4
2482#define M_ULP_TXPKT_FID 0x7ff
2483#define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
2484
2485#define S_ULP_TXPKT_RO 3
2486#define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
2487#define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
2488
2489#endif /* T4_MSG_H */