t4_msg.h (218792) | t4_msg.h (237436) |
---|---|
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
26 * $FreeBSD: head/sys/dev/cxgbe/common/t4_msg.h 218792 2011-02-18 08:00:26Z np $ | 26 * $FreeBSD: head/sys/dev/cxgbe/common/t4_msg.h 237436 2012-06-22 07:51:15Z np $ |
27 * 28 */ 29 30#ifndef T4_MSG_H 31#define T4_MSG_H 32 33enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, | 27 * 28 */ 29 30#ifndef T4_MSG_H 31#define T4_MSG_H 32 33enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, |
40 CPL_PCMD = 0x7, | |
41 CPL_CLOSE_CON_REQ = 0x8, 42 CPL_CLOSE_LISTSRV_REQ = 0x9, 43 CPL_ABORT_REQ = 0xA, 44 CPL_ABORT_RPL = 0xB, 45 CPL_TX_DATA = 0xC, 46 CPL_RX_DATA_ACK = 0xD, 47 CPL_TX_PKT = 0xE, 48 CPL_RTE_DELETE_REQ = 0xF, 49 CPL_RTE_WRITE_REQ = 0x10, 50 CPL_RTE_READ_REQ = 0x11, 51 CPL_L2T_WRITE_REQ = 0x12, 52 CPL_L2T_READ_REQ = 0x13, 53 CPL_SMT_WRITE_REQ = 0x14, 54 CPL_SMT_READ_REQ = 0x15, | 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_SMT_WRITE_REQ = 0x14, 53 CPL_SMT_READ_REQ = 0x15, |
54 CPL_TAG_WRITE_REQ = 0x16, |
|
55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, | 55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, |
57 CPL_RX_MPS_PKT = 0x1B, | 57 CPL_TAG_READ_REQ = 0x1B, 58 CPL_TX_PKT_FSO = 0x1E, 59 CPL_TX_PKT_ISO = 0x1F, |
58 59 CPL_CLOSE_LISTSRV_RPL = 0x20, 60 CPL_ERROR = 0x21, 61 CPL_GET_TCB_RPL = 0x22, 62 CPL_L2T_WRITE_RPL = 0x23, 63 CPL_PASS_OPEN_RPL = 0x24, 64 CPL_ACT_OPEN_RPL = 0x25, 65 CPL_PEER_CLOSE = 0x26, 66 CPL_RTE_DELETE_RPL = 0x27, 67 CPL_RTE_WRITE_RPL = 0x28, 68 CPL_RX_URG_PKT = 0x29, | 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PASS_OPEN_RPL = 0x24, 66 CPL_ACT_OPEN_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_URG_PKT = 0x29, |
71 CPL_TAG_WRITE_RPL = 0x2A, |
|
69 CPL_ABORT_REQ_RSS = 0x2B, 70 CPL_RX_URG_NOTIFY = 0x2C, 71 CPL_ABORT_RPL_RSS = 0x2D, 72 CPL_SMT_WRITE_RPL = 0x2E, 73 CPL_TX_DATA_ACK = 0x2F, 74 75 CPL_RX_PHYS_ADDR = 0x30, 76 CPL_PCMD_READ_RPL = 0x31, 77 CPL_CLOSE_CON_RPL = 0x32, 78 CPL_ISCSI_HDR = 0x33, 79 CPL_L2T_READ_RPL = 0x34, 80 CPL_RDMA_CQE = 0x35, 81 CPL_RDMA_CQE_READ_RSP = 0x36, 82 CPL_RDMA_CQE_ERR = 0x37, 83 CPL_RTE_READ_RPL = 0x38, 84 CPL_RX_DATA = 0x39, 85 CPL_SET_TCB_RPL = 0x3A, 86 CPL_RX_PKT = 0x3B, | 72 CPL_ABORT_REQ_RSS = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_ABORT_RPL_RSS = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_RX_PHYS_ADDR = 0x30, 79 CPL_PCMD_READ_RPL = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 CPL_SET_TCB_RPL = 0x3A, 89 CPL_RX_PKT = 0x3B, |
87 CPL_PCMD_RPL = 0x3C, | 90 CPL_TAG_READ_RPL = 0x3C, |
88 CPL_HIT_NOTIFY = 0x3D, 89 CPL_PKT_NOTIFY = 0x3E, 90 CPL_RX_DDP_COMPLETE = 0x3F, 91 92 CPL_ACT_ESTABLISH = 0x40, 93 CPL_PASS_ESTABLISH = 0x41, 94 CPL_RX_DATA_DDP = 0x42, 95 CPL_SMT_READ_RPL = 0x43, 96 CPL_PASS_ACCEPT_REQ = 0x44, 97 CPL_RX2TX_PKT = 0x45, 98 CPL_RX_FCOE_DDP = 0x46, 99 CPL_FCOE_HDR = 0x47, | 91 CPL_HIT_NOTIFY = 0x3D, 92 CPL_PKT_NOTIFY = 0x3E, 93 CPL_RX_DDP_COMPLETE = 0x3F, 94 95 CPL_ACT_ESTABLISH = 0x40, 96 CPL_PASS_ESTABLISH = 0x41, 97 CPL_RX_DATA_DDP = 0x42, 98 CPL_SMT_READ_RPL = 0x43, 99 CPL_PASS_ACCEPT_REQ = 0x44, 100 CPL_RX2TX_PKT = 0x45, 101 CPL_RX_FCOE_DDP = 0x46, 102 CPL_FCOE_HDR = 0x47, |
103 CPL_T5_TRACE_PKT = 0x48, 104 CPL_RX_ISCSI_DDP = 0x49, 105 CPL_RX_FCOE_DIF = 0x4A, 106 CPL_RX_DATA_DIF = 0x4B, |
|
100 101 CPL_RDMA_READ_REQ = 0x60, | 107 108 CPL_RDMA_READ_REQ = 0x60, |
109 CPL_RX_ISCSI_DIF = 0x60, |
|
102 103 CPL_SET_LE_REQ = 0x80, 104 CPL_PASS_OPEN_REQ6 = 0x81, 105 CPL_ACT_OPEN_REQ6 = 0x83, 106 | 110 111 CPL_SET_LE_REQ = 0x80, 112 CPL_PASS_OPEN_REQ6 = 0x81, 113 CPL_ACT_OPEN_REQ6 = 0x83, 114 |
107 CPL_TX_DMA_ACK = 0xA0, | |
108 CPL_RDMA_TERMINATE = 0xA2, 109 CPL_RDMA_WRITE = 0xA4, 110 CPL_SGE_EGR_UPDATE = 0xA5, 111 CPL_SET_LE_RPL = 0xA6, 112 CPL_FW2_MSG = 0xA7, 113 CPL_FW2_PLD = 0xA8, | 115 CPL_RDMA_TERMINATE = 0xA2, 116 CPL_RDMA_WRITE = 0xA4, 117 CPL_SGE_EGR_UPDATE = 0xA5, 118 CPL_SET_LE_RPL = 0xA6, 119 CPL_FW2_MSG = 0xA7, 120 CPL_FW2_PLD = 0xA8, |
121 CPL_T5_RDMA_READ_REQ = 0xA9, 122 CPL_RDMA_ATOMIC_REQ = 0xAA, 123 CPL_RDMA_ATOMIC_RPL = 0xAB, 124 CPL_RDMA_IMM_DATA = 0xAC, 125 CPL_RDMA_IMM_DATA_SE = 0xAD, |
|
114 115 CPL_TRACE_PKT = 0xB0, 116 CPL_RX2TX_DATA = 0xB1, | 126 127 CPL_TRACE_PKT = 0xB0, 128 CPL_RX2TX_DATA = 0xB1, |
129 CPL_ISCSI_DATA = 0xB2, 130 CPL_FCOE_DATA = 0xB3, |
|
117 118 CPL_FW4_MSG = 0xC0, 119 CPL_FW4_PLD = 0xC1, 120 CPL_FW4_ACK = 0xC3, 121 122 CPL_FW6_MSG = 0xE0, 123 CPL_FW6_PLD = 0xE1, 124 CPL_TX_PKT_LSO = 0xED, --- 148 unchanged lines hidden (view full) --- 273}; 274 275struct tcp_options { 276 __be16 mss; 277 __u8 wsf; 278#if defined(__LITTLE_ENDIAN_BITFIELD) 279 __u8 :4; 280 __u8 unknown:1; | 131 132 CPL_FW4_MSG = 0xC0, 133 CPL_FW4_PLD = 0xC1, 134 CPL_FW4_ACK = 0xC3, 135 136 CPL_FW6_MSG = 0xE0, 137 CPL_FW6_PLD = 0xE1, 138 CPL_TX_PKT_LSO = 0xED, --- 148 unchanged lines hidden (view full) --- 287}; 288 289struct tcp_options { 290 __be16 mss; 291 __u8 wsf; 292#if defined(__LITTLE_ENDIAN_BITFIELD) 293 __u8 :4; 294 __u8 unknown:1; |
281 __u8 :1; | 295 __u8 ecn:1; |
282 __u8 sack:1; 283 __u8 tstamp:1; 284#else 285 __u8 tstamp:1; 286 __u8 sack:1; | 296 __u8 sack:1; 297 __u8 tstamp:1; 298#else 299 __u8 tstamp:1; 300 __u8 sack:1; |
287 __u8 :1; | 301 __u8 ecn:1; |
288 __u8 unknown:1; 289 __u8 :4; 290#endif 291}; 292 293struct rss_header { 294 __u8 opcode; 295#if defined(__LITTLE_ENDIAN_BITFIELD) --- 324 unchanged lines hidden (view full) --- 620#define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 621 622#define S_IP_HDR_LEN 16 623#define M_IP_HDR_LEN 0x3FF 624#define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 625#define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 626 627#define S_ETH_HDR_LEN 26 | 302 __u8 unknown:1; 303 __u8 :4; 304#endif 305}; 306 307struct rss_header { 308 __u8 opcode; 309#if defined(__LITTLE_ENDIAN_BITFIELD) --- 324 unchanged lines hidden (view full) --- 634#define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 635 636#define S_IP_HDR_LEN 16 637#define M_IP_HDR_LEN 0x3FF 638#define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 639#define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 640 641#define S_ETH_HDR_LEN 26 |
628#define M_ETH_HDR_LEN 0x1F | 642#define M_ETH_HDR_LEN 0x3F |
629#define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 630#define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 631 632/* cpl_pass_accept_req.l2info fields */ 633#define S_SYN_MAC_IDX 0 634#define M_SYN_MAC_IDX 0x1FF 635#define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 636#define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) --- 21 unchanged lines hidden (view full) --- 658 __be16 peer_port; 659 __be32 local_ip; 660 __be32 peer_ip; 661 __be64 opt0; 662 __be32 params; 663 __be32 opt2; 664}; 665 | 643#define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 644#define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 645 646/* cpl_pass_accept_req.l2info fields */ 647#define S_SYN_MAC_IDX 0 648#define M_SYN_MAC_IDX 0x1FF 649#define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 650#define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) --- 21 unchanged lines hidden (view full) --- 672 __be16 peer_port; 673 __be32 local_ip; 674 __be32 peer_ip; 675 __be64 opt0; 676 __be32 params; 677 __be32 opt2; 678}; 679 |
666/* cpl_act_open_req.params fields XXX */ 667#define S_AOPEN_VLAN_PRI 9 668#define M_AOPEN_VLAN_PRI 0x3 669#define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI) 670#define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI) | 680struct cpl_t5_act_open_req { 681 WR_HDR; 682 union opcode_tid ot; 683 __be16 local_port; 684 __be16 peer_port; 685 __be32 local_ip; 686 __be32 peer_ip; 687 __be64 opt0; 688 __be32 rsvd; 689 __be32 opt2; 690 __be64 params; 691}; |
671 | 692 |
672#define S_AOPEN_VLAN_PRI_VALID 11 673#define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID) 674#define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U) 675 676#define S_AOPEN_PKT_TYPE 12 677#define M_AOPEN_PKT_TYPE 0x3 678#define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE) 679#define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE) 680 681#define S_AOPEN_MAC_MATCH 14 682#define M_AOPEN_MAC_MATCH 0x1F 683#define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH) 684#define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH) 685 686#define S_AOPEN_MAC_MATCH_VALID 19 687#define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID) 688#define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U) 689 690#define S_AOPEN_IFF_VLAN 20 691#define M_AOPEN_IFF_VLAN 0xFFF 692#define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN) 693#define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) 694 | |
695struct cpl_act_open_req6 { 696 WR_HDR; 697 union opcode_tid ot; 698 __be16 local_port; 699 __be16 peer_port; 700 __be64 local_ip_hi; 701 __be64 local_ip_lo; 702 __be64 peer_ip_hi; 703 __be64 peer_ip_lo; 704 __be64 opt0; 705 __be32 params; 706 __be32 opt2; 707}; 708 | 693struct cpl_act_open_req6 { 694 WR_HDR; 695 union opcode_tid ot; 696 __be16 local_port; 697 __be16 peer_port; 698 __be64 local_ip_hi; 699 __be64 local_ip_lo; 700 __be64 peer_ip_hi; 701 __be64 peer_ip_lo; 702 __be64 opt0; 703 __be32 params; 704 __be32 opt2; 705}; 706 |
707struct cpl_t5_act_open_req6 { 708 WR_HDR; 709 union opcode_tid ot; 710 __be16 local_port; 711 __be16 peer_port; 712 __be64 local_ip_hi; 713 __be64 local_ip_lo; 714 __be64 peer_ip_hi; 715 __be64 peer_ip_lo; 716 __be64 opt0; 717 __be32 rsvd; 718 __be32 opt2; 719 __be64 params; 720}; 721 |
|
709struct cpl_act_open_rpl { 710 RSS_HDR 711 union opcode_tid ot; 712 __be32 atid_status; 713}; 714 715/* cpl_act_open_rpl.atid_status fields */ 716#define S_AOPEN_STATUS 0 --- 329 unchanged lines hidden (view full) --- 1046#define S_TXPKT_STAT_DIS 22 1047#define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1048#define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1049 1050#define S_TXPKT_LOOPBACK 23 1051#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1052#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1053 | 722struct cpl_act_open_rpl { 723 RSS_HDR 724 union opcode_tid ot; 725 __be32 atid_status; 726}; 727 728/* cpl_act_open_rpl.atid_status fields */ 729#define S_AOPEN_STATUS 0 --- 329 unchanged lines hidden (view full) --- 1059#define S_TXPKT_STAT_DIS 22 1060#define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1061#define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1062 1063#define S_TXPKT_LOOPBACK 23 1064#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1065#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1066 |
1067#define S_TXPKT_TSTAMP 23 1068#define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1069#define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1070 |
|
1054#define S_TXPKT_OPCODE 24 1055#define M_TXPKT_OPCODE 0xFF 1056#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1057#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1058 1059/* cpl_tx_pkt_core.ctrl1 fields */ 1060#define S_TXPKT_SA_IDX 0 1061#define M_TXPKT_SA_IDX 0xFFF --- 46 unchanged lines hidden (view full) --- 1108#define S_TXPKT_IPCSUM_DIS 62 1109#define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1110#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1111 1112#define S_TXPKT_L4CSUM_DIS 63 1113#define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1114#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1115 | 1071#define S_TXPKT_OPCODE 24 1072#define M_TXPKT_OPCODE 0xFF 1073#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1074#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1075 1076/* cpl_tx_pkt_core.ctrl1 fields */ 1077#define S_TXPKT_SA_IDX 0 1078#define M_TXPKT_SA_IDX 0xFFF --- 46 unchanged lines hidden (view full) --- 1125#define S_TXPKT_IPCSUM_DIS 62 1126#define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1127#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1128 1129#define S_TXPKT_L4CSUM_DIS 63 1130#define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1131#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1132 |
1116struct cpl_tx_pkt_lso { | 1133struct cpl_tx_pkt_lso_core { |
1117 __be32 lso_ctrl; 1118 __be16 ipid_ofst; 1119 __be16 mss; 1120 __be32 seqno_offset; 1121 __be32 len; 1122 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1123}; 1124 | 1134 __be32 lso_ctrl; 1135 __be16 ipid_ofst; 1136 __be16 mss; 1137 __be32 seqno_offset; 1138 __be32 len; 1139 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1140}; 1141 |
1125/* cpl_tx_pkt_lso.lso_ctrl fields */ | 1142struct cpl_tx_pkt_lso { 1143 WR_HDR; 1144 struct cpl_tx_pkt_lso_core c; 1145 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1146}; 1147 1148struct cpl_tx_pkt_ufo_core { 1149 __be16 ethlen; 1150 __be16 iplen; 1151 __be16 udplen; 1152 __be16 mss; 1153 __be32 len; 1154 __be32 r1; 1155 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1156}; 1157 1158struct cpl_tx_pkt_ufo { 1159 WR_HDR; 1160 struct cpl_tx_pkt_ufo_core c; 1161 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1162}; 1163 1164/* cpl_tx_pkt_lso_core.lso_ctrl fields */ |
1126#define S_LSO_TCPHDR_LEN 0 1127#define M_LSO_TCPHDR_LEN 0xF 1128#define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1129#define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1130 1131#define S_LSO_IPHDR_LEN 4 1132#define M_LSO_IPHDR_LEN 0xFFF 1133#define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) --- 20 unchanged lines hidden (view full) --- 1154#define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1155#define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1156 1157#define S_LSO_OPCODE 24 1158#define M_LSO_OPCODE 0xFF 1159#define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1160#define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1161 | 1165#define S_LSO_TCPHDR_LEN 0 1166#define M_LSO_TCPHDR_LEN 0xF 1167#define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1168#define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1169 1170#define S_LSO_IPHDR_LEN 4 1171#define M_LSO_IPHDR_LEN 0xFFF 1172#define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) --- 20 unchanged lines hidden (view full) --- 1193#define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1194#define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1195 1196#define S_LSO_OPCODE 24 1197#define M_LSO_OPCODE 0xFF 1198#define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1199#define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1200 |
1162/* cpl_tx_pkt_lso.mss fields */ | 1201/* cpl_tx_pkt_lso_core.mss fields */ |
1163#define S_LSO_MSS 0 1164#define M_LSO_MSS 0x3FFF 1165#define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1166#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1167 1168#define S_LSO_IPID_SPLIT 15 1169#define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1170#define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1171 | 1202#define S_LSO_MSS 0 1203#define M_LSO_MSS 0x3FFF 1204#define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1205#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1206 1207#define S_LSO_IPID_SPLIT 15 1208#define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1209#define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1210 |
1172struct cpl_tx_pkt_coalesce { 1173 __be32 cntrl; | 1211struct cpl_tx_pkt_fso { 1212 WR_HDR; 1213 __be32 fso_ctrl; 1214 __be16 seqcnt_ofst; 1215 __be16 mtu; 1216 __be32 param_offset; |
1174 __be32 len; | 1217 __be32 len; |
1175 __be64 addr; | 1218 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ |
1176}; 1177 | 1219}; 1220 |
1178struct tx_pkt_coalesce_wr { 1179 WR_HDR; 1180#if !(defined C99_NOT_SUPPORTED) 1181 struct cpl_tx_pkt_coalesce cpl[0]; 1182#endif 1183}; | 1221/* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1222#define S_FSO_XCHG_CLASS 21 1223#define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1224#define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) |
1184 | 1225 |
1185struct mngt_pktsched_wr { 1186 __be32 wr_hi; 1187 __be32 wr_lo; 1188 __u8 mngt_opcode; 1189 __u8 rsvd[7]; 1190 __u8 sched; 1191 __u8 idx; 1192 __u8 min; 1193 __u8 max; 1194 __u8 binding; 1195 __u8 rsvd1[3]; 1196}; | 1226#define S_FSO_INITIATOR 20 1227#define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1228#define F_FSO_INITIATOR V_FSO_INITIATOR(1U) |
1197 | 1229 |
1230#define S_FSO_FCHDR_LEN 12 1231#define M_FSO_FCHDR_LEN 0xF 1232#define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1233#define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1234 |
|
1198struct cpl_iscsi_hdr_no_rss { 1199 union opcode_tid ot; 1200 __be16 pdu_len_ddp; 1201 __be16 len; 1202 __be32 seq; 1203 __be16 urg; 1204 __u8 rsvd; 1205 __u8 status; 1206}; 1207 | 1235struct cpl_iscsi_hdr_no_rss { 1236 union opcode_tid ot; 1237 __be16 pdu_len_ddp; 1238 __be16 len; 1239 __be32 seq; 1240 __be16 urg; 1241 __u8 rsvd; 1242 __u8 status; 1243}; 1244 |
1245struct cpl_tx_data_iso { 1246 WR_HDR; 1247 __be32 iso_ctrl; 1248 __u8 rsvd; 1249 __u8 ahs_len; 1250 __be16 mss; 1251 __be32 burst_size; 1252 __be32 len; 1253 /* encapsulated CPL_TX_DATA follows here */ 1254}; 1255 1256/* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1257#define S_ISO_CPLHDR_LEN 18 1258#define M_ISO_CPLHDR_LEN 0xF 1259#define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN) 1260#define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN) 1261 1262#define S_ISO_HDR_CRC 17 1263#define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC) 1264#define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U) 1265 1266#define S_ISO_DATA_CRC 16 1267#define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC) 1268#define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U) 1269 1270#define S_ISO_IMD_DATA_EN 15 1271#define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN) 1272#define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U) 1273 1274#define S_ISO_PDU_TYPE 13 1275#define M_ISO_PDU_TYPE 0x3 1276#define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE) 1277#define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE) 1278 |
|
1208struct cpl_iscsi_hdr { 1209 RSS_HDR 1210 union opcode_tid ot; 1211 __be16 pdu_len_ddp; 1212 __be16 len; 1213 __be32 seq; 1214 __be16 urg; 1215 __u8 rsvd; --- 5 unchanged lines hidden (view full) --- 1221#define M_ISCSI_PDU_LEN 0x7FFF 1222#define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1223#define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1224 1225#define S_ISCSI_DDP 15 1226#define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1227#define F_ISCSI_DDP V_ISCSI_DDP(1U) 1228 | 1279struct cpl_iscsi_hdr { 1280 RSS_HDR 1281 union opcode_tid ot; 1282 __be16 pdu_len_ddp; 1283 __be16 len; 1284 __be32 seq; 1285 __be16 urg; 1286 __u8 rsvd; --- 5 unchanged lines hidden (view full) --- 1292#define M_ISCSI_PDU_LEN 0x7FFF 1293#define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1294#define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1295 1296#define S_ISCSI_DDP 15 1297#define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1298#define F_ISCSI_DDP V_ISCSI_DDP(1U) 1299 |
1300struct cpl_iscsi_data { 1301 RSS_HDR 1302 union opcode_tid ot; 1303 __u8 rsvd0[2]; 1304 __be16 len; 1305 __be32 seq; 1306 __be16 urg; 1307 __u8 rsvd1; 1308 __u8 status; 1309}; 1310 |
|
1229struct cpl_rx_data { 1230 RSS_HDR 1231 union opcode_tid ot; 1232 __be16 rsvd; 1233 __be16 len; 1234 __be32 seq; 1235 __be16 urg; 1236#if defined(__LITTLE_ENDIAN_BITFIELD) --- 23 unchanged lines hidden (view full) --- 1260 __u8 sof; 1261 __u8 eof; 1262 __be16 seq_cnt; 1263 __u8 seq_id; 1264 __u8 type; 1265 __be32 param; 1266}; 1267 | 1311struct cpl_rx_data { 1312 RSS_HDR 1313 union opcode_tid ot; 1314 __be16 rsvd; 1315 __be16 len; 1316 __be32 seq; 1317 __be16 urg; 1318#if defined(__LITTLE_ENDIAN_BITFIELD) --- 23 unchanged lines hidden (view full) --- 1342 __u8 sof; 1343 __u8 eof; 1344 __be16 seq_cnt; 1345 __u8 seq_id; 1346 __u8 type; 1347 __be32 param; 1348}; 1349 |
1350struct cpl_fcoe_data { 1351 RSS_HDR 1352 union opcode_tid ot; 1353 __u8 rsvd0[2]; 1354 __be16 len; 1355 __be32 seq; 1356 __u8 rsvd1[3]; 1357 __u8 status; 1358}; 1359 |
|
1268struct cpl_rx_urg_notify { 1269 RSS_HDR 1270 union opcode_tid ot; 1271 __be32 seq; 1272}; 1273 1274struct cpl_rx_urg_pkt { 1275 RSS_HDR --- 52 unchanged lines hidden (view full) --- 1328 union { 1329 __be32 nxt_seq; 1330 __be32 ddp_report; 1331 } u; 1332 __be32 ulp_crc; 1333 __be32 ddpvld; 1334}; 1335 | 1360struct cpl_rx_urg_notify { 1361 RSS_HDR 1362 union opcode_tid ot; 1363 __be32 seq; 1364}; 1365 1366struct cpl_rx_urg_pkt { 1367 RSS_HDR --- 52 unchanged lines hidden (view full) --- 1420 union { 1421 __be32 nxt_seq; 1422 __be32 ddp_report; 1423 } u; 1424 __be32 ulp_crc; 1425 __be32 ddpvld; 1426}; 1427 |
1428#define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1429 |
|
1336struct cpl_rx_fcoe_ddp { 1337 RSS_HDR 1338 union opcode_tid ot; 1339 __be16 rsvd; 1340 __be16 len; 1341 __be32 seq; 1342 __be32 ddp_report; 1343 __be32 ulp_crc; 1344 __be32 ddpvld; 1345}; 1346 | 1430struct cpl_rx_fcoe_ddp { 1431 RSS_HDR 1432 union opcode_tid ot; 1433 __be16 rsvd; 1434 __be16 len; 1435 __be32 seq; 1436 __be32 ddp_report; 1437 __be32 ulp_crc; 1438 __be32 ddpvld; 1439}; 1440 |
1347/* cpl_rx_{data,fcoe}_ddp.ddpvld fields */ | 1441struct cpl_rx_data_dif { 1442 RSS_HDR 1443 union opcode_tid ot; 1444 __be16 ddp_len; 1445 __be16 msg_len; 1446 __be32 seq; 1447 union { 1448 __be32 nxt_seq; 1449 __be32 ddp_report; 1450 } u; 1451 __be32 err_vec; 1452 __be32 ddpvld; 1453}; 1454 1455struct cpl_rx_iscsi_dif { 1456 RSS_HDR 1457 union opcode_tid ot; 1458 __be16 ddp_len; 1459 __be16 msg_len; 1460 __be32 seq; 1461 union { 1462 __be32 nxt_seq; 1463 __be32 ddp_report; 1464 } u; 1465 __be32 ulp_crc; 1466 __be32 ddpvld; 1467 __u8 rsvd0[8]; 1468 __be32 err_vec; 1469 __u8 rsvd1[4]; 1470}; 1471 1472struct cpl_rx_fcoe_dif { 1473 RSS_HDR 1474 union opcode_tid ot; 1475 __be16 ddp_len; 1476 __be16 msg_len; 1477 __be32 seq; 1478 __be32 ddp_report; 1479 __be32 err_vec; 1480 __be32 ddpvld; 1481}; 1482 1483/* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ |
1348#define S_DDP_VALID 15 1349#define M_DDP_VALID 0x1FFFF 1350#define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1351#define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1352 1353#define S_DDP_PPOD_MISMATCH 15 1354#define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1355#define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) --- 46 unchanged lines hidden (view full) --- 1402#define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1403#define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1404 1405#define S_DDP_ULP_MODE 28 1406#define M_DDP_ULP_MODE 0xF 1407#define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1408#define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1409 | 1484#define S_DDP_VALID 15 1485#define M_DDP_VALID 0x1FFFF 1486#define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1487#define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1488 1489#define S_DDP_PPOD_MISMATCH 15 1490#define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1491#define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) --- 46 unchanged lines hidden (view full) --- 1538#define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1539#define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1540 1541#define S_DDP_ULP_MODE 28 1542#define M_DDP_ULP_MODE 0xF 1543#define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1544#define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1545 |
1410/* cpl_rx_{data,fcoe}_ddp.ddp_report fields */ | 1546/* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ |
1411#define S_DDP_OFFSET 0 1412#define M_DDP_OFFSET 0xFFFFFF 1413#define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1414#define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1415 1416#define S_DDP_DACK_MODE 24 1417#define M_DDP_DACK_MODE 0x3 1418#define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) --- 48 unchanged lines hidden (view full) --- 1467}; 1468 1469/* rx_pkt.l2info fields */ 1470#define S_RX_ETHHDR_LEN 0 1471#define M_RX_ETHHDR_LEN 0x1F 1472#define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1473#define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1474 | 1547#define S_DDP_OFFSET 0 1548#define M_DDP_OFFSET 0xFFFFFF 1549#define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1550#define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1551 1552#define S_DDP_DACK_MODE 24 1553#define M_DDP_DACK_MODE 0x3 1554#define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) --- 48 unchanged lines hidden (view full) --- 1603}; 1604 1605/* rx_pkt.l2info fields */ 1606#define S_RX_ETHHDR_LEN 0 1607#define M_RX_ETHHDR_LEN 0x1F 1608#define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1609#define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1610 |
1611#define S_RX_T5_ETHHDR_LEN 0 1612#define M_RX_T5_ETHHDR_LEN 0x3F 1613#define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1614#define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1615 |
|
1475#define S_RX_PKTYPE 5 1476#define M_RX_PKTYPE 0x7 1477#define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1478#define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1479 | 1616#define S_RX_PKTYPE 5 1617#define M_RX_PKTYPE 0x7 1618#define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1619#define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1620 |
1621#define S_RX_T5_DATYPE 6 1622#define M_RX_T5_DATYPE 0x3 1623#define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1624#define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1625 |
|
1480#define S_RX_MACIDX 8 1481#define M_RX_MACIDX 0x1FF 1482#define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1483#define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1484 | 1626#define S_RX_MACIDX 8 1627#define M_RX_MACIDX 0x1FF 1628#define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1629#define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1630 |
1631#define S_RX_T5_PKTYPE 17 1632#define M_RX_T5_PKTYPE 0x7 1633#define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1634#define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1635 |
|
1485#define S_RX_DATYPE 18 1486#define M_RX_DATYPE 0x3 1487#define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1488#define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1489 1490#define S_RXF_PSH 20 1491#define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1492#define F_RXF_PSH V_RXF_PSH(1U) --- 116 unchanged lines hidden (view full) --- 1609 __u8 err:1; 1610 __u8 :6; 1611#endif 1612 __be16 rsvd; 1613 __be16 len; 1614 __be64 tstamp; 1615}; 1616 | 1636#define S_RX_DATYPE 18 1637#define M_RX_DATYPE 0x3 1638#define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1639#define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1640 1641#define S_RXF_PSH 20 1642#define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1643#define F_RXF_PSH V_RXF_PSH(1U) --- 116 unchanged lines hidden (view full) --- 1760 __u8 err:1; 1761 __u8 :6; 1762#endif 1763 __be16 rsvd; 1764 __be16 len; 1765 __be64 tstamp; 1766}; 1767 |
1768struct cpl_t5_trace_pkt { 1769 RSS_HDR 1770 __u8 opcode; 1771 __u8 intf; 1772#if defined(__LITTLE_ENDIAN_BITFIELD) 1773 __u8 runt:4; 1774 __u8 filter_hit:4; 1775 __u8 :6; 1776 __u8 err:1; 1777 __u8 trunc:1; 1778#else 1779 __u8 filter_hit:4; 1780 __u8 runt:4; 1781 __u8 trunc:1; 1782 __u8 err:1; 1783 __u8 :6; 1784#endif 1785 __be16 rsvd; 1786 __be16 len; 1787 __be64 tstamp; 1788 __be64 rsvd1; 1789}; 1790 |
|
1617struct cpl_rte_delete_req { 1618 WR_HDR; 1619 union opcode_tid ot; 1620 __be32 params; 1621}; 1622 1623/* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1624#define S_RTE_REQ_LUT_IX 8 --- 134 unchanged lines hidden (view full) --- 1759 union opcode_tid ot; 1760 __be32 params; 1761 __be16 pfvf1; 1762 __u8 src_mac1[6]; 1763 __be16 pfvf0; 1764 __u8 src_mac0[6]; 1765}; 1766 | 1791struct cpl_rte_delete_req { 1792 WR_HDR; 1793 union opcode_tid ot; 1794 __be32 params; 1795}; 1796 1797/* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1798#define S_RTE_REQ_LUT_IX 8 --- 134 unchanged lines hidden (view full) --- 1933 union opcode_tid ot; 1934 __be32 params; 1935 __be16 pfvf1; 1936 __u8 src_mac1[6]; 1937 __be16 pfvf0; 1938 __u8 src_mac0[6]; 1939}; 1940 |
1941struct cpl_smt_write_rpl { 1942 RSS_HDR 1943 union opcode_tid ot; 1944 __u8 status; 1945 __u8 rsvd[3]; 1946}; 1947 1948struct cpl_smt_read_req { 1949 WR_HDR; 1950 union opcode_tid ot; 1951 __be32 params; 1952}; 1953 1954struct cpl_smt_read_rpl { 1955 RSS_HDR 1956 union opcode_tid ot; 1957 __u8 status; 1958 __u8 ovlan_idx; 1959 __be16 rsvd; 1960 __be16 pfvf1; 1961 __u8 src_mac1[6]; 1962 __be16 pfvf0; 1963 __u8 src_mac0[6]; 1964}; 1965 |
|
1767/* cpl_smt_{read,write}_req.params fields */ 1768#define S_SMTW_OVLAN_IDX 16 1769#define M_SMTW_OVLAN_IDX 0xF 1770#define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 1771#define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 1772 1773#define S_SMTW_IDX 20 1774#define M_SMTW_IDX 0x7F --- 14 unchanged lines hidden (view full) --- 1789#define M_SMTW_PF 0x7 1790#define V_SMTW_PF(x) ((x) << S_SMTW_PF) 1791#define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 1792 1793#define S_SMTW_VF_VLD 11 1794#define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 1795#define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 1796 | 1966/* cpl_smt_{read,write}_req.params fields */ 1967#define S_SMTW_OVLAN_IDX 16 1968#define M_SMTW_OVLAN_IDX 0xF 1969#define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 1970#define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 1971 1972#define S_SMTW_IDX 20 1973#define M_SMTW_IDX 0x7F --- 14 unchanged lines hidden (view full) --- 1988#define M_SMTW_PF 0x7 1989#define V_SMTW_PF(x) ((x) << S_SMTW_PF) 1990#define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 1991 1992#define S_SMTW_VF_VLD 11 1993#define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 1994#define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 1995 |
1797struct cpl_smt_write_rpl { | 1996struct cpl_tag_write_req { 1997 WR_HDR; 1998 union opcode_tid ot; 1999 __be32 params; 2000 __be64 tag_val; 2001}; 2002 2003struct cpl_tag_write_rpl { |
1798 RSS_HDR 1799 union opcode_tid ot; 1800 __u8 status; | 2004 RSS_HDR 2005 union opcode_tid ot; 2006 __u8 status; |
1801 __u8 rsvd[3]; | 2007 __u8 rsvd[2]; 2008 __u8 idx; |
1802}; 1803 | 2009}; 2010 |
1804struct cpl_smt_read_req { | 2011struct cpl_tag_read_req { |
1805 WR_HDR; 1806 union opcode_tid ot; 1807 __be32 params; 1808}; 1809 | 2012 WR_HDR; 2013 union opcode_tid ot; 2014 __be32 params; 2015}; 2016 |
1810struct cpl_smt_read_rpl { | 2017struct cpl_tag_read_rpl { |
1811 RSS_HDR 1812 union opcode_tid ot; 1813 __u8 status; | 2018 RSS_HDR 2019 union opcode_tid ot; 2020 __u8 status; |
1814 __u8 ovlan_idx; 1815 __be16 rsvd; 1816 __be16 pfvf1; 1817 __u8 src_mac1[6]; 1818 __be16 pfvf0; 1819 __u8 src_mac0[6]; | 2021#if defined(__LITTLE_ENDIAN_BITFIELD) 2022 __u8 :4; 2023 __u8 tag_len:1; 2024 __u8 :2; 2025 __u8 ins_enable:1; 2026#else 2027 __u8 ins_enable:1; 2028 __u8 :2; 2029 __u8 tag_len:1; 2030 __u8 :4; 2031#endif 2032 __u8 rsvd; 2033 __u8 tag_idx; 2034 __be64 tag_val; |
1820}; 1821 | 2035}; 2036 |
2037/* cpl_tag{read,write}_req.params fields */ 2038#define S_TAGW_IDX 0 2039#define M_TAGW_IDX 0x7F 2040#define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2041#define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2042 2043#define S_TAGW_LEN 20 2044#define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2045#define F_TAGW_LEN V_TAGW_LEN(1U) 2046 2047#define S_TAGW_INS_ENABLE 23 2048#define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2049#define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2050 2051#define S_TAGW_NORPL 31 2052#define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2053#define F_TAGW_NORPL V_TAGW_NORPL(1U) 2054 |
|
1822struct cpl_barrier { 1823 WR_HDR; 1824 __u8 opcode; 1825 __u8 chan_map; 1826 __be16 rsvd0; 1827 __be32 rsvd1; 1828}; 1829 --- 47 unchanged lines hidden (view full) --- 1877#define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 1878#define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 1879 1880#define S_NTFY_ETHHDR_LEN 27 1881#define M_NTFY_ETHHDR_LEN 0x1F 1882#define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 1883#define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 1884 | 2055struct cpl_barrier { 2056 WR_HDR; 2057 __u8 opcode; 2058 __u8 chan_map; 2059 __be16 rsvd0; 2060 __be32 rsvd1; 2061}; 2062 --- 47 unchanged lines hidden (view full) --- 2110#define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2111#define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2112 2113#define S_NTFY_ETHHDR_LEN 27 2114#define M_NTFY_ETHHDR_LEN 0x1F 2115#define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2116#define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2117 |
2118#define S_NTFY_T5_IPHDR_LEN 18 2119#define M_NTFY_T5_IPHDR_LEN 0xFF 2120#define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2121#define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2122 2123#define S_NTFY_T5_ETHHDR_LEN 26 2124#define M_NTFY_T5_ETHHDR_LEN 0x3F 2125#define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2126#define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2127 |
|
1885struct cpl_rdma_terminate { 1886 RSS_HDR 1887 union opcode_tid ot; 1888 __be16 rsvd; 1889 __be16 len; 1890}; 1891 1892struct cpl_set_le_req { --- 113 unchanged lines hidden (view full) --- 2006 __be64 data[2]; 2007}; 2008 2009struct cpl_fw4_ack { 2010 RSS_HDR 2011 union opcode_tid ot; 2012 u8 credits; 2013 u8 rsvd0[2]; | 2128struct cpl_rdma_terminate { 2129 RSS_HDR 2130 union opcode_tid ot; 2131 __be16 rsvd; 2132 __be16 len; 2133}; 2134 2135struct cpl_set_le_req { --- 113 unchanged lines hidden (view full) --- 2249 __be64 data[2]; 2250}; 2251 2252struct cpl_fw4_ack { 2253 RSS_HDR 2254 union opcode_tid ot; 2255 u8 credits; 2256 u8 rsvd0[2]; |
2014 u8 seq_vld; | 2257 u8 flags; |
2015 __be32 snd_nxt; 2016 __be32 snd_una; 2017 __be64 rsvd1; 2018}; 2019 | 2258 __be32 snd_nxt; 2259 __be32 snd_una; 2260 __be64 rsvd1; 2261}; 2262 |
2263enum { 2264 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2265 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2266 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2267}; 2268 |
|
2020struct cpl_fw6_msg { 2021 RSS_HDR 2022 u8 opcode; 2023 u8 type; 2024 __be16 rsvd0; 2025 __be32 rsvd1; 2026 __be64 data[4]; 2027}; 2028 2029/* cpl_fw6_msg.type values */ 2030enum { 2031 FW6_TYPE_CMD_RPL = 0, | 2269struct cpl_fw6_msg { 2270 RSS_HDR 2271 u8 opcode; 2272 u8 type; 2273 __be16 rsvd0; 2274 __be32 rsvd1; 2275 __be64 data[4]; 2276}; 2277 2278/* cpl_fw6_msg.type values */ 2279enum { 2280 FW6_TYPE_CMD_RPL = 0, |
2281 FW6_TYPE_WR_RPL = 1, 2282 FW6_TYPE_CQE = 2, 2283 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, |
|
2032}; 2033 | 2284}; 2285 |
2286struct cpl_fw6_msg_ofld_connection_wr_rpl { 2287 __u64 cookie; 2288 __be32 tid; /* or atid in case of active failure */ 2289 __u8 t_state; 2290 __u8 retval; 2291 __u8 rsvd[2]; 2292}; 2293 |
|
2034/* ULP_TX opcodes */ 2035enum { 2036 ULP_TX_MEM_READ = 2, 2037 ULP_TX_MEM_WRITE = 3, 2038 ULP_TX_PKT = 4 2039}; 2040 2041enum { --- 88 unchanged lines hidden (view full) --- 2130#define S_ULP_TXPKT_DEST 16 2131#define M_ULP_TXPKT_DEST 0x3 2132#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2133 2134#define S_ULP_TXPKT_FID 4 2135#define M_ULP_TXPKT_FID 0x7ff 2136#define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2137 | 2294/* ULP_TX opcodes */ 2295enum { 2296 ULP_TX_MEM_READ = 2, 2297 ULP_TX_MEM_WRITE = 3, 2298 ULP_TX_PKT = 4 2299}; 2300 2301enum { --- 88 unchanged lines hidden (view full) --- 2390#define S_ULP_TXPKT_DEST 16 2391#define M_ULP_TXPKT_DEST 0x3 2392#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2393 2394#define S_ULP_TXPKT_FID 4 2395#define M_ULP_TXPKT_FID 0x7ff 2396#define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2397 |
2398#define S_ULP_TXPKT_RO 3 2399#define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2400#define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2401 |
|
2138#endif /* T4_MSG_H */ | 2402#endif /* T4_MSG_H */ |