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adapter.h (269356) adapter.h (270297)
1/*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
1/*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 10 unchanged lines hidden (view full) ---

19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: stable/10/sys/dev/cxgbe/adapter.h 269356 2014-07-31 23:04:41Z np $
27 * $FreeBSD: stable/10/sys/dev/cxgbe/adapter.h 270297 2014-08-21 19:54:02Z np $
28 *
29 */
30
31#ifndef __T4_ADAPTER_H__
32#define __T4_ADAPTER_H__
33
34#include <sys/kernel.h>
35#include <sys/bus.h>

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43#include <sys/sysctl.h>
44#include <net/ethernet.h>
45#include <net/if.h>
46#include <net/if_media.h>
47#include <netinet/in.h>
48#include <netinet/tcp_lro.h>
49
50#include "offload.h"
28 *
29 */
30
31#ifndef __T4_ADAPTER_H__
32#define __T4_ADAPTER_H__
33
34#include <sys/kernel.h>
35#include <sys/bus.h>

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43#include <sys/sysctl.h>
44#include <net/ethernet.h>
45#include <net/if.h>
46#include <net/if_media.h>
47#include <netinet/in.h>
48#include <netinet/tcp_lro.h>
49
50#include "offload.h"
51#include "common/t4_msg.h"
51#include "firmware/t4fw_interface.h"
52
53MALLOC_DECLARE(M_CXGBE);
54#define CXGBE_UNIMPLEMENTED(s) \
55 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
56
57#if defined(__i386__) || defined(__amd64__)
58static __inline void

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113 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
114}
115#endif
116
117struct adapter;
118typedef struct adapter adapter_t;
119
120enum {
52#include "firmware/t4fw_interface.h"
53
54MALLOC_DECLARE(M_CXGBE);
55#define CXGBE_UNIMPLEMENTED(s) \
56 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
57
58#if defined(__i386__) || defined(__amd64__)
59static __inline void

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114 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
115}
116#endif
117
118struct adapter;
119typedef struct adapter adapter_t;
120
121enum {
121 FW_IQ_QSIZE = 256,
122 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */
122 /*
123 * All ingress queues use this entry size. Note that the firmware event
124 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
125 * be at least 64.
126 */
127 IQ_ESIZE = 64,
123
128
129 /* Default queue sizes for all kinds of ingress queues */
130 FW_IQ_QSIZE = 256,
124 RX_IQ_QSIZE = 1024,
131 RX_IQ_QSIZE = 1024,
125 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */
126
132
127 EQ_ESIZE = 64, /* All egress queues use this entry size */
133 /* All egress queues use this entry size */
134 EQ_ESIZE = 64,
128
135
129 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */
136 /* Default queue sizes for all kinds of egress queues */
137 CTRL_EQ_QSIZE = 128,
138 TX_EQ_QSIZE = 1024,
139
130#if MJUMPAGESIZE != MCLBYTES
131 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
132#else
133 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
134#endif
135 CL_METADATA_SIZE = CACHE_LINE_SIZE,
136
140#if MJUMPAGESIZE != MCLBYTES
141 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
142#else
143 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
144#endif
145 CL_METADATA_SIZE = CACHE_LINE_SIZE,
146
137 CTRL_EQ_QSIZE = 128,
138
139 TX_EQ_QSIZE = 1024,
147 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
140 TX_SGL_SEGS = 36,
141 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
142};
143
144enum {
145 /* adapter intr_type */
146 INTR_INTX = (1 << 0),
147 INTR_MSI = (1 << 1),
148 INTR_MSIX = (1 << 2)
149};
150
151enum {
148 TX_SGL_SEGS = 36,
149 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
150};
151
152enum {
153 /* adapter intr_type */
154 INTR_INTX = (1 << 0),
155 INTR_MSI = (1 << 1),
156 INTR_MSIX = (1 << 2)
157};
158
159enum {
160 XGMAC_MTU = (1 << 0),
161 XGMAC_PROMISC = (1 << 1),
162 XGMAC_ALLMULTI = (1 << 2),
163 XGMAC_VLANEX = (1 << 3),
164 XGMAC_UCADDR = (1 << 4),
165 XGMAC_MCADDRS = (1 << 5),
166
167 XGMAC_ALL = 0xffff
168};
169
170enum {
152 /* flags understood by begin_synchronized_op */
153 HOLD_LOCK = (1 << 0),
154 SLEEP_OK = (1 << 1),
155 INTR_OK = (1 << 2),
156
157 /* flags understood by end_synchronized_op */
158 LOCK_HELD = HOLD_LOCK,
159};
160
161enum {
162 /* adapter flags */
163 FULL_INIT_DONE = (1 << 0),
164 FW_OK = (1 << 1),
171 /* flags understood by begin_synchronized_op */
172 HOLD_LOCK = (1 << 0),
173 SLEEP_OK = (1 << 1),
174 INTR_OK = (1 << 2),
175
176 /* flags understood by end_synchronized_op */
177 LOCK_HELD = HOLD_LOCK,
178};
179
180enum {
181 /* adapter flags */
182 FULL_INIT_DONE = (1 << 0),
183 FW_OK = (1 << 1),
165 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */
184 /* INTR_DIRECT = (1 << 2), No longer used. */
166 MASTER_PF = (1 << 3),
167 ADAP_SYSCTL_CTX = (1 << 4),
168 TOM_INIT_DONE = (1 << 5),
169 BUF_PACKING_OK = (1 << 6),
170
171 CXGBE_BUSY = (1 << 9),
172
173 /* port flags */
174 DOOMED = (1 << 0),
175 PORT_INIT_DONE = (1 << 1),
176 PORT_SYSCTL_CTX = (1 << 2),
177 HAS_TRACEQ = (1 << 3),
185 MASTER_PF = (1 << 3),
186 ADAP_SYSCTL_CTX = (1 << 4),
187 TOM_INIT_DONE = (1 << 5),
188 BUF_PACKING_OK = (1 << 6),
189
190 CXGBE_BUSY = (1 << 9),
191
192 /* port flags */
193 DOOMED = (1 << 0),
194 PORT_INIT_DONE = (1 << 1),
195 PORT_SYSCTL_CTX = (1 << 2),
196 HAS_TRACEQ = (1 << 3),
197 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
198 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
199 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */
200 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ),
178};
179
180#define IS_DOOMED(pi) ((pi)->flags & DOOMED)
181#define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0)
182#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
183#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
184#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
185

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214 int nrxq; /* # of rx queues */
215 int first_rxq; /* index of first rx queue */
216#ifdef TCP_OFFLOAD
217 int nofldtxq; /* # of offload tx queues */
218 int first_ofld_txq; /* index of first offload tx queue */
219 int nofldrxq; /* # of offload rx queues */
220 int first_ofld_rxq; /* index of first offload rx queue */
221#endif
201};
202
203#define IS_DOOMED(pi) ((pi)->flags & DOOMED)
204#define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0)
205#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
206#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
207#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
208

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237 int nrxq; /* # of rx queues */
238 int first_rxq; /* index of first rx queue */
239#ifdef TCP_OFFLOAD
240 int nofldtxq; /* # of offload tx queues */
241 int first_ofld_txq; /* index of first offload tx queue */
242 int nofldrxq; /* # of offload rx queues */
243 int first_ofld_rxq; /* index of first offload rx queue */
244#endif
245#ifdef DEV_NETMAP
246 int nnmtxq; /* # of netmap tx queues */
247 int first_nm_txq; /* index of first netmap tx queue */
248 int nnmrxq; /* # of netmap rx queues */
249 int first_nm_rxq; /* index of first netmap rx queue */
250
251 struct ifnet *nm_ifp;
252 struct ifmedia nm_media;
253 int nmif_flags;
254 uint16_t nm_viid;
255 int16_t nm_xact_addr_filt;
256 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */
257#endif
222 int tmr_idx;
223 int pktc_idx;
224 int qsize_rxq;
225 int qsize_txq;
226
227 int linkdnrc;
228 struct link_config link_cfg;
229 struct port_stats stats;

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276 uint32_t map_avail; /* # of available maps */
277};
278
279struct tx_sdesc {
280 uint8_t desc_used; /* # of hardware descriptors used by the WR */
281 uint8_t credits; /* NIC txq: # of frames sent out in the WR */
282};
283
258 int tmr_idx;
259 int pktc_idx;
260 int qsize_rxq;
261 int qsize_txq;
262
263 int linkdnrc;
264 struct link_config link_cfg;
265 struct port_stats stats;

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312 uint32_t map_avail; /* # of available maps */
313};
314
315struct tx_sdesc {
316 uint8_t desc_used; /* # of hardware descriptors used by the WR */
317 uint8_t credits; /* NIC txq: # of frames sent out in the WR */
318};
319
320
321#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
322struct iq_desc {
323 struct rss_header rss;
324 uint8_t cpl[IQ_PAD];
325 struct rsp_ctrl rsp;
326};
327#undef IQ_PAD
328CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
329
284enum {
285 /* iq flags */
286 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
287 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
288 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
289 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
290
291 /* iq state */
292 IQS_DISABLED = 0,
293 IQS_BUSY = 1,
294 IQS_IDLE = 2,
295};
296
297/*
298 * Ingress Queue: T4 is producer, driver is consumer.
299 */
300struct sge_iq {
330enum {
331 /* iq flags */
332 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
333 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
334 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
335 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
336
337 /* iq state */
338 IQS_DISABLED = 0,
339 IQS_BUSY = 1,
340 IQS_IDLE = 2,
341};
342
343/*
344 * Ingress Queue: T4 is producer, driver is consumer.
345 */
346struct sge_iq {
301 bus_dma_tag_t desc_tag;
302 bus_dmamap_t desc_map;
303 bus_addr_t ba; /* bus address of descriptor ring */
304 uint32_t flags;
347 uint32_t flags;
305 uint16_t abs_id; /* absolute SGE id for the iq */
306 int8_t intr_pktc_idx; /* packet count threshold index */
307 int8_t pad0;
308 __be64 *desc; /* KVA of descriptor ring */
309
310 volatile int state;
311 struct adapter *adapter;
348 volatile int state;
349 struct adapter *adapter;
312 const __be64 *cdesc; /* current descriptor */
350 struct iq_desc *desc; /* KVA of descriptor ring */
351 int8_t intr_pktc_idx; /* packet count threshold index */
313 uint8_t gen; /* generation bit */
314 uint8_t intr_params; /* interrupt holdoff parameters */
315 uint8_t intr_next; /* XXX: holdoff for next interrupt */
352 uint8_t gen; /* generation bit */
353 uint8_t intr_params; /* interrupt holdoff parameters */
354 uint8_t intr_next; /* XXX: holdoff for next interrupt */
316 uint8_t esize; /* size (bytes) of each entry in the queue */
317 uint16_t qsize; /* size (# of entries) of the queue */
355 uint16_t qsize; /* size (# of entries) of the queue */
356 uint16_t sidx; /* index of the entry with the status page */
318 uint16_t cidx; /* consumer index */
319 uint16_t cntxt_id; /* SGE context id for the iq */
357 uint16_t cidx; /* consumer index */
358 uint16_t cntxt_id; /* SGE context id for the iq */
359 uint16_t abs_id; /* absolute SGE id for the iq */
320
321 STAILQ_ENTRY(sge_iq) link;
360
361 STAILQ_ENTRY(sge_iq) link;
362
363 bus_dma_tag_t desc_tag;
364 bus_dmamap_t desc_map;
365 bus_addr_t ba; /* bus address of descriptor ring */
322};
323
324enum {
325 EQ_CTRL = 1,
326 EQ_ETH = 2,
327#ifdef TCP_OFFLOAD
328 EQ_OFLD = 3,
329#endif

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351 bus_dma_tag_t desc_tag;
352 bus_dmamap_t desc_map;
353 char lockname[16];
354 struct mtx eq_lock;
355
356 struct tx_desc *desc; /* KVA of descriptor ring */
357 bus_addr_t ba; /* bus address of descriptor ring */
358 struct sge_qstat *spg; /* status page, for convenience */
366};
367
368enum {
369 EQ_CTRL = 1,
370 EQ_ETH = 2,
371#ifdef TCP_OFFLOAD
372 EQ_OFLD = 3,
373#endif

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395 bus_dma_tag_t desc_tag;
396 bus_dmamap_t desc_map;
397 char lockname[16];
398 struct mtx eq_lock;
399
400 struct tx_desc *desc; /* KVA of descriptor ring */
401 bus_addr_t ba; /* bus address of descriptor ring */
402 struct sge_qstat *spg; /* status page, for convenience */
359 int doorbells;
403 uint16_t doorbells;
360 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
361 u_int udb_qid; /* relative qid within the doorbell page */
362 uint16_t cap; /* max # of desc, for convenience */
363 uint16_t avail; /* available descriptors, for convenience */
364 uint16_t qsize; /* size (# of entries) of the queue */
365 uint16_t cidx; /* consumer idx (desc idx) */
366 uint16_t pidx; /* producer idx (desc idx) */
367 uint16_t pending; /* # of descriptors used since last doorbell */

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389 int8_t next; /* next hwidx for this zone; -1 means no more */
390 int size;
391};
392
393enum {
394 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
395 FL_DOOMED = (1 << 1), /* about to be destroyed */
396 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
404 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
405 u_int udb_qid; /* relative qid within the doorbell page */
406 uint16_t cap; /* max # of desc, for convenience */
407 uint16_t avail; /* available descriptors, for convenience */
408 uint16_t qsize; /* size (# of entries) of the queue */
409 uint16_t cidx; /* consumer idx (desc idx) */
410 uint16_t pidx; /* producer idx (desc idx) */
411 uint16_t pending; /* # of descriptors used since last doorbell */

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433 int8_t next; /* next hwidx for this zone; -1 means no more */
434 int size;
435};
436
437enum {
438 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
439 FL_DOOMED = (1 << 1), /* about to be destroyed */
440 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
441 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
397};
398
442};
443
399#define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat)
400#define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat)
444#define FL_RUNNING_LOW(fl) \
445 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
446#define FL_NOT_RUNNING_LOW(fl) \
447 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
401
402struct sge_fl {
448
449struct sge_fl {
403 bus_dma_tag_t desc_tag;
404 bus_dmamap_t desc_map;
405 struct cluster_layout cll_def; /* default refill zone, layout */
406 struct cluster_layout cll_alt; /* alternate refill zone, layout */
407 struct mtx fl_lock;
450 struct mtx fl_lock;
408 char lockname[16];
409 int flags;
410
411 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
451 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
412 bus_addr_t ba; /* bus address of descriptor ring */
413 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
452 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
414 uint32_t cap; /* max # of buffers, for convenience */
415 uint16_t qsize; /* size (# of entries) of the queue */
416 uint16_t cntxt_id; /* SGE context id for the freelist */
417 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */
418 uint32_t rx_offset; /* offset in fl buf (when buffer packing) */
419 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */
420 uint32_t needed; /* # of buffers needed to fill up fl. */
421 uint32_t lowat; /* # of buffers <= this means fl needs help */
422 uint32_t pending; /* # of bufs allocated since last doorbell */
423 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
453 struct cluster_layout cll_def; /* default refill zone, layout */
454 uint16_t lowat; /* # of buffers <= this means fl needs help */
455 int flags;
456 uint16_t buf_boundary;
424
457
425 struct mbuf *m0;
426 struct mbuf **pnext;
427 u_int remaining;
458 /* The 16b idx all deal with hw descriptors */
459 uint16_t dbidx; /* hw pidx after last doorbell */
460 uint16_t sidx; /* index of status page */
461 volatile uint16_t hw_cidx;
428
462
463 /* The 32b idx are all buffer idx, not hardware descriptor idx */
464 uint32_t cidx; /* consumer index */
465 uint32_t pidx; /* producer index */
466
467 uint32_t dbval;
468 u_int rx_offset; /* offset in fl buf (when buffer packing) */
469 volatile uint32_t *udb;
470
429 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
430 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
431 uint64_t cl_allocated; /* # of clusters allocated */
432 uint64_t cl_recycled; /* # of clusters recycled */
433 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
471 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
472 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
473 uint64_t cl_allocated; /* # of clusters allocated */
474 uint64_t cl_recycled; /* # of clusters recycled */
475 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
476
477 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
478 struct mbuf *m0;
479 struct mbuf **pnext;
480 u_int remaining;
481
482 uint16_t qsize; /* # of hw descriptors (status page included) */
483 uint16_t cntxt_id; /* SGE context id for the freelist */
484 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
485 bus_dma_tag_t desc_tag;
486 bus_dmamap_t desc_map;
487 char lockname[16];
488 bus_addr_t ba; /* bus address of descriptor ring */
489 struct cluster_layout cll_alt; /* alternate refill zone, layout */
434};
435
436/* txq: SGE egress queue + what's needed for Ethernet NIC */
437struct sge_txq {
438 struct sge_eq eq; /* MUST be first */
439
440 struct ifnet *ifp; /* the interface this txq belongs to */
441 bus_dma_tag_t tx_tag; /* tag for transmit buffers */

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527
528 uint64_t tx_wrs; /* # of tx work requests */
529
530 /* stats for not-that-common events */
531
532 uint32_t no_desc; /* out of hardware descriptors */
533} __aligned(CACHE_LINE_SIZE);
534
490};
491
492/* txq: SGE egress queue + what's needed for Ethernet NIC */
493struct sge_txq {
494 struct sge_eq eq; /* MUST be first */
495
496 struct ifnet *ifp; /* the interface this txq belongs to */
497 bus_dma_tag_t tx_tag; /* tag for transmit buffers */

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583
584 uint64_t tx_wrs; /* # of tx work requests */
585
586 /* stats for not-that-common events */
587
588 uint32_t no_desc; /* out of hardware descriptors */
589} __aligned(CACHE_LINE_SIZE);
590
591
592#ifdef DEV_NETMAP
593struct sge_nm_rxq {
594 struct port_info *pi;
595
596 struct iq_desc *iq_desc;
597 uint16_t iq_abs_id;
598 uint16_t iq_cntxt_id;
599 uint16_t iq_cidx;
600 uint16_t iq_sidx;
601 uint8_t iq_gen;
602
603 __be64 *fl_desc;
604 uint16_t fl_cntxt_id;
605 uint32_t fl_cidx;
606 uint32_t fl_pidx;
607 uint32_t fl_sidx;
608 uint32_t fl_db_val;
609 u_int fl_hwidx:4;
610
611 u_int nid; /* netmap ring # for this queue */
612
613 /* infrequently used items after this */
614
615 bus_dma_tag_t iq_desc_tag;
616 bus_dmamap_t iq_desc_map;
617 bus_addr_t iq_ba;
618 int intr_idx;
619
620 bus_dma_tag_t fl_desc_tag;
621 bus_dmamap_t fl_desc_map;
622 bus_addr_t fl_ba;
623} __aligned(CACHE_LINE_SIZE);
624
625struct sge_nm_txq {
626 struct tx_desc *desc;
627 uint16_t cidx;
628 uint16_t pidx;
629 uint16_t sidx;
630 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
631 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
632 uint16_t dbidx; /* pidx of the most recent doorbell */
633 uint16_t doorbells;
634 volatile uint32_t *udb;
635 u_int udb_qid;
636 u_int cntxt_id;
637 __be32 cpl_ctrl0; /* for convenience */
638 u_int nid; /* netmap ring # for this queue */
639
640 /* infrequently used items after this */
641
642 bus_dma_tag_t desc_tag;
643 bus_dmamap_t desc_map;
644 bus_addr_t ba;
645 int iqidx;
646} __aligned(CACHE_LINE_SIZE);
647#endif
648
535struct sge {
536 int timer_val[SGE_NTIMERS];
537 int counter_val[SGE_NCOUNTERS];
538 int fl_starve_threshold;
539 int fl_starve_threshold2;
540 int eq_s_qpp;
541 int iq_s_qpp;
542
543 int nrxq; /* total # of Ethernet rx queues */
544 int ntxq; /* total # of Ethernet tx tx queues */
545#ifdef TCP_OFFLOAD
546 int nofldrxq; /* total # of TOE rx queues */
547 int nofldtxq; /* total # of TOE tx queues */
548#endif
649struct sge {
650 int timer_val[SGE_NTIMERS];
651 int counter_val[SGE_NCOUNTERS];
652 int fl_starve_threshold;
653 int fl_starve_threshold2;
654 int eq_s_qpp;
655 int iq_s_qpp;
656
657 int nrxq; /* total # of Ethernet rx queues */
658 int ntxq; /* total # of Ethernet tx tx queues */
659#ifdef TCP_OFFLOAD
660 int nofldrxq; /* total # of TOE rx queues */
661 int nofldtxq; /* total # of TOE tx queues */
662#endif
663#ifdef DEV_NETMAP
664 int nnmrxq; /* total # of netmap rx queues */
665 int nnmtxq; /* total # of netmap tx queues */
666#endif
549 int niq; /* total # of ingress queues */
550 int neq; /* total # of egress queues */
551
552 struct sge_iq fwq; /* Firmware event queue */
553 struct sge_wrq mgmtq; /* Management queue (control queue) */
554 struct sge_wrq *ctrlq; /* Control queues */
555 struct sge_txq *txq; /* NIC tx queues */
556 struct sge_rxq *rxq; /* NIC rx queues */
557#ifdef TCP_OFFLOAD
558 struct sge_wrq *ofld_txq; /* TOE tx queues */
559 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
560#endif
667 int niq; /* total # of ingress queues */
668 int neq; /* total # of egress queues */
669
670 struct sge_iq fwq; /* Firmware event queue */
671 struct sge_wrq mgmtq; /* Management queue (control queue) */
672 struct sge_wrq *ctrlq; /* Control queues */
673 struct sge_txq *txq; /* NIC tx queues */
674 struct sge_rxq *rxq; /* NIC rx queues */
675#ifdef TCP_OFFLOAD
676 struct sge_wrq *ofld_txq; /* TOE tx queues */
677 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
678#endif
679#ifdef DEV_NETMAP
680 struct sge_nm_txq *nm_txq; /* netmap tx queues */
681 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
682#endif
561
562 uint16_t iq_start;
563 int eq_start;
564 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
565 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
566
567 int pack_boundary;
568 int8_t safe_hwidx1; /* may not have room for metadata */

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614 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */
615 struct port_info *port[MAX_NPORTS];
616 uint8_t chan_map[NCHAN];
617
618#ifdef TCP_OFFLOAD
619 void *tom_softc; /* (struct tom_data *) */
620 struct tom_tunables tt;
621 void *iwarp_softc; /* (struct c4iw_dev *) */
683
684 uint16_t iq_start;
685 int eq_start;
686 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
687 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
688
689 int pack_boundary;
690 int8_t safe_hwidx1; /* may not have room for metadata */

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736 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */
737 struct port_info *port[MAX_NPORTS];
738 uint8_t chan_map[NCHAN];
739
740#ifdef TCP_OFFLOAD
741 void *tom_softc; /* (struct tom_data *) */
742 struct tom_tunables tt;
743 void *iwarp_softc; /* (struct c4iw_dev *) */
744 void *iscsi_softc;
622#endif
623 struct l2t_data *l2t; /* L2 table */
624 struct tid_info tids;
625
745#endif
746 struct l2t_data *l2t; /* L2 table */
747 struct tid_info tids;
748
626 int doorbells;
749 uint16_t doorbells;
627 int open_device_map;
628#ifdef TCP_OFFLOAD
629 int offload_map;
630#endif
631 int flags;
632
633 char ifp_lockname[16];
634 struct mtx ifp_lock;

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719 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \
720 iter < pi->nrxq; ++iter, ++q)
721#define for_each_ofld_txq(pi, iter, q) \
722 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \
723 iter < pi->nofldtxq; ++iter, ++q)
724#define for_each_ofld_rxq(pi, iter, q) \
725 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \
726 iter < pi->nofldrxq; ++iter, ++q)
750 int open_device_map;
751#ifdef TCP_OFFLOAD
752 int offload_map;
753#endif
754 int flags;
755
756 char ifp_lockname[16];
757 struct mtx ifp_lock;

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842 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \
843 iter < pi->nrxq; ++iter, ++q)
844#define for_each_ofld_txq(pi, iter, q) \
845 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \
846 iter < pi->nofldtxq; ++iter, ++q)
847#define for_each_ofld_rxq(pi, iter, q) \
848 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \
849 iter < pi->nofldrxq; ++iter, ++q)
850#define for_each_nm_txq(pi, iter, q) \
851 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \
852 iter < pi->nnmtxq; ++iter, ++q)
853#define for_each_nm_rxq(pi, iter, q) \
854 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \
855 iter < pi->nnmrxq; ++iter, ++q)
727
856
857#define IDXINCR(idx, incr, wrap) do { \
858 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
859} while (0)
860#define IDXDIFF(head, tail, wrap) \
861 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
862
728/* One for errors, one for firmware events */
729#define T4_EXTRA_INTR 2
730
731static inline uint32_t
732t4_read_reg(struct adapter *sc, uint32_t reg)
733{
734
735 return bus_space_read_4(sc->bt, sc->bh, reg);

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843void t4_os_link_changed(struct adapter *, int, int, int);
844void t4_iterate(void (*)(struct adapter *, void *), void *);
845int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
846int t4_register_an_handler(struct adapter *, an_handler_t);
847int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
848int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
849int begin_synchronized_op(struct adapter *, struct port_info *, int, char *);
850void end_synchronized_op(struct adapter *, int);
863/* One for errors, one for firmware events */
864#define T4_EXTRA_INTR 2
865
866static inline uint32_t
867t4_read_reg(struct adapter *sc, uint32_t reg)
868{
869
870 return bus_space_read_4(sc->bt, sc->bh, reg);

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978void t4_os_link_changed(struct adapter *, int, int, int);
979void t4_iterate(void (*)(struct adapter *, void *), void *);
980int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
981int t4_register_an_handler(struct adapter *, an_handler_t);
982int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
983int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
984int begin_synchronized_op(struct adapter *, struct port_info *, int, char *);
985void end_synchronized_op(struct adapter *, int);
986int update_mac_settings(struct ifnet *, int);
987int adapter_full_init(struct adapter *);
988int adapter_full_uninit(struct adapter *);
989int port_full_init(struct port_info *);
990int port_full_uninit(struct port_info *);
851
991
992#ifdef DEV_NETMAP
993/* t4_netmap.c */
994int create_netmap_ifnet(struct port_info *);
995int destroy_netmap_ifnet(struct port_info *);
996void t4_nm_intr(void *);
997#endif
998
852/* t4_sge.c */
853void t4_sge_modload(void);
854void t4_sge_modunload(void);
855uint64_t t4_sge_extfree_refs(void);
856void t4_init_sge_cpl_handlers(struct adapter *);
857void t4_tweak_chip_settings(struct adapter *);
858int t4_read_chip_settings(struct adapter *);
859int t4_create_dma_tag(struct adapter *);

--- 65 unchanged lines hidden --- 		999/* t4_sge.c */
1000void t4_sge_modload(void);
1001void t4_sge_modunload(void);
1002uint64_t t4_sge_extfree_refs(void);
1003void t4_init_sge_cpl_handlers(struct adapter *);
1004void t4_tweak_chip_settings(struct adapter *);
1005int t4_read_chip_settings(struct adapter *);
1006int t4_create_dma_tag(struct adapter *);

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