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cxgb_common.h (180583) cxgb_common.h (181614)
1/**************************************************************************
2
3Copyright (c) 2007-2008, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

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20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
1/**************************************************************************
2
3Copyright (c) 2007-2008, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

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20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28$FreeBSD: head/sys/dev/cxgb/common/cxgb_common.h 180583 2008-07-18 06:12:31Z kmacy $
28$FreeBSD: head/sys/dev/cxgb/common/cxgb_common.h 181614 2008-08-11 23:01:34Z kmacy $
29
30***************************************************************************/
31#ifndef __CHELSIO_COMMON_H
32#define __CHELSIO_COMMON_H
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_osdep.h>
36#else

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102
103enum {
104 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
105 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
106 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
107};
108
109enum sge_context_type { /* SGE egress context types */
29
30***************************************************************************/
31#ifndef __CHELSIO_COMMON_H
32#define __CHELSIO_COMMON_H
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_osdep.h>
36#else

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102
103enum {
104 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
105 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
106 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
107};
108
109enum sge_context_type { /* SGE egress context types */
110 SGE_CNTXT_RDMA = 0,
111 SGE_CNTXT_ETH = 2,
112 SGE_CNTXT_OFLD = 4,
113 SGE_CNTXT_CTRL = 5
110 SGE_CNTXT_RDMA = 0,
111 SGE_CNTXT_ETH = 2,
112 SGE_CNTXT_OFLD = 4,
113 SGE_CNTXT_CTRL = 5
114};
115
116enum {
117 AN_PKT_SIZE = 32, /* async notification packet size */
118 IMMED_PKT_SIZE = 48 /* packet size for immediate data */
119};
120
121struct sg_ent { /* SGE scatter/gather entry */

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126#ifndef SGE_NUM_GENBITS
127/* Must be 1 or 2 */
128# define SGE_NUM_GENBITS 2
129#endif
130
131#define TX_DESC_FLITS 16U
132#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
133
114};
115
116enum {
117 AN_PKT_SIZE = 32, /* async notification packet size */
118 IMMED_PKT_SIZE = 48 /* packet size for immediate data */
119};
120
121struct sg_ent { /* SGE scatter/gather entry */

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126#ifndef SGE_NUM_GENBITS
127/* Must be 1 or 2 */
128# define SGE_NUM_GENBITS 2
129#endif
130
131#define TX_DESC_FLITS 16U
132#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
133
134#define MAX_PHYINTRS 4
135
134struct cphy;
135
136struct mdio_ops {
137 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
138 int reg_addr, unsigned int *val);
136struct cphy;
137
138struct mdio_ops {
139 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
140 int reg_addr, unsigned int *val);
139 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
141 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
140 int reg_addr, unsigned int val);
141};
142
143struct adapter_info {
144 unsigned char nports0; /* # of ports on channel 0 */
145 unsigned char nports1; /* # of ports on channel 1 */
146 unsigned char phy_base_addr; /* MDIO PHY base address */
147 unsigned char mdien:1;
148 unsigned char mdiinv:1;
149 unsigned int gpio_out; /* GPIO output settings */
142 int reg_addr, unsigned int val);
143};
144
145struct adapter_info {
146 unsigned char nports0; /* # of ports on channel 0 */
147 unsigned char nports1; /* # of ports on channel 1 */
148 unsigned char phy_base_addr; /* MDIO PHY base address */
149 unsigned char mdien:1;
150 unsigned char mdiinv:1;
151 unsigned int gpio_out; /* GPIO output settings */
150 unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */
152 unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */
151 unsigned long caps; /* adapter capabilities */
152 const struct mdio_ops *mdio_ops; /* MDIO operations */
153 const char *desc; /* product description */
154};
155
153 unsigned long caps; /* adapter capabilities */
154 const struct mdio_ops *mdio_ops; /* MDIO operations */
155 const char *desc; /* product description */
156};
157
156struct port_type_info {
157 int (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr,
158 const struct mdio_ops *ops);
159};
160
161struct mc5_stats {
162 unsigned long parity_err;
163 unsigned long active_rgn_full;
164 unsigned long nfa_srch_err;
165 unsigned long unknown_cmd;
166 unsigned long reqq_parity_err;
167 unsigned long dispq_parity_err;
168 unsigned long del_act_empty;

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392 T3_REV_A = 0,
393 T3_REV_B = 2,
394 T3_REV_B2 = 3,
395 T3_REV_C = 4,
396};
397
398struct trace_params {
399 u32 sip;
158struct mc5_stats {
159 unsigned long parity_err;
160 unsigned long active_rgn_full;
161 unsigned long nfa_srch_err;
162 unsigned long unknown_cmd;
163 unsigned long reqq_parity_err;
164 unsigned long dispq_parity_err;
165 unsigned long del_act_empty;

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389 T3_REV_A = 0,
390 T3_REV_B = 2,
391 T3_REV_B2 = 3,
392 T3_REV_C = 4,
393};
394
395struct trace_params {
396 u32 sip;
400 u32 sip_mask;
397 u32 sip_mask;
401 u32 dip;
398 u32 dip;
402 u32 dip_mask;
399 u32 dip_mask;
403 u16 sport;
404 u16 sport_mask;
405 u16 dport;
406 u16 dport_mask;
407 u32 vlan:12;
408 u32 vlan_mask:12;
409 u32 intf:4;
410 u32 intf_mask:4;
411 u8 proto;
412 u8 proto_mask;
413};
414
415struct link_config {
416 unsigned int supported; /* link capabilities */
417 unsigned int advertising; /* advertised capabilities */
400 u16 sport;
401 u16 sport_mask;
402 u16 dport;
403 u16 dport_mask;
404 u32 vlan:12;
405 u32 vlan_mask:12;
406 u32 intf:4;
407 u32 intf_mask:4;
408 u8 proto;
409 u8 proto_mask;
410};
411
412struct link_config {
413 unsigned int supported; /* link capabilities */
414 unsigned int advertising; /* advertised capabilities */
418 unsigned short requested_speed; /* speed user has requested */
415 unsigned short requested_speed; /* speed user has requested */
419 unsigned short speed; /* actual link speed */
416 unsigned short speed; /* actual link speed */
420 unsigned char requested_duplex; /* duplex user has requested */
417 unsigned char requested_duplex; /* duplex user has requested */
421 unsigned char duplex; /* actual link duplex */
422 unsigned char requested_fc; /* flow control user has requested */
423 unsigned char fc; /* actual link flow control */
424 unsigned char autoneg; /* autonegotiating? */
418 unsigned char duplex; /* actual link duplex */
419 unsigned char requested_fc; /* flow control user has requested */
420 unsigned char fc; /* actual link flow control */
421 unsigned char autoneg; /* autonegotiating? */
425 unsigned int link_ok; /* link up? */
422 unsigned int link_ok; /* link up? */
426};
427
428#define SPEED_INVALID 0xffff
429#define DUPLEX_INVALID 0xff
430
431struct mc5 {
432 adapter_t *adapter;
433 unsigned int tcam_size;

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506enum {
507 PHY_LOOPBACK_TX = 1,
508 PHY_LOOPBACK_RX = 2
509};
510
511/* PHY interrupt types */
512enum {
513 cphy_cause_link_change = 1,
423};
424
425#define SPEED_INVALID 0xffff
426#define DUPLEX_INVALID 0xff
427
428struct mc5 {
429 adapter_t *adapter;
430 unsigned int tcam_size;

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503enum {
504 PHY_LOOPBACK_TX = 1,
505 PHY_LOOPBACK_RX = 2
506};
507
508/* PHY interrupt types */
509enum {
510 cphy_cause_link_change = 1,
514 cphy_cause_fifo_error = 2
511 cphy_cause_fifo_error = 2,
512 cphy_cause_module_change = 4,
515};
516
513};
514
515/* PHY module types */
516enum {
517 phy_modtype_none,
518 phy_modtype_sr,
519 phy_modtype_lr,
520 phy_modtype_lrm,
521 phy_modtype_twinax,
522 phy_modtype_twinax_long,
523 phy_modtype_unknown
524};
525
517/* PHY operations */
518struct cphy_ops {
519 int (*reset)(struct cphy *phy, int wait);
520
521 int (*intr_enable)(struct cphy *phy);
522 int (*intr_disable)(struct cphy *phy);
523 int (*intr_clear)(struct cphy *phy);
524 int (*intr_handler)(struct cphy *phy);

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531 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
532 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
533 int *duplex, int *fc);
534 int (*power_down)(struct cphy *phy, int enable);
535};
536
537/* A PHY instance */
538struct cphy {
526/* PHY operations */
527struct cphy_ops {
528 int (*reset)(struct cphy *phy, int wait);
529
530 int (*intr_enable)(struct cphy *phy);
531 int (*intr_disable)(struct cphy *phy);
532 int (*intr_clear)(struct cphy *phy);
533 int (*intr_handler)(struct cphy *phy);

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540 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
541 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
542 int *duplex, int *fc);
543 int (*power_down)(struct cphy *phy, int enable);
544};
545
546/* A PHY instance */
547struct cphy {
539 int addr; /* PHY address */
548 u8 addr; /* PHY address */
549 u8 modtype; /* PHY module type */
550 short priv; /* scratch pad */
540 unsigned int caps; /* PHY capabilities */
541 adapter_t *adapter; /* associated adapter */
542 const char *desc; /* PHY description */
543 unsigned long fifo_errors; /* FIFO over/under-flows */
544 const struct cphy_ops *ops; /* PHY operations */
545 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
546 int reg_addr, unsigned int *val);
547 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
548 int reg_addr, unsigned int val);
549};
550
551/* Convenience MDIO read/write wrappers */
552static inline int mdio_read(struct cphy *phy, int mmd, int reg,
553 unsigned int *valp)
554{
551 unsigned int caps; /* PHY capabilities */
552 adapter_t *adapter; /* associated adapter */
553 const char *desc; /* PHY description */
554 unsigned long fifo_errors; /* FIFO over/under-flows */
555 const struct cphy_ops *ops; /* PHY operations */
556 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
557 int reg_addr, unsigned int *val);
558 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
559 int reg_addr, unsigned int val);
560};
561
562/* Convenience MDIO read/write wrappers */
563static inline int mdio_read(struct cphy *phy, int mmd, int reg,
564 unsigned int *valp)
565{
555 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
566 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
556}
557
558static inline int mdio_write(struct cphy *phy, int mmd, int reg,
559 unsigned int val)
560{
567}
568
569static inline int mdio_write(struct cphy *phy, int mmd, int reg,
570 unsigned int val)
571{
561 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
572 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
562}
563
564/* Convenience initializer */
565static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
566 int phy_addr, struct cphy_ops *phy_ops,
567 const struct mdio_ops *mdio_ops, unsigned int caps,
568 const char *desc)
569{
573}
574
575/* Convenience initializer */
576static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
577 int phy_addr, struct cphy_ops *phy_ops,
578 const struct mdio_ops *mdio_ops, unsigned int caps,
579 const char *desc)
580{
570 phy->adapter = adapter;
571 phy->addr = phy_addr;
581 phy->addr = (u8)phy_addr;
572 phy->caps = caps;
582 phy->caps = caps;
583 phy->adapter = adapter;
573 phy->desc = desc;
574 phy->ops = phy_ops;
575 if (mdio_ops) {
576 phy->mdio_read = mdio_ops->read;
577 phy->mdio_write = mdio_ops->write;
578 }
579}
580

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614
615static inline int is_10G(const adapter_t *adap)
616{
617 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
618}
619
620static inline int is_offload(const adapter_t *adap)
621{
584 phy->desc = desc;
585 phy->ops = phy_ops;
586 if (mdio_ops) {
587 phy->mdio_read = mdio_ops->read;
588 phy->mdio_write = mdio_ops->write;
589 }
590}
591

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625
626static inline int is_10G(const adapter_t *adap)
627{
628 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
629}
630
631static inline int is_offload(const adapter_t *adap)
632{
622#ifdef CONFIG_CHELSIO_T3_CORE
633#if defined(CONFIG_CHELSIO_T3_CORE)
623 return adap->params.offload;
624#else
625 return 0;
626#endif
627}
628
629static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
630{

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689int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
690int t3_get_fw_version(adapter_t *adapter, u32 *vers);
691int t3_check_fw_version(adapter_t *adapter, int *must_load);
692int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size);
693int t3_init_hw(adapter_t *adapter, u32 fw_params);
694void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
695void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
696int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
634 return adap->params.offload;
635#else
636 return 0;
637#endif
638}
639
640static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
641{

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700int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
701int t3_get_fw_version(adapter_t *adapter, u32 *vers);
702int t3_check_fw_version(adapter_t *adapter, int *must_load);
703int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size);
704int t3_init_hw(adapter_t *adapter, u32 fw_params);
705void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
706void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
707int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
708int t3_reinit_adapter(adapter_t *adap);
697void t3_led_ready(adapter_t *adapter);
698void t3_fatal_err(adapter_t *adapter);
699void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
700void t3_enable_filters(adapter_t *adap);
701void t3_tp_set_offload_mode(adapter_t *adap, int enable);
702void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
703 const u16 *rspq);
704int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);

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732int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
733 u32 *buf);
734
735#ifdef CONFIG_CHELSIO_T3_CORE
736int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
737void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
738void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
739void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
709void t3_led_ready(adapter_t *adapter);
710void t3_fatal_err(adapter_t *adapter);
711void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
712void t3_enable_filters(adapter_t *adap);
713void t3_tp_set_offload_mode(adapter_t *adap, int enable);
714void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
715 const u16 *rspq);
716int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);

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744int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
745 u32 *buf);
746
747#ifdef CONFIG_CHELSIO_T3_CORE
748int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
749void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
750void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
751void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
740 unsigned short alpha[NCCTRL_WIN],
752 unsigned short alpha[NCCTRL_WIN],
741 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
742void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
743void t3_get_cong_cntl_tab(adapter_t *adap,
744 unsigned short incr[NMTUS][NCCTRL_WIN]);
745void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
746 int filter_index, int invert, int enable);
747int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
748int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg);

--- 60 unchanged lines hidden --- 		753 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
754void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
755void t3_get_cong_cntl_tab(adapter_t *adap,
756 unsigned short incr[NMTUS][NCCTRL_WIN]);
757void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
758 int filter_index, int invert, int enable);
759int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
760int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg);

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