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cxgb_common.h (177340) cxgb_common.h (180583)
1/**************************************************************************
2
3Copyright (c) 2007-2008, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

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20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
1/**************************************************************************
2
3Copyright (c) 2007-2008, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

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20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28$FreeBSD: head/sys/dev/cxgb/common/cxgb_common.h 177340 2008-03-18 03:55:12Z kmacy $
28$FreeBSD: head/sys/dev/cxgb/common/cxgb_common.h 180583 2008-07-18 06:12:31Z kmacy $
29
30***************************************************************************/
31#ifndef __CHELSIO_COMMON_H
32#define __CHELSIO_COMMON_H
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_osdep.h>
36#else

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42 EEPROMSIZE = 8192, /* Serial EEPROM size */
43 SERNUM_LEN = 16, /* Serial # length */
44 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
45 TCB_SIZE = 128, /* TCB size */
46 NMTUS = 16, /* size of MTU table */
47 NCCTRL_WIN = 32, /* # of congestion control windows */
48 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
49 PROTO_SRAM_LINES = 128, /* size of protocol sram */
29
30***************************************************************************/
31#ifndef __CHELSIO_COMMON_H
32#define __CHELSIO_COMMON_H
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_osdep.h>
36#else

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42 EEPROMSIZE = 8192, /* Serial EEPROM size */
43 SERNUM_LEN = 16, /* Serial # length */
44 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
45 TCB_SIZE = 128, /* TCB size */
46 NMTUS = 16, /* size of MTU table */
47 NCCTRL_WIN = 32, /* # of congestion control windows */
48 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
49 PROTO_SRAM_LINES = 128, /* size of protocol sram */
50 MAX_NPORTS = 4,
51 TP_TMR_RES = 200,
52 TP_SRAM_OFFSET = 4096, /* TP SRAM content offset in eeprom */
53 TP_SRAM_LEN = 2112, /* TP SRAM content offset in eeprom */
50 EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */
54};
55
56#define MAX_RX_COALESCING_LEN 12288U
57
58enum {
59 PAUSE_RX = 1 << 0,
60 PAUSE_TX = 1 << 1,
61 PAUSE_AUTONEG = 1 << 2

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117};
118
119enum {
120 AN_PKT_SIZE = 32, /* async notification packet size */
121 IMMED_PKT_SIZE = 48 /* packet size for immediate data */
122};
123
124struct sg_ent { /* SGE scatter/gather entry */
51};
52
53#define MAX_RX_COALESCING_LEN 12288U
54
55enum {
56 PAUSE_RX = 1 << 0,
57 PAUSE_TX = 1 << 1,
58 PAUSE_AUTONEG = 1 << 2

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114};
115
116enum {
117 AN_PKT_SIZE = 32, /* async notification packet size */
118 IMMED_PKT_SIZE = 48 /* packet size for immediate data */
119};
120
121struct sg_ent { /* SGE scatter/gather entry */
125 u32 len[2];
126 u64 addr[2];
122 __be32 len[2];
123 __be64 addr[2];
127};
128
129#ifndef SGE_NUM_GENBITS
130/* Must be 1 or 2 */
131# define SGE_NUM_GENBITS 2
132#endif
133
134#define TX_DESC_FLITS 16U

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145
146struct adapter_info {
147 unsigned char nports0; /* # of ports on channel 0 */
148 unsigned char nports1; /* # of ports on channel 1 */
149 unsigned char phy_base_addr; /* MDIO PHY base address */
150 unsigned char mdien:1;
151 unsigned char mdiinv:1;
152 unsigned int gpio_out; /* GPIO output settings */
124};
125
126#ifndef SGE_NUM_GENBITS
127/* Must be 1 or 2 */
128# define SGE_NUM_GENBITS 2
129#endif
130
131#define TX_DESC_FLITS 16U

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142
143struct adapter_info {
144 unsigned char nports0; /* # of ports on channel 0 */
145 unsigned char nports1; /* # of ports on channel 1 */
146 unsigned char phy_base_addr; /* MDIO PHY base address */
147 unsigned char mdien:1;
148 unsigned char mdiinv:1;
149 unsigned int gpio_out; /* GPIO output settings */
153 unsigned int gpio_intr; /* GPIO IRQ enable mask */
150 unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */
154 unsigned long caps; /* adapter capabilities */
155 const struct mdio_ops *mdio_ops; /* MDIO operations */
156 const char *desc; /* product description */
157};
158
159struct port_type_info {
160 int (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr,
161 const struct mdio_ops *ops);
151 unsigned long caps; /* adapter capabilities */
152 const struct mdio_ops *mdio_ops; /* MDIO operations */
153 const char *desc; /* product description */
154};
155
156struct port_type_info {
157 int (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr,
158 const struct mdio_ops *ops);
162
163
164};
165
166struct mc5_stats {
167 unsigned long parity_err;
168 unsigned long active_rgn_full;
169 unsigned long nfa_srch_err;
170 unsigned long unknown_cmd;
171 unsigned long reqq_parity_err;

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302 unsigned int ntimer_qs; /* # of timer queues */
303 unsigned int tre; /* log2 of core clocks per TP tick */
304 unsigned int dack_re; /* DACK timer resolution */
305};
306
307struct qset_params { /* SGE queue set parameters */
308 unsigned int polling; /* polling/interrupt service for rspq */
309 unsigned int lro; /* large receive offload */
159};
160
161struct mc5_stats {
162 unsigned long parity_err;
163 unsigned long active_rgn_full;
164 unsigned long nfa_srch_err;
165 unsigned long unknown_cmd;
166 unsigned long reqq_parity_err;

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297 unsigned int ntimer_qs; /* # of timer queues */
298 unsigned int tre; /* log2 of core clocks per TP tick */
299 unsigned int dack_re; /* DACK timer resolution */
300};
301
302struct qset_params { /* SGE queue set parameters */
303 unsigned int polling; /* polling/interrupt service for rspq */
304 unsigned int lro; /* large receive offload */
310 unsigned int coalesce_nsecs; /* irq coalescing timer */
305 unsigned int coalesce_usecs; /* irq coalescing timer */
311 unsigned int rspq_size; /* # of entries in response queue */
312 unsigned int fl_size; /* # of entries in regular free list */
313 unsigned int jumbo_size; /* # of entries in jumbo free list */
314 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
315 unsigned int cong_thres; /* FL congestion threshold */
316 unsigned int vector; /* Interrupt (line or vector) number */
317};
318

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481};
482
483enum {
484 MAC_DIRECTION_RX = 1,
485 MAC_DIRECTION_TX = 2,
486 MAC_RXFIFO_SIZE = 32768
487};
488
306 unsigned int rspq_size; /* # of entries in response queue */
307 unsigned int fl_size; /* # of entries in regular free list */
308 unsigned int jumbo_size; /* # of entries in jumbo free list */
309 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
310 unsigned int cong_thres; /* FL congestion threshold */
311 unsigned int vector; /* Interrupt (line or vector) number */
312};
313

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476};
477
478enum {
479 MAC_DIRECTION_RX = 1,
480 MAC_DIRECTION_TX = 2,
481 MAC_RXFIFO_SIZE = 32768
482};
483
489/* IEEE 802.3ae specified MDIO devices */
484/* IEEE 802.3 specified MDIO devices */
490enum {
491 MDIO_DEV_PMA_PMD = 1,
492 MDIO_DEV_WIS = 2,
493 MDIO_DEV_PCS = 3,
485enum {
486 MDIO_DEV_PMA_PMD = 1,
487 MDIO_DEV_WIS = 2,
488 MDIO_DEV_PCS = 3,
494 MDIO_DEV_XGXS = 4
489 MDIO_DEV_XGXS = 4,
490 MDIO_DEV_ANEG = 7,
491 MDIO_DEV_VEND1 = 30,
492 MDIO_DEV_VEND2 = 31
495};
496
493};
494
495/* LASI control and status registers */
496enum {
497 RX_ALARM_CTRL = 0x9000,
498 TX_ALARM_CTRL = 0x9001,
499 LASI_CTRL = 0x9002,
500 RX_ALARM_STAT = 0x9003,
501 TX_ALARM_STAT = 0x9004,
502 LASI_STAT = 0x9005
503};
504
497/* PHY loopback direction */
498enum {
499 PHY_LOOPBACK_TX = 1,
500 PHY_LOOPBACK_RX = 2
501};
502
503/* PHY interrupt types */
504enum {

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551 unsigned int val)
552{
553 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
554}
555
556/* Convenience initializer */
557static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
558 int phy_addr, struct cphy_ops *phy_ops,
505/* PHY loopback direction */
506enum {
507 PHY_LOOPBACK_TX = 1,
508 PHY_LOOPBACK_RX = 2
509};
510
511/* PHY interrupt types */
512enum {

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559 unsigned int val)
560{
561 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
562}
563
564/* Convenience initializer */
565static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
566 int phy_addr, struct cphy_ops *phy_ops,
559 const struct mdio_ops *mdio_ops, unsigned int caps,
560 const char *desc)
567 const struct mdio_ops *mdio_ops, unsigned int caps,
568 const char *desc)
561{
562 phy->adapter = adapter;
563 phy->addr = phy_addr;
564 phy->caps = caps;
565 phy->desc = desc;
566 phy->ops = phy_ops;
567 if (mdio_ops) {
568 phy->mdio_read = mdio_ops->read;

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646 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
647 delay, NULL);
648}
649
650int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
651 unsigned int set);
652int t3_phy_reset(struct cphy *phy, int mmd, int wait);
653int t3_phy_advertise(struct cphy *phy, unsigned int advert);
569{
570 phy->adapter = adapter;
571 phy->addr = phy_addr;
572 phy->caps = caps;
573 phy->desc = desc;
574 phy->ops = phy_ops;
575 if (mdio_ops) {
576 phy->mdio_read = mdio_ops->read;

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654 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
655 delay, NULL);
656}
657
658int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
659 unsigned int set);
660int t3_phy_reset(struct cphy *phy, int mmd, int wait);
661int t3_phy_advertise(struct cphy *phy, unsigned int advert);
662int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);
654int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
663int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
664int t3_phy_lasi_intr_enable(struct cphy *phy);
665int t3_phy_lasi_intr_disable(struct cphy *phy);
666int t3_phy_lasi_intr_clear(struct cphy *phy);
667int t3_phy_lasi_intr_handler(struct cphy *phy);
655
656void t3_intr_enable(adapter_t *adapter);
657void t3_intr_disable(adapter_t *adapter);
658void t3_intr_clear(adapter_t *adapter);
659void t3_port_intr_enable(adapter_t *adapter, int idx);
660void t3_port_intr_disable(adapter_t *adapter, int idx);
661void t3_port_intr_clear(adapter_t *adapter, int idx);
662int t3_slow_intr_handler(adapter_t *adapter);

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668int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
669int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
670int t3_seeprom_wp(adapter_t *adapter, int enable);
671int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
672 u32 *data, int byte_oriented);
673int t3_get_tp_version(adapter_t *adapter, u32 *vers);
674int t3_check_tpsram_version(adapter_t *adapter, int *must_load);
675int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
668
669void t3_intr_enable(adapter_t *adapter);
670void t3_intr_disable(adapter_t *adapter);
671void t3_intr_clear(adapter_t *adapter);
672void t3_port_intr_enable(adapter_t *adapter, int idx);
673void t3_port_intr_disable(adapter_t *adapter, int idx);
674void t3_port_intr_clear(adapter_t *adapter, int idx);
675int t3_slow_intr_handler(adapter_t *adapter);

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681int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
682int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
683int t3_seeprom_wp(adapter_t *adapter, int enable);
684int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
685 u32 *data, int byte_oriented);
686int t3_get_tp_version(adapter_t *adapter, u32 *vers);
687int t3_check_tpsram_version(adapter_t *adapter, int *must_load);
688int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
676int t3_load_fw(adapter_t *adapter, const const u8 *fw_data, unsigned int size);
677int t3_load_boot(adapter_t *adapter, u8 *boot_data, unsigned int size);
689int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
678int t3_get_fw_version(adapter_t *adapter, u32 *vers);
679int t3_check_fw_version(adapter_t *adapter, int *must_load);
690int t3_get_fw_version(adapter_t *adapter, u32 *vers);
691int t3_check_fw_version(adapter_t *adapter, int *must_load);
692int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size);
680int t3_init_hw(adapter_t *adapter, u32 fw_params);
681void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
682void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
683int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
684void t3_led_ready(adapter_t *adapter);
685void t3_fatal_err(adapter_t *adapter);
686void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
693int t3_init_hw(adapter_t *adapter, u32 fw_params);
694void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
695void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
696int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
697void t3_led_ready(adapter_t *adapter);
698void t3_fatal_err(adapter_t *adapter);
699void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
687void t3_tp_set_offload_mode(adapter_t *adap, int enable);
688void t3_enable_filters(adapter_t *adap);
700void t3_enable_filters(adapter_t *adap);
701void t3_tp_set_offload_mode(adapter_t *adap, int enable);
689void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
690 const u16 *rspq);
691int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
692int t3_set_proto_sram(adapter_t *adap, const u8 *data);
693int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
694void t3_port_failover(adapter_t *adapter, int port);
695void t3_failover_done(adapter_t *adapter, int port);
696void t3_failover_clear(adapter_t *adapter);

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714
715void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode);
716int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
717 unsigned int nroutes);
718void t3_mc5_intr_handler(struct mc5 *mc5);
719int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
720 u32 *buf);
721
702void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
703 const u16 *rspq);
704int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
705int t3_set_proto_sram(adapter_t *adap, const u8 *data);
706int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
707void t3_port_failover(adapter_t *adapter, int port);
708void t3_failover_done(adapter_t *adapter, int port);
709void t3_failover_clear(adapter_t *adapter);

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727
728void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode);
729int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
730 unsigned int nroutes);
731void t3_mc5_intr_handler(struct mc5 *mc5);
732int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
733 u32 *buf);
734
722#if defined(CONFIG_CHELSIO_T3_CORE)
735#ifdef CONFIG_CHELSIO_T3_CORE
723int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
724void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
725void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
726void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
727 unsigned short alpha[NCCTRL_WIN],
728 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
729void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
730void t3_get_cong_cntl_tab(adapter_t *adap,

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769int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
770int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
771int t3_vsc7323_init(adapter_t *adap, int nports);
772int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
773int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
774int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
775int t3_vsc7323_enable(adapter_t *adap, int port, int which);
776int t3_vsc7323_disable(adapter_t *adap, int port, int which);
736int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
737void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
738void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
739void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
740 unsigned short alpha[NCCTRL_WIN],
741 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
742void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
743void t3_get_cong_cntl_tab(adapter_t *adap,

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782int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
783int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
784int t3_vsc7323_init(adapter_t *adap, int nports);
785int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
786int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
787int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
788int t3_vsc7323_enable(adapter_t *adap, int port, int which);
789int t3_vsc7323_disable(adapter_t *adap, int port, int which);
777
778int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);
779
780const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
781
782int t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
790const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
791
792int t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
783 const struct mdio_ops *mdio_ops);
793 const struct mdio_ops *mdio_ops);
784int t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
794int t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
785 const struct mdio_ops *mdio_ops);
795 const struct mdio_ops *mdio_ops);
786int t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
796int t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
787 const struct mdio_ops *mdio_ops);
797 const struct mdio_ops *mdio_ops);
788int t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
798int t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
789 const struct mdio_ops *mdio_ops);
790int t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
791 const struct mdio_ops *mdio_ops);
799 const struct mdio_ops *mdio_ops);
800int t3_ael2005_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
801 const struct mdio_ops *mdio_ops);
802int t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
803 const struct mdio_ops *mdio_ops);
804int t3_tn1010_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
805 const struct mdio_ops *mdio_ops);
792int t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
806int t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
793 const struct mdio_ops *mdio_ops);
807 const struct mdio_ops *mdio_ops);
794#endif /* __CHELSIO_COMMON_H */
808#endif /* __CHELSIO_COMMON_H */