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tau32-ddk.h (154899) tau32-ddk.h (156143)
1/*
2 * DDK (Driver Development Kit) for Cronyx Tau32-PCI adapter.
3 *
1/*
2 * DDK (Driver Development Kit) for Cronyx Tau32-PCI adapter.
3 *
4 * Copyright (C) 2003-2005 Cronyx Engineering, http://www.cronyx.ru
4 * Copyright (C) 2003-2006 Cronyx Engineering, http://www.cronyx.ru
5 * All rights reserved.
6 *
7 * Author: Leo Yuriev <ly@cronyx.ru>, http://leo.yuriev.ru
8 *
5 * All rights reserved.
6 *
7 * Author: Leo Yuriev <ly@cronyx.ru>, http://leo.yuriev.ru
8 *
9 * $Cronyx: tau32-ddk.h,v 1.6 2005/07/15 15:01:26 rik Exp $
10 * $FreeBSD: head/sys/dev/ce/tau32-ddk.h 154899 2006-01-27 09:02:09Z rik $
9 * $Cronyx: tau32-ddk.h,v 1.2 2006/02/01 09:14:40 ly Exp $
10 * $Rik: tau32-ddk.h,v 1.7 2006/02/28 22:33:29 rik Exp $
11 * $FreeBSD: head/sys/dev/ce/tau32-ddk.h 156143 2006-03-01 09:50:20Z rik $
11 */
12
13#if defined(__GNUC__) || defined(__TURBOC__)
14# ifndef __int8
15# define __int8 char
16# endif
17# ifndef __int16
18# define __int16 short
19# endif
20# ifndef __int32
21# define __int32 long
22# endif
23# ifndef __int64
24# define __int64 long long
25# endif
26#endif
27
28#if !defined(BOOLEAN) && !defined(_NTDDK_)
29# define BOOLEAN int
30#endif
31
32#if defined(__GNUC__) && !defined(__stdcall)
33# define __stdcall __attribute__((stdcall))
34#endif
35
36#if defined(__GNUC__) && !defined(__cdecl)
37# define __cdecl __attribute__((cdecl))
38#endif
39
40#ifndef TAU32_CALLBACK_TYPE
41# if defined(__WINDOWS__) || defined(_MSC_VER) || defined(WIN32) || defined(WIN64)
42# define TAU32_CALLBACK_TYPE __stdcall
43# else
44# define TAU32_CALLBACK_TYPE __cdecl
45# endif
46#endif
47
48#ifndef TAU32_CALL_TYPE
49# if defined(__WINDOWS__) || defined(_MSC_VER) || defined(WIN32) || defined(WIN64)
50# define TAU32_CALL_TYPE __stdcall
51# else
52# define TAU32_CALL_TYPE __cdecl
53# endif
54#endif
55
56#ifndef PCI_PHYSICAL_ADDRESS
57# ifdef PCI64
58# error PCI64 currently is not supported
59# else
60# define PCI_PHYSICAL_ADDRESS unsigned __int32
61# endif
62#endif
63
64#define TAU32_PCI_VENDOR_ID 0x110A
65#define TAU32_PCI_DEVICE_ID 0x2101
66#define TAU32_PCI_IO_BAR1_SIZE 0x0100
67#define TAU32_PCI_RESET_ADDRESS 0x004C
68#define TAU32_PCI_RESET_ON 0xF00F0000ul /*0xFFFFFFFFul */
69#define TAU32_PCI_RESET_OFF 0
70#define TAU32_PCI_RESET_LENGTH 4
71
72/* TAU32_MODELS */
73#define TAU32_ERROR (-1)
74#define TAU32_UNKNOWN 0
75#define TAU32_BASE 1
76#define TAU32_LITE 2
77#define TAU32_ADPCM 3
78
79/* TAU32_INIT_ERRORS */
80#define TAU32_IE_OK 0x0000u
81#define TAU32_IE_FIRMWARE 0x0001u
82#define TAU32_IE_MODEL 0x0002u
83#define TAU32_IE_E1_A 0x0004u
84#define TAU32_IE_E1_B 0x0008u
85#define TAU32_IE_INTERNAL_BUS 0x0010u
86#define TAU32_IE_HDLC 0x0020u
87#define TAU32_IE_ADPCM 0x0040u
88#define TAU32_IE_CLOCK 0x0080u
89#define TAU32_IE_DXC 0x0100u
90#define TAU32_IE_XIRQ 0x0200u
91
92/* TAU32_INTERFACES */
93#define TAU32_E1_ALL (-1)
94#define TAU32_E1_A 0
95#define TAU32_E1_B 1
96
97/* TAU32_LIMITS */
98#define TAU32_CHANNELS 32
99#define TAU32_TIMESLOTS 32
100#define TAU32_MAX_INTERFACES 2
101#define TAU32_MTU 8184
102#define TAU32_FLAT_MTU 4096
103#define TAU32_IO_QUEUE 4
104#define TAU32_IO_QUEUE_BYTES 128
105#define TAU32_MAX_REQUESTS 512
106#define TAU32_MAX_BUFFERS 256
107#define TAU32_FIFO_SIZE 256
108
109/* TAU32_REQUEST_COMMANDS */
110#define TAU32_Tx_Start 0x0001u
111#define TAU32_Tx_Stop 0x0002u
112/*#define TAU32_Tx_Flush 0x0004u // yet not implemented */
113#define TAU32_Tx_Data 0x0008u
114#define TAU32_Rx_Start 0x0010u
115#define TAU32_Rx_Stop 0x0020u
116#define TAU32_Rx_Data 0x0080u
117#define TAU32_Configure_Channel 0x0100u
118#define TAU32_Timeslots_Complete 0x0200u
119#define TAU32_Timeslots_Map 0x0400u
120#define TAU32_Timeslots_Channel 0x0800u
121#define TAU32_ConfigureDigitalLoop 0x1000u
122#define TAU32_Configure_Commit 0x2000u
123#define TAU32_Tx_FrameEnd 0x4000u
124#define TAU32_Tx_NoCrc 0x8000u
125#define TAU32_Configure_E1 0x0040u
126
127/* TAU32_ERRORS */
128#define TAU32_NOERROR 0x000000ul
129#define TAU32_SUCCESSFUL 0x000000ul
130#define TAU32_ERROR_ALLOCATION 0x000001ul /* not enough tx/rx descriptors */
131#define TAU32_ERROR_BUS 0x000002ul /* PEB could not access to host memory by PCI bus for load/store information */
132#define TAU32_ERROR_FAIL 0x000004ul /* PEB action request failed */
133#define TAU32_ERROR_TIMEOUT 0x000008ul /* PEB action request timeout */
134#define TAU32_ERROR_CANCELLED 0x000010ul
135#define TAU32_ERROR_TX_UNDERFLOW 0x000020ul /* transmission underflow */
136#define TAU32_ERROR_TX_PROTOCOL 0x000040ul /* reserved */
137#define TAU32_ERROR_RX_OVERFLOW 0x000080ul
138#define TAU32_ERROR_RX_ABORT 0x000100ul
139#define TAU32_ERROR_RX_CRC 0x000200ul
140#define TAU32_ERROR_RX_SHORT 0x000400ul
141#define TAU32_ERROR_RX_SYNC 0x000800ul
142#define TAU32_ERROR_RX_FRAME 0x001000ul
143#define TAU32_ERROR_RX_LONG 0x002000ul
144#define TAU32_ERROR_RX_SPLIT 0x004000ul /* frame has splitted between two requests due rx-gap allocation */
145#define TAU32_ERROR_RX_UNFIT 0x008000ul /* frame can't be fit into request buffer */
146#define TAU32_ERROR_TSP 0x010000ul
147#define TAU32_ERROR_RSP 0x020000ul
148#define TAU32_ERROR_INT_OVER_TX 0x040000ul
149#define TAU32_ERROR_INT_OVER_RX 0x080000ul
150#define TAU32_ERROR_INT_STORM 0x100000ul
151#define TAU32_ERROR_INT_E1LOST 0x200000ul
152#define TAU32_WARN_TX_JUMP 0x400000ul
153#define TAU32_WARN_RX_JUMP 0x800000ul
154
155/* TAU32_CHANNEL_MODES */
156#define TAU32_HDLC 0
157#define TAU32_V110_x30 1
158#define TAU32_TMA 2
159#define TAU32_TMB 3
160#define TAU32_TMR 4
161
162/* TAU32_SYNC_MODES */
163#define TAU32_SYNC_INTERNAL 0
164#define TAU32_SYNC_RCV_A 1
165#define TAU32_SYNC_RCV_B 2
166#define TAU32_SYNC_LYGEN 3
167#define TAU32_LYGEN_RESET 0
168
169/* TAU32_CHANNEL_CONFIG_BITS */
170#define TAU32_channel_mode_mask 0x0000000Ful
171#define TAU32_data_inversion 0x00000010ul
172#define TAU32_fr_rx_splitcheck 0x00000020ul
173#define TAU32_fr_rx_fitcheck 0x00000040ul
174#define TAU32_fr_tx_auto 0x00000080ul
175#define TAU32_hdlc_crc32 0x00000100ul
176#define TAU32_hdlc_adjustment 0x00000200ul
177#define TAU32_hdlc_interframe_fill 0x00000400ul
178#define TAU32_hdlc_nocrc 0x00000800ul
179#define TAU32_tma_flag_filtering 0x00001000ul
180#define TAU32_tma_nopack 0x00002000ul
181#define TAU32_tma_flags_mask 0x00FF0000ul
182#define TAU32_tma_flags_shift 16u
183#define TAU32_v110_x30_tr_mask 0x03000000ul
184#define TAU32_v110_x30_tr_shift 24u
185
186typedef struct tag_TAU32_TimeslotAssignment
187{
188 unsigned __int8 TxChannel, RxChannel;
189 unsigned __int8 TxFillmask, RxFillmask;
190} TAU32_TimeslotAssignment;
191
192#define TAU32_CROSS_WIDTH 96
193#define TAU32_CROSS_OFF 127
194typedef unsigned __int8 TAU32_CrossMatrix[TAU32_CROSS_WIDTH];
195
196/* TAU32_INTERFACE_CONFIG_BITS */
197#define TAU32_LineOff (0ul << 0)
198#define TAU32_LineLoopInt (1ul << 0)
199#define TAU32_LineLoopExt (2ul << 0)
200#define TAU32_LineNormal (3ul << 0)
201#define TAU32_LineAIS (4ul << 0)
202#define TAU32_line_mode_mask 0x0000000Ful
203#define TAU32_unframed_64 (0ul << 4)
204#define TAU32_unframed_128 (1ul << 4)
205#define TAU32_unframed_256 (2ul << 4)
206#define TAU32_unframed_512 (3ul << 4)
207#define TAU32_unframed_1024 (4ul << 4)
208#define TAU32_unframed_2048 (5ul << 4)
209#define TAU32_unframed TAU32_unframed_2048
210#define TAU32_framed_no_cas (6ul << 4)
211#define TAU32_framed_cas_set (7ul << 4)
12 */
13
14#if defined(__GNUC__) || defined(__TURBOC__)
15# ifndef __int8
16# define __int8 char
17# endif
18# ifndef __int16
19# define __int16 short
20# endif
21# ifndef __int32
22# define __int32 long
23# endif
24# ifndef __int64
25# define __int64 long long
26# endif
27#endif
28
29#if !defined(BOOLEAN) && !defined(_NTDDK_)
30# define BOOLEAN int
31#endif
32
33#if defined(__GNUC__) && !defined(__stdcall)
34# define __stdcall __attribute__((stdcall))
35#endif
36
37#if defined(__GNUC__) && !defined(__cdecl)
38# define __cdecl __attribute__((cdecl))
39#endif
40
41#ifndef TAU32_CALLBACK_TYPE
42# if defined(__WINDOWS__) || defined(_MSC_VER) || defined(WIN32) || defined(WIN64)
43# define TAU32_CALLBACK_TYPE __stdcall
44# else
45# define TAU32_CALLBACK_TYPE __cdecl
46# endif
47#endif
48
49#ifndef TAU32_CALL_TYPE
50# if defined(__WINDOWS__) || defined(_MSC_VER) || defined(WIN32) || defined(WIN64)
51# define TAU32_CALL_TYPE __stdcall
52# else
53# define TAU32_CALL_TYPE __cdecl
54# endif
55#endif
56
57#ifndef PCI_PHYSICAL_ADDRESS
58# ifdef PCI64
59# error PCI64 currently is not supported
60# else
61# define PCI_PHYSICAL_ADDRESS unsigned __int32
62# endif
63#endif
64
65#define TAU32_PCI_VENDOR_ID 0x110A
66#define TAU32_PCI_DEVICE_ID 0x2101
67#define TAU32_PCI_IO_BAR1_SIZE 0x0100
68#define TAU32_PCI_RESET_ADDRESS 0x004C
69#define TAU32_PCI_RESET_ON 0xF00F0000ul /*0xFFFFFFFFul */
70#define TAU32_PCI_RESET_OFF 0
71#define TAU32_PCI_RESET_LENGTH 4
72
73/* TAU32_MODELS */
74#define TAU32_ERROR (-1)
75#define TAU32_UNKNOWN 0
76#define TAU32_BASE 1
77#define TAU32_LITE 2
78#define TAU32_ADPCM 3
79
80/* TAU32_INIT_ERRORS */
81#define TAU32_IE_OK 0x0000u
82#define TAU32_IE_FIRMWARE 0x0001u
83#define TAU32_IE_MODEL 0x0002u
84#define TAU32_IE_E1_A 0x0004u
85#define TAU32_IE_E1_B 0x0008u
86#define TAU32_IE_INTERNAL_BUS 0x0010u
87#define TAU32_IE_HDLC 0x0020u
88#define TAU32_IE_ADPCM 0x0040u
89#define TAU32_IE_CLOCK 0x0080u
90#define TAU32_IE_DXC 0x0100u
91#define TAU32_IE_XIRQ 0x0200u
92
93/* TAU32_INTERFACES */
94#define TAU32_E1_ALL (-1)
95#define TAU32_E1_A 0
96#define TAU32_E1_B 1
97
98/* TAU32_LIMITS */
99#define TAU32_CHANNELS 32
100#define TAU32_TIMESLOTS 32
101#define TAU32_MAX_INTERFACES 2
102#define TAU32_MTU 8184
103#define TAU32_FLAT_MTU 4096
104#define TAU32_IO_QUEUE 4
105#define TAU32_IO_QUEUE_BYTES 128
106#define TAU32_MAX_REQUESTS 512
107#define TAU32_MAX_BUFFERS 256
108#define TAU32_FIFO_SIZE 256
109
110/* TAU32_REQUEST_COMMANDS */
111#define TAU32_Tx_Start 0x0001u
112#define TAU32_Tx_Stop 0x0002u
113/*#define TAU32_Tx_Flush 0x0004u // yet not implemented */
114#define TAU32_Tx_Data 0x0008u
115#define TAU32_Rx_Start 0x0010u
116#define TAU32_Rx_Stop 0x0020u
117#define TAU32_Rx_Data 0x0080u
118#define TAU32_Configure_Channel 0x0100u
119#define TAU32_Timeslots_Complete 0x0200u
120#define TAU32_Timeslots_Map 0x0400u
121#define TAU32_Timeslots_Channel 0x0800u
122#define TAU32_ConfigureDigitalLoop 0x1000u
123#define TAU32_Configure_Commit 0x2000u
124#define TAU32_Tx_FrameEnd 0x4000u
125#define TAU32_Tx_NoCrc 0x8000u
126#define TAU32_Configure_E1 0x0040u
127
128/* TAU32_ERRORS */
129#define TAU32_NOERROR 0x000000ul
130#define TAU32_SUCCESSFUL 0x000000ul
131#define TAU32_ERROR_ALLOCATION 0x000001ul /* not enough tx/rx descriptors */
132#define TAU32_ERROR_BUS 0x000002ul /* PEB could not access to host memory by PCI bus for load/store information */
133#define TAU32_ERROR_FAIL 0x000004ul /* PEB action request failed */
134#define TAU32_ERROR_TIMEOUT 0x000008ul /* PEB action request timeout */
135#define TAU32_ERROR_CANCELLED 0x000010ul
136#define TAU32_ERROR_TX_UNDERFLOW 0x000020ul /* transmission underflow */
137#define TAU32_ERROR_TX_PROTOCOL 0x000040ul /* reserved */
138#define TAU32_ERROR_RX_OVERFLOW 0x000080ul
139#define TAU32_ERROR_RX_ABORT 0x000100ul
140#define TAU32_ERROR_RX_CRC 0x000200ul
141#define TAU32_ERROR_RX_SHORT 0x000400ul
142#define TAU32_ERROR_RX_SYNC 0x000800ul
143#define TAU32_ERROR_RX_FRAME 0x001000ul
144#define TAU32_ERROR_RX_LONG 0x002000ul
145#define TAU32_ERROR_RX_SPLIT 0x004000ul /* frame has splitted between two requests due rx-gap allocation */
146#define TAU32_ERROR_RX_UNFIT 0x008000ul /* frame can't be fit into request buffer */
147#define TAU32_ERROR_TSP 0x010000ul
148#define TAU32_ERROR_RSP 0x020000ul
149#define TAU32_ERROR_INT_OVER_TX 0x040000ul
150#define TAU32_ERROR_INT_OVER_RX 0x080000ul
151#define TAU32_ERROR_INT_STORM 0x100000ul
152#define TAU32_ERROR_INT_E1LOST 0x200000ul
153#define TAU32_WARN_TX_JUMP 0x400000ul
154#define TAU32_WARN_RX_JUMP 0x800000ul
155
156/* TAU32_CHANNEL_MODES */
157#define TAU32_HDLC 0
158#define TAU32_V110_x30 1
159#define TAU32_TMA 2
160#define TAU32_TMB 3
161#define TAU32_TMR 4
162
163/* TAU32_SYNC_MODES */
164#define TAU32_SYNC_INTERNAL 0
165#define TAU32_SYNC_RCV_A 1
166#define TAU32_SYNC_RCV_B 2
167#define TAU32_SYNC_LYGEN 3
168#define TAU32_LYGEN_RESET 0
169
170/* TAU32_CHANNEL_CONFIG_BITS */
171#define TAU32_channel_mode_mask 0x0000000Ful
172#define TAU32_data_inversion 0x00000010ul
173#define TAU32_fr_rx_splitcheck 0x00000020ul
174#define TAU32_fr_rx_fitcheck 0x00000040ul
175#define TAU32_fr_tx_auto 0x00000080ul
176#define TAU32_hdlc_crc32 0x00000100ul
177#define TAU32_hdlc_adjustment 0x00000200ul
178#define TAU32_hdlc_interframe_fill 0x00000400ul
179#define TAU32_hdlc_nocrc 0x00000800ul
180#define TAU32_tma_flag_filtering 0x00001000ul
181#define TAU32_tma_nopack 0x00002000ul
182#define TAU32_tma_flags_mask 0x00FF0000ul
183#define TAU32_tma_flags_shift 16u
184#define TAU32_v110_x30_tr_mask 0x03000000ul
185#define TAU32_v110_x30_tr_shift 24u
186
187typedef struct tag_TAU32_TimeslotAssignment
188{
189 unsigned __int8 TxChannel, RxChannel;
190 unsigned __int8 TxFillmask, RxFillmask;
191} TAU32_TimeslotAssignment;
192
193#define TAU32_CROSS_WIDTH 96
194#define TAU32_CROSS_OFF 127
195typedef unsigned __int8 TAU32_CrossMatrix[TAU32_CROSS_WIDTH];
196
197/* TAU32_INTERFACE_CONFIG_BITS */
198#define TAU32_LineOff (0ul << 0)
199#define TAU32_LineLoopInt (1ul << 0)
200#define TAU32_LineLoopExt (2ul << 0)
201#define TAU32_LineNormal (3ul << 0)
202#define TAU32_LineAIS (4ul << 0)
203#define TAU32_line_mode_mask 0x0000000Ful
204#define TAU32_unframed_64 (0ul << 4)
205#define TAU32_unframed_128 (1ul << 4)
206#define TAU32_unframed_256 (2ul << 4)
207#define TAU32_unframed_512 (3ul << 4)
208#define TAU32_unframed_1024 (4ul << 4)
209#define TAU32_unframed_2048 (5ul << 4)
210#define TAU32_unframed TAU32_unframed_2048
211#define TAU32_framed_no_cas (6ul << 4)
212#define TAU32_framed_cas_set (7ul << 4)
212#define TAU32_framed_cas_cross (8ul << 4)
213#define TAU32_framed_cas_pass (8ul << 4)
214#define TAU32_framed_cas_cross (9ul << 4)
213#define TAU32_framing_mode_mask 0x000000F0ul
214#define TAU32_monitor 0x00000100ul
215#define TAU32_higain 0x00000200ul
216#define TAU32_sa_bypass 0x00000400ul
217#define TAU32_si_bypass 0x00000800ul
218#define TAU32_cas_fe 0x00001000ul
219#define TAU32_ais_on_loss 0x00002000ul
220#define TAU32_cas_all_ones 0x00004000ul
221#define TAU32_cas_io 0x00008000ul
222#define TAU32_fas_io 0x00010000ul
223#define TAU32_fas8_io 0x00020000ul
224#define TAU32_auto_ais 0x00040000ul
225#define TAU32_not_auto_ra 0x00080000ul
226#define TAU32_not_auto_dmra 0x00100000ul
227#define TAU32_ra 0x00200000ul
228#define TAU32_dmra 0x00400000ul
229#define TAU32_scrambler 0x00800000ul
230#define TAU32_tx_ami 0x01000000ul
231#define TAU32_rx_ami 0x02000000ul
232#define TAU32_ja_tx 0x04000000ul
215#define TAU32_framing_mode_mask 0x000000F0ul
216#define TAU32_monitor 0x00000100ul
217#define TAU32_higain 0x00000200ul
218#define TAU32_sa_bypass 0x00000400ul
219#define TAU32_si_bypass 0x00000800ul
220#define TAU32_cas_fe 0x00001000ul
221#define TAU32_ais_on_loss 0x00002000ul
222#define TAU32_cas_all_ones 0x00004000ul
223#define TAU32_cas_io 0x00008000ul
224#define TAU32_fas_io 0x00010000ul
225#define TAU32_fas8_io 0x00020000ul
226#define TAU32_auto_ais 0x00040000ul
227#define TAU32_not_auto_ra 0x00080000ul
228#define TAU32_not_auto_dmra 0x00100000ul
229#define TAU32_ra 0x00200000ul
230#define TAU32_dmra 0x00400000ul
231#define TAU32_scrambler 0x00800000ul
232#define TAU32_tx_ami 0x01000000ul
233#define TAU32_rx_ami 0x02000000ul
234#define TAU32_ja_tx 0x04000000ul
233#define TAU32_crc4_mf_tx_only 0x08000000ul
234#define TAU32_crc4_mf_rx_only 0x10000000ul
235#define TAU32_crc4_mf (TAU32_crc4_mf_rx_only | TAU32_crc4_mf_tx_only)
235#define TAU32_crc4_mf_tx 0x08000000ul
236#define TAU32_crc4_mf_rx 0x10000000ul
237#define TAU32_crc4_mf (TAU32_crc4_mf_rx | TAU32_crc4_mf_tx)
236
237/* TAU32_SA_CROSS_VALUES */
238#define TAU32_SaDisable 0u
239#define TAU32_SaSystem 1u
240#define TAU32_SaIntA 2u
241#define TAU32_SaIntB 3u
242#define TAU32_SaAllZeros 4u
243
244typedef struct tag_TAU32_SaCross
245{
246 unsigned __int8 InterfaceA, InterfaceB;
247 unsigned __int8 SystemEnableTs0;
248} TAU32_SaCross;
249
250/* TAU32_INTERFACE_STATUS_BITS */
251#define TAU32_RCL 0x0001u /* receive carrier lost */
252#define TAU32_RLOS 0x0002u /* receive sync lost */
253#define TAU32_RUA1 0x0004u /* received unframed all ones */
254#define TAU32_RRA 0x0008u /* receive remote alarm */
255#define TAU32_RSA1 0x0010u /* receive signaling all ones */
256#define TAU32_RSA0 0x0020u /* receive signaling all zeros */
257#define TAU32_RDMA 0x0040u /* receive distant multiframe alarm */
258#define TAU32_LOTC 0x0080u /* transmit clock lost */
259#define TAU32_RSLIP 0x0100u /* receiver slip event */
260#define TAU32_TSLIP 0x0200u /* transmitter slip event */
261#define TAU32_RFAS 0x0400u /* receiver lost and searching for FAS */
262#define TAU32_RCRC4 0x0800u /* receiver lost and searching for CRC4 MF */
263#define TAU32_RCAS 0x1000u /* received lost and searching for CAS MF */
264#define TAU32_JITTER 0x2000u /* jitter attenuator limit */
265#define TAU32_RCRC4LONG 0x4000u /* G.706 400ms limit of searching for CRC4 */
266#define TAU32_E1OFF 0x8000u /* E1 line power-off */
267#define TAU32_LOS TAU32_RLOS
268#define TAU32_AIS TAU32_RUA1
269#define TAU32_LOF TAU32_RFAS
270#define TAU32_AIS16 TAU32_RSA1
271#define TAU32_LOFM TAU32_RCAS
272#define TAU32_FLOFM TAU32_RDMA
273
274/* TAU32_STATUS */
238
239/* TAU32_SA_CROSS_VALUES */
240#define TAU32_SaDisable 0u
241#define TAU32_SaSystem 1u
242#define TAU32_SaIntA 2u
243#define TAU32_SaIntB 3u
244#define TAU32_SaAllZeros 4u
245
246typedef struct tag_TAU32_SaCross
247{
248 unsigned __int8 InterfaceA, InterfaceB;
249 unsigned __int8 SystemEnableTs0;
250} TAU32_SaCross;
251
252/* TAU32_INTERFACE_STATUS_BITS */
253#define TAU32_RCL 0x0001u /* receive carrier lost */
254#define TAU32_RLOS 0x0002u /* receive sync lost */
255#define TAU32_RUA1 0x0004u /* received unframed all ones */
256#define TAU32_RRA 0x0008u /* receive remote alarm */
257#define TAU32_RSA1 0x0010u /* receive signaling all ones */
258#define TAU32_RSA0 0x0020u /* receive signaling all zeros */
259#define TAU32_RDMA 0x0040u /* receive distant multiframe alarm */
260#define TAU32_LOTC 0x0080u /* transmit clock lost */
261#define TAU32_RSLIP 0x0100u /* receiver slip event */
262#define TAU32_TSLIP 0x0200u /* transmitter slip event */
263#define TAU32_RFAS 0x0400u /* receiver lost and searching for FAS */
264#define TAU32_RCRC4 0x0800u /* receiver lost and searching for CRC4 MF */
265#define TAU32_RCAS 0x1000u /* received lost and searching for CAS MF */
266#define TAU32_JITTER 0x2000u /* jitter attenuator limit */
267#define TAU32_RCRC4LONG 0x4000u /* G.706 400ms limit of searching for CRC4 */
268#define TAU32_E1OFF 0x8000u /* E1 line power-off */
269#define TAU32_LOS TAU32_RLOS
270#define TAU32_AIS TAU32_RUA1
271#define TAU32_LOF TAU32_RFAS
272#define TAU32_AIS16 TAU32_RSA1
273#define TAU32_LOFM TAU32_RCAS
274#define TAU32_FLOFM TAU32_RDMA
275
276/* TAU32_STATUS */
275#define TAU32_FRCAS 0x0001u /* CAS framer searching for CAS MF */
276#define TAU32_CMWAITING 0x0002u /* Connection memory swap waiting */
277#define TAU32_CMPENDING 0x0004u /* Connection memory swap pending */
278#define TAU32_LED 0x0008u /* Let status (on/off) */
277#define TAU32_FRLOFM 0x0001u /* CAS framer searching for CAS MF */
278#define TAU32_CMWAITING 0x0002u /* Connection memory swap waiting */
279#define TAU32_CMPENDING 0x0004u /* Connection memory swap pending */
280#define TAU32_LED 0x0008u /* Led status (on/off) */
279
280typedef struct tag_TAU32_Controller TAU32_Controller;
281typedef struct tag_TAU32_UserRequest TAU32_UserRequest;
282typedef struct tag_TAU32_UserContext TAU32_UserContext;
283typedef union tag_TAU32_tsc TAU32_tsc;
284typedef struct tag_TAU32_FlatIoContext TAU32_FlatIoContext;
285typedef void(TAU32_CALLBACK_TYPE *TAU32_RequestCallback)(TAU32_UserContext *pContext, TAU32_UserRequest *pUserRequest);
286typedef void(TAU32_CALLBACK_TYPE *TAU32_NotifyCallback)(TAU32_UserContext *pContext, int Item, unsigned NotifyBits);
287typedef void(TAU32_CALLBACK_TYPE *TAU32_FifoTrigger)(TAU32_UserContext *pContext, int Interface, unsigned FifoId, unsigned Level);
288typedef void(TAU32_CALLBACK_TYPE *TAU32_FlatIoCallback)(TAU32_UserContext *pContext, TAU32_FlatIoContext *pFlatIoContext);
289
290union tag_TAU32_tsc
291{
292 unsigned __int32 osc, sync;
293};
294
295struct tag_TAU32_FlatIoContext
296{
297 void *pInternal;
298 PCI_PHYSICAL_ADDRESS PhysicalBufferAddress;
299 unsigned Channel, ItemsCount, EachItemBufferSize;
300 unsigned Received, ActualOffset, Errors;
301#if defined(_NTDDK_)
302 KDPC CallbackDpc;
303 void SetupCallback(PKDEFERRED_ROUTINE DeferredCallbackRoutine, void* pContext)
304 {
305 CallbackDpc.DeferredRoutine = DeferredCallbackRoutine;
306 CallbackDpc.DeferredContext = pContext;
307 }
308 void SetupCallback(TAU32_FlatIoCallback pCallback)
309 {
310 CallbackDpc.DeferredRoutine = (PKDEFERRED_ROUTINE) pCallback;
311 CallbackDpc.DeferredContext = 0;
312 }
313#else
314 TAU32_FlatIoCallback pCallback;
315#endif
316};
317
318/* TAU32_FIFO_ID */
319#define TAU32_FifoId_CasRx 0u
320#define TAU32_FifoId_CasTx 1u
321#define TAU32_FifoId_FasRx 2u
322#define TAU32_FifoId_FasTx 3u
323#define TAU32_FifoId_Max 4u
324
325typedef struct tag_TAU32_E1_State
326{
327 unsigned __int32 TickCounter;
328 unsigned __int32 RxViolations;
329 unsigned __int32 Crc4Errors;
330 unsigned __int32 FarEndBlockErrors;
331 unsigned __int32 FasErrors;
332 unsigned __int32 TransmitSlips;
333 unsigned __int32 ReceiveSlips;
334 unsigned __int32 Status;
335 unsigned __int32 FifoSlip[TAU32_FifoId_Max];
336} TAU32_E1_State;
337
338struct tag_TAU32_UserContext
339{
340 /* fields provided by user for for TAU32_Initiaize() */
341 TAU32_Controller *pControllerObject;
342 PCI_PHYSICAL_ADDRESS ControllerObjectPhysicalAddress;
343 void *PciBar1VirtualAddress;
344 TAU32_NotifyCallback pErrorNotifyCallback;
345 TAU32_NotifyCallback pStatusNotifyCallback;
346#if defined(_NTDDK_)
347 PKINTERRUPT InterruptObject;
348#endif
349 /* TODO: remove from release */
350 #define TAU32_CUSTOM_FIRMWARE
351 #ifdef TAU32_CUSTOM_FIRMWARE
352 void *pCustomFirmware;
353 unsigned CustomFirmwareSize;
354 #endif
355 /* fields filled by TAU32_Initiaize() */
356 int Model;
357 int Interfaces;
358 unsigned InitErrors;
359 unsigned __int32 DeadBits;
360
361 /* fields managed by DDK */
362 unsigned AdapterStatus;
363 unsigned CasIoLofCount;
364 unsigned E1IntLostCount;
365 unsigned CableTypeJumpers;
366 TAU32_E1_State InterfacesInfo[TAU32_MAX_INTERFACES];
367
368 /* fields which are't used by DDK, but nice for user */
369#ifdef TAU32_UserContext_Add
370 TAU32_UserContext_Add
371#endif
372};
373
374struct tag_TAU32_UserRequest
375{
376 /* required fields */
377 void *pInternal; /* internal */
378 unsigned Command; /* in */
379#if defined(_NTDDK_)
380 KDPC CallbackDpc;
381 void SetupCallback(PKDEFERRED_ROUTINE DeferredCallbackRoutine, void* pContext)
382 {
383 CallbackDpc.DeferredRoutine = DeferredCallbackRoutine;
384 CallbackDpc.DeferredContext = pContext;
385 }
386 void SetupCallback(TAU32_RequestCallback pCallback)
387 {
388 CallbackDpc.DeferredRoutine = (PKDEFERRED_ROUTINE) pCallback;
389 CallbackDpc.DeferredContext = 0;
390 }
391#else
392 TAU32_RequestCallback pCallback; /* in */
393#endif
394 unsigned __int32 ErrorCode; /* out */
395
396 union
397 {
398 unsigned ChannelNumber; /* just common field */
399
400 struct
401 {
402 unsigned Channel; /* in */
403 unsigned __int32 Config; /* in */
404 unsigned __int32 AssignedTsMask; /* build channel from timeslots which is selected by mask */
405 } ChannelConfig;
406
407 struct
408 {
409 int Interface;
410 unsigned __int32 Config; /* in */
411 unsigned __int32 UnframedTsMask;
412 } InterfaceConfig;
413
414 struct
415 {
416 unsigned Channel; /* in */
417 PCI_PHYSICAL_ADDRESS PhysicalDataAddress; /* in */
418 unsigned DataLength; /* in */
419 unsigned Transmitted; /* out */
420 } Tx;
421
422 struct
423 {
424 unsigned Channel; /* in */
425 PCI_PHYSICAL_ADDRESS PhysicalDataAddress; /* in */
426 unsigned BufferLength; /* in */
427 unsigned Received; /* out */
428 BOOLEAN FrameEnd; /* out */
429 } Rx;
430
431 BOOLEAN DigitalLoop; /* in, loop by PEB */
432
433 union
434 {
435 TAU32_TimeslotAssignment Complete[TAU32_TIMESLOTS];
436 unsigned __int32 Map[TAU32_CHANNELS];
437 } TimeslotsAssignment;
438 } Io;
439
440 /* fields which are't used by DDK, but nice for user */
441#ifdef TAU32_UserRequest_Add
442 TAU32_UserRequest_Add
443#endif
444};
445
446#define TAU32_IS_REQUEST_RUNNING(pUserRequest) ((pUserRequest)->pInternal != NULL)
447#define TAU32_IS_REQUEST_NOT_RUNNING(pUserRequest) ((pUserRequest)->pInternal == NULL)
448
449#ifndef TAU32_DDK_DLL
450# if defined(_NTDDK_)
451# ifdef TAU32_DDK_IMP
452# define TAU32_DDK_DLL __declspec(dllexport)
453# else
454# define TAU32_DDK_DLL __declspec(dllimport)
455# endif
456# else
457# define TAU32_DDK_DLL
458# endif
459#endif
460
461#ifdef __cplusplus
462extern "C"
463{
464#endif
465 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_BeforeReset(TAU32_UserContext *pUserContext);
466 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_Initialize(TAU32_UserContext *pUserContext, BOOLEAN CronyxDiag);
467 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_DestructiveHalt(TAU32_Controller *pControllerObject, BOOLEAN CancelRequests);
468 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_IsInterruptPending(TAU32_Controller *pControllerObject);
469 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_HandleInterrupt(TAU32_Controller *pControllerObject);
470 extern unsigned const TAU32_ControllerObjectSize;
471
472 /* LY: ��� ������� ����, ����� �������������� ���������� �� callback-�� */
473 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_EnableInterrupts(TAU32_Controller *pControllerObject);
474 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_DisableInterrupts(TAU32_Controller *pControllerObject);
475 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SubmitRequest(TAU32_Controller *pControllerObject, TAU32_UserRequest *pRequest);
476 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_CancelRequest(TAU32_Controller *pControllerObject, TAU32_UserRequest *pRequest, BOOLEAN BreakIfRunning);
477 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_LedBlink(TAU32_Controller *pControllerObject);
478 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_LedSet(TAU32_Controller *pControllerObject, BOOLEAN On);
479 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetCasIo(TAU32_Controller *pControllerObject, BOOLEAN Enabled);
480 unsigned __int64 TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_ProbeGeneratorFrequency(unsigned __int64 Frequency);
481 unsigned __int64 TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetGeneratorFrequency(TAU32_Controller *pControllerObject, unsigned __int64 Frequency);
482 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetSyncMode(TAU32_Controller *pControllerObject, unsigned Mode);
483 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetCrossMatrix(TAU32_Controller *pControllerObject, unsigned __int8 *pCrossMatrix, unsigned __int32 ReverseMask);
484 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetIdleCodes(TAU32_Controller *pControllerObject, unsigned __int8 *pIdleCodes);
485 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_UpdateIdleCodes(TAU32_Controller *pControllerObject, int Interface, unsigned __int32 TimeslotMask, unsigned __int8 IdleCode);
486 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetSaCross(TAU32_Controller *pControllerObject, TAU32_SaCross SaCross);
487 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoPutCasAppend(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
488 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoPutCasAhead(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
489 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoGetCas(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
490 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoPutFasAppend(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
491 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoPutFasAhead(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
492 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoGetFas(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
493 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetFifoTrigger(TAU32_Controller *pControllerObject, int Interface, unsigned FifoId, unsigned Level, TAU32_FifoTrigger Trigger);
494 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_ReadTsc(TAU32_Controller *pControllerObject, TAU32_tsc *pResult);
495
496 /* for Cronyx Engineering use only !!! */
497 #define TAU32_CRONYX_P 0
498 #define TAU32_CRONYX_PS 1
499 #define TAU32_CRONYX_PA 2
500 #define TAU32_CRONYX_PB 3
501 #define TAU32_CRONYX_I 4
502 #define TAU32_CRONYX_O 5
503 #define TAU32_CRONYX_U 6
504 #define TAU32_CRONYX_R 7
505 #define TAU32_CRONYX_W 8
506 #define TAU32_CRONYX_RW 9
507 #define TAU32_CRONYX_WR 10
508 #define TAU32_CRONYX_S 11
509 #define TAU32_CRONYX_G 12
510 unsigned __int32 TAU32_CALL_TYPE TAU32_Diag(TAU32_Controller *pControllerObject, unsigned Operation, unsigned __int32 Data);
511
512#ifdef __cplusplus
513}
514#endif
281
282typedef struct tag_TAU32_Controller TAU32_Controller;
283typedef struct tag_TAU32_UserRequest TAU32_UserRequest;
284typedef struct tag_TAU32_UserContext TAU32_UserContext;
285typedef union tag_TAU32_tsc TAU32_tsc;
286typedef struct tag_TAU32_FlatIoContext TAU32_FlatIoContext;
287typedef void(TAU32_CALLBACK_TYPE *TAU32_RequestCallback)(TAU32_UserContext *pContext, TAU32_UserRequest *pUserRequest);
288typedef void(TAU32_CALLBACK_TYPE *TAU32_NotifyCallback)(TAU32_UserContext *pContext, int Item, unsigned NotifyBits);
289typedef void(TAU32_CALLBACK_TYPE *TAU32_FifoTrigger)(TAU32_UserContext *pContext, int Interface, unsigned FifoId, unsigned Level);
290typedef void(TAU32_CALLBACK_TYPE *TAU32_FlatIoCallback)(TAU32_UserContext *pContext, TAU32_FlatIoContext *pFlatIoContext);
291
292union tag_TAU32_tsc
293{
294 unsigned __int32 osc, sync;
295};
296
297struct tag_TAU32_FlatIoContext
298{
299 void *pInternal;
300 PCI_PHYSICAL_ADDRESS PhysicalBufferAddress;
301 unsigned Channel, ItemsCount, EachItemBufferSize;
302 unsigned Received, ActualOffset, Errors;
303#if defined(_NTDDK_)
304 KDPC CallbackDpc;
305 void SetupCallback(PKDEFERRED_ROUTINE DeferredCallbackRoutine, void* pContext)
306 {
307 CallbackDpc.DeferredRoutine = DeferredCallbackRoutine;
308 CallbackDpc.DeferredContext = pContext;
309 }
310 void SetupCallback(TAU32_FlatIoCallback pCallback)
311 {
312 CallbackDpc.DeferredRoutine = (PKDEFERRED_ROUTINE) pCallback;
313 CallbackDpc.DeferredContext = 0;
314 }
315#else
316 TAU32_FlatIoCallback pCallback;
317#endif
318};
319
320/* TAU32_FIFO_ID */
321#define TAU32_FifoId_CasRx 0u
322#define TAU32_FifoId_CasTx 1u
323#define TAU32_FifoId_FasRx 2u
324#define TAU32_FifoId_FasTx 3u
325#define TAU32_FifoId_Max 4u
326
327typedef struct tag_TAU32_E1_State
328{
329 unsigned __int32 TickCounter;
330 unsigned __int32 RxViolations;
331 unsigned __int32 Crc4Errors;
332 unsigned __int32 FarEndBlockErrors;
333 unsigned __int32 FasErrors;
334 unsigned __int32 TransmitSlips;
335 unsigned __int32 ReceiveSlips;
336 unsigned __int32 Status;
337 unsigned __int32 FifoSlip[TAU32_FifoId_Max];
338} TAU32_E1_State;
339
340struct tag_TAU32_UserContext
341{
342 /* fields provided by user for for TAU32_Initiaize() */
343 TAU32_Controller *pControllerObject;
344 PCI_PHYSICAL_ADDRESS ControllerObjectPhysicalAddress;
345 void *PciBar1VirtualAddress;
346 TAU32_NotifyCallback pErrorNotifyCallback;
347 TAU32_NotifyCallback pStatusNotifyCallback;
348#if defined(_NTDDK_)
349 PKINTERRUPT InterruptObject;
350#endif
351 /* TODO: remove from release */
352 #define TAU32_CUSTOM_FIRMWARE
353 #ifdef TAU32_CUSTOM_FIRMWARE
354 void *pCustomFirmware;
355 unsigned CustomFirmwareSize;
356 #endif
357 /* fields filled by TAU32_Initiaize() */
358 int Model;
359 int Interfaces;
360 unsigned InitErrors;
361 unsigned __int32 DeadBits;
362
363 /* fields managed by DDK */
364 unsigned AdapterStatus;
365 unsigned CasIoLofCount;
366 unsigned E1IntLostCount;
367 unsigned CableTypeJumpers;
368 TAU32_E1_State InterfacesInfo[TAU32_MAX_INTERFACES];
369
370 /* fields which are't used by DDK, but nice for user */
371#ifdef TAU32_UserContext_Add
372 TAU32_UserContext_Add
373#endif
374};
375
376struct tag_TAU32_UserRequest
377{
378 /* required fields */
379 void *pInternal; /* internal */
380 unsigned Command; /* in */
381#if defined(_NTDDK_)
382 KDPC CallbackDpc;
383 void SetupCallback(PKDEFERRED_ROUTINE DeferredCallbackRoutine, void* pContext)
384 {
385 CallbackDpc.DeferredRoutine = DeferredCallbackRoutine;
386 CallbackDpc.DeferredContext = pContext;
387 }
388 void SetupCallback(TAU32_RequestCallback pCallback)
389 {
390 CallbackDpc.DeferredRoutine = (PKDEFERRED_ROUTINE) pCallback;
391 CallbackDpc.DeferredContext = 0;
392 }
393#else
394 TAU32_RequestCallback pCallback; /* in */
395#endif
396 unsigned __int32 ErrorCode; /* out */
397
398 union
399 {
400 unsigned ChannelNumber; /* just common field */
401
402 struct
403 {
404 unsigned Channel; /* in */
405 unsigned __int32 Config; /* in */
406 unsigned __int32 AssignedTsMask; /* build channel from timeslots which is selected by mask */
407 } ChannelConfig;
408
409 struct
410 {
411 int Interface;
412 unsigned __int32 Config; /* in */
413 unsigned __int32 UnframedTsMask;
414 } InterfaceConfig;
415
416 struct
417 {
418 unsigned Channel; /* in */
419 PCI_PHYSICAL_ADDRESS PhysicalDataAddress; /* in */
420 unsigned DataLength; /* in */
421 unsigned Transmitted; /* out */
422 } Tx;
423
424 struct
425 {
426 unsigned Channel; /* in */
427 PCI_PHYSICAL_ADDRESS PhysicalDataAddress; /* in */
428 unsigned BufferLength; /* in */
429 unsigned Received; /* out */
430 BOOLEAN FrameEnd; /* out */
431 } Rx;
432
433 BOOLEAN DigitalLoop; /* in, loop by PEB */
434
435 union
436 {
437 TAU32_TimeslotAssignment Complete[TAU32_TIMESLOTS];
438 unsigned __int32 Map[TAU32_CHANNELS];
439 } TimeslotsAssignment;
440 } Io;
441
442 /* fields which are't used by DDK, but nice for user */
443#ifdef TAU32_UserRequest_Add
444 TAU32_UserRequest_Add
445#endif
446};
447
448#define TAU32_IS_REQUEST_RUNNING(pUserRequest) ((pUserRequest)->pInternal != NULL)
449#define TAU32_IS_REQUEST_NOT_RUNNING(pUserRequest) ((pUserRequest)->pInternal == NULL)
450
451#ifndef TAU32_DDK_DLL
452# if defined(_NTDDK_)
453# ifdef TAU32_DDK_IMP
454# define TAU32_DDK_DLL __declspec(dllexport)
455# else
456# define TAU32_DDK_DLL __declspec(dllimport)
457# endif
458# else
459# define TAU32_DDK_DLL
460# endif
461#endif
462
463#ifdef __cplusplus
464extern "C"
465{
466#endif
467 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_BeforeReset(TAU32_UserContext *pUserContext);
468 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_Initialize(TAU32_UserContext *pUserContext, BOOLEAN CronyxDiag);
469 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_DestructiveHalt(TAU32_Controller *pControllerObject, BOOLEAN CancelRequests);
470 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_IsInterruptPending(TAU32_Controller *pControllerObject);
471 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_HandleInterrupt(TAU32_Controller *pControllerObject);
472 extern unsigned const TAU32_ControllerObjectSize;
473
474 /* LY: ��� ������� ����, ����� �������������� ���������� �� callback-�� */
475 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_EnableInterrupts(TAU32_Controller *pControllerObject);
476 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_DisableInterrupts(TAU32_Controller *pControllerObject);
477 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SubmitRequest(TAU32_Controller *pControllerObject, TAU32_UserRequest *pRequest);
478 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_CancelRequest(TAU32_Controller *pControllerObject, TAU32_UserRequest *pRequest, BOOLEAN BreakIfRunning);
479 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_LedBlink(TAU32_Controller *pControllerObject);
480 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_LedSet(TAU32_Controller *pControllerObject, BOOLEAN On);
481 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetCasIo(TAU32_Controller *pControllerObject, BOOLEAN Enabled);
482 unsigned __int64 TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_ProbeGeneratorFrequency(unsigned __int64 Frequency);
483 unsigned __int64 TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetGeneratorFrequency(TAU32_Controller *pControllerObject, unsigned __int64 Frequency);
484 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetSyncMode(TAU32_Controller *pControllerObject, unsigned Mode);
485 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetCrossMatrix(TAU32_Controller *pControllerObject, unsigned __int8 *pCrossMatrix, unsigned __int32 ReverseMask);
486 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetIdleCodes(TAU32_Controller *pControllerObject, unsigned __int8 *pIdleCodes);
487 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_UpdateIdleCodes(TAU32_Controller *pControllerObject, int Interface, unsigned __int32 TimeslotMask, unsigned __int8 IdleCode);
488 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetSaCross(TAU32_Controller *pControllerObject, TAU32_SaCross SaCross);
489 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoPutCasAppend(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
490 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoPutCasAhead(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
491 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoGetCas(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
492 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoPutFasAppend(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
493 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoPutFasAhead(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
494 int TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_FifoGetFas(TAU32_Controller *pControllerObject, int Interface, unsigned __int8 *pBuffer, unsigned Length);
495 BOOLEAN TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_SetFifoTrigger(TAU32_Controller *pControllerObject, int Interface, unsigned FifoId, unsigned Level, TAU32_FifoTrigger Trigger);
496 void TAU32_DDK_DLL TAU32_CALL_TYPE TAU32_ReadTsc(TAU32_Controller *pControllerObject, TAU32_tsc *pResult);
497
498 /* for Cronyx Engineering use only !!! */
499 #define TAU32_CRONYX_P 0
500 #define TAU32_CRONYX_PS 1
501 #define TAU32_CRONYX_PA 2
502 #define TAU32_CRONYX_PB 3
503 #define TAU32_CRONYX_I 4
504 #define TAU32_CRONYX_O 5
505 #define TAU32_CRONYX_U 6
506 #define TAU32_CRONYX_R 7
507 #define TAU32_CRONYX_W 8
508 #define TAU32_CRONYX_RW 9
509 #define TAU32_CRONYX_WR 10
510 #define TAU32_CRONYX_S 11
511 #define TAU32_CRONYX_G 12
512 unsigned __int32 TAU32_CALL_TYPE TAU32_Diag(TAU32_Controller *pControllerObject, unsigned Operation, unsigned __int32 Data);
513
514#ifdef __cplusplus
515}
516#endif