1/*-
2 * Copyright (c) 2008 Nathan Whitehorn
3 * Copyright (c) 2003 Peter Grehan
4 * All rights reserved
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
| 1/*-
2 * Copyright (c) 2008 Nathan Whitehorn
3 * Copyright (c) 2003 Peter Grehan
4 * All rights reserved
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
|
27 * $FreeBSD: head/sys/dev/bm/if_bmvar.h 180233 2008-07-03 21:51:30Z nwhitehorn $
| 27 * $FreeBSD: head/sys/dev/bm/if_bmvar.h 226995 2011-11-01 16:13:59Z marius $
|
28 */
29
30/*
31 * Number of transmit/receive DBDMA descriptors.
32 * XXX allow override with a tuneable ?
33 */
34#define BM_MAX_DMA_COMMANDS 256
35#define BM_NTXSEGS 16
36
37#define BM_MAX_TX_PACKETS 100
38#define BM_MAX_RX_PACKETS 100
39
40/*
41 * Mutex macros
42 */
43#define BM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
44#define BM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
45
46/*
47 * software state for transmit job mbufs (may be elements of mbuf chains)
48 */
| 28 */
29
30/*
31 * Number of transmit/receive DBDMA descriptors.
32 * XXX allow override with a tuneable ?
33 */
34#define BM_MAX_DMA_COMMANDS 256
35#define BM_NTXSEGS 16
36
37#define BM_MAX_TX_PACKETS 100
38#define BM_MAX_RX_PACKETS 100
39
40/*
41 * Mutex macros
42 */
43#define BM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
44#define BM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
45
46/*
47 * software state for transmit job mbufs (may be elements of mbuf chains)
48 */
|
49
| |
50struct bm_txsoft {
51 struct mbuf *txs_mbuf; /* head of our mbuf chain */
52 bus_dmamap_t txs_dmamap; /* our DMA map */
53 int txs_firstdesc; /* first descriptor in packet */
54 int txs_lastdesc; /* last descriptor in packet */
55 int txs_stopdesc; /* the location of the closing STOP */
56
57 int txs_ndescs; /* number of descriptors */
58 STAILQ_ENTRY(bm_txsoft) txs_q;
59};
60
61STAILQ_HEAD(bm_txsq, bm_txsoft);
62
63/*
64 * software state for receive jobs
65 */
66struct bm_rxsoft {
67 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
68 bus_dmamap_t rxs_dmamap; /* our DMA map */
69
70 int dbdma_slot;
71 bus_dma_segment_t segment;
72};
73
| 49struct bm_txsoft {
50 struct mbuf *txs_mbuf; /* head of our mbuf chain */
51 bus_dmamap_t txs_dmamap; /* our DMA map */
52 int txs_firstdesc; /* first descriptor in packet */
53 int txs_lastdesc; /* last descriptor in packet */
54 int txs_stopdesc; /* the location of the closing STOP */
55
56 int txs_ndescs; /* number of descriptors */
57 STAILQ_ENTRY(bm_txsoft) txs_q;
58};
59
60STAILQ_HEAD(bm_txsq, bm_txsoft);
61
62/*
63 * software state for receive jobs
64 */
65struct bm_rxsoft {
66 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
67 bus_dmamap_t rxs_dmamap; /* our DMA map */
68
69 int dbdma_slot;
70 bus_dma_segment_t segment;
71};
72
|
74
| |
75struct bm_softc {
76 struct ifnet *sc_ifp;
77 struct mtx sc_mtx;
78 u_char sc_enaddr[ETHER_ADDR_LEN];
79
80 int sc_streaming;
81 int sc_ifpflags;
82 int sc_duplex;
83 int sc_wdog_timer;
84
85 struct callout sc_tick_ch;
86
87 device_t sc_dev; /* back ptr to dev */
88 struct resource *sc_memr; /* macio bus mem resource */
89 int sc_memrid;
90 device_t sc_miibus;
91
92 struct mii_data *sc_mii;
93
94 struct resource *sc_txdmar, *sc_rxdmar;
95 int sc_txdmarid, sc_rxdmarid;
96
97 struct resource *sc_txdmairq, *sc_rxdmairq;
98 void *sc_txihtx, *sc_rxih;
99 int sc_txdmairqid, sc_rxdmairqid;
100
101 bus_dma_tag_t sc_pdma_tag;
102
103 bus_dma_tag_t sc_tdma_tag;
104 struct bm_txsoft sc_txsoft[BM_MAX_TX_PACKETS];
105 int first_used_txdma_slot, next_txdma_slot;
106
107 struct bm_txsq sc_txfreeq;
108 struct bm_txsq sc_txdirtyq;
109
110 bus_dma_tag_t sc_rdma_tag;
111 struct bm_rxsoft sc_rxsoft[BM_MAX_TX_PACKETS];
112 int next_rxdma_slot, rxdma_loop_slot;
113
114 dbdma_channel_t *sc_txdma, *sc_rxdma;
115};
| 73struct bm_softc {
74 struct ifnet *sc_ifp;
75 struct mtx sc_mtx;
76 u_char sc_enaddr[ETHER_ADDR_LEN];
77
78 int sc_streaming;
79 int sc_ifpflags;
80 int sc_duplex;
81 int sc_wdog_timer;
82
83 struct callout sc_tick_ch;
84
85 device_t sc_dev; /* back ptr to dev */
86 struct resource *sc_memr; /* macio bus mem resource */
87 int sc_memrid;
88 device_t sc_miibus;
89
90 struct mii_data *sc_mii;
91
92 struct resource *sc_txdmar, *sc_rxdmar;
93 int sc_txdmarid, sc_rxdmarid;
94
95 struct resource *sc_txdmairq, *sc_rxdmairq;
96 void *sc_txihtx, *sc_rxih;
97 int sc_txdmairqid, sc_rxdmairqid;
98
99 bus_dma_tag_t sc_pdma_tag;
100
101 bus_dma_tag_t sc_tdma_tag;
102 struct bm_txsoft sc_txsoft[BM_MAX_TX_PACKETS];
103 int first_used_txdma_slot, next_txdma_slot;
104
105 struct bm_txsq sc_txfreeq;
106 struct bm_txsq sc_txdirtyq;
107
108 bus_dma_tag_t sc_rdma_tag;
109 struct bm_rxsoft sc_rxsoft[BM_MAX_TX_PACKETS];
110 int next_rxdma_slot, rxdma_loop_slot;
111
112 dbdma_channel_t *sc_txdma, *sc_rxdma;
113};
|
116
117struct bm_mii_frame {
118 u_int8_t mii_stdelim;
119 u_int8_t mii_opcode;
120 u_int8_t mii_phyaddr;
121 u_int8_t mii_regaddr;
122 u_int8_t mii_turnaround;
123 u_int16_t mii_data;
124};
125
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