1/*
2 * Copyright 1991-1998 by Open Software Foundation, Inc.
3 * All Rights Reserved
4 *
5 * Permission to use, copy, modify, and distribute this software and
6 * its documentation for any purpose and without fee is hereby granted,
7 * provided that the above copyright notice appears in all copies and
8 * that both the copyright notice and this permission notice appear in
9 * supporting documentation.
10 *
11 * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
12 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
13 * FOR A PARTICULAR PURPOSE.
14 *
15 * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
16 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
17 * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
18 * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
19 * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 */
21/*
22 * Copyright 2003 by Peter Grehan. All rights reserved.
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. The name of the author may not be used to endorse or promote products
33 * derived from this software without specific prior written permission.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
36 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
37 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
38 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
40 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
41 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
42 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * SUCH DAMAGE.
46 *
| 1/*
2 * Copyright 1991-1998 by Open Software Foundation, Inc.
3 * All Rights Reserved
4 *
5 * Permission to use, copy, modify, and distribute this software and
6 * its documentation for any purpose and without fee is hereby granted,
7 * provided that the above copyright notice appears in all copies and
8 * that both the copyright notice and this permission notice appear in
9 * supporting documentation.
10 *
11 * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
12 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
13 * FOR A PARTICULAR PURPOSE.
14 *
15 * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
16 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
17 * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
18 * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
19 * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 */
21/*
22 * Copyright 2003 by Peter Grehan. All rights reserved.
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. The name of the author may not be used to endorse or promote products
33 * derived from this software without specific prior written permission.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
36 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
37 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
38 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
40 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
41 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
42 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * SUCH DAMAGE.
46 *
|
47 * $FreeBSD: head/sys/dev/bm/if_bmreg.h 180233 2008-07-03 21:51:30Z nwhitehorn $
| 47 * $FreeBSD: head/sys/dev/bm/if_bmreg.h 226995 2011-11-01 16:13:59Z marius $
|
48 */
49
50/*
51 * BMAC resource indices
52 */
53
54#define BM_MAIN_REGISTERS 0
55#define BM_TXDMA_REGISTERS 1
56#define BM_RXDMA_REGISTERS 2
57
58#define BM_MAIN_INTERRUPT 0
59#define BM_TXDMA_INTERRUPT 1
60#define BM_RXDMA_INTERRUPT 2
61
62/*
63 * BMAC/BMAC+ register offsets
64 */
65
66#define BM_TX_IFC 0x0000 /* interface control */
67#define BM_TXFIFO_CSR 0x0100 /* TX FIFO control/status */
68#define BM_TX_THRESH 0x0110 /* TX threshold */
69#define BM_RXFIFO_CSR 0x0120 /* receive FIFO control/status */
70#define BM_MEMADD 0x0130 /* unused */
71#define BM_MEMDATA_HI 0x0140 /* unused */
72#define BM_MEMDATA_LO 0x0150 /* unused */
73#define BM_XCVR 0x0160 /* transceiver control register */
74#define BM_CHIPID 0x0170 /* chip ID */
75#define BM_MII_CSR 0x0180 /* MII control register */
76#define BM_SROM_CSR 0x0190 /* unused, OFW provides enet addr */
77#define BM_TX_PTR 0x01A0 /* unused */
78#define BM_RX_PTR 0x01B0 /* unused */
79#define BM_STATUS 0x01C0 /* status register */
80#define BM_INTR_DISABLE 0x0200 /* interrupt control register */
81#define BM_TX_RESET 0x0420 /* TX reset */
82#define BM_TX_CONFIG 0x0430 /* TX config */
83#define BM_IPG1 0x0440 /* inter-packet gap hi */
84#define BM_IPG2 0x0450 /* inter-packet gap lo */
85#define BM_TX_ALIMIT 0x0460 /* TX attempt limit */
86#define BM_TX_STIME 0x0470 /* TX slot time */
87#define BM_TX_PASIZE 0x0480 /* TX preamble size */
88#define BM_TX_PAPAT 0x0490 /* TX preamble pattern */
89#define BM_TX_SFD 0x04A0 /* TX start-frame delimiter */
90#define BM_JAMSIZE 0x04B0 /* collision jam size */
91#define BM_TX_MAXLEN 0x04C0 /* max TX packet length */
92#define BM_TX_MINLEN 0x04D0 /* min TX packet length */
93#define BM_TX_PEAKCNT 0x04E0 /* TX peak attempts count */
94#define BM_TX_DCNT 0x04F0 /* TX defer timer */
95#define BM_TX_NCCNT 0x0500 /* TX normal collision cnt */
96#define BM_TX_FCCNT 0x0510 /* TX first collision cnt */
97#define BM_TX_EXCNT 0x0520 /* TX excess collision cnt */
98#define BM_TX_LTCNT 0x0530 /* TX late collision cnt */
99#define BM_TX_RANDSEED 0x0540 /* TX random seed */
100#define BM_TXSM 0x0550 /* TX state machine */
101#define BM_RX_RESET 0x0620 /* RX reset */
102#define BM_RX_CONFIG 0x0630 /* RX config */
103#define BM_RX_MAXLEN 0x0640 /* max RX packet length */
104#define BM_RX_MINLEN 0x0650 /* min RX packet length */
105#define BM_MACADDR2 0x0660 /* MAC address */
106#define BM_MACADDR1 0x0670
107#define BM_MACADDR0 0x0680
108#define BM_RX_FRCNT 0x0690 /* RX frame count */
109#define BM_RX_LECNT 0x06A0 /* RX too-long frame count */
110#define BM_RX_AECNT 0x06B0 /* RX misaligned frame count */
111#define BM_RX_FECNT 0x06C0 /* RX CRC error count */
112#define BM_RXSM 0x06D0 /* RX state machine */
113#define BM_RXCV 0x06E0 /* RX code violations */
114#define BM_HASHTAB3 0x0700 /* Address hash table */
115#define BM_HASHTAB2 0x0710
116#define BM_HASHTAB1 0x0720
117#define BM_HASHTAB0 0x0730
118#define BM_AFILTER2 0x0740 /* Address filter */
119#define BM_AFILTER1 0x0750
120#define BM_AFILTER0 0x0760
121#define BM_AFILTER_MASK 0x0770
122
123/*
124 * MII control register bits
125 */
126#define BM_MII_CLK 0x0001 /* MDIO clock */
127#define BM_MII_DATAOUT 0x0002 /* MDIO data out */
128#define BM_MII_OENABLE 0x0004 /* MDIO output enable */
129#define BM_MII_DATAIN 0x0008 /* MDIO data in */
130
131/*
| 48 */
49
50/*
51 * BMAC resource indices
52 */
53
54#define BM_MAIN_REGISTERS 0
55#define BM_TXDMA_REGISTERS 1
56#define BM_RXDMA_REGISTERS 2
57
58#define BM_MAIN_INTERRUPT 0
59#define BM_TXDMA_INTERRUPT 1
60#define BM_RXDMA_INTERRUPT 2
61
62/*
63 * BMAC/BMAC+ register offsets
64 */
65
66#define BM_TX_IFC 0x0000 /* interface control */
67#define BM_TXFIFO_CSR 0x0100 /* TX FIFO control/status */
68#define BM_TX_THRESH 0x0110 /* TX threshold */
69#define BM_RXFIFO_CSR 0x0120 /* receive FIFO control/status */
70#define BM_MEMADD 0x0130 /* unused */
71#define BM_MEMDATA_HI 0x0140 /* unused */
72#define BM_MEMDATA_LO 0x0150 /* unused */
73#define BM_XCVR 0x0160 /* transceiver control register */
74#define BM_CHIPID 0x0170 /* chip ID */
75#define BM_MII_CSR 0x0180 /* MII control register */
76#define BM_SROM_CSR 0x0190 /* unused, OFW provides enet addr */
77#define BM_TX_PTR 0x01A0 /* unused */
78#define BM_RX_PTR 0x01B0 /* unused */
79#define BM_STATUS 0x01C0 /* status register */
80#define BM_INTR_DISABLE 0x0200 /* interrupt control register */
81#define BM_TX_RESET 0x0420 /* TX reset */
82#define BM_TX_CONFIG 0x0430 /* TX config */
83#define BM_IPG1 0x0440 /* inter-packet gap hi */
84#define BM_IPG2 0x0450 /* inter-packet gap lo */
85#define BM_TX_ALIMIT 0x0460 /* TX attempt limit */
86#define BM_TX_STIME 0x0470 /* TX slot time */
87#define BM_TX_PASIZE 0x0480 /* TX preamble size */
88#define BM_TX_PAPAT 0x0490 /* TX preamble pattern */
89#define BM_TX_SFD 0x04A0 /* TX start-frame delimiter */
90#define BM_JAMSIZE 0x04B0 /* collision jam size */
91#define BM_TX_MAXLEN 0x04C0 /* max TX packet length */
92#define BM_TX_MINLEN 0x04D0 /* min TX packet length */
93#define BM_TX_PEAKCNT 0x04E0 /* TX peak attempts count */
94#define BM_TX_DCNT 0x04F0 /* TX defer timer */
95#define BM_TX_NCCNT 0x0500 /* TX normal collision cnt */
96#define BM_TX_FCCNT 0x0510 /* TX first collision cnt */
97#define BM_TX_EXCNT 0x0520 /* TX excess collision cnt */
98#define BM_TX_LTCNT 0x0530 /* TX late collision cnt */
99#define BM_TX_RANDSEED 0x0540 /* TX random seed */
100#define BM_TXSM 0x0550 /* TX state machine */
101#define BM_RX_RESET 0x0620 /* RX reset */
102#define BM_RX_CONFIG 0x0630 /* RX config */
103#define BM_RX_MAXLEN 0x0640 /* max RX packet length */
104#define BM_RX_MINLEN 0x0650 /* min RX packet length */
105#define BM_MACADDR2 0x0660 /* MAC address */
106#define BM_MACADDR1 0x0670
107#define BM_MACADDR0 0x0680
108#define BM_RX_FRCNT 0x0690 /* RX frame count */
109#define BM_RX_LECNT 0x06A0 /* RX too-long frame count */
110#define BM_RX_AECNT 0x06B0 /* RX misaligned frame count */
111#define BM_RX_FECNT 0x06C0 /* RX CRC error count */
112#define BM_RXSM 0x06D0 /* RX state machine */
113#define BM_RXCV 0x06E0 /* RX code violations */
114#define BM_HASHTAB3 0x0700 /* Address hash table */
115#define BM_HASHTAB2 0x0710
116#define BM_HASHTAB1 0x0720
117#define BM_HASHTAB0 0x0730
118#define BM_AFILTER2 0x0740 /* Address filter */
119#define BM_AFILTER1 0x0750
120#define BM_AFILTER0 0x0760
121#define BM_AFILTER_MASK 0x0770
122
123/*
124 * MII control register bits
125 */
126#define BM_MII_CLK 0x0001 /* MDIO clock */
127#define BM_MII_DATAOUT 0x0002 /* MDIO data out */
128#define BM_MII_OENABLE 0x0004 /* MDIO output enable */
129#define BM_MII_DATAIN 0x0008 /* MDIO data in */
130
131/*
|
132 * MII constants
133 */
134#define BM_MII_STARTDELIM 0x01
135#define BM_MII_READOP 0x02
136#define BM_MII_WRITEOP 0x01
137#define BM_MII_TURNAROUND 0x02
138
139/*
| |
140 * Various flags
141 */
142
143#define BM_ENABLE 0x0001
144
145#define BM_CRC_ENABLE 0x0100
146#define BM_HASH_FILTER_ENABLE 0x0200
147#define BM_REJECT_OWN_PKTS 0x0800
148#define BM_PROMISC 0x0040
149
150#define BM_TX_FULLDPX 0x0200
151#define BM_TX_IGNORECOLL 0x0040
152
153#define BM_INTR_PKT_RX 0x0001
154#define BM_INTR_PKT_TX 0x0100
155#define BM_INTR_TX_UNDERRUN 0x0200
156
157#define BM_INTR_NORMAL ~(BM_INTR_PKT_TX | BM_INTR_TX_UNDERRUN)
158#define BM_INTR_NONE 0xffff
159
160/*
161 * register space access macros
162 */
163#define CSR_WRITE_4(sc, reg, val) \
164 bus_write_4(sc->sc_memr, reg, val)
165#define CSR_WRITE_2(sc, reg, val) \
166 bus_write_2(sc->sc_memr, reg, val)
167#define CSR_WRITE_1(sc, reg, val) \
168 bus_write_1(sc->sc_memr, reg, val)
169
170#define CSR_READ_4(sc, reg) \
171 bus_read_4(sc->sc_memr, reg)
172#define CSR_READ_2(sc, reg) \
173 bus_read_2(sc->sc_memr, reg)
174#define CSR_READ_1(sc, reg) \
175 bus_read_1(sc->sc_memr, reg)
176
| 132 * Various flags
133 */
134
135#define BM_ENABLE 0x0001
136
137#define BM_CRC_ENABLE 0x0100
138#define BM_HASH_FILTER_ENABLE 0x0200
139#define BM_REJECT_OWN_PKTS 0x0800
140#define BM_PROMISC 0x0040
141
142#define BM_TX_FULLDPX 0x0200
143#define BM_TX_IGNORECOLL 0x0040
144
145#define BM_INTR_PKT_RX 0x0001
146#define BM_INTR_PKT_TX 0x0100
147#define BM_INTR_TX_UNDERRUN 0x0200
148
149#define BM_INTR_NORMAL ~(BM_INTR_PKT_TX | BM_INTR_TX_UNDERRUN)
150#define BM_INTR_NONE 0xffff
151
152/*
153 * register space access macros
154 */
155#define CSR_WRITE_4(sc, reg, val) \
156 bus_write_4(sc->sc_memr, reg, val)
157#define CSR_WRITE_2(sc, reg, val) \
158 bus_write_2(sc->sc_memr, reg, val)
159#define CSR_WRITE_1(sc, reg, val) \
160 bus_write_1(sc->sc_memr, reg, val)
161
162#define CSR_READ_4(sc, reg) \
163 bus_read_4(sc->sc_memr, reg)
164#define CSR_READ_2(sc, reg) \
165 bus_read_2(sc->sc_memr, reg)
166#define CSR_READ_1(sc, reg) \
167 bus_read_1(sc->sc_memr, reg)
168
|
| 169#define CSR_BARRIER(sc, reg, length, flags) \
170 bus_barrier(sc->sc_memr, reg, length, flags)
|
| |